diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
6 files changed, 2733 insertions, 2637 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 028711e47..158e17e5b 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -11,14 +11,15 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +clock=1000 +console=/projects/pd/randd/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/projects/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/projects/pd/randd/dist/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -34,18 +35,17 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge +clock=1000 delay=50000 -nack_delay=4000 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[0] [system.cpu0] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -93,6 +93,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu0.itb @@ -111,7 +112,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -145,16 +145,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -437,16 +439,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -460,6 +464,9 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=AlphaInterrupts +[system.cpu0.isa] +type=AlphaISA + [system.cpu0.itb] type=AlphaTLB size=48 @@ -469,7 +476,7 @@ type=ExeTracer [system.cpu1] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -517,6 +524,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu1.itb @@ -535,7 +543,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -569,16 +576,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -861,16 +870,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -884,6 +895,9 @@ mem_side=system.toL2Bus.slave[2] [system.cpu1.interrupts] type=AlphaInterrupts +[system.cpu1.isa] +type=AlphaISA + [system.cpu1.itb] type=AlphaTLB size=48 @@ -908,7 +922,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -928,7 +942,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -951,16 +965,18 @@ type=BaseCache addr_ranges=0:8589934591 assoc=8 block_size=64 +clock=1000 forward_snoops=false hash_delay=1 +hit_latency=50 is_top_level=true -latency=50000 max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=50 size=1024 subblock_size=0 system=system @@ -976,20 +992,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=4194304 subblock_size=0 system=system -tgts_per_mshr=16 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -1010,9 +1028,10 @@ slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake +clock=1000 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -1025,14 +1044,28 @@ warn_access= pio=system.membus.default [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[1] @@ -1044,7 +1077,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -1057,7 +1090,7 @@ port=3456 [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false width=8 @@ -1072,10 +1105,11 @@ system=system [system.tsunami.backdoor] type=AlphaBackdoor +clock=1000 cpu=system.cpu0 disk=system.simple_disk pio_addr=8804682956800 -pio_latency=1000 +pio_latency=100000 platform=system.tsunami system=system terminal=system.terminal @@ -1083,8 +1117,9 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip +clock=1000 pio_addr=8803072344064 -pio_latency=1000 +pio_latency=100000 system=system tsunami=system.tsunami pio=system.iobus.master[0] @@ -1140,12 +1175,10 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.tsunami rss=false rx_delay=1000000 @@ -1162,9 +1195,10 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake +clock=1000 fake_mem=false pio_addr=8796093677568 -pio_latency=1000 +pio_latency=100000 pio_size=393216 ret_bad_addr=false ret_data16=65535 @@ -1178,9 +1212,10 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848432 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1194,9 +1229,10 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848304 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1210,9 +1246,10 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848569 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1226,9 +1263,10 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848451 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1242,9 +1280,10 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848515 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1258,9 +1297,10 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848579 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1274,9 +1314,10 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848643 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1290,9 +1331,10 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848707 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1306,9 +1348,10 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848771 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1322,9 +1365,10 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848835 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1338,9 +1382,10 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848899 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1354,9 +1399,10 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615850617 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1370,9 +1416,10 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848891 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1386,9 +1433,10 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848816 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1402,9 +1450,10 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848696 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1418,9 +1467,10 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848936 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1434,9 +1484,10 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848680 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1450,9 +1501,10 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848944 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1466,9 +1518,10 @@ pio=system.iobus.master[6] [system.tsunami.fb] type=BadDevice +clock=1000 devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[21] @@ -1512,16 +1565,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1000 config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 io_shift=0 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.tsunami system=system config=system.iobus.master[26] @@ -1530,9 +1582,10 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO +clock=1000 frequency=976562500 pio_addr=8804615847936 -pio_latency=1000 +pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami @@ -1541,8 +1594,9 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip +clock=1000 pio_addr=8802535473152 -pio_latency=1000 +pio_latency=100000 system=system tsunami=system.tsunami pio=system.iobus.master[1] @@ -1550,7 +1604,8 @@ pio=system.iobus.master[1] [system.tsunami.pciconfig] type=PciConfigAll bus=0 -pio_latency=1 +clock=1000 +pio_latency=30000 platform=system.tsunami size=16777216 system=system @@ -1558,8 +1613,9 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 +clock=1000 pio_addr=8804615848952 -pio_latency=1000 +pio_latency=100000 platform=system.tsunami system=system terminal=system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index acdd4bc1c..200b08796 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,13 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:20:05 -gem5 started Jul 26 2012 22:30:48 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 13:40:49 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 112168000 -Exiting @ tick 1900530295500 because m5_exit instruction encountered +info: Launching CPU 1 @ 107840000 +Exiting @ tick 1897857556000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 763ec5c7a..59d7770e6 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.896908 # Number of seconds simulated -sim_ticks 1896907607500 # Number of ticks simulated -final_tick 1896907607500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.897858 # Number of seconds simulated +sim_ticks 1897857556000 # Number of ticks simulated +final_tick 1897857556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91997 # Simulator instruction rate (inst/s) -host_op_rate 91997 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3111116066 # Simulator tick rate (ticks/s) -host_mem_usage 330780 # Number of bytes of host memory used -host_seconds 609.72 # Real time elapsed on the host -sim_insts 56092592 # Number of instructions simulated -sim_ops 56092592 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 788928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24066944 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 193664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1095360 # Number of bytes read from this memory -system.physmem.bytes_read::total 28794304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 788928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 193664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 982592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7762048 # Number of bytes written to this memory -system.physmem.bytes_written::total 7762048 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12327 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 376046 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41397 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3026 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 17115 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449911 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121282 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121282 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 415902 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12687462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1396698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 102095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 577445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15179603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 415902 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 102095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517997 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4091948 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4091948 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4091948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 415902 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12687462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1396698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 102095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 577445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19271551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 449911 # Total number of read requests seen -system.physmem.writeReqs 121282 # Total number of write requests seen -system.physmem.cpureqs 578344 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28794304 # Total number of bytes read from memory -system.physmem.bytesWritten 7762048 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28794304 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7762048 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 53 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3357 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28022 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27737 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28393 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27975 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28585 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28204 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 28175 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28470 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28412 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28316 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28619 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27813 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27389 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27281 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7511 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7339 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7747 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7422 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7940 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7694 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7599 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7607 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7865 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7795 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7764 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 8092 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7767 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7407 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6820 # Track writes on a per bank basis +host_inst_rate 131170 # Simulator instruction rate (inst/s) +host_op_rate 131170 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4437782045 # Simulator tick rate (ticks/s) +host_mem_usage 332328 # Number of bytes of host memory used +host_seconds 427.66 # Real time elapsed on the host +sim_insts 56096024 # Number of instructions simulated +sim_ops 56096024 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 762816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24264832 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 217920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 955136 # Number of bytes read from this memory +system.physmem.bytes_read::total 28851328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 762816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 217920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 980736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7805952 # Number of bytes written to this memory +system.physmem.bytes_written::total 7805952 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11919 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 379138 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3405 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 14924 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450802 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121968 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121968 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 401935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12785381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1396640 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 114824 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 503271 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15202051 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 401935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 114824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4113034 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4113034 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4113034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 401935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12785381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1396640 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 114824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 503271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19315085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450802 # Total number of read requests seen +system.physmem.writeReqs 121968 # Total number of write requests seen +system.physmem.cpureqs 580318 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28851328 # Total number of bytes read from memory +system.physmem.bytesWritten 7805952 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28851328 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7805952 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 52 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3354 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28275 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28002 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28406 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28112 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28525 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28215 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27879 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27987 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28286 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28166 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28504 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 28066 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28252 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27946 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27814 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7745 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7549 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7802 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7514 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7914 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7617 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7286 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7648 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7558 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7984 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7855 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7634 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7769 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7378 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7280 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 313 # Number of times wr buffer was full causing retry -system.physmem.totGap 1896888917000 # Total gap between requests +system.physmem.numWrRetry 525 # Number of times wr buffer was full causing retry +system.physmem.totGap 1897852967000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 449911 # Categorize read packet sizes +system.physmem.readPktSize::6 450802 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -107,7 +107,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 121595 # categorize write packet sizes +system.physmem.writePktSize::6 122493 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -116,31 +116,31 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 3357 # categorize neither packet sizes +system.physmem.neitherpktsize::6 3354 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 322755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1798 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 322811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66355 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 31450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2903 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1788 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 1259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1472 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 908 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -152,225 +152,225 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 178 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 6417421318 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13706967318 # Sum of mem lat for all requests -system.physmem.totBusLat 1799432000 # Total cycles spent in databus access -system.physmem.totBankLat 5490114000 # Total cycles spent in bank access -system.physmem.avgQLat 14265.44 # Average queueing delay per request -system.physmem.avgBankLat 12204.10 # Average bank access latency per request +system.physmem.totQLat 6654880960 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13976960960 # Sum of mem lat for all requests +system.physmem.totBusLat 1803000000 # Total cycles spent in databus access +system.physmem.totBankLat 5519080000 # Total cycles spent in bank access +system.physmem.avgQLat 14764.02 # Average queueing delay per request +system.physmem.avgBankLat 12244.22 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30469.54 # Average memory access latency -system.physmem.avgRdBW 15.18 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.18 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.09 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31008.23 # Average memory access latency +system.physmem.avgRdBW 15.20 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.20 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.11 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.19 # Average write queue length over time -system.physmem.readRowHits 429697 # Number of row buffer hits during reads -system.physmem.writeRowHits 77704 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 64.07 # Row buffer hit rate for writes -system.physmem.avgGap 3320924.66 # Average gap between requests -system.l2c.replacements 342985 # number of replacements -system.l2c.tagsinuse 65321.507443 # Cycle average of tags in use -system.l2c.total_refs 2664537 # Total number of references to valid blocks. -system.l2c.sampled_refs 407990 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.530888 # Average number of references to valid blocks. +system.physmem.avgWrQLen 7.39 # Average write queue length over time +system.physmem.readRowHits 429728 # Number of row buffer hits during reads +system.physmem.writeRowHits 77127 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 63.24 # Row buffer hit rate for writes +system.physmem.avgGap 3313464.33 # Average gap between requests +system.l2c.replacements 343886 # number of replacements +system.l2c.tagsinuse 65330.449226 # Cycle average of tags in use +system.l2c.total_refs 2612992 # Total number of references to valid blocks. +system.l2c.sampled_refs 408910 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.390140 # Average number of references to valid blocks. system.l2c.warmup_cycle 5415654002 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 53803.345548 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4275.017757 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 5362.992247 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 1295.991254 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 584.160637 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.820974 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.065232 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.081833 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.019775 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.008914 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996727 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 631150 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 433289 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 452366 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 409982 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1926787 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 859408 # number of Writeback hits -system.l2c.Writeback_hits::total 859408 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 132 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 86 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 218 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 33 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 35 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 121498 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 74869 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 196367 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 631150 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 554787 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 452366 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 484851 # number of demand (read+write) hits -system.l2c.demand_hits::total 2123154 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 631150 # number of overall hits -system.l2c.overall_hits::cpu0.data 554787 # number of overall hits -system.l2c.overall_hits::cpu1.inst 452366 # number of overall hits -system.l2c.overall_hits::cpu1.data 484851 # number of overall hits -system.l2c.overall_hits::total 2123154 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 12329 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 272557 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3043 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1706 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289635 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2549 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 508 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3057 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 48 # number of SCUpgradeReq misses +system.l2c.occ_blocks::writebacks 53692.952391 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4245.749457 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 5529.153379 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 1310.829137 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 551.764862 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.819289 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.064785 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.084368 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.020002 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.008419 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996864 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 779502 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 594261 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 294591 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 226328 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1894682 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 840085 # number of Writeback hits +system.l2c.Writeback_hits::total 840085 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 143 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 80 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 223 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 34 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 29 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 63 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 147131 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 42889 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 190020 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 779502 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 741392 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 294591 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 269217 # number of demand (read+write) hits +system.l2c.demand_hits::total 2084702 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 779502 # number of overall hits +system.l2c.overall_hits::cpu0.data 741392 # number of overall hits +system.l2c.overall_hits::cpu1.inst 294591 # number of overall hits +system.l2c.overall_hits::cpu1.data 269217 # number of overall hits +system.l2c.overall_hits::total 2084702 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 11921 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 272257 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 3421 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1751 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289350 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2525 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 517 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3042 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 47 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 90 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 138 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 103909 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15834 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 119743 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 12329 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 376466 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3043 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 17540 # number of demand (read+write) misses -system.l2c.demand_misses::total 409378 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 12329 # number of overall misses -system.l2c.overall_misses::cpu0.data 376466 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3043 # number of overall misses -system.l2c.overall_misses::cpu1.data 17540 # number of overall misses -system.l2c.overall_misses::total 409378 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 738936500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 11707644000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 199188500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 90303499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 12736072499 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 388500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 888500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1277000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 198500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 114000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 312500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7293917000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1622405000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 8916322000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 738936500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 19001561000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 199188500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1712708499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21652394499 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 738936500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 19001561000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 199188500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1712708499 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21652394499 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 643479 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 705846 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 455409 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 411688 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2216422 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 859408 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 859408 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2681 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 594 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3275 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_misses::total 137 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 107281 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 13452 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 120733 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 11921 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 379538 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3421 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 15203 # number of demand (read+write) misses +system.l2c.demand_misses::total 410083 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11921 # number of overall misses +system.l2c.overall_misses::cpu0.data 379538 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3421 # number of overall misses +system.l2c.overall_misses::cpu1.data 15203 # number of overall misses +system.l2c.overall_misses::total 410083 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 712478500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 11719521500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 222220000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 113744499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 12767964499 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 468000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 936000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1404000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 313000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 113500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 426500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 7724029500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1451007500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9175037000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 712478500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 19443551000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 222220000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1564751999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21943001499 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 712478500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 19443551000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 222220000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1564751999 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21943001499 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 791423 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 866518 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 298012 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 228079 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2184032 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 840085 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 840085 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2668 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 597 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3265 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 81 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 125 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 206 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 225407 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 90703 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 316110 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 643479 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 931253 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 455409 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 502391 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2532532 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 643479 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 931253 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 455409 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 502391 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2532532 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.019160 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.386142 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.006682 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.004144 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.130677 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.950765 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.855219 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.933435 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.592593 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.720000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.669903 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.460984 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.174570 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.378802 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.019160 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.404257 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.006682 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.034913 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.161648 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.019160 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.404257 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.006682 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.034913 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.161648 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 59934.828453 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 42954.846142 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 65457.936247 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52932.883353 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 43972.836498 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 152.412711 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1749.015748 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 417.729800 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4135.416667 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1266.666667 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2264.492754 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70195.238141 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102463.369963 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 74462.156452 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 59934.828453 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 50473.511552 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 65457.936247 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 97645.866534 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52890.957743 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 59934.828453 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 50473.511552 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 65457.936247 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 97645.866534 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52890.957743 # average overall miss latency +system.l2c.SCUpgradeReq_accesses::cpu1.data 119 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 200 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 254412 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 56341 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 310753 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 791423 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1120930 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 298012 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 284420 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2494785 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 791423 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1120930 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 298012 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 284420 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2494785 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015063 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.314197 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.011479 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.007677 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.132484 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.946402 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.865997 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.931700 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.580247 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.756303 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.685000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.421682 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.238760 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.388518 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015063 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.338592 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.011479 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.053453 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.164376 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015063 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.338592 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.011479 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.053453 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.164376 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 59766.672259 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 43045.804148 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 64957.614733 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 64959.736722 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 44126.367717 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 185.346535 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1810.444874 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 461.538462 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6659.574468 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1261.111111 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3113.138686 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71998.112434 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 107865.559025 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 75994.442282 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 59766.672259 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 51229.523789 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 64957.614733 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 102923.896534 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53508.683606 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 59766.672259 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 51229.523789 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 64957.614733 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 102923.896534 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53508.683606 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,122 +379,125 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 79759 # number of writebacks -system.l2c.writebacks::total 79759 # number of writebacks +system.l2c.writebacks::writebacks 80445 # number of writebacks +system.l2c.writebacks::total 80445 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 12328 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 272557 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 3026 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1706 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 289617 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2549 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 508 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3057 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 48 # number of SCUpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 11920 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 272257 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 3405 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1750 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 289332 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2525 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 517 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3042 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 47 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 90 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 138 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 103909 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 15834 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 119743 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 12328 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 376466 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 3026 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 17540 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 409360 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 12328 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 376466 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 3026 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 17540 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 409360 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 583232769 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8178123323 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 160268481 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 113657266 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 9035281839 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25542512 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5088001 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 30630513 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 501546 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 901090 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 1402636 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6022075568 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1425456611 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7447532179 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 583232769 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 14200198891 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 160268481 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1539113877 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16482814018 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 583232769 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 14200198891 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 160268481 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1539113877 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16482814018 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 936128000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 454553000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1390681000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1589336500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 869577500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2458914000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2525464500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1324130500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 3849595000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.019158 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.386142 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.006645 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.004144 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.130669 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.950765 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.855219 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.933435 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.592593 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.720000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.669903 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.460984 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.174570 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.378802 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.019158 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.404257 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006645 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.034913 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.161641 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.019158 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.404257 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006645 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.034913 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.161641 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 47309.601639 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30005.185422 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 52963.807336 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66622.078546 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 31197.346285 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10020.601020 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.750000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.794897 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10448.875000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10012.111111 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10164.028986 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57955.283642 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 90025.048061 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 62195.971197 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 47309.601639 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37719.738014 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 52963.807336 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 87748.795724 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40264.837840 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 47309.601639 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37719.738014 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52963.807336 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 87748.795724 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40264.837840 # average overall mshr miss latency +system.l2c.SCUpgradeReq_mshr_misses::total 137 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 107281 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 13452 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 120733 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 11920 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 379538 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 3405 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 15202 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 410065 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 11920 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 379538 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 3405 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 15202 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 410065 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 561911095 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8192955588 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 178565558 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 113324293 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 9046756534 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25301493 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5294512 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 30596005 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 516543 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 904088 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 1420631 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6410159669 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1283732505 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7693892174 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 561911095 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 14603115257 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 178565558 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1397056798 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16740648708 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 561911095 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 14603115257 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 178565558 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1397056798 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16740648708 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 936053000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 455620500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1391673500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1587348000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 874199500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2461547500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2523401000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1329820000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3853221000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015061 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.314197 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011426 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.007673 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.132476 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.946402 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.865997 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.931700 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.580247 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.756303 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.685000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.421682 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.238760 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.388518 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015061 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.338592 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011426 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.053449 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.164369 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015061 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.338592 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011426 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.053449 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.164369 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 47140.192534 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30092.727048 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 52442.160940 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64756.738857 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 31267.735798 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10020.393267 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10240.835590 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10057.858317 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10990.276596 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10045.422222 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10369.569343 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59751.117803 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 95430.605486 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63726.505380 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 47140.192534 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38476.029428 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 52442.160940 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 91899.539403 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40824.378350 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 47140.192534 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38476.029428 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52442.160940 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 91899.539403 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40824.378350 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -505,39 +508,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41699 # number of replacements -system.iocache.tagsinuse 0.478350 # Cycle average of tags in use +system.iocache.replacements 41695 # number of replacements +system.iocache.tagsinuse 0.486173 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41715 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1705464300000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.478350 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.029897 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.029897 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses -system.iocache.ReadReq_misses::total 176 # number of ReadReq misses +system.iocache.warmup_cycle 1705465376000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.486173 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.030386 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.030386 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 172 # number of ReadReq misses +system.iocache.ReadReq_misses::total 172 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses -system.iocache.demand_misses::total 41728 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses -system.iocache.overall_misses::total 41728 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9523967806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9523967806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9545236804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9545236804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9545236804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9545236804 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41724 # number of demand (read+write) misses +system.iocache.demand_misses::total 41724 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41724 # number of overall misses +system.iocache.overall_misses::total 41724 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 20816998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 20816998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 9540304806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9540304806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9561121804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9561121804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9561121804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9561121804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 172 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 172 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41724 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41724 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41724 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41724 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -546,40 +549,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 229206.002262 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 229206.002262 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 228748.964820 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228748.964820 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 228748.964820 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228748.964820 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 193065 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121029.058140 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 121029.058140 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 229599.172266 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 229599.172266 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 229151.610680 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 229151.610680 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 229151.610680 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 229151.610680 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 192730 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23193 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23021 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.324279 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.371921 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41523 # number of writebacks system.iocache.writebacks::total 41523 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 172 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12116000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7361197521 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7361197521 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7373313521 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7373313521 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7373313521 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7373313521 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41724 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41724 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41724 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41724 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11872000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11872000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7377518046 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7377518046 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 7389390046 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7389390046 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 7389390046 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7389390046 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -588,14 +591,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 177156.274572 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 177156.274572 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176699.422953 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176699.422953 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176699.422953 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176699.422953 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69023.255814 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 69023.255814 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 177549.048084 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 177549.048084 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 177101.669207 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 177101.669207 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 177101.669207 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 177101.669207 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -613,22 +616,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7007258 # DTB read hits -system.cpu0.dtb.read_misses 29214 # DTB read misses -system.cpu0.dtb.read_acv 555 # DTB read access violations -system.cpu0.dtb.read_accesses 627494 # DTB read accesses -system.cpu0.dtb.write_hits 4619142 # DTB write hits -system.cpu0.dtb.write_misses 6985 # DTB write misses -system.cpu0.dtb.write_acv 345 # DTB write access violations -system.cpu0.dtb.write_accesses 208744 # DTB write accesses -system.cpu0.dtb.data_hits 11626400 # DTB hits -system.cpu0.dtb.data_misses 36199 # DTB misses -system.cpu0.dtb.data_acv 900 # DTB access violations -system.cpu0.dtb.data_accesses 836238 # DTB accesses -system.cpu0.itb.fetch_hits 888386 # ITB hits -system.cpu0.itb.fetch_misses 27286 # ITB misses -system.cpu0.itb.fetch_acv 998 # ITB acv -system.cpu0.itb.fetch_accesses 915672 # ITB accesses +system.cpu0.dtb.read_hits 7996955 # DTB read hits +system.cpu0.dtb.read_misses 29938 # DTB read misses +system.cpu0.dtb.read_acv 553 # DTB read access violations +system.cpu0.dtb.read_accesses 624438 # DTB read accesses +system.cpu0.dtb.write_hits 5309744 # DTB write hits +system.cpu0.dtb.write_misses 7955 # DTB write misses +system.cpu0.dtb.write_acv 319 # DTB write access violations +system.cpu0.dtb.write_accesses 207916 # DTB write accesses +system.cpu0.dtb.data_hits 13306699 # DTB hits +system.cpu0.dtb.data_misses 37893 # DTB misses +system.cpu0.dtb.data_acv 872 # DTB access violations +system.cpu0.dtb.data_accesses 832354 # DTB accesses +system.cpu0.itb.fetch_hits 944692 # ITB hits +system.cpu0.itb.fetch_misses 28693 # ITB misses +system.cpu0.itb.fetch_acv 988 # ITB acv +system.cpu0.itb.fetch_accesses 973385 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -641,277 +644,277 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 83155415 # number of cpu cycles simulated +system.cpu0.numCycles 92901317 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 9804849 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 8272695 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 286303 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 6905955 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 4307856 # Number of BTB hits +system.cpu0.BPredUnit.lookups 11220993 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 9498823 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 301088 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 7731310 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 4807164 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 619842 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 27789 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 19011041 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 50915714 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 9804849 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4927698 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 9659436 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1473505 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 28455218 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 29555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 194299 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 211367 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 143 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6349535 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 190370 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 58504859 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.870282 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.201063 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 696053 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 31347 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 22682478 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 57580156 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 11220993 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5503217 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10836671 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1573403 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 32658351 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 28974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 198560 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 186652 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 190 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6976582 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 207142 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 67595352 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.851836 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.189286 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 48845423 83.49% 83.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 638375 1.09% 84.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1232766 2.11% 86.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 545499 0.93% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2228588 3.81% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 432839 0.74% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 448017 0.77% 92.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 658155 1.12% 94.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3475197 5.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 56758681 83.97% 83.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 707820 1.05% 85.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1385949 2.05% 87.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 615643 0.91% 87.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2401218 3.55% 91.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 457628 0.68% 92.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 501258 0.74% 92.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 784291 1.16% 94.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3982864 5.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 58504859 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.117910 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.612296 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 20221803 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 27858596 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8736076 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 771700 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 916683 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 397847 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 27467 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 49800366 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 84499 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 916683 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 21025049 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 10730618 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14396247 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8233599 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3202661 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 46975607 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6729 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 282251 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1314603 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 31610949 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 57450568 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 57189305 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 261263 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 27436892 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4174049 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1166690 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 177857 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8656888 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7389019 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 4877617 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 925746 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 640404 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 41641305 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1430691 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 40525941 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 100515 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 4996937 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2778091 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 970759 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 58504859 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.692694 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.328093 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 67595352 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.120784 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.619799 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 23783356 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 32156359 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9819480 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 864593 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 971563 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 447466 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 32236 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56434658 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 99123 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 971563 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 24717335 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12372612 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 16597679 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9220139 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3716022 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53261468 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6752 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 462341 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1402867 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 35633564 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 64862965 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 64519168 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 343797 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31292257 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4341299 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1345733 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 201778 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10181749 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8375667 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5571987 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1008121 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 649590 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 47223004 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1661663 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 46145441 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 96356 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5312296 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2839377 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1124463 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 67595352 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.682672 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.326673 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 40198625 68.71% 68.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 8496961 14.52% 83.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3824833 6.54% 89.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2421122 4.14% 93.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1801555 3.08% 96.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 974491 1.67% 98.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 509636 0.87% 99.53% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 241631 0.41% 99.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 36005 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 46917740 69.41% 69.41% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9524699 14.09% 83.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4257234 6.30% 89.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2757377 4.08% 93.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2128651 3.15% 97.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1105682 1.64% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 579516 0.86% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 281591 0.42% 99.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 42862 0.06% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 58504859 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 67595352 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 54985 10.35% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 255079 48.00% 58.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 221355 41.65% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 67879 11.08% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.08% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 286167 46.73% 57.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 258352 42.19% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 27833265 68.68% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 41848 0.10% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 13219 0.03% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.83% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 7301690 18.02% 86.85% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 4678009 11.54% 98.39% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 652246 1.61% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3762 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 31627354 68.54% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48263 0.10% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 14877 0.03% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8323640 18.04% 86.73% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5371898 11.64% 98.37% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 753768 1.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 40525941 # Type of FU issued -system.cpu0.iq.rate 0.487352 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 531419 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013113 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 139814106 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 47896052 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 39650626 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 374568 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 182665 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 177037 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 40857986 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 195589 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 455505 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 46145441 # Type of FU issued +system.cpu0.iq.rate 0.496715 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 612398 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013271 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 160102230 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 53968976 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 45199549 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 492757 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 238910 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 232575 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 46496253 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 257824 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 502915 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1004949 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2086 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 10010 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 405892 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1032397 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2215 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 11166 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 416538 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 11959 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 139790 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 13927 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 141497 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 916683 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7413565 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 614240 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 45518060 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 556785 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7389019 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 4877617 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1263664 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 539342 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5760 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 10010 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149941 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 281478 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 431419 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 40181745 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 7054742 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 344195 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 971563 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8614462 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 715502 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 51740003 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 598208 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8375667 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5571987 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1467274 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 578076 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5429 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 11166 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 147373 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 320873 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 468246 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 45797277 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8048095 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 348163 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 2446064 # number of nop insts executed -system.cpu0.iew.exec_refs 11690884 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6330042 # Number of branches executed -system.cpu0.iew.exec_stores 4636142 # Number of stores executed -system.cpu0.iew.exec_rate 0.483213 # Inst execution rate -system.cpu0.iew.wb_sent 39909560 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 39827663 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 19855593 # num instructions producing a value -system.cpu0.iew.wb_consumers 26361633 # num instructions consuming a value +system.cpu0.iew.exec_nop 2855336 # number of nop insts executed +system.cpu0.iew.exec_refs 13377753 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7249094 # Number of branches executed +system.cpu0.iew.exec_stores 5329658 # Number of stores executed +system.cpu0.iew.exec_rate 0.492967 # Inst execution rate +system.cpu0.iew.wb_sent 45516467 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 45432124 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22555336 # num instructions producing a value +system.cpu0.iew.wb_consumers 30242853 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.478955 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.753200 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.489036 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.745807 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 5375485 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 459932 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 404147 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 57588176 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.695477 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.605159 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5732411 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 537200 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 438547 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 66623789 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.689159 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.608194 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 42371011 73.58% 73.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6488229 11.27% 84.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3374360 5.86% 90.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1907115 3.31% 94.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1044719 1.81% 95.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 416558 0.72% 96.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 355194 0.62% 97.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 347785 0.60% 97.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1283205 2.23% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 49353923 74.08% 74.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7278183 10.92% 85.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3860099 5.79% 90.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2143933 3.22% 94.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1188584 1.78% 95.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 481737 0.72% 96.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 414393 0.62% 97.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 388678 0.58% 97.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1514259 2.27% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 57588176 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 40051259 # Number of instructions committed -system.cpu0.commit.committedOps 40051259 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 66623789 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 45914377 # Number of instructions committed +system.cpu0.commit.committedOps 45914377 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 10855795 # Number of memory references committed -system.cpu0.commit.loads 6384070 # Number of loads committed -system.cpu0.commit.membars 151085 # Number of memory barriers committed -system.cpu0.commit.branches 6007416 # Number of branches committed -system.cpu0.commit.fp_insts 174841 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 37190024 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489523 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1283205 # number cycles where commit BW limit reached +system.cpu0.commit.refs 12498719 # Number of memory references committed +system.cpu0.commit.loads 7343270 # Number of loads committed +system.cpu0.commit.membars 179286 # Number of memory barriers committed +system.cpu0.commit.branches 6902899 # Number of branches committed +system.cpu0.commit.fp_insts 230540 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 42546523 # Number of committed integer instructions. +system.cpu0.commit.function_calls 573621 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1514259 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 101537476 # The number of ROB reads -system.cpu0.rob.rob_writes 91770556 # The number of ROB writes -system.cpu0.timesIdled 793139 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 24650556 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3710654942 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 37835874 # Number of Instructions Simulated -system.cpu0.committedOps 37835874 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 37835874 # Number of Instructions Simulated -system.cpu0.cpi 2.197793 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.197793 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.455002 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.455002 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 52969279 # number of integer regfile reads -system.cpu0.int_regfile_writes 28937240 # number of integer regfile writes -system.cpu0.fp_regfile_reads 87038 # number of floating regfile reads -system.cpu0.fp_regfile_writes 87248 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1306578 # number of misc regfile reads -system.cpu0.misc_regfile_writes 663412 # number of misc regfile writes +system.cpu0.rob.rob_reads 116563585 # The number of ROB reads +system.cpu0.rob.rob_writes 104266102 # The number of ROB writes +system.cpu0.timesIdled 937015 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25305965 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3702808960 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 43304295 # Number of Instructions Simulated +system.cpu0.committedOps 43304295 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 43304295 # Number of Instructions Simulated +system.cpu0.cpi 2.145314 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.145314 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.466132 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.466132 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 60234005 # number of integer regfile reads +system.cpu0.int_regfile_writes 32862786 # number of integer regfile writes +system.cpu0.fp_regfile_reads 114240 # number of floating regfile reads +system.cpu0.fp_regfile_writes 115409 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1561000 # number of misc regfile reads +system.cpu0.misc_regfile_writes 765601 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -943,245 +946,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 642913 # number of replacements -system.cpu0.icache.tagsinuse 510.325206 # Cycle average of tags in use -system.cpu0.icache.total_refs 5670885 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 643421 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.813646 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 20341529000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.325206 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996729 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996729 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5670885 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5670885 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5670885 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5670885 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5670885 # number of overall hits -system.cpu0.icache.overall_hits::total 5670885 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 678650 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 678650 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 678650 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 678650 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 678650 # number of overall misses -system.cpu0.icache.overall_misses::total 678650 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9582412994 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9582412994 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9582412994 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9582412994 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9582412994 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9582412994 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6349535 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6349535 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6349535 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6349535 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6349535 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6349535 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.106882 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.106882 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.106882 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.106882 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.106882 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.106882 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14119.815802 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14119.815802 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14119.815802 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14119.815802 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14119.815802 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14119.815802 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2234 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 145 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.406897 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.replacements 790851 # number of replacements +system.cpu0.icache.tagsinuse 510.328171 # Cycle average of tags in use +system.cpu0.icache.total_refs 6144778 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 791359 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.764843 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 20315369000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.328171 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996735 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996735 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6144778 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6144778 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6144778 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6144778 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6144778 # number of overall hits +system.cpu0.icache.overall_hits::total 6144778 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 831804 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 831804 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 831804 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 831804 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 831804 # number of overall misses +system.cpu0.icache.overall_misses::total 831804 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11563264492 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11563264492 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11563264492 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11563264492 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11563264492 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11563264492 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6976582 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6976582 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6976582 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6976582 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6976582 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6976582 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119228 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.119228 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119228 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.119228 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119228 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.119228 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13901.429293 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13901.429293 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13901.429293 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13901.429293 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13901.429293 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13901.429293 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2068 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1976 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 129 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.031008 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 988 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 35068 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 35068 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 35068 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 35068 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 35068 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 35068 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 643582 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 643582 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 643582 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 643582 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 643582 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 643582 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7877266496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 7877266496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7877266496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 7877266496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7877266496 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 7877266496 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.101359 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.101359 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.101359 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.101359 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.101359 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.101359 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12239.724691 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12239.724691 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12239.724691 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12239.724691 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12239.724691 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12239.724691 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40285 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 40285 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 40285 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 40285 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 40285 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 40285 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 791519 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 791519 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 791519 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 791519 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 791519 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 791519 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9521125993 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9521125993 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9521125993 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9521125993 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9521125993 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9521125993 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113454 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.113454 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.113454 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12028.929177 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12028.929177 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12028.929177 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 932591 # number of replacements -system.cpu0.dcache.tagsinuse 478.331784 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8251917 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 933103 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.843522 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 21811000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 478.331784 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.934242 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.934242 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5164945 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5164945 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 2787881 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 2787881 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 136688 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 136688 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 157014 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 157014 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7952826 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 7952826 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7952826 # number of overall hits -system.cpu0.dcache.overall_hits::total 7952826 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1127907 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1127907 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1514074 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1514074 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12708 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 12708 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 640 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 640 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2641981 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2641981 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2641981 # number of overall misses -system.cpu0.dcache.overall_misses::total 2641981 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26996447000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 26996447000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62901501244 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 62901501244 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 187201000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 187201000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3956000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3956000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 89897948244 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 89897948244 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 89897948244 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 89897948244 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6292852 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6292852 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4301955 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4301955 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 149396 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 149396 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157654 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157654 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10594807 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10594807 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10594807 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10594807 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.179236 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.179236 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.351950 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.351950 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085063 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085063 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004060 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004060 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249366 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.249366 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249366 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.249366 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23934.993754 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 23934.993754 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41544.535633 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41544.535633 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14730.956878 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14730.956878 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6181.250000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6181.250000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34026.720194 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34026.720194 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34026.720194 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34026.720194 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2213633 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2219 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 43644 # number of cycles access was blocked +system.cpu0.dcache.replacements 1122816 # number of replacements +system.cpu0.dcache.tagsinuse 467.302243 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9451134 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1123328 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.413512 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 21802000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 467.302243 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.912700 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.912700 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5816576 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5816576 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3291002 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3291002 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156681 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 156681 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 180603 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 180603 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9107578 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9107578 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9107578 # number of overall hits +system.cpu0.dcache.overall_hits::total 9107578 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1395487 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1395487 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1670757 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1670757 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 17192 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 17192 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 672 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 672 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3066244 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3066244 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3066244 # number of overall misses +system.cpu0.dcache.overall_misses::total 3066244 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31388896500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 31388896500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67591366614 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 67591366614 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 251807000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 251807000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4105000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4105000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 98980263114 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 98980263114 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 98980263114 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 98980263114 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7212063 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7212063 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4961759 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4961759 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 173873 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 173873 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 181275 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 181275 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12173822 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12173822 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12173822 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12173822 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.193493 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.193493 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.336727 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.336727 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.098877 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.098877 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003707 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003707 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.251872 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.251872 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251872 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.251872 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22493.148628 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 22493.148628 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.533997 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.533997 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.754304 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.754304 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6108.630952 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6108.630952 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.621866 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32280.621866 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32280.621866 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32280.621866 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2359081 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 46623 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 50.720214 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 317 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 50.599082 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 131.285714 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 453711 # number of writebacks -system.cpu0.dcache.writebacks::total 453711 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 427154 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 427154 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1285155 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1285155 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3146 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3146 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1712309 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1712309 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1712309 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1712309 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 700753 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 700753 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 228919 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 228919 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9562 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9562 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 640 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 640 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 929672 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 929672 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 929672 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 929672 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 17299108000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 17299108000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9077949457 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9077949457 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117930500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117930500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2676000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2676000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26377057457 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 26377057457 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26377057457 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 26377057457 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 998607000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 998607000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1686748998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1686748998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2685355998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2685355998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.111357 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.111357 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.053213 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.053213 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064004 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064004 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004060 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004060 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.087748 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.087748 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.087748 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.087748 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24686.455855 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24686.455855 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39655.727384 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39655.727384 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12333.246183 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12333.246183 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4181.250000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4181.250000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28372.433995 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28372.433995 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28372.433995 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28372.433995 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 614637 # number of writebacks +system.cpu0.dcache.writebacks::total 614637 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 536909 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 536909 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1412908 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1412908 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3986 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3986 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1949817 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1949817 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1949817 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1949817 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 858578 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 858578 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257849 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 257849 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13206 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13206 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 672 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 672 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1116427 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1116427 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1116427 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1116427 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19432503500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19432503500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9843225287 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9843225287 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 161840000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 161840000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2761000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2761000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29275728787 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 29275728787 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29275728787 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 29275728787 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 998479000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 998479000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1684532498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1684532498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2683011498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2683011498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.119047 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.119047 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051967 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051967 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075952 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075952 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003707 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003707 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091707 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.091707 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091707 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.091707 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22633.358297 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22633.358297 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.378365 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.378365 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12255.035590 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12255.035590 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4108.630952 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4108.630952 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.698651 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.698651 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1193,22 +1196,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 3713266 # DTB read hits -system.cpu1.dtb.read_misses 14359 # DTB read misses -system.cpu1.dtb.read_acv 33 # DTB read access violations -system.cpu1.dtb.read_accesses 328215 # DTB read accesses -system.cpu1.dtb.write_hits 2351870 # DTB write hits -system.cpu1.dtb.write_misses 2326 # DTB write misses -system.cpu1.dtb.write_acv 62 # DTB write access violations -system.cpu1.dtb.write_accesses 130566 # DTB write accesses -system.cpu1.dtb.data_hits 6065136 # DTB hits -system.cpu1.dtb.data_misses 16685 # DTB misses -system.cpu1.dtb.data_acv 95 # DTB access violations -system.cpu1.dtb.data_accesses 458781 # DTB accesses -system.cpu1.itb.fetch_hits 552396 # ITB hits -system.cpu1.itb.fetch_misses 7861 # ITB misses -system.cpu1.itb.fetch_acv 226 # ITB acv -system.cpu1.itb.fetch_accesses 560257 # ITB accesses +system.cpu1.dtb.read_hits 2657978 # DTB read hits +system.cpu1.dtb.read_misses 12789 # DTB read misses +system.cpu1.dtb.read_acv 27 # DTB read access violations +system.cpu1.dtb.read_accesses 325192 # DTB read accesses +system.cpu1.dtb.write_hits 1642917 # DTB write hits +system.cpu1.dtb.write_misses 2443 # DTB write misses +system.cpu1.dtb.write_acv 63 # DTB write access violations +system.cpu1.dtb.write_accesses 132832 # DTB write accesses +system.cpu1.dtb.data_hits 4300895 # DTB hits +system.cpu1.dtb.data_misses 15232 # DTB misses +system.cpu1.dtb.data_acv 90 # DTB access violations +system.cpu1.dtb.data_accesses 458024 # DTB accesses +system.cpu1.itb.fetch_hits 468004 # ITB hits +system.cpu1.itb.fetch_misses 6860 # ITB misses +system.cpu1.itb.fetch_acv 223 # ITB acv +system.cpu1.itb.fetch_accesses 474864 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1221,516 +1224,516 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 34615367 # number of cpu cycles simulated +system.cpu1.numCycles 24425153 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 5312293 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 4360790 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 184753 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 3627578 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 1933378 # Number of BTB hits +system.cpu1.BPredUnit.lookups 3729082 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 3054181 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 119454 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 2320080 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 1316503 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 383381 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 19114 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 12153279 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 25592027 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 5312293 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 2316759 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 4666723 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 848042 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 13957627 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 25440 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65073 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 147747 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 2992364 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 115997 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 31571084 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.810616 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.170872 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 271618 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 12328 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 8114039 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 17895154 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3729082 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1588121 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 3257696 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 589472 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 9888413 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24413 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65338 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 153630 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 457 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 2125846 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 78174 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 21892478 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.817411 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.179159 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 26904361 85.22% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 276998 0.88% 86.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 593564 1.88% 87.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 353090 1.12% 89.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 710175 2.25% 91.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 234476 0.74% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 277213 0.88% 92.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 377383 1.20% 94.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1843824 5.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 18634782 85.12% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 188286 0.86% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 405463 1.85% 87.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 257415 1.18% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 494265 2.26% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 174627 0.80% 92.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 196879 0.90% 92.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 233860 1.07% 94.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1306901 5.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 31571084 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.153466 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.739326 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 12173556 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 14265063 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 4322746 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 271541 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 538177 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 245868 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 17179 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 25069869 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 51217 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 538177 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 12622413 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 4307697 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 8552551 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 4022106 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1528138 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 23469307 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 521 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 403073 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 318746 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 15460907 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 27951432 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 27722595 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 228837 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 13017644 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2443263 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 711049 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 79879 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 4546986 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 3946391 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 2480141 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 398992 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 247125 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 20556503 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 873226 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 19920635 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 45889 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 3011838 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1481780 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 622079 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 31571084 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.630977 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.308978 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 21892478 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.152674 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.732653 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8206589 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 10101487 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 3024410 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 183126 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 376865 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 172901 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 11788 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 17533822 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 34638 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 376865 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 8509917 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2827279 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6300793 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2835389 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1042233 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 16406077 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 208 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 240400 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 230284 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 10874639 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 19629758 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 19484069 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 145689 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 9164172 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1710467 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 526024 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 52355 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 3079996 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2820928 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1739172 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 303279 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 178063 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 14428831 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 617828 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 13962547 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 36109 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2150385 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1081456 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 443630 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 21892478 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.637778 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.318020 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 22947759 72.69% 72.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 3816292 12.09% 84.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1671768 5.30% 90.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 1218822 3.86% 93.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 1072376 3.40% 97.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 425454 1.35% 98.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 262904 0.83% 99.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 135529 0.43% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 20180 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 15854245 72.42% 72.42% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2672796 12.21% 84.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1184242 5.41% 90.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 847687 3.87% 93.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 726248 3.32% 97.23% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 300582 1.37% 98.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 191038 0.87% 99.47% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 101044 0.46% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 14596 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 31571084 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 21892478 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28274 8.56% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 166109 50.30% 58.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 135868 41.14% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 17685 7.13% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 130361 52.59% 59.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 99827 40.27% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 13189448 66.21% 66.23% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 28632 0.14% 66.37% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.37% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 12556 0.06% 66.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 3884810 19.50% 85.94% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 2385812 11.98% 97.92% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 414088 2.08% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3526 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 9165178 65.64% 65.67% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 22201 0.16% 65.83% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10896 0.08% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2775695 19.88% 85.80% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1670228 11.96% 97.76% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 313060 2.24% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 19920635 # Type of FU issued -system.cpu1.iq.rate 0.575485 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 330251 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.016578 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 71458593 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 24286363 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 19388343 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 329901 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 159417 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 155652 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 20074577 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 172783 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 184439 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 13962547 # Type of FU issued +system.cpu1.iq.rate 0.571646 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 247873 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.017753 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 49890568 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 17097827 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 13608739 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 210986 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 102380 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 99816 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 14096605 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 110289 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 133191 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 581301 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1183 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4340 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 230089 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 414475 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 850 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 3253 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 172072 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 6918 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 18073 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 4939 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 13663 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 538177 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 3253999 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 229517 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 22699099 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 268114 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 3946391 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 2480141 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 779721 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 89744 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2529 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4340 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 96593 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 181110 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 277703 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 19708494 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 3738657 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 212141 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 376865 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2193720 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 124101 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 15871795 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 185768 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2820928 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1739172 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 554609 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 45814 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2212 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 3253 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 57900 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 130435 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 188335 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 13825969 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2678414 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 136578 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 1269370 # number of nop insts executed -system.cpu1.iew.exec_refs 6100523 # number of memory reference insts executed -system.cpu1.iew.exec_branches 3128191 # Number of branches executed -system.cpu1.iew.exec_stores 2361866 # Number of stores executed -system.cpu1.iew.exec_rate 0.569357 # Inst execution rate -system.cpu1.iew.wb_sent 19587937 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 19543995 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 9462232 # num instructions producing a value -system.cpu1.iew.wb_consumers 13383566 # num instructions consuming a value +system.cpu1.iew.exec_nop 825136 # number of nop insts executed +system.cpu1.iew.exec_refs 4329493 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2168898 # Number of branches executed +system.cpu1.iew.exec_stores 1651079 # Number of stores executed +system.cpu1.iew.exec_rate 0.566055 # Inst execution rate +system.cpu1.iew.wb_sent 13745874 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 13708555 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 6651311 # num instructions producing a value +system.cpu1.iew.wb_consumers 9340604 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.564605 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.707004 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.561247 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.712086 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 3264810 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 251147 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 260251 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 31032907 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.624350 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.557822 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 2293261 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 174198 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 176022 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 21515613 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.628195 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.562431 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 23883562 76.96% 76.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2995086 9.65% 86.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1581522 5.10% 91.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 799862 2.58% 94.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 502768 1.62% 95.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 236983 0.76% 96.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 224339 0.72% 97.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 194617 0.63% 98.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 614168 1.98% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 16491806 76.65% 76.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2174989 10.11% 86.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1058158 4.92% 91.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 548223 2.55% 94.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 352308 1.64% 95.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 166690 0.77% 96.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 160522 0.75% 97.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 129128 0.60% 97.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 433789 2.02% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 31032907 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 19375400 # Number of instructions committed -system.cpu1.commit.committedOps 19375400 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 21515613 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 13515996 # Number of instructions committed +system.cpu1.commit.committedOps 13515996 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 5615142 # Number of memory references committed -system.cpu1.commit.loads 3365090 # Number of loads committed -system.cpu1.commit.membars 85627 # Number of memory barriers committed -system.cpu1.commit.branches 2912516 # Number of branches committed -system.cpu1.commit.fp_insts 154287 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 17850043 # Number of committed integer instructions. -system.cpu1.commit.function_calls 300496 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 614168 # number cycles where commit BW limit reached +system.cpu1.commit.refs 3973553 # Number of memory references committed +system.cpu1.commit.loads 2406453 # Number of loads committed +system.cpu1.commit.membars 57533 # Number of memory barriers committed +system.cpu1.commit.branches 2017672 # Number of branches committed +system.cpu1.commit.fp_insts 98521 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 12496541 # Number of committed integer instructions. +system.cpu1.commit.function_calls 216490 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 433789 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 52972716 # The number of ROB reads -system.cpu1.rob.rob_writes 45818344 # The number of ROB writes -system.cpu1.timesIdled 377037 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 3044283 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3758611040 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 18256718 # Number of Instructions Simulated -system.cpu1.committedOps 18256718 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 18256718 # Number of Instructions Simulated -system.cpu1.cpi 1.896034 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.896034 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.527417 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.527417 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 25482349 # number of integer regfile reads -system.cpu1.int_regfile_writes 13944369 # number of integer regfile writes -system.cpu1.fp_regfile_reads 81651 # number of floating regfile reads -system.cpu1.fp_regfile_writes 82372 # number of floating regfile writes -system.cpu1.misc_regfile_reads 840995 # number of misc regfile reads -system.cpu1.misc_regfile_writes 357443 # number of misc regfile writes -system.cpu1.icache.replacements 454861 # number of replacements -system.cpu1.icache.tagsinuse 506.121737 # Cycle average of tags in use -system.cpu1.icache.total_refs 2515591 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 455373 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.524243 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 42848278000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 506.121737 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.988519 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.988519 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 2515591 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 2515591 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 2515591 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 2515591 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 2515591 # number of overall hits -system.cpu1.icache.overall_hits::total 2515591 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 476773 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 476773 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 476773 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 476773 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 476773 # number of overall misses -system.cpu1.icache.overall_misses::total 476773 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6462749000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6462749000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6462749000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6462749000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6462749000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6462749000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 2992364 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 2992364 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 2992364 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 2992364 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 2992364 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 2992364 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.159330 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.159330 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.159330 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.159330 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.159330 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.159330 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13555.190835 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13555.190835 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13555.190835 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13555.190835 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13555.190835 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13555.190835 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 884 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 47 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.808511 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 36803153 # The number of ROB reads +system.cpu1.rob.rob_writes 31994561 # The number of ROB writes +system.cpu1.timesIdled 237566 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2532675 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3770663279 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 12791729 # Number of Instructions Simulated +system.cpu1.committedOps 12791729 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 12791729 # Number of Instructions Simulated +system.cpu1.cpi 1.909449 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.909449 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.523711 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.523711 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 17892474 # number of integer regfile reads +system.cpu1.int_regfile_writes 9829261 # number of integer regfile writes +system.cpu1.fp_regfile_reads 54188 # number of floating regfile reads +system.cpu1.fp_regfile_writes 54153 # number of floating regfile writes +system.cpu1.misc_regfile_reads 586782 # number of misc regfile reads +system.cpu1.misc_regfile_writes 255768 # number of misc regfile writes +system.cpu1.icache.replacements 297472 # number of replacements +system.cpu1.icache.tagsinuse 505.689996 # Cycle average of tags in use +system.cpu1.icache.total_refs 1814154 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 297984 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 6.088092 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 42534295000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 505.689996 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.987676 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.987676 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1814154 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1814154 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1814154 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1814154 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1814154 # number of overall hits +system.cpu1.icache.overall_hits::total 1814154 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 311692 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 311692 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 311692 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 311692 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 311692 # number of overall misses +system.cpu1.icache.overall_misses::total 311692 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4307826496 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4307826496 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4307826496 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4307826496 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4307826496 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4307826496 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 2125846 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2125846 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 2125846 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 2125846 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 2125846 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 2125846 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146620 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.146620 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146620 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.146620 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.146620 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.146620 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13820.779795 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13820.779795 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13820.779795 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13820.779795 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13820.779795 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13820.779795 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 806 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 423 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 43 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.744186 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 423 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 21323 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 21323 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 21323 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 21323 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 21323 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 21323 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 455450 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 455450 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 455450 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 455450 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 455450 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 455450 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5356907000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5356907000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5356907000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5356907000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5356907000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5356907000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.152204 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.152204 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.152204 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.152204 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.152204 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.152204 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11761.789439 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11761.789439 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11761.789439 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11761.789439 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11761.789439 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11761.789439 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 13650 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 13650 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 13650 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 13650 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 13650 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 13650 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 298042 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 298042 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 298042 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 298042 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 298042 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 298042 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3567181997 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3567181997 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3567181997 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3567181997 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3567181997 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3567181997 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.140199 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.140199 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.140199 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11968.722519 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11968.722519 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11968.722519 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 520860 # number of replacements -system.cpu1.dcache.tagsinuse 498.284346 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4488456 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 521257 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 8.610831 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 31290571500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 498.284346 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.973212 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.973212 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2711578 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2711578 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1652227 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1652227 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 59380 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 59380 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 66046 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 66046 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4363805 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4363805 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4363805 # number of overall hits -system.cpu1.dcache.overall_hits::total 4363805 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 735473 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 735473 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 523667 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 523667 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 12800 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 12800 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 689 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 689 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1259140 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1259140 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1259140 # number of overall misses -system.cpu1.dcache.overall_misses::total 1259140 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 11275775500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 11275775500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 16995132775 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 16995132775 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 186282500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 186282500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5003500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5003500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 28270908275 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 28270908275 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 28270908275 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 28270908275 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3447051 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3447051 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2175894 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2175894 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72180 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 72180 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 66735 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 66735 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 5622945 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 5622945 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 5622945 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 5622945 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.213363 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.213363 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.240668 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.240668 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177334 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177334 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.010324 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.010324 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.223929 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.223929 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.223929 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.223929 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15331.324875 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15331.324875 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32454.083941 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32454.083941 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14553.320312 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14553.320312 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7261.973875 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7261.973875 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22452.553548 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 22452.553548 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22452.553548 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 22452.553548 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 551348 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 10411 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 52.958217 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.replacements 296647 # number of replacements +system.cpu1.dcache.tagsinuse 497.527759 # Cycle average of tags in use +system.cpu1.dcache.total_refs 3293413 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 297044 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 11.087290 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 36352469000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 497.527759 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.971734 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.971734 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2035773 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2035773 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1175370 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1175370 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40064 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 40064 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 42523 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 42523 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3211143 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3211143 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3211143 # number of overall hits +system.cpu1.dcache.overall_hits::total 3211143 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 433262 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 433262 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 341345 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 341345 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7035 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 7035 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 719 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 719 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 774607 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 774607 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 774607 # number of overall misses +system.cpu1.dcache.overall_misses::total 774607 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6736451500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6736451500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13519924674 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 13519924674 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 102051000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 102051000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5076000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5076000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 20256376174 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 20256376174 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 20256376174 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 20256376174 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2469035 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2469035 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1516715 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1516715 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 47099 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 47099 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 43242 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 43242 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3985750 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3985750 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3985750 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3985750 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.175478 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.175478 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.225055 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.225055 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149366 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149366 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.016627 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.016627 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.194344 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.194344 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.194344 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.194344 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.216783 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.216783 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39607.800536 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39607.800536 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14506.183369 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14506.183369 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7059.805285 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7059.805285 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26150.520424 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 26150.520424 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26150.520424 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 26150.520424 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 473544 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 3 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 7013 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 67.523742 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 3 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 405697 # number of writebacks -system.cpu1.dcache.writebacks::total 405697 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 310580 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 310580 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 431476 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 431476 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 2432 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 2432 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 742056 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 742056 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 742056 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 742056 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 424893 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 424893 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92191 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 92191 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 10368 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 10368 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 689 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 689 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 517084 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 517084 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 517084 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 517084 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5584148500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5584148500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2607634127 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2607634127 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 126008000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 126008000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3625500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3625500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8191782627 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8191782627 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8191782627 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8191782627 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 485715000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 485715000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 920480500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 920480500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1406195500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1406195500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.123263 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.123263 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.042369 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.042369 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.143641 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.143641 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.010324 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.010324 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.091960 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.091960 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.091960 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.091960 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13142.481754 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13142.481754 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28285.126824 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28285.126824 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12153.549383 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12153.549383 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5261.973875 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5261.973875 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15842.266686 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15842.266686 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15842.266686 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15842.266686 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 225448 # number of writebacks +system.cpu1.dcache.writebacks::total 225448 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 193837 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 193837 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 283225 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 283225 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1368 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1368 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 477062 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 477062 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 477062 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 477062 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 239425 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 239425 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58120 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 58120 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5667 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5667 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 718 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 718 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 297545 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 297545 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 297545 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 297545 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3123298500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3123298500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2029112304 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2029112304 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67015000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67015000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3640000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3640000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5152410804 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5152410804 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5152410804 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5152410804 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 486888000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 486888000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 925465000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 925465000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1412353000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1412353000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.096971 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.096971 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038320 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038320 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120321 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120321 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.016604 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.016604 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.074652 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.074652 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.997390 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.997390 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34912.462216 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34912.462216 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11825.480854 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11825.480854 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5069.637883 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5069.637883 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.408624 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.408624 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1739,170 +1742,170 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4859 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 144961 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 48033 39.13% 39.13% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 133 0.11% 39.24% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1924 1.57% 40.81% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 40.82% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 72639 59.18% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 122745 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 47372 48.94% 48.94% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 133 0.14% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1924 1.99% 51.06% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.02% 51.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 47357 48.92% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 96802 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1866486525500 98.40% 98.40% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63938000 0.00% 98.40% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 572947000 0.03% 98.43% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 8827500 0.00% 98.43% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 29774513500 1.57% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1896906751500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.986239 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4836 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 169372 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 58506 39.88% 39.88% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 135 0.09% 39.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.31% 41.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 41.29% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 86127 58.71% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 146709 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 57513 49.12% 49.12% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 135 0.12% 49.23% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.64% 50.88% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.01% 50.89% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 57499 49.11% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 117088 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1866028984500 98.32% 98.32% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63917500 0.00% 98.33% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 571228500 0.03% 98.36% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8802500 0.00% 98.36% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 31183758000 1.64% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1897856691000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983027 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.651950 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.788643 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed -system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed -system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed -system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 211 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.667607 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.798097 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.35% 3.35% # number of syscalls executed +system.cpu0.kern.syscall::3 17 8.13% 11.48% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.91% 13.40% # number of syscalls executed +system.cpu0.kern.syscall::6 29 13.88% 27.27% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.48% 27.75% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.31% 32.06% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.35% 35.41% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.91% 37.32% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.48% 37.80% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.44% 39.23% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.35% 42.58% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.96% 43.54% # number of syscalls executed +system.cpu0.kern.syscall::45 37 17.70% 61.24% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.44% 62.68% # number of syscalls executed +system.cpu0.kern.syscall::48 8 3.83% 66.51% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.31% 70.81% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.48% 71.29% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.39% 73.68% # number of syscalls executed +system.cpu0.kern.syscall::71 27 12.92% 86.60% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.44% 88.04% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.35% 91.39% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.48% 91.87% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.96% 92.82% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.35% 96.17% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.96% 97.13% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.96% 98.09% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.48% 98.56% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.48% 99.04% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.96% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 209 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 97 0.07% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2435 1.87% 1.95% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.04% 1.98% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.01% 1.99% # number of callpals executed -system.cpu0.kern.callpal::swpipl 116655 89.61% 91.60% # number of callpals executed -system.cpu0.kern.callpal::rdps 6417 4.93% 96.53% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.53% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.54% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.01% 96.54% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.54% # number of callpals executed -system.cpu0.kern.callpal::rti 4017 3.09% 99.63% # number of callpals executed -system.cpu0.kern.callpal::callsys 345 0.27% 99.89% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.11% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 130177 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5807 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1287 # number of protection mode switches +system.cpu0.kern.callpal::wripir 100 0.06% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3082 1.99% 2.06% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.09% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed +system.cpu0.kern.callpal::swpipl 140299 90.69% 92.78% # number of callpals executed +system.cpu0.kern.callpal::rdps 6336 4.10% 96.88% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.88% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.88% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.01% 96.89% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.89% # number of callpals executed +system.cpu0.kern.callpal::rti 4335 2.80% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 342 0.22% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 154704 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6439 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1272 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1286 -system.cpu0.kern.mode_good::user 1287 +system.cpu0.kern.mode_good::kernel 1271 +system.cpu0.kern.mode_good::user 1272 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.221457 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.197391 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.362701 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1894993254500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1913489000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.329789 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1895973773500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1882909500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2436 # number of times the context was actually changed +system.cpu0.kern.swap_context 3083 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3786 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 92502 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 33560 40.13% 40.13% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1921 2.30% 42.42% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 97 0.12% 42.54% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 48058 57.46% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 83636 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 32844 48.58% 48.58% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1921 2.84% 51.42% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 97 0.14% 51.56% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 32747 48.44% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 67609 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1867334401000 98.46% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533283000 0.03% 98.48% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 45472500 0.00% 98.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 28701925000 1.51% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1896615081500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978665 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3800 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 68195 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 23112 38.67% 38.67% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1924 3.22% 41.89% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 100 0.17% 42.06% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 34629 57.94% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 59765 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 22728 47.97% 47.97% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1924 4.06% 52.03% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 100 0.21% 52.24% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 22629 47.76% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 47381 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870052426500 98.55% 98.55% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533448500 0.03% 98.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 47034500 0.00% 98.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 26913191500 1.42% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1897546101000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.983385 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.681406 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.808372 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed -system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed -system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed -system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed -system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed -system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed -system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 115 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.653470 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.792788 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.85% 0.85% # number of syscalls executed +system.cpu1.kern.syscall::3 13 11.11% 11.97% # number of syscalls executed +system.cpu1.kern.syscall::6 13 11.11% 23.08% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.85% 23.93% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.13% 29.06% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.56% 31.62% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.71% 33.33% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.56% 35.90% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.56% 38.46% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.42% 41.88% # number of syscalls executed +system.cpu1.kern.syscall::45 17 14.53% 56.41% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.56% 58.97% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.71% 60.68% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.85% 61.54% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.71% 63.25% # number of syscalls executed +system.cpu1.kern.syscall::71 27 23.08% 86.32% # number of syscalls executed +system.cpu1.kern.syscall::74 9 7.69% 94.02% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.85% 94.87% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.71% 96.58% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.56% 99.15% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.85% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 117 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1813 2.11% 2.13% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.14% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.14% # number of callpals executed -system.cpu1.kern.callpal::swpipl 78432 91.18% 93.32% # number of callpals executed -system.cpu1.kern.callpal::rdps 2336 2.72% 96.04% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 96.04% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 96.04% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 96.04% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 96.05% # number of callpals executed -system.cpu1.kern.callpal::rti 3185 3.70% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 172 0.20% 99.95% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.05% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.03% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1165 1.89% 1.92% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 1.93% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 1.94% # number of callpals executed +system.cpu1.kern.callpal::swpipl 54867 89.09% 91.04% # number of callpals executed +system.cpu1.kern.callpal::rdps 2419 3.93% 94.96% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.96% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.97% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 94.97% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.98% # number of callpals executed +system.cpu1.kern.callpal::rti 2874 4.67% 99.64% # number of callpals executed +system.cpu1.kern.callpal::callsys 175 0.28% 99.93% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.07% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 86022 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2264 # number of protection mode switches -system.cpu1.kern.mode_switch::user 459 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 518 -system.cpu1.kern.mode_good::user 459 -system.cpu1.kern.mode_good::idle 59 -system.cpu1.kern.mode_switch_good::kernel 0.228799 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 61585 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1629 # number of protection mode switches +system.cpu1.kern.mode_switch::user 476 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 537 +system.cpu1.kern.mode_good::user 476 +system.cpu1.kern.mode_good::idle 61 +system.cpu1.kern.mode_switch_good::kernel 0.329650 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.028964 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.217647 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 42822911000 2.26% 2.26% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 817792500 0.04% 2.30% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1852963538500 97.70% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1814 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.029814 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.258733 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 37752222500 1.99% 1.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 817466500 0.04% 2.03% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1858966004500 97.97% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1166 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 353ee4820..4e3852a72 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -8,17 +8,18 @@ time_sync_spin_threshold=100000000 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami +children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +clock=1000 +console=/projects/pd/randd/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/projects/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal +pal=/projects/pd/randd/dist/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -34,18 +35,17 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge +clock=1000 delay=50000 -nack_delay=4000 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -93,6 +93,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -111,7 +112,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -145,16 +145,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -163,7 +165,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=AlphaTLB @@ -437,16 +439,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=32768 subblock_size=0 system=system @@ -455,15 +459,55 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 +[system.cpu.l2cache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hash_delay=1 +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +response_latency=20 +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.cpu.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + [system.cpu.tracer] type=ExeTracer @@ -484,7 +528,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -504,7 +548,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -527,16 +571,18 @@ type=BaseCache addr_ranges=0:8589934591 assoc=8 block_size=64 +clock=1000 forward_snoops=false hash_delay=1 +hit_latency=50 is_top_level=true -latency=50000 max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=50 size=1024 subblock_size=0 system=system @@ -547,31 +593,6 @@ write_buffers=8 cpu_side=system.iobus.master[29] mem_side=system.membus.slave[1] -[system.l2c] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=10000 -max_miss_count=0 -mshrs=92 -prefetch_on_access=false -prefetcher=Null -prioritizeRequests=false -repl=Null -size=4194304 -subblock_size=0 -system=system -tgts_per_mshr=16 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] - [system.membus] type=CoherentBus children=badaddr_responder @@ -582,13 +603,14 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.physmem.port -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side [system.membus.badaddr_responder] type=IsaFake +clock=1000 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -601,14 +623,28 @@ warn_access= pio=system.membus.default [system.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[1] @@ -620,7 +656,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -630,16 +666,6 @@ number=0 output=true port=3456 -[system.toL2Bus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.l2c.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - [system.tsunami] type=Tsunami children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -648,10 +674,11 @@ system=system [system.tsunami.backdoor] type=AlphaBackdoor +clock=1000 cpu=system.cpu disk=system.simple_disk pio_addr=8804682956800 -pio_latency=1000 +pio_latency=100000 platform=system.tsunami system=system terminal=system.terminal @@ -659,8 +686,9 @@ pio=system.iobus.master[24] [system.tsunami.cchip] type=TsunamiCChip +clock=1000 pio_addr=8803072344064 -pio_latency=1000 +pio_latency=100000 system=system tsunami=system.tsunami pio=system.iobus.master[0] @@ -716,12 +744,10 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.tsunami rss=false rx_delay=1000000 @@ -738,9 +764,10 @@ pio=system.iobus.master[27] [system.tsunami.fake_OROM] type=IsaFake +clock=1000 fake_mem=false pio_addr=8796093677568 -pio_latency=1000 +pio_latency=100000 pio_size=393216 ret_bad_addr=false ret_data16=65535 @@ -754,9 +781,10 @@ pio=system.iobus.master[8] [system.tsunami.fake_ata0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848432 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -770,9 +798,10 @@ pio=system.iobus.master[19] [system.tsunami.fake_ata1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848304 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -786,9 +815,10 @@ pio=system.iobus.master[20] [system.tsunami.fake_pnp_addr] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848569 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -802,9 +832,10 @@ pio=system.iobus.master[9] [system.tsunami.fake_pnp_read0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848451 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -818,9 +849,10 @@ pio=system.iobus.master[11] [system.tsunami.fake_pnp_read1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848515 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -834,9 +866,10 @@ pio=system.iobus.master[12] [system.tsunami.fake_pnp_read2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848579 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -850,9 +883,10 @@ pio=system.iobus.master[13] [system.tsunami.fake_pnp_read3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848643 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -866,9 +900,10 @@ pio=system.iobus.master[14] [system.tsunami.fake_pnp_read4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848707 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -882,9 +917,10 @@ pio=system.iobus.master[15] [system.tsunami.fake_pnp_read5] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848771 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -898,9 +934,10 @@ pio=system.iobus.master[16] [system.tsunami.fake_pnp_read6] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848835 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -914,9 +951,10 @@ pio=system.iobus.master[17] [system.tsunami.fake_pnp_read7] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848899 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -930,9 +968,10 @@ pio=system.iobus.master[18] [system.tsunami.fake_pnp_write] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615850617 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -946,9 +985,10 @@ pio=system.iobus.master[10] [system.tsunami.fake_ppc] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848891 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -962,9 +1002,10 @@ pio=system.iobus.master[7] [system.tsunami.fake_sm_chip] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848816 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -978,9 +1019,10 @@ pio=system.iobus.master[2] [system.tsunami.fake_uart1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848696 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -994,9 +1036,10 @@ pio=system.iobus.master[3] [system.tsunami.fake_uart2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848936 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1010,9 +1053,10 @@ pio=system.iobus.master[4] [system.tsunami.fake_uart3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848680 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1026,9 +1070,10 @@ pio=system.iobus.master[5] [system.tsunami.fake_uart4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848944 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1042,9 +1087,10 @@ pio=system.iobus.master[6] [system.tsunami.fb] type=BadDevice +clock=1000 devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[21] @@ -1088,16 +1134,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1000 config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 io_shift=0 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.tsunami system=system config=system.iobus.master[26] @@ -1106,9 +1151,10 @@ pio=system.iobus.master[25] [system.tsunami.io] type=TsunamiIO +clock=1000 frequency=976562500 pio_addr=8804615847936 -pio_latency=1000 +pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami @@ -1117,8 +1163,9 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip +clock=1000 pio_addr=8802535473152 -pio_latency=1000 +pio_latency=100000 system=system tsunami=system.tsunami pio=system.iobus.master[1] @@ -1126,7 +1173,8 @@ pio=system.iobus.master[1] [system.tsunami.pciconfig] type=PciConfigAll bus=0 -pio_latency=1 +clock=1000 +pio_latency=30000 platform=system.tsunami size=16777216 system=system @@ -1134,8 +1182,9 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 +clock=1000 pio_addr=8804615848952 -pio_latency=1000 +pio_latency=100000 platform=system.tsunami system=system terminal=system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index f67dea3de..6a7037f2d 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:20:05 -gem5 started Jul 26 2012 22:30:38 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 13:34:06 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1864423957500 because m5_exit instruction encountered +Exiting @ tick 1854349611000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index e834f19f3..cbfa90061 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.854370 # Number of seconds simulated -sim_ticks 1854370484500 # Number of ticks simulated -final_tick 1854370484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.854350 # Number of seconds simulated +sim_ticks 1854349611000 # Number of ticks simulated +final_tick 1854349611000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120780 # Simulator instruction rate (inst/s) -host_op_rate 120780 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4226353954 # Simulator tick rate (ticks/s) -host_mem_usage 326684 # Number of bytes of host memory used -host_seconds 438.76 # Real time elapsed on the host -sim_insts 52993965 # Number of instructions simulated -sim_ops 52993965 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 969088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24876288 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28497728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 969088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 969088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7507712 # Number of bytes written to this memory -system.physmem.bytes_written::total 7507712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15142 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388692 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445277 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117308 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117308 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 522597 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13414950 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1430325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15367872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 522597 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 522597 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4048658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4048658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4048658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 522597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13414950 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1430325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19416530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445277 # Total number of read requests seen -system.physmem.writeReqs 117308 # Total number of write requests seen -system.physmem.cpureqs 564090 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28497728 # Total number of bytes read from memory -system.physmem.bytesWritten 7507712 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28497728 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7507712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q +host_inst_rate 135035 # Simulator instruction rate (inst/s) +host_op_rate 135035 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4724741522 # Simulator tick rate (ticks/s) +host_mem_usage 327760 # Number of bytes of host memory used +host_seconds 392.48 # Real time elapsed on the host +sim_insts 52998188 # Number of instructions simulated +sim_ops 52998188 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 967168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory +system.physmem.bytes_read::total 28499904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 967168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 967168 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7518592 # Number of bytes written to this memory +system.physmem.bytes_written::total 7518592 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15112 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388757 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 445311 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117478 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117478 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 521567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13417345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1430306 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15369218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 521567 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 521567 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4054571 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4054571 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4054571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 521567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13417345 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1430306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19423789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445311 # Total number of read requests seen +system.physmem.writeReqs 117478 # Total number of write requests seen +system.physmem.cpureqs 564077 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28499904 # Total number of bytes read from memory +system.physmem.bytesWritten 7518592 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28499904 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7518592 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28080 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27911 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28123 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28001 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27770 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27692 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27278 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27918 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28145 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27785 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27747 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27834 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27734 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7584 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7291 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7101 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7583 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7405 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7380 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7215 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6854 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7428 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7671 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7427 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7350 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7315 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7174 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 28171 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27744 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27861 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27384 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28325 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28126 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27859 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27693 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27840 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27508 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27634 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27843 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27857 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27753 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27753 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27902 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7651 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7405 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6891 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7793 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7560 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7306 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7181 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7405 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7055 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7397 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7475 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7357 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7210 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7329 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 772 # Number of times wr buffer was full causing retry -system.physmem.totGap 1854365055000 # Total gap between requests +system.physmem.numWrRetry 554 # Number of times wr buffer was full causing retry +system.physmem.totGap 1854344226000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445277 # Categorize read packet sizes +system.physmem.readPktSize::6 445311 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -97,7 +97,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 118080 # categorize write packet sizes +system.physmem.writePktSize::6 118032 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -109,29 +109,29 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 175 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 331917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 65103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2872 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1980 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 331896 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 65179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2875 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1797 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2003 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1654 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1608 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1648 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1518 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 888 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -142,47 +142,47 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 56 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 6175504423 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13385770423 # Sum of mem lat for all requests -system.physmem.totBusLat 1780884000 # Total cycles spent in databus access -system.physmem.totBankLat 5429382000 # Total cycles spent in bank access -system.physmem.avgQLat 13870.65 # Average queueing delay per request -system.physmem.avgBankLat 12194.80 # Average bank access latency per request +system.physmem.totQLat 6253510302 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13461286302 # Sum of mem lat for all requests +system.physmem.totBusLat 1781012000 # Total cycles spent in databus access +system.physmem.totBankLat 5426764000 # Total cycles spent in bank access +system.physmem.avgQLat 14044.85 # Average queueing delay per request +system.physmem.avgBankLat 12188.05 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30065.45 # Average memory access latency +system.physmem.avgMemAccLat 30232.89 # Average memory access latency system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s @@ -190,21 +190,21 @@ system.physmem.avgConsumedWrBW 4.05 # Av system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.01 # Average write queue length over time -system.physmem.readRowHits 425232 # Number of row buffer hits during reads -system.physmem.writeRowHits 76485 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.20 # Row buffer hit rate for writes -system.physmem.avgGap 3296150.90 # Average gap between requests +system.physmem.avgWrQLen 11.07 # Average write queue length over time +system.physmem.readRowHits 425296 # Number of row buffer hits during reads +system.physmem.writeRowHits 76454 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.08 # Row buffer hit rate for writes +system.physmem.avgGap 3294919.10 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.265505 # Cycle average of tags in use +system.iocache.tagsinuse 1.265413 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1704471567000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.265505 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079094 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079094 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1704469740000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.265413 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079088 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079088 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -213,14 +213,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 20930998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 20930998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9501230806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9501230806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9522161804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9522161804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9522161804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9522161804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 9494924806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9494924806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9515852804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9515852804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9515852804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9515852804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -237,19 +237,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120988.427746 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120988.427746 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228658.808385 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 228658.808385 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 228212.385956 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228212.385956 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 228212.385956 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228212.385956 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 190847 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228507.046737 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 228507.046737 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 228061.181642 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 228061.181642 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 228061.181642 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 228061.181642 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 189089 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 22837 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 22862 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.356921 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.270886 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -263,14 +263,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11934000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11934000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7338470481 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7338470481 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7350404481 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7350404481 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7350404481 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7350404481 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11931000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7332138561 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7332138561 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 7344069561 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7344069561 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 7344069561 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7344069561 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -279,14 +279,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68982.658960 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68982.658960 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176609.320394 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176609.320394 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176163.079233 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176163.079233 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176163.079233 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176163.079233 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176456.934949 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176456.934949 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176011.253709 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 176011.253709 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176011.253709 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 176011.253709 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -304,22 +304,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10013236 # DTB read hits -system.cpu.dtb.read_misses 44959 # DTB read misses -system.cpu.dtb.read_acv 558 # DTB read access violations -system.cpu.dtb.read_accesses 947796 # DTB read accesses -system.cpu.dtb.write_hits 6616814 # DTB write hits -system.cpu.dtb.write_misses 10390 # DTB write misses -system.cpu.dtb.write_acv 394 # DTB write access violations -system.cpu.dtb.write_accesses 338465 # DTB write accesses -system.cpu.dtb.data_hits 16630050 # DTB hits -system.cpu.dtb.data_misses 55349 # DTB misses -system.cpu.dtb.data_acv 952 # DTB access violations -system.cpu.dtb.data_accesses 1286261 # DTB accesses -system.cpu.itb.fetch_hits 1329992 # ITB hits -system.cpu.itb.fetch_misses 37108 # ITB misses -system.cpu.itb.fetch_acv 1110 # ITB acv -system.cpu.itb.fetch_accesses 1367100 # ITB accesses +system.cpu.dtb.read_hits 9959916 # DTB read hits +system.cpu.dtb.read_misses 41524 # DTB read misses +system.cpu.dtb.read_acv 557 # DTB read access violations +system.cpu.dtb.read_accesses 942700 # DTB read accesses +system.cpu.dtb.write_hits 6603148 # DTB write hits +system.cpu.dtb.write_misses 10669 # DTB write misses +system.cpu.dtb.write_acv 409 # DTB write access violations +system.cpu.dtb.write_accesses 338186 # DTB write accesses +system.cpu.dtb.data_hits 16563064 # DTB hits +system.cpu.dtb.data_misses 52193 # DTB misses +system.cpu.dtb.data_acv 966 # DTB access violations +system.cpu.dtb.data_accesses 1280886 # DTB accesses +system.cpu.itb.fetch_hits 1308562 # ITB hits +system.cpu.itb.fetch_misses 36917 # ITB misses +system.cpu.itb.fetch_acv 1051 # ITB acv +system.cpu.itb.fetch_accesses 1345479 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -332,147 +332,147 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 109331520 # number of cpu cycles simulated +system.cpu.numCycles 108866981 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14034298 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11727409 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 442398 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10070774 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5936443 # Number of BTB hits +system.cpu.BPredUnit.lookups 13878911 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11630816 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 403232 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9482716 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5833581 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 932889 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 42550 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28466944 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 71882691 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14034298 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6869332 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13501507 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2157830 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37395098 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33730 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 253371 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 308992 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8797269 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 284448 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81356873 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.883548 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.225368 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 911561 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 38998 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 28184398 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70994195 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13878911 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6745142 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13311939 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2031019 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37417570 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32583 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 255429 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 315513 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8617973 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 269432 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80827249 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.878345 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.221663 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67855366 83.40% 83.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 872636 1.07% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1735283 2.13% 86.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 845860 1.04% 87.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2811672 3.46% 91.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 591009 0.73% 91.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 671901 0.83% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1016398 1.25% 93.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4956748 6.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67515310 83.53% 83.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 859289 1.06% 84.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1709305 2.11% 86.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 824937 1.02% 87.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2774546 3.43% 91.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 565272 0.70% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 652347 0.81% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1007085 1.25% 93.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4919158 6.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81356873 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.128365 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.657475 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29579770 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37116941 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12329905 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 976081 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1354175 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 610220 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43308 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 70446207 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129922 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1354175 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30731567 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13642128 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19830185 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11551170 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4247646 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 66474061 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6758 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 499961 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1485755 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 44416415 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 80669752 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 80190207 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479545 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38187514 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6228893 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1695379 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 248206 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12171415 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10595299 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6961029 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1313529 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 845283 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58768050 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2080813 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57151750 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 119190 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7476261 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3968695 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1415822 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81356873 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.702482 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.362452 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80827249 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.127485 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.652119 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29306094 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37119542 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12159527 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 975132 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1266953 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 590499 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43097 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69660736 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 130298 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1266953 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30443941 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13656496 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19805604 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11392846 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4261407 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65802441 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6765 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 504009 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1491914 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43932847 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79894315 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79415060 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479255 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38191269 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5741570 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1687796 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 244874 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12188114 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10482106 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6925475 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1313213 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 855117 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58302952 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2055207 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56888280 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 110464 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6988476 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3659625 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1390229 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80827249 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.703826 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.364551 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56509823 69.46% 69.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10919806 13.42% 82.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5202066 6.39% 89.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3421332 4.21% 93.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2660699 3.27% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1462898 1.80% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 750627 0.92% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 334208 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 95414 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56119293 69.43% 69.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10851228 13.43% 82.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5175866 6.40% 89.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3389461 4.19% 93.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2645582 3.27% 96.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1466047 1.81% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 750476 0.93% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 332850 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 96446 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81356873 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80827249 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 88942 11.25% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 375615 47.50% 58.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 326165 41.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91026 11.51% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 373270 47.20% 58.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326472 41.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7287 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38947584 68.15% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61688 0.11% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38768679 68.15% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61732 0.11% 68.27% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.32% # Type of FU issued @@ -495,114 +495,114 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.32% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10460697 18.30% 86.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6696198 11.72% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949053 1.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10391331 18.27% 86.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6681118 11.74% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948891 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57151750 # Type of FU issued -system.cpu.iq.rate 0.522738 # Inst issue rate -system.cpu.iq.fu_busy_cnt 790722 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013835 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 195876834 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68001610 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55798747 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 693450 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336801 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327935 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57573031 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 362154 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 597795 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56888280 # Type of FU issued +system.cpu.iq.rate 0.522549 # Inst issue rate +system.cpu.iq.fu_busy_cnt 790768 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013900 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194812399 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67023826 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55617934 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692641 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336620 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327880 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57310327 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361435 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 598219 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1500833 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3663 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13623 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 580148 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1386761 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3497 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14147 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 544022 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17973 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 208284 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17955 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 206298 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1354175 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9957840 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684465 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64406962 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 718774 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10595299 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6961029 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1833098 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512595 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 19043 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13623 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 239398 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 420347 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 659745 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56634449 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10087078 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 517300 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1266953 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9965004 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 682330 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63888752 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 694377 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10482106 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6925475 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1810071 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 511236 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18909 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14147 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 204344 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411597 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 615941 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56420713 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10029634 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 467566 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3558099 # number of nop insts executed -system.cpu.iew.exec_refs 16729501 # number of memory reference insts executed -system.cpu.iew.exec_branches 8966109 # Number of branches executed -system.cpu.iew.exec_stores 6642423 # Number of stores executed -system.cpu.iew.exec_rate 0.518007 # Inst execution rate -system.cpu.iew.wb_sent 56249945 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56126682 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27860065 # num instructions producing a value -system.cpu.iew.wb_consumers 37718288 # num instructions consuming a value +system.cpu.iew.exec_nop 3530593 # number of nop insts executed +system.cpu.iew.exec_refs 16658677 # number of memory reference insts executed +system.cpu.iew.exec_branches 8937468 # Number of branches executed +system.cpu.iew.exec_stores 6629043 # Number of stores executed +system.cpu.iew.exec_rate 0.518254 # Inst execution rate +system.cpu.iew.wb_sent 56060470 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55945814 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27785553 # num instructions producing a value +system.cpu.iew.wb_consumers 37633865 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.513362 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738635 # average fanout of values written-back +system.cpu.iew.wb_rate 0.513891 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738313 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8108089 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 664991 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 610571 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80002698 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.702279 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.626723 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7580888 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 664978 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 571532 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79560296 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.706241 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.634825 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59120920 73.90% 73.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8670305 10.84% 84.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4656948 5.82% 90.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2544039 3.18% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1525301 1.91% 95.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 612184 0.77% 96.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 529748 0.66% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 518714 0.65% 97.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1824539 2.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58754657 73.85% 73.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8628270 10.84% 84.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4624578 5.81% 90.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2529268 3.18% 93.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1515738 1.91% 95.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 609533 0.77% 96.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 524421 0.66% 97.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 524312 0.66% 97.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1849519 2.32% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80002698 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56184240 # Number of instructions committed -system.cpu.commit.committedOps 56184240 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79560296 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56188709 # Number of instructions committed +system.cpu.commit.committedOps 56188709 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15475347 # Number of memory references committed -system.cpu.commit.loads 9094466 # Number of loads committed -system.cpu.commit.membars 226347 # Number of memory barriers committed -system.cpu.commit.branches 8447798 # Number of branches committed +system.cpu.commit.refs 15476798 # Number of memory references committed +system.cpu.commit.loads 9095345 # Number of loads committed +system.cpu.commit.membars 226320 # Number of memory barriers committed +system.cpu.commit.branches 8447896 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52030338 # Number of committed integer instructions. -system.cpu.commit.function_calls 740415 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1824539 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52034633 # Number of committed integer instructions. +system.cpu.commit.function_calls 740447 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1849519 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 142220969 # The number of ROB reads -system.cpu.rob.rob_writes 129940455 # The number of ROB writes -system.cpu.timesIdled 1178635 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27974647 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599403014 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52993965 # Number of Instructions Simulated -system.cpu.committedOps 52993965 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52993965 # Number of Instructions Simulated -system.cpu.cpi 2.063094 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.063094 # CPI: Total CPI of All Threads -system.cpu.ipc 0.484709 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.484709 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74218754 # number of integer regfile reads -system.cpu.int_regfile_writes 40498790 # number of integer regfile writes -system.cpu.fp_regfile_reads 166070 # number of floating regfile reads -system.cpu.fp_regfile_writes 167447 # number of floating regfile writes -system.cpu.misc_regfile_reads 1994018 # number of misc regfile reads -system.cpu.misc_regfile_writes 947042 # number of misc regfile writes +system.cpu.rob.rob_reads 141230883 # The number of ROB reads +system.cpu.rob.rob_writes 128808067 # The number of ROB writes +system.cpu.timesIdled 1177683 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28039732 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599825806 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52998188 # Number of Instructions Simulated +system.cpu.committedOps 52998188 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52998188 # Number of Instructions Simulated +system.cpu.cpi 2.054164 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.054164 # CPI: Total CPI of All Threads +system.cpu.ipc 0.486816 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.486816 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73962724 # number of integer regfile reads +system.cpu.int_regfile_writes 40347354 # number of integer regfile writes +system.cpu.fp_regfile_reads 166024 # number of floating regfile reads +system.cpu.fp_regfile_writes 167429 # number of floating regfile writes +system.cpu.misc_regfile_reads 1993125 # number of misc regfile reads +system.cpu.misc_regfile_writes 947074 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -634,355 +634,189 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1020188 # number of replacements -system.cpu.icache.tagsinuse 510.304097 # Cycle average of tags in use -system.cpu.icache.total_refs 7717774 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1020696 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.561286 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20124452000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.304097 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996688 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996688 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7717775 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7717775 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7717775 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7717775 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7717775 # number of overall hits -system.cpu.icache.overall_hits::total 7717775 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1079494 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1079494 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1079494 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1079494 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1079494 # number of overall misses -system.cpu.icache.overall_misses::total 1079494 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14680685994 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14680685994 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14680685994 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14680685994 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14680685994 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14680685994 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8797269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8797269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8797269 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8797269 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8797269 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8797269 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.122708 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.122708 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.122708 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.122708 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.122708 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.122708 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13599.599436 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13599.599436 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13599.599436 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13599.599436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13599.599436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13599.599436 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3410 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 686 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 137 # number of cycles access was blocked +system.cpu.icache.replacements 1012720 # number of replacements +system.cpu.icache.tagsinuse 510.299473 # Cycle average of tags in use +system.cpu.icache.total_refs 7548318 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1013228 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.449772 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 20110483000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.299473 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996679 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996679 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7548319 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7548319 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7548319 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7548319 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7548319 # number of overall hits +system.cpu.icache.overall_hits::total 7548319 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1069652 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1069652 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1069652 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1069652 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1069652 # number of overall misses +system.cpu.icache.overall_misses::total 1069652 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14542561994 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14542561994 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14542561994 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14542561994 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14542561994 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14542561994 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8617971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8617971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8617971 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8617971 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8617971 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8617971 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124119 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124119 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124119 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124119 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124119 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124119 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13595.601181 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13595.601181 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13595.601181 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13595.601181 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13595.601181 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13595.601181 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4808 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 32 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 175 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 24.890511 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 686 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 27.474286 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 32 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 58579 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 58579 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 58579 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 58579 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 58579 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 58579 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1020915 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1020915 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1020915 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1020915 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1020915 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1020915 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12036646497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12036646497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12036646497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12036646497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12036646497 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12036646497 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116049 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116049 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116049 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116049 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116049 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116049 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11790.057446 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11790.057446 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11790.057446 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11790.057446 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11790.057446 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11790.057446 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56203 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 56203 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 56203 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 56203 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 56203 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 56203 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1013449 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1013449 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1013449 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1013449 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1013449 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1013449 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11948814497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11948814497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11948814497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11948814497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11948814497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11948814497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117597 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117597 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117597 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.117597 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117597 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.117597 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11790.247459 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11790.247459 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11790.247459 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11790.247459 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11790.247459 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11790.247459 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1402245 # number of replacements -system.cpu.dcache.tagsinuse 511.995160 # Cycle average of tags in use -system.cpu.dcache.total_refs 11879672 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1402757 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.468803 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21544000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995160 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7264730 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7264730 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4204895 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4204895 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 190246 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 190246 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 219552 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 219552 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11469625 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11469625 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11469625 # number of overall hits -system.cpu.dcache.overall_hits::total 11469625 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1801434 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1801434 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1941730 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1941730 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22995 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22995 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3743164 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3743164 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3743164 # number of overall misses -system.cpu.dcache.overall_misses::total 3743164 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33852672500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33852672500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 70445061639 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 70445061639 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 307962000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 307962000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 38000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 38000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 104297734139 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 104297734139 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 104297734139 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 104297734139 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9066164 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9066164 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6146625 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6146625 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 213241 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 213241 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 219554 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219554 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15212789 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15212789 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15212789 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15212789 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198699 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.198699 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315902 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.315902 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.107836 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.107836 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.246054 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.246054 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.246054 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.246054 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18792.069263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18792.069263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36279.535074 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36279.535074 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13392.563601 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13392.563601 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 27863.522448 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 27863.522448 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27863.522448 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27863.522448 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2571680 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 508 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 95435 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.946927 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 72.571429 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 841139 # number of writebacks -system.cpu.dcache.writebacks::total 841139 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 716695 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 716695 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1641513 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1641513 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5045 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5045 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2358208 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2358208 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2358208 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2358208 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084739 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1084739 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300217 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300217 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17950 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17950 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384956 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384956 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384956 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384956 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21195472500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21195472500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10712386769 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10712386769 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204757500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204757500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 34000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 34000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31907859269 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31907859269 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31907859269 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31907859269 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423908000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423908000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997720998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997720998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421628998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421628998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119647 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119647 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048843 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048843 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084177 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084177 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091039 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091039 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091039 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091039 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19539.698029 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19539.698029 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35682.145811 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35682.145811 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11407.103064 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11407.103064 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23038.897459 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23038.897459 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23038.897459 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23038.897459 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 338360 # number of replacements -system.cpu.l2cache.tagsinuse 65364.997376 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2558215 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 403528 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.339622 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 4044746002 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 53963.120652 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 5350.230870 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6051.645853 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.823412 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.081638 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.092341 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997391 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 1005648 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 828171 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1833819 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 841139 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 841139 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185483 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185483 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1005648 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1013654 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2019302 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1005648 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1013654 # number of overall hits -system.cpu.l2cache.overall_hits::total 2019302 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 15144 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 273859 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 289003 # number of ReadReq misses +system.cpu.l2cache.replacements 338368 # number of replacements +system.cpu.l2cache.tagsinuse 65364.962205 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2548619 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 403534 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.315748 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 4043215002 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 54020.981996 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 5337.307261 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6006.672948 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.824295 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.081441 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.091655 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997390 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 998214 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 826620 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1824834 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 840489 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 840489 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 185505 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 185505 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 998214 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1012125 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2010339 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 998214 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1012125 # number of overall hits +system.cpu.l2cache.overall_hits::total 2010339 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 15114 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 273846 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 288960 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 36 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 36 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 115327 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 115327 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15144 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389186 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404330 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15144 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389186 # number of overall misses -system.cpu.l2cache.overall_misses::total 404330 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 916217000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11804091500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12720308500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_misses::cpu.data 115406 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 115406 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15114 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389252 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404366 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15114 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389252 # number of overall misses +system.cpu.l2cache.overall_misses::total 404366 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 909377000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11791174000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12700551000 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 261500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 261500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8496188000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8496188000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 916217000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20300279500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21216496500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 916217000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20300279500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21216496500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1020792 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1102030 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2122822 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 841139 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 841139 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 67 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 67 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8601240000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8601240000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 909377000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 20392414000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21301791000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 909377000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 20392414000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21301791000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1013328 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1100466 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2113794 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 840489 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 840489 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 62 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 62 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 300810 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 300810 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1020792 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1402840 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2423632 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1020792 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1402840 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2423632 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014836 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248504 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.136141 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.537313 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.537313 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383388 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383388 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014836 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.277427 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.166828 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014836 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.277427 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.166828 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60500.330164 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43102.806554 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 44014.451407 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 300911 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 300911 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1013328 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1401377 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2414705 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1013328 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1401377 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2414705 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014915 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248845 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.136702 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.580645 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.580645 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383522 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383522 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014915 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.277764 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.167460 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014915 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.277764 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.167460 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60167.857615 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43057.682055 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 43952.626661 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7263.888889 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7263.888889 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73670.415427 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73670.415427 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52160.867811 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52473.218658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.330164 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52160.867811 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52473.218658 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74530.267057 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74530.267057 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60167.857615 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52388.719904 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52679.480965 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60167.857615 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52388.719904 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52679.480965 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -991,80 +825,72 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75796 # number of writebacks -system.cpu.l2cache.writebacks::total 75796 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75966 # number of writebacks +system.cpu.l2cache.writebacks::total 75966 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15143 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 289002 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15113 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273846 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288959 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 36 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 36 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115327 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115327 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15143 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389186 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404329 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15143 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389186 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404329 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 725022440 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8259922361 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8984944801 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115406 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115406 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15113 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389252 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404365 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15113 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389252 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404365 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 718571789 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8247220261 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8965792050 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 511032 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 511032 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7067947103 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7067947103 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 725022440 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15327869464 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16052891904 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 725022440 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15327869464 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16052891904 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333831000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333831000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882540500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882540500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216371500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216371500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248504 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136140 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.537313 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.537313 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383388 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383388 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277427 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.166828 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014835 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277427 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.166828 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47878.388694 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30161.222969 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31089.559245 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7172240815 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7172240815 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 718571789 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15419461076 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16138032865 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 718571789 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15419461076 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16138032865 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333809500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333809500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882195500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882195500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216005000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216005000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248845 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136702 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.580645 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.580645 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383522 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383522 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277764 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.167459 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014914 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277764 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.167459 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47546.601535 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30116.270681 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31027.903786 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14195.333333 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14195.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61286.143774 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61286.143774 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39384.431773 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39702.548924 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47878.388694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39384.431773 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39702.548924 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62147.902319 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62147.902319 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47546.601535 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39613.055491 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39909.568991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47546.601535 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39613.055491 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39909.568991 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1072,29 +898,191 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1400783 # number of replacements +system.cpu.dcache.tagsinuse 511.995190 # Cycle average of tags in use +system.cpu.dcache.total_refs 11827578 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1401295 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.440463 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21532000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.995190 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7213661 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7213661 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4203894 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4203894 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 190181 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 190181 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 219613 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 219613 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11417555 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11417555 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11417555 # number of overall hits +system.cpu.dcache.overall_hits::total 11417555 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1801125 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1801125 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1943246 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1943246 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22685 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22685 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3744371 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3744371 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3744371 # number of overall misses +system.cpu.dcache.overall_misses::total 3744371 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33805478000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33805478000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 71113991647 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 71113991647 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 303653500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 303653500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 104919469647 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 104919469647 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 104919469647 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 104919469647 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9014786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9014786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147140 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147140 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 212866 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 212866 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 219615 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219615 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15161926 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15161926 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15161926 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15161926 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199797 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.199797 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316122 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316122 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.106569 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.106569 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.246959 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.246959 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.246959 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.246959 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18769.090430 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18769.090430 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36595.465344 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36595.465344 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13385.651311 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13385.651311 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28020.586007 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28020.586007 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28020.586007 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28020.586007 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2640119 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 587 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 95652 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.601294 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 73.375000 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 840489 # number of writebacks +system.cpu.dcache.writebacks::total 840489 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717559 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 717559 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642936 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1642936 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5123 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5123 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2360495 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2360495 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2360495 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2360495 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083566 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083566 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300310 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300310 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17562 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17562 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1383876 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1383876 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1383876 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1383876 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21170477000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21170477000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10817290277 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10817290277 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199800500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199800500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31987767277 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31987767277 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31987767277 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31987767277 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423886500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423886500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997350998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997350998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421237498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421237498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120199 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120199 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048854 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048854 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082503 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082503 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091273 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091273 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19537.782655 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19537.782655 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36020.413163 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36020.413163 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11376.864822 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11376.864822 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23114.619574 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23114.619574 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23114.619574 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23114.619574 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211013 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 210973 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74651 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105569 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182243 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105545 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182205 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73284 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818451122500 98.06% 98.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64044500 0.00% 98.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 561305000 0.03% 98.10% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 35293166500 1.90% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1854369638500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73284 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148577 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818516202000 98.07% 98.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64252000 0.00% 98.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 558035000 0.03% 98.10% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 35210286000 1.90% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1854348775000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981688 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694295 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694339 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815439 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1133,29 +1121,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175126 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175092 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191972 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.callpal::total 191934 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1741 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326269 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326778 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29748704000 1.60% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2690261500 0.15% 1.75% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1821930665000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394590 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29709775500 1.60% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2660669000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1821978322500 98.25% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |