diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
4 files changed, 5326 insertions, 5334 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 401e8a630..9abb1e987 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,123 +1,126 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.884209 # Number of seconds simulated -sim_ticks 1884208734500 # Number of ticks simulated -final_tick 1884208734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.883224 # Number of seconds simulated +sim_ticks 1883223940000 # Number of ticks simulated +final_tick 1883223940000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147223 # Simulator instruction rate (inst/s) -host_op_rate 147223 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4942377286 # Simulator tick rate (ticks/s) -host_mem_usage 320260 # Number of bytes of host memory used -host_seconds 381.24 # Real time elapsed on the host -sim_insts 56126572 # Number of instructions simulated -sim_ops 56126572 # Number of ops (including micro ops) simulated +host_inst_rate 180615 # Simulator instruction rate (inst/s) +host_op_rate 180615 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6060637883 # Simulator tick rate (ticks/s) +host_mem_usage 316396 # Number of bytes of host memory used +host_seconds 310.73 # Real time elapsed on the host +sim_insts 56122642 # Number of instructions simulated +sim_ops 56122642 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 25914048 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28566400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1052800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1052800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7560448 # Number of bytes written to this memory -system.physmem.bytes_written::total 7560448 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 404907 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 446350 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118132 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118132 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13753279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1407674 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15160953 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 558749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 558749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4012532 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4012532 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4012532 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13753279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1407674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19173485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 446350 # Number of read requests accepted -system.physmem.writeReqs 118132 # Number of write requests accepted -system.physmem.readBursts 446350 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118132 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28559040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue -system.physmem.bytesWritten 7558400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28566400 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7560448 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 25930944 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 25931904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1052544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1052544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4902720 # Number of bytes written to this memory +system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory +system.physmem.bytes_written::total 7562048 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 405171 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 405186 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 76605 # Number of write requests responded to by this memory +system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118157 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13769443 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13769952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 558905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 558905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2603365 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1412115 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4015480 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2603365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13769443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1412624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17785432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 405186 # Number of read requests accepted +system.physmem.writeReqs 118157 # Number of write requests accepted +system.physmem.readBursts 405186 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118157 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25919424 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12480 # Total number of bytes read from write queue +system.physmem.bytesWritten 7560064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25931904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7562048 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 195 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28089 # Per bank write bursts -system.physmem.perBankRdBursts::1 28219 # Per bank write bursts -system.physmem.perBankRdBursts::2 28571 # Per bank write bursts -system.physmem.perBankRdBursts::3 28273 # Per bank write bursts -system.physmem.perBankRdBursts::4 27775 # Per bank write bursts -system.physmem.perBankRdBursts::5 27529 # Per bank write bursts -system.physmem.perBankRdBursts::6 27274 # Per bank write bursts -system.physmem.perBankRdBursts::7 26987 # Per bank write bursts -system.physmem.perBankRdBursts::8 27827 # Per bank write bursts -system.physmem.perBankRdBursts::9 27514 # Per bank write bursts -system.physmem.perBankRdBursts::10 28065 # Per bank write bursts -system.physmem.perBankRdBursts::11 27430 # Per bank write bursts -system.physmem.perBankRdBursts::12 27510 # Per bank write bursts -system.physmem.perBankRdBursts::13 28401 # Per bank write bursts -system.physmem.perBankRdBursts::14 28311 # Per bank write bursts -system.physmem.perBankRdBursts::15 28460 # Per bank write bursts -system.physmem.perBankWrBursts::0 7814 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25480 # Per bank write bursts +system.physmem.perBankRdBursts::1 25741 # Per bank write bursts +system.physmem.perBankRdBursts::2 25855 # Per bank write bursts +system.physmem.perBankRdBursts::3 25788 # Per bank write bursts +system.physmem.perBankRdBursts::4 25233 # Per bank write bursts +system.physmem.perBankRdBursts::5 24956 # Per bank write bursts +system.physmem.perBankRdBursts::6 24811 # Per bank write bursts +system.physmem.perBankRdBursts::7 24586 # Per bank write bursts +system.physmem.perBankRdBursts::8 25127 # Per bank write bursts +system.physmem.perBankRdBursts::9 25280 # Per bank write bursts +system.physmem.perBankRdBursts::10 25532 # Per bank write bursts +system.physmem.perBankRdBursts::11 24857 # Per bank write bursts +system.physmem.perBankRdBursts::12 24547 # Per bank write bursts +system.physmem.perBankRdBursts::13 25588 # Per bank write bursts +system.physmem.perBankRdBursts::14 25870 # Per bank write bursts +system.physmem.perBankRdBursts::15 25740 # Per bank write bursts +system.physmem.perBankWrBursts::0 7812 # Per bank write bursts system.physmem.perBankWrBursts::1 7677 # Per bank write bursts -system.physmem.perBankWrBursts::2 8054 # Per bank write bursts -system.physmem.perBankWrBursts::3 7732 # Per bank write bursts -system.physmem.perBankWrBursts::4 7319 # Per bank write bursts -system.physmem.perBankWrBursts::5 6955 # Per bank write bursts +system.physmem.perBankWrBursts::2 8067 # Per bank write bursts +system.physmem.perBankWrBursts::3 7744 # Per bank write bursts +system.physmem.perBankWrBursts::4 7318 # Per bank write bursts +system.physmem.perBankWrBursts::5 6954 # Per bank write bursts system.physmem.perBankWrBursts::6 6788 # Per bank write bursts system.physmem.perBankWrBursts::7 6406 # Per bank write bursts system.physmem.perBankWrBursts::8 7235 # Per bank write bursts -system.physmem.perBankWrBursts::9 6877 # Per bank write bursts -system.physmem.perBankWrBursts::10 7390 # Per bank write bursts +system.physmem.perBankWrBursts::9 6889 # Per bank write bursts +system.physmem.perBankWrBursts::10 7393 # Per bank write bursts system.physmem.perBankWrBursts::11 6865 # Per bank write bursts -system.physmem.perBankWrBursts::12 7046 # Per bank write bursts -system.physmem.perBankWrBursts::13 8008 # Per bank write bursts -system.physmem.perBankWrBursts::14 7991 # Per bank write bursts -system.physmem.perBankWrBursts::15 7943 # Per bank write bursts +system.physmem.perBankWrBursts::12 7045 # Per bank write bursts +system.physmem.perBankWrBursts::13 8007 # Per bank write bursts +system.physmem.perBankWrBursts::14 7989 # Per bank write bursts +system.physmem.perBankWrBursts::15 7937 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 1884200137500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 1883215178500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 446350 # Read request sizes (log2) +system.physmem.readPktSize::6 405186 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118132 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3909 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2828 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4354 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2519 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 877 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118157 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -144,283 +147,274 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1024 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65499 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 551.419716 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 340.219574 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.619626 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14326 21.87% 21.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10638 16.24% 38.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5049 7.71% 45.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3016 4.60% 50.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2484 3.79% 54.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2116 3.23% 57.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1384 2.11% 59.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1595 2.44% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24891 38.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65499 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6964 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 64.074383 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 16.502018 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2530.928651 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 6961 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6964 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6964 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.958644 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.733261 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.741198 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5665 81.35% 81.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 36 0.52% 81.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 854 12.26% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 55 0.79% 94.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 10 0.14% 95.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 13 0.19% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 23 0.33% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 94 1.35% 96.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 12 0.17% 97.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 41 0.59% 97.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 13 0.19% 97.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 17 0.24% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 13 0.19% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 12 0.17% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.04% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 21 0.30% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 7 0.10% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 2 0.03% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.03% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.01% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 2 0.03% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 3 0.04% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 3 0.04% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 2 0.03% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 8 0.11% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 7 0.10% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 3 0.04% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 1 0.01% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 1 0.01% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 1 0.01% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 7 0.10% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 2 0.03% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 1 0.01% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 1 0.01% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 1 0.01% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 4 0.06% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54 1 0.01% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 9 0.13% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 8 0.11% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58 4 0.06% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::59 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6964 # Writes before turning the bus around for reads -system.physmem.totQLat 7297586750 # Total ticks spent queuing -system.physmem.totMemAccLat 15664493000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2231175000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16353.69 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62955 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 531.800302 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 324.503879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.177975 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14434 22.93% 22.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10626 16.88% 39.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4984 7.92% 47.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3035 4.82% 52.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2479 3.94% 56.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2063 3.28% 59.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1365 2.17% 61.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1615 2.57% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22354 35.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62955 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5310 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.265725 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2898.384419 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5307 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5310 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5310 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.245951 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.963647 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.434666 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4660 87.76% 87.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 16 0.30% 88.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 15 0.28% 88.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 227 4.27% 92.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 38 0.72% 93.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 5 0.09% 93.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 8 0.15% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.11% 93.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 26 0.49% 94.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.08% 94.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.09% 94.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 14 0.26% 94.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.04% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.09% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 26 0.49% 95.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 9 0.17% 95.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 5 0.09% 95.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 6 0.11% 95.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 182 3.43% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.11% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 3 0.06% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.04% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 6 0.11% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 5 0.09% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.08% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.04% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.13% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 5 0.09% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5310 # Writes before turning the bus around for reads +system.physmem.totQLat 2131293750 # Total ticks spent queuing +system.physmem.totMemAccLat 9724875000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2024955000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5262.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35103.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24012.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.76 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.16 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.97 # Average write queue length when enqueuing -system.physmem.readRowHits 402726 # Number of row buffer hits during reads -system.physmem.writeRowHits 96110 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.36 # Row buffer hit rate for writes -system.physmem.avgGap 3337927.76 # Average gap between requests -system.physmem.pageHitRate 88.39 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1774702818500 # Time in different power states -system.physmem.memoryStateTime::REF 62917660000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing +system.physmem.readRowHits 364467 # Number of row buffer hits during reads +system.physmem.writeRowHits 95695 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.99 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.99 # Row buffer hit rate for writes +system.physmem.avgGap 3598433.87 # Average gap between requests +system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1774121817500 # Time in different power states +system.physmem.memoryStateTime::REF 62884900000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 46582219000 # Time in different power states +system.physmem.memoryStateTime::ACT 46214912500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 19215856 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 295757 # Transaction distribution -system.membus.trans_dist::ReadResp 295741 # Transaction distribution -system.membus.trans_dist::WriteReq 9619 # Transaction distribution -system.membus.trans_dist::WriteResp 9619 # Transaction distribution -system.membus.trans_dist::Writeback 118132 # Transaction distribution -system.membus.trans_dist::UpgradeReq 156 # Transaction distribution -system.membus.trans_dist::UpgradeResp 156 # Transaction distribution -system.membus.trans_dist::ReadExReq 158094 # Transaction distribution -system.membus.trans_dist::ReadExResp 158094 # Transaction distribution +system.membus.throughput 17814330 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 295751 # Transaction distribution +system.membus.trans_dist::ReadResp 295735 # Transaction distribution +system.membus.trans_dist::WriteReq 9618 # Transaction distribution +system.membus.trans_dist::WriteResp 9618 # Transaction distribution +system.membus.trans_dist::Writeback 76605 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 157 # Transaction distribution +system.membus.trans_dist::UpgradeResp 157 # Transaction distribution +system.membus.trans_dist::ReadExReq 116539 # Transaction distribution +system.membus.trans_dist::ReadExResp 116539 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887017 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33096 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887261 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920147 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1044827 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30817728 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30862044 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36171164 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36171164 # Total data (bytes) -system.membus.snoop_data_through_bus 35520 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29834000 # Layer occupancy (ticks) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920389 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1003681 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44308 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30833664 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30877972 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 33538260 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 33538260 # Total data (bytes) +system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 29840000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1588295250 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1547069500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 19500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3825084824 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3825068843 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376625999 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43112000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.295855 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.288165 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1728026399000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.295855 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.080991 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.080991 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1728026235000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.288165 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.080510 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.080510 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375525 # Number of tag accesses -system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.tags.tag_accesses 375533 # Number of tag accesses +system.iocache.tags.data_accesses 375533 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21134133 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21134133 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12414876231 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12414876231 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12436010364 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12436010364 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12436010364 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12436010364 # number of overall miss cycles +system.iocache.WriteInvalidateReq_misses::tsunami.ide 1 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses +system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses +system.iocache.demand_misses::total 173 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 173 # number of overall misses +system.iocache.overall_misses::total 173 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21132383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21132383 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21132383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21132383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21132383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21132383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41553 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41553 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000024 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000024 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122162.618497 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122162.618497 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 298779.270095 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 298779.270095 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 298046.982960 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 298046.982960 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 298046.982960 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 298046.982960 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 364154 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122152.502890 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122152.502890 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122152.502890 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122152.502890 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122152.502890 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122152.502890 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28275 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.879010 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41512 # number of writebacks -system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12137133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10251971233 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10251971233 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10264108366 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10264108366 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10264108366 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10264108366 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12135383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12135383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2514597305 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2514597305 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12135383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12135383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12135383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12135383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999976 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999976 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70156.838150 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70156.838150 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 246726.300371 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 246726.300371 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 245994.208892 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 245994.208892 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 245994.208892 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 245994.208892 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70146.722543 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60516.877768 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60516.877768 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70146.722543 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70146.722543 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -434,36 +428,36 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14968340 # Number of BP lookups -system.cpu.branchPred.condPredicted 12984271 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 377638 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10101234 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5190890 # Number of BTB hits +system.cpu.branchPred.lookups 14964215 # Number of BP lookups +system.cpu.branchPred.condPredicted 12981470 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 376025 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10003487 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5188980 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 51.388672 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 808188 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32062 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 51.871712 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 807651 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32040 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9240282 # DTB read hits -system.cpu.dtb.read_misses 17901 # DTB read misses +system.cpu.dtb.read_hits 9238395 # DTB read hits +system.cpu.dtb.read_misses 17814 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 766280 # DTB read accesses -system.cpu.dtb.write_hits 6385567 # DTB write hits -system.cpu.dtb.write_misses 2310 # DTB write misses +system.cpu.dtb.read_accesses 766068 # DTB read accesses +system.cpu.dtb.write_hits 6385066 # DTB write hits +system.cpu.dtb.write_misses 2311 # DTB write misses system.cpu.dtb.write_acv 159 # DTB write access violations -system.cpu.dtb.write_accesses 298488 # DTB write accesses -system.cpu.dtb.data_hits 15625849 # DTB hits -system.cpu.dtb.data_misses 20211 # DTB misses +system.cpu.dtb.write_accesses 298441 # DTB write accesses +system.cpu.dtb.data_hits 15623461 # DTB hits +system.cpu.dtb.data_misses 20125 # DTB misses system.cpu.dtb.data_acv 370 # DTB access violations -system.cpu.dtb.data_accesses 1064768 # DTB accesses -system.cpu.itb.fetch_hits 4001359 # ITB hits -system.cpu.itb.fetch_misses 6809 # ITB misses -system.cpu.itb.fetch_acv 657 # ITB acv -system.cpu.itb.fetch_accesses 4008168 # ITB accesses +system.cpu.dtb.data_accesses 1064509 # DTB accesses +system.cpu.itb.fetch_hits 4000795 # ITB hits +system.cpu.itb.fetch_misses 6874 # ITB misses +system.cpu.itb.fetch_acv 703 # ITB acv +system.cpu.itb.fetch_accesses 4007669 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -476,39 +470,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 176815826 # number of cpu cycles simulated +system.cpu.numCycles 176776474 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56126572 # Number of instructions committed -system.cpu.committedOps 56126572 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2538059 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5497 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593513250 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.150305 # CPI: cycles per instruction -system.cpu.ipc 0.317430 # IPC: instructions per cycle +system.cpu.committedInsts 56122642 # Number of instructions committed +system.cpu.committedOps 56122642 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2532635 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5494 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3591582755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.149825 # CPI: cycles per instruction +system.cpu.ipc 0.317478 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211465 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74787 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211451 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74783 40.94% 40.94% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105856 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182675 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73420 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1900 1.04% 42.05% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105851 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182665 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73416 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73420 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148872 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1833844528000 97.33% 97.33% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 80077500 0.00% 97.33% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 673181000 0.04% 97.37% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 49609971000 2.63% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1884207757500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981721 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1900 1.28% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73416 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148863 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1832860357500 97.33% 97.33% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 80169000 0.00% 97.33% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 672803000 0.04% 97.37% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 49609630000 2.63% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1883222959500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981720 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693584 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814956 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693579 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814951 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -544,35 +538,35 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175516 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175508 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6803 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5125 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192403 # number of callpals executed +system.cpu.kern.callpal::total 192390 # number of callpals executed system.cpu.kern.mode_switch::kernel 5869 # number of protection mode switches -system.cpu.kern.mode_switch::user 1735 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2100 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1905 -system.cpu.kern.mode_good::user 1735 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.324587 # fraction of useful protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1741 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.325439 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080952 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392622 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36214076000 1.92% 1.92% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4058025000 0.22% 2.14% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1843935646500 97.86% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed -system.cpu.tickCycles 85802593 # Number of cycles that the object actually ticked -system.cpu.idleCycles 91013233 # Total number of cycles that the object has spent stopped +system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.393571 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 36245351000 1.92% 1.92% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4057630500 0.22% 2.14% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1842919968000 97.86% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4175 # number of times the context was actually changed +system.cpu.tickCycles 85798616 # Number of cycles that the object actually ticked +system.cpu.idleCycles 90977858 # Total number of cycles that the object has spent stopped system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -604,12 +598,13 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1436106 # Throughput (bytes/s) +system.iobus.throughput 1436853 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51171 # Transaction distribution -system.iobus.trans_dist::WriteResp 51171 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5094 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51169 # Transaction distribution +system.iobus.trans_dist::WriteResp 51170 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5092 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -621,11 +616,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33098 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33096 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116548 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20376 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116546 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20368 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -637,12 +632,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 44316 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 44308 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2705924 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2705924 # Total data (bytes) -system.iobus.reqLayer0.occupancy 4705000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2705916 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2705916 # Total data (bytes) +system.iobus.reqLayer0.occupancy 4703000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -664,66 +659,66 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380105365 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374409688 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23478000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43180001 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42012000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 1458006 # number of replacements -system.cpu.icache.tags.tagsinuse 509.628197 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 18953120 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1458517 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12.994789 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 31559763000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.628197 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995368 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995368 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1458007 # number of replacements +system.cpu.icache.tags.tagsinuse 509.627041 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 18950160 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1458518 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12.992750 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 31562091250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.627041 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995365 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995365 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 386 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 21870509 # Number of tag accesses -system.cpu.icache.tags.data_accesses 21870509 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 18953123 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 18953123 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 18953123 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 18953123 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 18953123 # number of overall hits -system.cpu.icache.overall_hits::total 18953123 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1458693 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1458693 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1458693 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1458693 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1458693 # number of overall misses -system.cpu.icache.overall_misses::total 1458693 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20024605540 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20024605540 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20024605540 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20024605540 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20024605540 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20024605540 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 20411816 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 20411816 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 20411816 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 20411816 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 20411816 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 20411816 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071463 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.071463 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.071463 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.071463 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.071463 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.071463 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.772424 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13727.772424 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.772424 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13727.772424 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.772424 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13727.772424 # average overall miss latency +system.cpu.icache.tags.tag_accesses 21867553 # Number of tag accesses +system.cpu.icache.tags.data_accesses 21867553 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 18950163 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 18950163 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 18950163 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 18950163 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 18950163 # number of overall hits +system.cpu.icache.overall_hits::total 18950163 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1458695 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1458695 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1458695 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1458695 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1458695 # number of overall misses +system.cpu.icache.overall_misses::total 1458695 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20021954296 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20021954296 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20021954296 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20021954296 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20021954296 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20021954296 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 20408858 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 20408858 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 20408858 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 20408858 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 20408858 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 20408858 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071474 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.071474 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.071474 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.071474 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.071474 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.071474 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13725.936057 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13725.936057 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13725.936057 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13725.936057 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13725.936057 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13725.936057 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -732,142 +727,143 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458693 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1458693 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1458693 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1458693 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1458693 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1458693 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17099831460 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17099831460 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17099831460 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17099831460 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17099831460 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17099831460 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071463 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071463 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071463 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.071463 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071463 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.071463 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11722.707561 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11722.707561 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11722.707561 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11722.707561 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11722.707561 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11722.707561 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458695 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1458695 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1458695 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1458695 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1458695 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1458695 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17097209704 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17097209704 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17097209704 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17097209704 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17097209704 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17097209704 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071474 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.071474 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.071474 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11720.894158 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11720.894158 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11720.894158 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11720.894158 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11720.894158 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11720.894158 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 125457945 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2557417 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2557383 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 838210 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 345773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304222 # Transaction distribution +system.cpu.toL2Bus.throughput 126942050 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2557486 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2557452 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 838282 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41557 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304264 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304264 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917325 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663192 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6580517 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93352448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143032604 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 236385052 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 236375068 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 13888 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2697678498 # Layer occupancy (ticks) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917328 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663485 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6580813 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93352512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143044180 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 236396692 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 236386772 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 2673536 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2697842997 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 232500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2191733540 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2191719796 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194708666 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2194901157 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 339421 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65326.541432 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2981708 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 404583 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.369830 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 339412 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65326.749870 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2981869 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 404575 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.370374 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 5872511750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 54488.510247 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10838.031185 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.831429 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165375 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996804 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1468 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2781 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55528 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 30250697 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 30250697 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2261599 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2261599 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 838210 # 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miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.113186 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.818182 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.818182 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383537 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383537 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.142000 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.142000 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.142000 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.142000 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65540.328507 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 65540.328507 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 6150131 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6150131 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200006 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200006 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198983 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 198983 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 15158531 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15158531 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 15158531 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15158531 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133388 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133388 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093282 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093282 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086492 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086492 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.117117 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117117 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.117117 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117117 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25813.836117 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25813.836117 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36165.857085 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36165.857085 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13393.216371 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13393.216371 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29159.126433 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29159.126433 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29159.126433 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29159.126433 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1019,64 +1015,64 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838210 # number of writebacks -system.cpu.dcache.writebacks::total 838210 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127240 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127240 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269470 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269470 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838282 # number of writebacks +system.cpu.dcache.writebacks::total 838282 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127187 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 127187 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269448 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269448 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 396710 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 396710 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 396710 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 396710 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074353 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074353 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304205 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304205 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17306 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17306 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1378558 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378558 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1378558 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378558 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26912219745 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26912219745 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10275413589 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10275413589 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196866500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196866500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37187633334 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37187633334 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37187633334 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37187633334 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423283000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423283000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2003033000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2003033000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426316000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426316000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119244 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119244 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049460 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049460 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086522 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086522 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090932 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090932 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090932 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090932 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25049.699442 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25049.699442 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33777.924719 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33777.924719 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11375.621172 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11375.621172 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26975.748089 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26975.748089 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26975.748089 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26975.748089 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.inst 396635 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 396635 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 396635 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 396635 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074429 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074429 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304251 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304251 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17296 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17296 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 1378680 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378680 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 1378680 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378680 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26906996250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26906996250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10272860843 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10272860843 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196930250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196930250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37179857093 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 37179857093 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37179857093 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 37179857093 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423313500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423313500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2002790500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002790500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426104000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426104000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119270 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119270 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049471 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049471 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086477 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086477 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090951 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090951 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090951 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090951 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25043.065898 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25043.065898 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33764.427538 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33764.427538 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11385.884019 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11385.884019 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26967.720641 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26967.720641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26967.720641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26967.720641 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 2b53a578a..683e407e9 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,138 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.906207 # Number of seconds simulated -sim_ticks 1906207240000 # Number of ticks simulated -final_tick 1906207240000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.903124 # Number of seconds simulated +sim_ticks 1903123778500 # Number of ticks simulated +final_tick 1903123778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147655 # Simulator instruction rate (inst/s) -host_op_rate 147655 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5021061637 # Simulator tick rate (ticks/s) -host_mem_usage 308576 # Number of bytes of host memory used -host_seconds 379.64 # Real time elapsed on the host -sim_insts 56056069 # Number of instructions simulated -sim_ops 56056069 # Number of ops (including micro ops) simulated +host_inst_rate 103415 # Simulator instruction rate (inst/s) +host_op_rate 103415 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3505224116 # Simulator tick rate (ticks/s) +host_mem_usage 322696 # Number of bytes of host memory used +host_seconds 542.94 # Real time elapsed on the host +sim_insts 56148221 # Number of instructions simulated +sim_ops 56148221 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 903488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24906304 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 74560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 378304 # Number of bytes read from this memory -system.physmem.bytes_read::total 28912320 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 903488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 74560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 978048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7848000 # Number of bytes written to this memory -system.physmem.bytes_written::total 7848000 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14117 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 389161 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41401 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 5911 # Number of read requests responded to by this memory -system.physmem.num_reads::total 451755 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122625 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122625 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 473972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13065895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1390019 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 39114 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 198459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15167459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 473972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 39114 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513086 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4117076 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4117076 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4117076 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 473972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13065895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1390019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 39114 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 198459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19284535 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 451755 # Number of read requests accepted -system.physmem.writeReqs 122625 # Number of write requests accepted -system.physmem.readBursts 451755 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122625 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28904128 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue -system.physmem.bytesWritten 7846080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28912320 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7848000 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu0.inst 744192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24296448 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 238144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1067328 # Number of bytes read from this memory +system.physmem.bytes_read::total 26347072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 744192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 238144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 982336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5275328 # Number of bytes written to this memory +system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory +system.physmem.bytes_written::total 7934656 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11628 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 379632 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3721 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16677 # Number of read requests responded to by this memory +system.physmem.num_reads::total 411673 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 82427 # Number of write requests responded to by this memory +system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123979 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 391037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12766615 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 125133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 560830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13844119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 391037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 125133 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2771931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1397349 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4169280 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2771931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 391037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12766615 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1397853 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 125133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 560830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18013399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 411673 # Number of read requests accepted +system.physmem.writeReqs 123979 # Number of write requests accepted +system.physmem.readBursts 411673 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123979 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26335040 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue +system.physmem.bytesWritten 7932928 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26347072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7934656 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3217 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28097 # Per bank write bursts -system.physmem.perBankRdBursts::1 28602 # Per bank write bursts -system.physmem.perBankRdBursts::2 29043 # Per bank write bursts -system.physmem.perBankRdBursts::3 27571 # Per bank write bursts -system.physmem.perBankRdBursts::4 27384 # Per bank write bursts -system.physmem.perBankRdBursts::5 27564 # Per bank write bursts -system.physmem.perBankRdBursts::6 27744 # Per bank write bursts -system.physmem.perBankRdBursts::7 27694 # Per bank write bursts -system.physmem.perBankRdBursts::8 27865 # Per bank write bursts -system.physmem.perBankRdBursts::9 28720 # Per bank write bursts -system.physmem.perBankRdBursts::10 28531 # Per bank write bursts -system.physmem.perBankRdBursts::11 28618 # Per bank write bursts -system.physmem.perBankRdBursts::12 28938 # Per bank write bursts -system.physmem.perBankRdBursts::13 28977 # Per bank write bursts -system.physmem.perBankRdBursts::14 28277 # Per bank write bursts -system.physmem.perBankRdBursts::15 28002 # Per bank write bursts -system.physmem.perBankWrBursts::0 7839 # Per bank write bursts -system.physmem.perBankWrBursts::1 8045 # Per bank write bursts -system.physmem.perBankWrBursts::2 8418 # Per bank write bursts -system.physmem.perBankWrBursts::3 7040 # Per bank write bursts -system.physmem.perBankWrBursts::4 6886 # Per bank write bursts -system.physmem.perBankWrBursts::5 7040 # Per bank write bursts -system.physmem.perBankWrBursts::6 7326 # Per bank write bursts -system.physmem.perBankWrBursts::7 7097 # Per bank write bursts -system.physmem.perBankWrBursts::8 7158 # Per bank write bursts -system.physmem.perBankWrBursts::9 7908 # Per bank write bursts -system.physmem.perBankWrBursts::10 7739 # Per bank write bursts -system.physmem.perBankWrBursts::11 7821 # Per bank write bursts -system.physmem.perBankWrBursts::12 8331 # Per bank write bursts -system.physmem.perBankWrBursts::13 8401 # Per bank write bursts -system.physmem.perBankWrBursts::14 7959 # Per bank write bursts -system.physmem.perBankWrBursts::15 7587 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 3444 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25632 # Per bank write bursts +system.physmem.perBankRdBursts::1 25720 # Per bank write bursts +system.physmem.perBankRdBursts::2 26346 # Per bank write bursts +system.physmem.perBankRdBursts::3 25660 # Per bank write bursts +system.physmem.perBankRdBursts::4 25672 # Per bank write bursts +system.physmem.perBankRdBursts::5 25150 # Per bank write bursts +system.physmem.perBankRdBursts::6 25568 # Per bank write bursts +system.physmem.perBankRdBursts::7 25491 # Per bank write bursts +system.physmem.perBankRdBursts::8 25973 # Per bank write bursts +system.physmem.perBankRdBursts::9 26167 # Per bank write bursts +system.physmem.perBankRdBursts::10 25812 # Per bank write bursts +system.physmem.perBankRdBursts::11 25687 # Per bank write bursts +system.physmem.perBankRdBursts::12 26023 # Per bank write bursts +system.physmem.perBankRdBursts::13 25844 # Per bank write bursts +system.physmem.perBankRdBursts::14 25108 # Per bank write bursts +system.physmem.perBankRdBursts::15 25632 # Per bank write bursts +system.physmem.perBankWrBursts::0 8431 # Per bank write bursts +system.physmem.perBankWrBursts::1 7989 # Per bank write bursts +system.physmem.perBankWrBursts::2 8275 # Per bank write bursts +system.physmem.perBankWrBursts::3 7382 # Per bank write bursts +system.physmem.perBankWrBursts::4 7684 # Per bank write bursts +system.physmem.perBankWrBursts::5 7400 # Per bank write bursts +system.physmem.perBankWrBursts::6 7193 # Per bank write bursts +system.physmem.perBankWrBursts::7 7021 # Per bank write bursts +system.physmem.perBankWrBursts::8 7374 # Per bank write bursts +system.physmem.perBankWrBursts::9 7755 # Per bank write bursts +system.physmem.perBankWrBursts::10 7777 # Per bank write bursts +system.physmem.perBankWrBursts::11 7454 # Per bank write bursts +system.physmem.perBankWrBursts::12 8052 # Per bank write bursts +system.physmem.perBankWrBursts::13 8097 # Per bank write bursts +system.physmem.perBankWrBursts::14 7762 # Per bank write bursts +system.physmem.perBankWrBursts::15 8306 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 1906202745000 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 1903119235000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 451755 # Read request sizes (log2) +system.physmem.readPktSize::6 411673 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 122625 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 319401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 41325 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46009 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2142 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 893 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123979 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 40920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 43295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 77 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -158,359 +161,357 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66892 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 549.396161 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 336.305192 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 420.466175 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14808 22.14% 22.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11177 16.71% 38.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5157 7.71% 46.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2881 4.31% 50.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2294 3.43% 54.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1713 2.56% 56.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1492 2.23% 59.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1822 2.72% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25548 38.19% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66892 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7192 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 62.794355 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2475.959084 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 7189 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7192 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7192 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.046023 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.810949 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.823344 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5742 79.84% 79.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 42 0.58% 80.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 691 9.61% 90.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 254 3.53% 93.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 102 1.42% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 28 0.39% 95.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 28 0.39% 95.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 90 1.25% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 10 0.14% 97.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 32 0.44% 97.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 22 0.31% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 14 0.19% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 15 0.21% 98.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 7 0.10% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 9 0.13% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 23 0.32% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 11 0.15% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.03% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 2 0.03% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.01% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 3 0.04% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 2 0.03% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 4 0.06% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 3 0.04% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 4 0.06% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.03% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 1 0.01% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 2 0.03% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 1 0.01% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 8 0.11% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 1 0.01% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 1 0.01% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 2 0.03% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 4 0.06% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 2 0.03% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 13 0.18% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 13 0.18% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7192 # Writes before turning the bus around for reads -system.physmem.totQLat 9007685000 # Total ticks spent queuing -system.physmem.totMemAccLat 17475691250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2258135000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19944.97 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 64910 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 527.930488 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 320.008348 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.202697 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14944 23.02% 23.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11454 17.65% 40.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5213 8.03% 48.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2920 4.50% 53.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2279 3.51% 56.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1787 2.75% 59.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1551 2.39% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1716 2.64% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23046 35.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64910 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5635 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 73.021650 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2812.727565 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5632 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5635 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5635 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.996806 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.958563 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 19.289473 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4843 85.94% 85.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 143 2.54% 88.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 10 0.18% 88.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 227 4.03% 92.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 45 0.80% 93.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 4 0.07% 93.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 10 0.18% 93.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.18% 93.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 34 0.60% 94.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.11% 94.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.09% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.04% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 9 0.16% 94.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.04% 94.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.07% 95.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.02% 95.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 41 0.73% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 13 0.23% 95.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.04% 96.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 176 3.12% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.09% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.05% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 3 0.05% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 6 0.11% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.05% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 6 0.11% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 10 0.18% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 6 0.11% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5635 # Writes before turning the bus around for reads +system.physmem.totQLat 3887945250 # Total ticks spent queuing +system.physmem.totMemAccLat 11603289000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2057425000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9448.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38694.97 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.16 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.17 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28198.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.04 # Average write queue length when enqueuing -system.physmem.readRowHits 408104 # Number of row buffer hits during reads -system.physmem.writeRowHits 99226 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.92 # Row buffer hit rate for writes -system.physmem.avgGap 3318713.65 # Average gap between requests -system.physmem.pageHitRate 88.35 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1805036475500 # Time in different power states -system.physmem.memoryStateTime::REF 63652420000 # Time in different power states +system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing +system.physmem.readRowHits 371100 # Number of row buffer hits during reads +system.physmem.writeRowHits 99427 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.20 # Row buffer hit rate for writes +system.physmem.avgGap 3552902.32 # Average gap between requests +system.physmem.pageHitRate 87.87 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1802319562500 # Time in different power states +system.physmem.memoryStateTime::REF 63549460000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37517744500 # Time in different power states +system.physmem.memoryStateTime::ACT 37254262500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 19340215 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296416 # Transaction distribution -system.membus.trans_dist::ReadResp 296338 # Transaction distribution -system.membus.trans_dist::WriteReq 12317 # Transaction distribution -system.membus.trans_dist::WriteResp 12317 # Transaction distribution -system.membus.trans_dist::Writeback 122625 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1033 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3220 # Transaction distribution -system.membus.trans_dist::ReadExReq 163308 # Transaction distribution -system.membus.trans_dist::ReadExResp 163210 # Transaction distribution -system.membus.trans_dist::BadAddressError 78 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39026 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 910934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 950116 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124653 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124653 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1074769 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 67930 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31453376 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31521306 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306944 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5306944 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36828250 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36828250 # Total data (bytes) -system.membus.snoop_data_through_bus 38208 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 36079499 # Layer occupancy (ticks) +system.membus.throughput 18054612 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296849 # Transaction distribution +system.membus.trans_dist::ReadResp 296569 # Transaction distribution +system.membus.trans_dist::WriteReq 12351 # Transaction distribution +system.membus.trans_dist::WriteResp 12351 # Transaction distribution +system.membus.trans_dist::Writeback 82427 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5284 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1479 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3444 # Transaction distribution +system.membus.trans_dist::ReadExReq 122594 # Transaction distribution +system.membus.trans_dist::ReadExResp 122459 # Transaction distribution +system.membus.trans_dist::BadAddressError 280 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39092 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 916085 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 560 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 955737 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83294 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83294 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1039031 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68194 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31621440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31689634 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34349922 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34349922 # Total data (bytes) +system.membus.snoop_data_through_bus 10240 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 35504996 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1585687750 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1560042750 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 97000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 374000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3823460772 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3834491323 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376710991 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43141738 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 344852 # number of replacements -system.l2c.tags.tagsinuse 65305.335131 # Cycle average of tags in use -system.l2c.tags.total_refs 2605080 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 409986 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.354071 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7095487750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53708.677879 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5228.517850 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6139.451939 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 202.418952 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 26.268512 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.819529 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079781 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.093681 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003089 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000401 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996480 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65134 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2578 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5246 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6338 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 50733 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.993866 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27313168 # Number of tag accesses -system.l2c.tags.data_accesses 27313168 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 979450 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 788527 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 94097 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 31413 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1893487 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 833565 # number of Writeback hits -system.l2c.Writeback_hits::total 833565 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 46 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 221 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 27 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 20 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 47 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 175693 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 7721 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183414 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 979450 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 964220 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 94097 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 39134 # number of demand (read+write) hits -system.l2c.demand_hits::total 2076901 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 979450 # number of overall hits -system.l2c.overall_hits::cpu0.data 964220 # number of overall hits -system.l2c.overall_hits::cpu1.inst 94097 # number of overall hits -system.l2c.overall_hits::cpu1.data 39134 # number of overall hits -system.l2c.overall_hits::total 2076901 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 14127 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273418 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1173 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 340 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289058 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 511 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2953 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 34 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 76 # 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number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1071252992 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17895085485 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 90289500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 26594999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 19083222976 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1079964 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 402483 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1482447 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 116495 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 68997 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 185492 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9654052371 # 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mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.952645 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.878444 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.938855 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.636364 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.735714 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.694561 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.433880 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.237142 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.393862 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015244 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.356133 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010503 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.049239 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.163038 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015244 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.356133 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010503 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.049239 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.163038 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63778.895769 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53148.244515 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65459.688256 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 78863.058152 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 53904.606206 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10021.580583 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.367159 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10021.369586 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10262.873016 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10059.203883 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10136.500000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70314.625224 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84710.913565 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72077.706793 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63778.895769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58011.646357 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65459.688256 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84046.157056 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59312.009753 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63778.895769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58011.646357 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65459.688256 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 84046.157056 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59312.009753 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -648,102 +649,94 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41700 # number of replacements -system.iocache.tags.tagsinuse 0.491390 # Cycle average of tags in use +system.iocache.tags.replacements 41695 # number of replacements +system.iocache.tags.tagsinuse 0.219567 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41716 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711322153000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.491390 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.030712 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.030712 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1710336549000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.219567 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.013723 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.013723 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375588 # Number of tag accesses -system.iocache.tags.data_accesses 375588 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 180 # number of ReadReq misses -system.iocache.ReadReq_misses::total 180 # number of ReadReq misses -system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41732 # number of demand (read+write) misses -system.iocache.demand_misses::total 41732 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41732 # number of overall misses -system.iocache.overall_misses::total 41732 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22063883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22063883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12446165943 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12446165943 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12468229826 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12468229826 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12468229826 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12468229826 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 180 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 180 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41732 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41732 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41732 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41732 # number of overall (read+write) accesses +system.iocache.tags.tag_accesses 375543 # Number of tag accesses +system.iocache.tags.data_accesses 375543 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses +system.iocache.demand_misses::total 175 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 175 # number of overall misses +system.iocache.overall_misses::total 175 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21364383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21364383 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21364383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21364383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21364383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21364383 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122577.127778 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122577.127778 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299532.295509 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 299532.295509 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 298769.045960 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 298769.045960 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 298769.045960 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 298769.045960 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 366756 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122082.188571 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122082.188571 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122082.188571 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122082.188571 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122082.188571 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122082.188571 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28394 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.916673 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 180 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 180 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41732 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41732 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41732 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41732 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12701883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12701883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10283217961 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10283217961 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10295919844 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10295919844 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10295919844 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10295919844 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12263383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12263383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2507056568 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2507056568 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12263383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12263383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12263383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12263383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70566.016667 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70566.016667 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247478.291322 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 247478.291322 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246715.226780 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 246715.226780 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246715.226780 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 246715.226780 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70076.474286 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60335.400655 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60335.400655 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70076.474286 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70076.474286 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -757,35 +750,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 13535285 # Number of BP lookups -system.cpu0.branchPred.condPredicted 11399113 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 368683 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 9302001 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5741441 # Number of BTB hits +system.cpu0.branchPred.lookups 13702956 # Number of BP lookups +system.cpu0.branchPred.condPredicted 11991857 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 276088 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 8588922 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4683455 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 61.722644 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 871515 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 32576 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 54.529020 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 677984 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 15448 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9655924 # DTB read hits -system.cpu0.dtb.read_misses 34371 # DTB read misses -system.cpu0.dtb.read_acv 569 # DTB read access violations -system.cpu0.dtb.read_accesses 673777 # DTB read accesses -system.cpu0.dtb.write_hits 6329246 # DTB write hits -system.cpu0.dtb.write_misses 8477 # DTB write misses -system.cpu0.dtb.write_acv 351 # DTB write access violations -system.cpu0.dtb.write_accesses 236111 # DTB write accesses -system.cpu0.dtb.data_hits 15985170 # DTB hits -system.cpu0.dtb.data_misses 42848 # DTB misses -system.cpu0.dtb.data_acv 920 # DTB access violations -system.cpu0.dtb.data_accesses 909888 # DTB accesses -system.cpu0.itb.fetch_hits 1092484 # ITB hits -system.cpu0.itb.fetch_misses 31809 # ITB misses -system.cpu0.itb.fetch_acv 996 # ITB acv -system.cpu0.itb.fetch_accesses 1124293 # ITB accesses +system.cpu0.dtb.read_hits 7950804 # DTB read hits +system.cpu0.dtb.read_misses 30543 # DTB read misses +system.cpu0.dtb.read_acv 546 # DTB read access violations +system.cpu0.dtb.read_accesses 683229 # DTB read accesses +system.cpu0.dtb.write_hits 5159026 # DTB write hits +system.cpu0.dtb.write_misses 6845 # DTB write misses +system.cpu0.dtb.write_acv 353 # DTB write access violations +system.cpu0.dtb.write_accesses 234573 # DTB write accesses +system.cpu0.dtb.data_hits 13109830 # DTB hits +system.cpu0.dtb.data_misses 37388 # DTB misses +system.cpu0.dtb.data_acv 899 # DTB access violations +system.cpu0.dtb.data_accesses 917802 # DTB accesses +system.cpu0.itb.fetch_hits 1312718 # ITB hits +system.cpu0.itb.fetch_misses 29261 # ITB misses +system.cpu0.itb.fetch_acv 629 # ITB acv +system.cpu0.itb.fetch_accesses 1341979 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -798,304 +791,304 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 120980731 # number of cpu cycles simulated +system.cpu0.numCycles 99665250 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 27854466 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 69491073 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13535285 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6612956 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12980522 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1985487 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 37586938 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31052 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 209286 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 361146 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 209 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8301805 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 269407 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 80329317 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.865077 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.209142 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 22511576 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 60582407 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 13702956 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5361439 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 70984108 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 933480 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 621 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 27412 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1463366 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 292819 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7109889 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 200075 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 95746858 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.632735 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.928110 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67348795 83.84% 83.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 826622 1.03% 84.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1640547 2.04% 86.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 764329 0.95% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2736993 3.41% 91.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 565546 0.70% 91.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 615994 0.77% 92.74% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1025224 1.28% 94.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4805267 5.98% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 84335489 88.08% 88.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 757900 0.79% 88.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1598110 1.67% 90.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 658612 0.69% 91.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2290747 2.39% 93.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 510807 0.53% 94.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 540667 0.56% 94.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 744782 0.78% 95.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4309744 4.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 80329317 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.111880 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.574398 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 28693302 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 37589637 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 12241193 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 539176 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1266008 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 554913 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 40031 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 68046301 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 123637 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1266008 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 29596220 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 13874520 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 19704370 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 11366279 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4521918 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 64294985 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 8881 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 963704 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 49626 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 1581472 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 42969329 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 77993479 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 77835647 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 147432 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36982529 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 5986792 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1597094 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 233553 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 9775023 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10212119 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6719453 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1264075 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 886942 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 56810323 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 2002217 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 55156303 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 107150 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 7195907 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 4115621 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1359252 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 80329317 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.686627 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.367653 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 95746858 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.137490 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.607859 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18154184 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 68366814 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 7221268 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1568077 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 436514 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 432928 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 30567 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 53177978 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 98719 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 436514 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18925396 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 44877173 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 16564638 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 7942906 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7000229 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 51314401 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 200370 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1702156 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 121650 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 3596195 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 34369689 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 62476617 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 62360377 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 107565 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30276917 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4092764 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1298231 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 191875 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11393500 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8037568 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5366781 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1135735 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 800748 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 45795204 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1644687 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 45103865 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 41971 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5328763 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2477826 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1134880 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 95746858 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.471074 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.201865 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 56644741 70.52% 70.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10637349 13.24% 83.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4503428 5.61% 89.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3111745 3.87% 93.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2708967 3.37% 96.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1473067 1.83% 98.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 832512 1.04% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 359476 0.45% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 58032 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 76985468 80.41% 80.41% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 8252195 8.62% 89.02% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3430688 3.58% 92.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2350675 2.46% 95.06% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2374207 2.48% 97.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1175968 1.23% 98.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 779493 0.81% 99.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 300669 0.31% 99.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 97495 0.10% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 80329317 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 95746858 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 91428 11.87% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 367704 47.76% 59.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 310812 40.37% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 143906 17.61% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 398143 48.73% 66.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 274956 33.65% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3793 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 37662855 68.28% 68.29% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60369 0.11% 68.40% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.40% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 16864 0.03% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 10116560 18.34% 86.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6398898 11.60% 98.38% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 895081 1.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 30829458 68.35% 68.36% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46395 0.10% 68.46% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.46% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 26948 0.06% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8252345 18.30% 86.82% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5217820 11.57% 98.39% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 725236 1.61% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 55156303 # Type of FU issued -system.cpu0.iq.rate 0.455910 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 769944 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013959 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 190884663 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 65713674 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 53746277 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 634353 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 307759 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 299045 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 55590646 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 331808 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 587688 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 45103865 # Type of FU issued +system.cpu0.iq.rate 0.452554 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 817005 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018114 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 186342910 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 52562719 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43916640 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 470653 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 221373 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 216432 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 45663938 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 253152 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 522094 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1466473 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4362 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13302 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 593267 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 946690 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4799 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15752 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 387148 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18777 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 290466 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 13610 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 357638 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1266008 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10034082 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1132931 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 62323042 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 565721 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10212119 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6719453 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1762676 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 460962 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 503945 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13302 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 186944 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 388547 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 575491 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 54610252 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9715916 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 546050 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 436514 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 41413967 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1424350 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50298451 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 103444 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8037568 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5366781 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1456887 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 31578 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1238658 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15752 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 134081 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 309122 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 443203 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 44677716 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8001376 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 426148 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3510502 # number of nop insts executed -system.cpu0.iew.exec_refs 16068148 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8653897 # Number of branches executed -system.cpu0.iew.exec_stores 6352232 # Number of stores executed -system.cpu0.iew.exec_rate 0.451396 # Inst execution rate -system.cpu0.iew.wb_sent 54145867 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 54045322 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 27468175 # num instructions producing a value -system.cpu0.iew.wb_consumers 37895992 # num instructions consuming a value +system.cpu0.iew.exec_nop 2858560 # number of nop insts executed +system.cpu0.iew.exec_refs 13178604 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7039370 # Number of branches executed +system.cpu0.iew.exec_stores 5177228 # Number of stores executed +system.cpu0.iew.exec_rate 0.448278 # Inst execution rate +system.cpu0.iew.wb_sent 44227196 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44133072 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22691402 # num instructions producing a value +system.cpu0.iew.wb_consumers 31140086 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.446727 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.724831 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.442813 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.728688 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 7798809 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 642965 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 531823 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 79063309 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.688507 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.631609 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5846321 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 509807 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 407712 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 94708833 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.468364 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.405169 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 59272342 74.97% 74.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8075780 10.21% 85.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4311536 5.45% 90.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2381088 3.01% 93.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1583020 2.00% 95.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 598155 0.76% 96.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 490827 0.62% 97.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 478799 0.61% 97.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1871762 2.37% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 79035549 83.45% 83.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6314508 6.67% 90.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3292930 3.48% 93.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1802282 1.90% 95.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1366338 1.44% 96.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 489382 0.52% 97.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 366889 0.39% 97.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 390234 0.41% 98.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1650721 1.74% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 79063309 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 54435622 # Number of instructions committed -system.cpu0.commit.committedOps 54435622 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 94708833 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 44358216 # Number of instructions committed +system.cpu0.commit.committedOps 44358216 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14871832 # Number of memory references committed -system.cpu0.commit.loads 8745646 # Number of loads committed -system.cpu0.commit.membars 219982 # Number of memory barriers committed -system.cpu0.commit.branches 8204799 # Number of branches committed -system.cpu0.commit.fp_insts 296843 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 50375539 # Number of committed integer instructions. -system.cpu0.commit.function_calls 712916 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 3148922 5.78% 5.78% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 35215746 64.69% 70.48% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 59292 0.11% 70.59% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.59% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 16864 0.03% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8965628 16.47% 87.09% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 6132206 11.27% 98.36% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 895081 1.64% 100.00% # Class of committed instruction +system.cpu0.commit.refs 12070511 # Number of memory references committed +system.cpu0.commit.loads 7090878 # Number of loads committed +system.cpu0.commit.membars 170277 # Number of memory barriers committed +system.cpu0.commit.branches 6663650 # Number of branches committed +system.cpu0.commit.fp_insts 213529 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 41141903 # Number of committed integer instructions. +system.cpu0.commit.function_calls 549728 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2498518 5.63% 5.63% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 28814427 64.96% 70.59% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 45393 0.10% 70.69% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.69% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 26477 0.06% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 7261155 16.37% 87.13% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 4985127 11.24% 98.37% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 725236 1.63% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 54435622 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1871762 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 44358216 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1650721 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 139225703 # The number of ROB reads -system.cpu0.rob.rob_writes 125735253 # The number of ROB writes -system.cpu0.timesIdled 1168278 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 40651414 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3691427340 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 51290467 # Number of Instructions Simulated -system.cpu0.committedOps 51290467 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.358737 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.358737 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.423956 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.423956 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 71570668 # number of integer regfile reads -system.cpu0.int_regfile_writes 39014056 # number of integer regfile writes -system.cpu0.fp_regfile_reads 147010 # number of floating regfile reads -system.cpu0.fp_regfile_writes 148900 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1947197 # number of misc regfile reads -system.cpu0.misc_regfile_writes 897129 # number of misc regfile writes +system.cpu0.rob.rob_reads 143064224 # The number of ROB reads +system.cpu0.rob.rob_writes 101447849 # The number of ROB writes +system.cpu0.timesIdled 414726 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3918392 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3706577488 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 41863465 # Number of Instructions Simulated +system.cpu0.committedOps 41863465 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.380721 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.380721 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.420041 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.420041 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 58777310 # number of integer regfile reads +system.cpu0.int_regfile_writes 31962259 # number of integer regfile writes +system.cpu0.fp_regfile_reads 106639 # number of floating regfile reads +system.cpu0.fp_regfile_writes 106808 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1588469 # number of misc regfile reads +system.cpu0.misc_regfile_writes 729535 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1127,49 +1120,50 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 111935595 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2200566 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2200471 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12317 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12317 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 833565 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 4571 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1080 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 5651 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 347592 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 306043 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1987262 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3563495 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 190571 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 127415 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5868743 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63588928 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 138451052 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 6097280 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4501998 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 212639258 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 212628634 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 743808 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5019455896 # Layer occupancy (ticks) +system.toL2Bus.throughput 115690704 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2250904 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2250609 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12351 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12351 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 841911 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41559 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 5326 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1552 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 6878 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 312265 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 312265 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 280 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1525692 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2740000 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 708608 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1000724 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5975024 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 48817472 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 104660497 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22674112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39558737 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 215710818 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 215700578 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4473152 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5085967365 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 747000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 720000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4476579522 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3437989936 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 6206391842 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4906988127 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 429200431 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 227242208 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1431950 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7376 # Transaction distribution -system.iobus.trans_dist::ReadResp 7376 # Transaction distribution -system.iobus.trans_dist::WriteReq 53869 # Transaction distribution -system.iobus.trans_dist::WriteResp 53869 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10422 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.toL2Bus.respLayer2.occupancy 1597018302 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 1654443775 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) +system.iobus.throughput 1434388 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7370 # Transaction distribution +system.iobus.trans_dist::ReadResp 7370 # Transaction distribution +system.iobus.trans_dist::WriteReq 53903 # Transaction distribution +system.iobus.trans_dist::WriteResp 53903 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10492 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1180,12 +1174,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39026 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83464 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83464 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122490 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41688 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39092 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122546 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1196,14 +1190,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 67930 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2729594 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2729594 # Total data (bytes) -system.iobus.reqLayer0.occupancy 9777000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 68194 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2729818 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2729818 # Total data (bytes) +system.iobus.reqLayer0.occupancy 9847000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1223,267 +1217,267 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380161835 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374411689 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26709000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26741000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43245009 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42019262 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 993039 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.694749 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7257459 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 993551 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.304566 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26718502250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.694749 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995498 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995498 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9295490 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9295490 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 7257459 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7257459 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7257459 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7257459 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7257459 # number of overall hits -system.cpu0.icache.overall_hits::total 7257459 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1044346 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1044346 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1044346 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1044346 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1044346 # number of overall misses -system.cpu0.icache.overall_misses::total 1044346 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14667970749 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14667970749 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14667970749 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14667970749 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14667970749 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14667970749 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8301805 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8301805 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8301805 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8301805 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8301805 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8301805 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125797 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.125797 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125797 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.125797 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125797 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.125797 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14045.125609 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14045.125609 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14045.125609 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14045.125609 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14045.125609 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14045.125609 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4303 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 762211 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.848890 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6309809 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 762721 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.272762 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26485928250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.848890 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993845 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 418 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 7872808 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 7872808 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6309809 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6309809 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6309809 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6309809 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6309809 # number of overall hits +system.cpu0.icache.overall_hits::total 6309809 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 800080 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 800080 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 800080 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 800080 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 800080 # number of overall misses +system.cpu0.icache.overall_misses::total 800080 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11341096711 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11341096711 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11341096711 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11341096711 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11341096711 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11341096711 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7109889 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7109889 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7109889 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7109889 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7109889 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7109889 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.112531 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.112531 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.112531 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.112531 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.112531 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.112531 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14174.953393 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14174.953393 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14174.953393 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14174.953393 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14174.953393 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14174.953393 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3387 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 182 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.642857 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.907407 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 50661 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 50661 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 50661 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 50661 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 50661 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 50661 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 993685 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 993685 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 993685 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 993685 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 993685 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 993685 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12074149969 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12074149969 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12074149969 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12074149969 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12074149969 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12074149969 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.119695 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.119695 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.119695 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12150.882794 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12150.882794 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12150.882794 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37161 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 37161 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 37161 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 37161 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 37161 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 37161 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 762919 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 762919 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 762919 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 762919 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 762919 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 762919 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9350852559 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9350852559 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9350852559 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9350852559 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9350852559 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9350852559 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.107304 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.107304 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.107304 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12256.678047 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12256.678047 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12256.678047 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1357625 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.932074 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11305784 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1358137 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.324480 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 25366000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.932074 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990102 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.990102 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 1069035 # number of replacements +system.cpu0.dcache.tags.tagsinuse 482.779727 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9141371 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1069547 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.546956 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 25151000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.779727 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.942929 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.942929 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 229 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 61088591 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 61088591 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6897589 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6897589 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4012977 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4012977 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 181053 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 181053 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208423 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 208423 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10910566 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10910566 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10910566 # number of overall hits -system.cpu0.dcache.overall_hits::total 10910566 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1718976 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1718976 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1889613 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1889613 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22934 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22934 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 507 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 507 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3608589 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3608589 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3608589 # number of overall misses -system.cpu0.dcache.overall_misses::total 3608589 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42674970043 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 42674970043 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 81294445080 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 81294445080 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 374188245 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 374188245 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3007034 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3007034 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 123969415123 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 123969415123 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 123969415123 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 123969415123 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8616565 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8616565 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5902590 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5902590 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 203987 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203987 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 208930 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 208930 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14519155 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14519155 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14519155 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14519155 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199497 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.199497 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320133 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.320133 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112429 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112429 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002427 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002427 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248540 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248540 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248540 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248540 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24825.809111 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 24825.809111 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43021.743119 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43021.743119 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16315.873594 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16315.873594 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5931.033531 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5931.033531 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34353.985761 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34353.985761 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34353.985761 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34353.985761 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 3433420 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 538 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 116463 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 29.480779 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 76.857143 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 49546788 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 49546788 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5665393 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5665393 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3152024 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3152024 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147109 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147109 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 170256 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 170256 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8817417 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8817417 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8817417 # number of overall hits +system.cpu0.dcache.overall_hits::total 8817417 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1322171 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1322171 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1644281 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1644281 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16610 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16610 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 766 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 766 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2966452 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2966452 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2966452 # number of overall misses +system.cpu0.dcache.overall_misses::total 2966452 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36169344894 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 36169344894 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74324803897 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 74324803897 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 267182493 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 267182493 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4788059 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4788059 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 110494148791 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 110494148791 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 110494148791 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 110494148791 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6987564 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6987564 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4796305 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4796305 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 163719 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 163719 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 171022 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 171022 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11783869 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11783869 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11783869 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11783869 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.189218 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.189218 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.342822 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.342822 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101454 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101454 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004479 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004479 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.251738 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.251738 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251738 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.251738 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27356.026485 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27356.026485 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45202.008596 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45202.008596 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16085.640759 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16085.640759 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6250.729765 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6250.729765 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37247.913936 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 37247.913936 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37247.913936 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 37247.913936 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 3702426 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3454 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 160595 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 88 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.054429 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 39.250000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 808609 # number of writebacks -system.cpu0.dcache.writebacks::total 808609 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 667238 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 667238 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1594728 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1594728 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5762 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5762 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2261966 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2261966 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2261966 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2261966 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1051738 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1051738 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 294885 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 294885 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17172 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17172 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 507 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 507 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1346623 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1346623 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1346623 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1346623 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27880739944 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27880739944 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12002536573 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12002536573 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 202887753 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 202887753 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1992966 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1992966 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 39883276517 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 39883276517 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 39883276517 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 39883276517 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1460997001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1460997001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2069284998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2069284998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3530281999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3530281999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122060 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122060 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049959 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049959 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.084182 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.084182 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002427 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002427 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092748 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092748 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092748 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092748 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26509.206612 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26509.206612 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40702.431704 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40702.431704 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11815.033368 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11815.033368 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3930.899408 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3930.899408 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29617.254805 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29617.254805 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29617.254805 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29617.254805 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 568073 # number of writebacks +system.cpu0.dcache.writebacks::total 568073 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 499697 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 499697 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1402831 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1402831 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4326 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4326 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1902528 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1902528 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1902528 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1902528 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 822474 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 822474 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 241450 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 241450 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12284 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12284 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 766 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 766 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1063924 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1063924 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1063924 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1063924 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24909734008 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24909734008 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10782476086 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10782476086 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 145144507 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145144507 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3254941 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3254941 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35692210094 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 35692210094 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35692210094 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 35692210094 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 992378000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 992378000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1672126998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1672126998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2664504998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2664504998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117705 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117705 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050341 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050341 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075031 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075031 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004479 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004479 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090286 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.090286 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090286 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.090286 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30286.348271 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30286.348271 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44657.179896 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44657.179896 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11815.736486 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11815.736486 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4249.270235 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4249.270235 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33547.706503 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33547.706503 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33547.706503 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33547.706503 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1491,35 +1485,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 1483279 # Number of BP lookups -system.cpu1.branchPred.condPredicted 1227619 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 44770 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 650934 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 463612 # Number of BTB hits +system.cpu1.branchPred.lookups 5770916 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5004196 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 122577 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 3556553 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1526133 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 71.222582 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 99211 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 4550 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 42.910453 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 301064 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7748 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1187167 # DTB read hits -system.cpu1.dtb.read_misses 8989 # DTB read misses -system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 276351 # DTB read accesses -system.cpu1.dtb.write_hits 628916 # DTB write hits -system.cpu1.dtb.write_misses 1890 # DTB write misses -system.cpu1.dtb.write_acv 35 # DTB write access violations -system.cpu1.dtb.write_accesses 104365 # DTB write accesses -system.cpu1.dtb.data_hits 1816083 # DTB hits -system.cpu1.dtb.data_misses 10879 # DTB misses -system.cpu1.dtb.data_acv 41 # DTB access violations -system.cpu1.dtb.data_accesses 380716 # DTB accesses -system.cpu1.itb.fetch_hits 316911 # ITB hits -system.cpu1.itb.fetch_misses 5517 # ITB misses -system.cpu1.itb.fetch_acv 125 # ITB acv -system.cpu1.itb.fetch_accesses 322428 # ITB accesses +system.cpu1.dtb.read_hits 3015540 # DTB read hits +system.cpu1.dtb.read_misses 12269 # DTB read misses +system.cpu1.dtb.read_acv 5 # DTB read access violations +system.cpu1.dtb.read_accesses 293761 # DTB read accesses +system.cpu1.dtb.write_hits 1836726 # DTB write hits +system.cpu1.dtb.write_misses 2353 # DTB write misses +system.cpu1.dtb.write_acv 39 # DTB write access violations +system.cpu1.dtb.write_accesses 109652 # DTB write accesses +system.cpu1.dtb.data_hits 4852266 # DTB hits +system.cpu1.dtb.data_misses 14622 # DTB misses +system.cpu1.dtb.data_acv 44 # DTB access violations +system.cpu1.dtb.data_accesses 403413 # DTB accesses +system.cpu1.itb.fetch_hits 632341 # ITB hits +system.cpu1.itb.fetch_misses 5352 # ITB misses +system.cpu1.itb.fetch_acv 51 # ITB acv +system.cpu1.itb.fetch_accesses 637693 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1532,553 +1526,554 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 8637240 # number of cpu cycles simulated +system.cpu1.numCycles 26335588 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 2818807 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 7093634 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 1483279 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 562823 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1271731 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 278690 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 3719491 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 23500 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 54196 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 48363 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 46 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 894062 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 29430 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 8117811 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.873836 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.252237 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 9800268 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 22981944 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 5770916 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1827197 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14019681 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 419510 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 307 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 23776 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 208449 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 196331 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 2522136 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 89875 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 24458620 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.939626 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.331670 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 6846080 84.33% 84.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 64163 0.79% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 148479 1.83% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 110798 1.36% 88.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 183312 2.26% 90.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 76211 0.94% 91.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 83539 1.03% 92.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 57250 0.71% 93.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 547979 6.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 20375648 83.31% 83.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 230665 0.94% 84.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 464859 1.90% 86.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 295118 1.21% 87.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 600413 2.45% 89.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 204861 0.84% 90.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 257669 1.05% 91.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 270860 1.11% 92.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1758527 7.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 8117811 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.171731 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.821285 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 2872853 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 3821739 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1206360 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 38891 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 177967 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 63499 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 3800 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 6911640 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 11536 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 177967 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 2981399 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 177384 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 3223332 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1138018 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 419709 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 6319378 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 203 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 45248 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 5428 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 135690 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 4267087 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 7667393 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 7641550 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 21648 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 3453234 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 813853 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 270338 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 17002 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1051064 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1262745 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 687524 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 118324 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 74010 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 5585108 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 271421 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 5341703 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 20645 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1049804 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 612834 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 207573 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 8117811 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.658023 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.347544 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 24458620 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.219130 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.872657 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8213195 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 12716086 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2925937 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 406668 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 196733 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 189397 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 13167 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 19294426 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 40930 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 196733 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 8443455 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 3954170 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 7253500 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 3074788 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1535972 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 18421784 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 5378 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 385976 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 36959 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 551165 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 12165906 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 21959681 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 21890085 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 63650 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 10221482 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1944424 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 582778 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 59316 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 3316426 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 3128488 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1940399 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 395849 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 259099 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 16224994 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 722304 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 15758531 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 26415 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2553169 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1203962 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 524576 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 24458620 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.644294 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.366216 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 5813637 71.62% 71.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1034901 12.75% 84.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 447279 5.51% 89.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 322285 3.97% 93.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 244246 3.01% 96.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 126246 1.56% 98.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 72876 0.90% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 50809 0.63% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 5532 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 17964380 73.45% 73.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2773024 11.34% 84.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1191873 4.87% 89.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 895755 3.66% 93.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 840464 3.44% 96.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 400907 1.64% 98.40% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 238226 0.97% 99.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 113179 0.46% 99.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 40812 0.17% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 8117811 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 24458620 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 4295 3.26% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 76591 58.14% 61.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 50850 38.60% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 56470 15.54% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 184321 50.72% 66.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 122598 33.74% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.07% 0.07% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 3268625 61.19% 61.26% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 9680 0.18% 61.44% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.44% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 8881 0.17% 61.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.03% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1232456 23.07% 84.71% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 646098 12.10% 96.80% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 170686 3.20% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 10371294 65.81% 65.84% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 24284 0.15% 65.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11773 0.07% 66.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 3139820 19.92% 86.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1865147 11.84% 97.84% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 340936 2.16% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 5341703 # Type of FU issued -system.cpu1.iq.rate 0.618450 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 131736 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.024662 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 18885884 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 6873502 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 5132762 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 67714 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 33978 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 32480 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 5434957 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 34964 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 63957 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 15758531 # Type of FU issued +system.cpu1.iq.rate 0.598374 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 363389 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.023060 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 56111313 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 19387392 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 15262127 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 254173 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 119441 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 117263 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 15982004 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 136398 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 157695 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 266370 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 353 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1238 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 98626 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 453605 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1302 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 6552 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 197079 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 353 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 72939 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 5589 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 74646 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 177967 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 80772 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 78093 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 6077668 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 83087 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1262745 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 687524 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 253926 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4593 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 73335 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1238 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 19913 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 60148 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 80061 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 5287979 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1198929 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 53724 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 196733 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 3102898 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 407577 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 17959821 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 47400 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 3128488 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1940399 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 647154 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 24325 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 312873 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 6552 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 58721 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 143362 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 202083 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 15559963 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 3035862 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 198568 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 221139 # number of nop insts executed -system.cpu1.iew.exec_refs 1832774 # number of memory reference insts executed -system.cpu1.iew.exec_branches 762873 # Number of branches executed -system.cpu1.iew.exec_stores 633845 # Number of stores executed -system.cpu1.iew.exec_rate 0.612230 # Inst execution rate -system.cpu1.iew.wb_sent 5189273 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 5165242 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 2532511 # num instructions producing a value -system.cpu1.iew.wb_consumers 3587094 # num instructions consuming a value +system.cpu1.iew.exec_nop 1012523 # number of nop insts executed +system.cpu1.iew.exec_refs 4881099 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2446532 # Number of branches executed +system.cpu1.iew.exec_stores 1845237 # Number of stores executed +system.cpu1.iew.exec_rate 0.590834 # Inst execution rate +system.cpu1.iew.wb_sent 15420680 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 15379390 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 7566791 # num instructions producing a value +system.cpu1.iew.wb_consumers 10761562 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.598020 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.706006 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.583977 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.703131 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1065222 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 63848 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 75650 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 7939844 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.623951 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.560784 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 2776166 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 197728 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 185190 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 23976589 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.630910 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.597118 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 6043541 76.12% 76.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 925286 11.65% 87.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 320402 4.04% 91.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 190890 2.40% 94.21% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 129096 1.63% 95.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 57238 0.72% 96.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 65164 0.82% 97.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 44060 0.55% 97.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 164167 2.07% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 18550941 77.37% 77.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2272481 9.48% 86.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1151381 4.80% 91.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 578443 2.41% 94.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 385291 1.61% 95.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 189866 0.79% 96.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 157998 0.66% 97.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 143488 0.60% 97.72% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 546700 2.28% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 7939844 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 4954074 # Number of instructions committed -system.cpu1.commit.committedOps 4954074 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 23976589 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 15127070 # Number of instructions committed +system.cpu1.commit.committedOps 15127070 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1585273 # Number of memory references committed -system.cpu1.commit.loads 996375 # Number of loads committed -system.cpu1.commit.membars 16576 # Number of memory barriers committed -system.cpu1.commit.branches 700739 # Number of branches committed -system.cpu1.commit.fp_insts 31280 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 4632533 # Number of committed integer instructions. -system.cpu1.commit.function_calls 77324 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 191990 3.88% 3.88% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 2969211 59.93% 63.81% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 9565 0.19% 64.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.00% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 8881 0.18% 64.18% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.18% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.18% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.18% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1759 0.04% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1012951 20.45% 84.66% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 589031 11.89% 96.55% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 170686 3.45% 100.00% # Class of committed instruction +system.cpu1.commit.refs 4418203 # Number of memory references committed +system.cpu1.commit.loads 2674883 # Number of loads committed +system.cpu1.commit.membars 66521 # Number of memory barriers committed +system.cpu1.commit.branches 2263870 # Number of branches committed +system.cpu1.commit.fp_insts 115331 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 13957396 # Number of committed integer instructions. +system.cpu1.commit.function_calls 240978 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 845832 5.59% 5.59% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 9417463 62.26% 67.85% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 23911 0.16% 68.01% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 68.01% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 11769 0.08% 68.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 68.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 68.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 68.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.01% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 2741404 18.12% 86.22% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1743996 11.53% 97.75% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 340936 2.25% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 4954074 # Class of committed instruction -system.cpu1.commit.bw_lim_events 164167 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 15127070 # Class of committed instruction +system.cpu1.commit.bw_lim_events 546700 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 13715407 # The number of ROB reads -system.cpu1.rob.rob_writes 12215098 # The number of ROB writes -system.cpu1.timesIdled 57372 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 519429 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3803095502 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 4765602 # Number of Instructions Simulated -system.cpu1.committedOps 4765602 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.812413 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.812413 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.551751 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.551751 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 6848640 # number of integer regfile reads -system.cpu1.int_regfile_writes 3746417 # number of integer regfile writes -system.cpu1.fp_regfile_reads 21244 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19994 # number of floating regfile writes -system.cpu1.misc_regfile_reads 693471 # number of misc regfile reads -system.cpu1.misc_regfile_writes 115172 # number of misc regfile writes -system.cpu1.icache.tags.replacements 94727 # number of replacements -system.cpu1.icache.tags.tagsinuse 453.369242 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 794363 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 95239 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 8.340732 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1880860642000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.369242 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885487 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.885487 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 41251186 # The number of ROB reads +system.cpu1.rob.rob_writes 36287802 # The number of ROB writes +system.cpu1.timesIdled 194891 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1876968 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3779240330 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 14284756 # Number of Instructions Simulated +system.cpu1.committedOps 14284756 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.843615 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.843615 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.542413 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.542413 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 20099122 # number of integer regfile reads +system.cpu1.int_regfile_writes 11015819 # number of integer regfile writes +system.cpu1.fp_regfile_reads 63024 # number of floating regfile reads +system.cpu1.fp_regfile_writes 62672 # number of floating regfile writes +system.cpu1.misc_regfile_reads 1065455 # number of misc regfile reads +system.cpu1.misc_regfile_writes 283847 # number of misc regfile writes +system.cpu1.icache.tags.replacements 353746 # number of replacements +system.cpu1.icache.tags.tagsinuse 504.553851 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 2153244 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 354258 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.078180 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 47615844250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.553851 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.985457 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.985457 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 989361 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 989361 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 794363 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 794363 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 794363 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 794363 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 794363 # number of overall hits -system.cpu1.icache.overall_hits::total 794363 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 99697 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 99697 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 99697 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 99697 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 99697 # number of overall misses -system.cpu1.icache.overall_misses::total 99697 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1381976879 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1381976879 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1381976879 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1381976879 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1381976879 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1381976879 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 894060 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 894060 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 894060 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 894060 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 894060 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 894060 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.111510 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.111510 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.111510 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.111510 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.111510 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.111510 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13861.769953 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13861.769953 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13861.769953 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13861.769953 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13861.769953 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13861.769953 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 350 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 2876460 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 2876460 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 2153244 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 2153244 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 2153244 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 2153244 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 2153244 # number of overall hits +system.cpu1.icache.overall_hits::total 2153244 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 368891 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 368891 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 368891 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 368891 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 368891 # number of overall misses +system.cpu1.icache.overall_misses::total 368891 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5137931940 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5137931940 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5137931940 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5137931940 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5137931940 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5137931940 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 2522135 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2522135 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 2522135 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 2522135 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 2522135 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 2522135 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146261 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.146261 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146261 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.146261 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.146261 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.146261 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13928.049044 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13928.049044 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13928.049044 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13928.049044 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13928.049044 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13928.049044 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1327 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 55 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.217391 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 24.127273 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 4396 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 4396 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 4396 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 4396 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 4396 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 4396 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 95301 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 95301 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 95301 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 95301 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 95301 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 95301 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1139734069 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1139734069 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1139734069 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1139734069 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1139734069 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1139734069 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.106594 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.106594 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.106594 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11959.308601 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11959.308601 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11959.308601 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 14566 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 14566 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 14566 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 14566 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 14566 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 14566 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 354325 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 354325 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 354325 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 354325 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 354325 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 354325 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4259071697 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4259071697 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4259071697 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4259071697 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4259071697 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4259071697 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.140486 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.140486 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.140486 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12020.240449 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12020.240449 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12020.240449 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 45361 # number of replacements -system.cpu1.dcache.tags.tagsinuse 428.999436 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 1451630 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 45680 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 31.778240 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1880566804000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 428.999436 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.837890 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.837890 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.623047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 6609919 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 6609919 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 960992 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 960992 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 477143 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 477143 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 12504 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 12504 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 10799 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 10799 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1438135 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1438135 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1438135 # number of overall hits -system.cpu1.dcache.overall_hits::total 1438135 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 81302 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 81302 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 95545 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 95545 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1156 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1156 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 573 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 573 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 176847 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 176847 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 176847 # number of overall misses -system.cpu1.dcache.overall_misses::total 176847 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1110177095 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1110177095 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5046033431 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 5046033431 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 13905498 # 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number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 13660 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 13660 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 11372 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 11372 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1614982 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1614982 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1614982 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1614982 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.078003 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.078003 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.166836 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.166836 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.084627 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.084627 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.050387 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.050387 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.109504 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.109504 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.109504 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.109504 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13654.978906 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13654.978906 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 52813.160615 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 52813.160615 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12028.977509 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12028.977509 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7211.300175 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7211.300175 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34810.941243 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 34810.941243 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34810.941243 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 34810.941243 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 236601 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6165 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 38.378102 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.tags.replacements 360788 # number of replacements +system.cpu1.dcache.tags.tagsinuse 496.086183 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3613456 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 361109 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 10.006552 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 40126349500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 496.086183 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968918 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.968918 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.626953 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 18510307 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 18510307 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2220866 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2220866 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1307515 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1307515 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 45364 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 45364 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 48883 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 48883 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3528381 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3528381 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3528381 # number of overall hits +system.cpu1.dcache.overall_hits::total 3528381 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 524895 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 524895 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 378889 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 378889 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8897 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8897 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 786 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 786 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 903784 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 903784 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 903784 # number of overall misses +system.cpu1.dcache.overall_misses::total 903784 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8191623763 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 8191623763 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 14087810149 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 14087810149 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 135761491 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 135761491 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5726098 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5726098 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 22279433912 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 22279433912 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 22279433912 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 22279433912 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2745761 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2745761 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1686404 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1686404 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 54261 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 54261 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 49669 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 49669 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4432165 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4432165 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4432165 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4432165 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.191166 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.191166 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.224673 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.224673 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.163967 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.163967 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.015825 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.015825 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.203915 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.203915 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.203915 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.203915 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15606.214125 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15606.214125 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37181.892715 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 37181.892715 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15259.243678 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15259.243678 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7285.111959 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7285.111959 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24651.281625 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24651.281625 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24651.281625 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24651.281625 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 560522 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 381 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 27149 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.646138 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 20.052632 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 24956 # number of writebacks -system.cpu1.dcache.writebacks::total 24956 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 46173 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 46173 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 80581 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 80581 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 235 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 235 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 126754 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 126754 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 126754 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 126754 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35129 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 35129 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 14964 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 14964 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 921 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 921 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 573 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 573 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 50093 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 50093 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 50093 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 50093 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 398615352 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 398615352 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 730663501 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 730663501 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8358752 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8358752 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2984925 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2984925 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1129278853 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1129278853 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1129278853 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1129278853 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 22397000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 22397000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 533147000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 533147000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555544000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555544000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033704 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033704 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026129 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067423 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067423 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.050387 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.050387 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031018 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031018 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031018 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031018 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11347.187566 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11347.187566 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48828.087477 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 48828.087477 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9075.735071 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9075.735071 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5209.293194 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5209.293194 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22543.645879 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22543.645879 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22543.645879 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22543.645879 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 273838 # number of writebacks +system.cpu1.dcache.writebacks::total 273838 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 229504 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 229504 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 313811 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 313811 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1705 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1705 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 543315 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 543315 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 543315 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 543315 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 295391 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 295391 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65078 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 65078 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7192 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7192 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 786 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 786 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 360469 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 360469 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 360469 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 360469 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3818838154 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3818838154 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2138006676 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2138006676 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 81043507 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 81043507 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4153902 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4153902 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5956844830 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5956844830 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5956844830 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5956844830 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 490391500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 490391500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 941927000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 941927000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1432318500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1432318500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.107581 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.107581 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038590 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038590 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.132545 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.132545 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.015825 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.015825 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.081330 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.081330 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.081330 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.081330 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12928.078899 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12928.078899 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32852.986816 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32852.986816 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11268.563265 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11268.563265 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5284.862595 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5284.862595 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16525.262450 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16525.262450 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16525.262450 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16525.262450 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2087,161 +2082,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6410 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 202830 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 72673 40.72% 40.72% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.07% 40.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1926 1.08% 41.87% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 6 0.00% 41.88% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 103726 58.12% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 178462 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71304 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.38% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1926 1.33% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 6 0.00% 50.72% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71298 49.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 144665 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1863558813000 97.76% 97.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63845500 0.00% 97.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 565237000 0.03% 97.80% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 3385500 0.00% 97.80% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 42015112000 2.20% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1906206393000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981162 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4820 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 161850 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 55184 39.67% 39.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 39.77% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1924 1.38% 41.15% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 41.16% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 81844 58.84% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 139099 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 54289 49.07% 49.07% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1924 1.74% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.01% 50.94% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 54273 49.06% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 110633 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1865924468000 98.05% 98.05% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 60967000 0.00% 98.05% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 531593000 0.03% 98.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8367000 0.00% 98.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 36597541500 1.92% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1903122936500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983782 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.687369 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810621 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed -system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed -system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 234 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.663127 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.795354 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.67% 28.44% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.44% 28.89% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.00% 32.89% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.44% 37.33% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.67% 40.00% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.44% 40.44% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.33% 41.78% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.11% 44.89% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.89% 45.78% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.00% 61.78% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.33% 63.11% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.44% 67.56% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.44% 72.00% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.44% 72.44% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.67% 75.11% # number of syscalls executed +system.cpu0.kern.syscall::71 25 11.11% 86.22% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.33% 87.56% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.67% 90.22% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.44% 90.67% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.33% 92.00% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.00% 96.00% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.89% 96.89% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.89% 97.78% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.44% 98.22% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.89% 99.11% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 225 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 95 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3930 2.10% 2.15% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.18% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed -system.cpu0.kern.callpal::swpipl 171605 91.48% 93.66% # number of callpals executed -system.cpu0.kern.callpal::rdps 6547 3.49% 97.15% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.16% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.16% # number of callpals executed -system.cpu0.kern.callpal::rti 4793 2.56% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.21% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 187581 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7378 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches +system.cpu0.kern.callpal::wripir 105 0.07% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2905 1.98% 2.05% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.09% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed +system.cpu0.kern.callpal::swpipl 132721 90.43% 92.52% # number of callpals executed +system.cpu0.kern.callpal::rdps 6135 4.18% 96.70% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.70% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::rti 4306 2.93% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 382 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 146768 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6331 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1342 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1369 -system.cpu0.kern.mode_good::user 1370 +system.cpu0.kern.mode_good::kernel 1341 +system.cpu0.kern.mode_good::user 1342 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.185552 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.211815 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.313100 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1904135221500 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2071163500 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.349668 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1901148119000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1974809500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3931 # number of times the context was actually changed +system.cpu0.kern.swap_context 2906 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2254 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 34590 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 8916 31.91% 31.91% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 6.89% 38.80% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 95 0.34% 39.14% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17006 60.86% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 27942 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 8908 45.12% 45.12% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 9.75% 54.88% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 95 0.48% 55.36% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 8813 44.64% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 19741 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1876395415500 98.45% 98.45% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 531818000 0.03% 98.48% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 44293500 0.00% 98.48% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 28895956000 1.52% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1905867483000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999103 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3853 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 75635 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26441 39.26% 39.26% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1922 2.85% 42.12% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 105 0.16% 42.27% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 38878 57.73% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 67346 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25959 48.22% 48.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1922 3.57% 51.78% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 105 0.20% 51.98% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25854 48.02% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53840 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1868834322000 98.22% 98.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 532397000 0.03% 98.24% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 48831000 0.00% 98.25% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 33374320500 1.75% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1902789870500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981771 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.518229 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.706499 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed -system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed -system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed -system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 92 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.665003 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.799454 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed +system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed +system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed +system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 101 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 298 1.04% 1.07% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.08% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.11% # number of callpals executed -system.cpu1.kern.callpal::swpipl 23527 82.20% 83.30% # number of callpals executed -system.cpu1.kern.callpal::rdps 2214 7.74% 91.04% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.04% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 91.05% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.06% # number of callpals executed -system.cpu1.kern.callpal::rti 2394 8.36% 99.43% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.42% 99.85% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.15% 100.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1334 1.92% 1.95% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 1.95% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 1.96% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62422 89.83% 91.80% # number of callpals executed +system.cpu1.kern.callpal::rdps 2621 3.77% 95.57% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 95.57% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 95.57% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 95.58% # number of callpals executed +system.cpu1.kern.callpal::rti 2896 4.17% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 133 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 28623 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 659 # number of protection mode switches -system.cpu1.kern.mode_switch::user 367 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2036 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 386 -system.cpu1.kern.mode_good::user 367 -system.cpu1.kern.mode_good::idle 19 -system.cpu1.kern.mode_switch_good::kernel 0.585736 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 69486 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1712 # number of protection mode switches +system.cpu1.kern.mode_switch::user 395 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2056 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 462 +system.cpu1.kern.mode_good::user 395 +system.cpu1.kern.mode_good::idle 67 +system.cpu1.kern.mode_switch_good::kernel 0.269860 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.009332 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.252123 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 1444110500 0.08% 0.08% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 692193000 0.04% 0.11% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1903401131500 99.89% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 299 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.032588 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.221955 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 38841912000 2.04% 2.04% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 712477500 0.04% 2.08% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1862932175500 97.92% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1335 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index f07e7eac0..6fda1994e 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,128 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.860172 # Number of seconds simulated -sim_ticks 1860172195000 # Number of ticks simulated -final_tick 1860172195000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.860009 # Number of seconds simulated +sim_ticks 1860008936000 # Number of ticks simulated +final_tick 1860008936000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152063 # Simulator instruction rate (inst/s) -host_op_rate 152063 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5340733222 # Simulator tick rate (ticks/s) -host_mem_usage 304984 # Number of bytes of host memory used -host_seconds 348.30 # Real time elapsed on the host -sim_insts 52963419 # Number of instructions simulated -sim_ops 52963419 # Number of ops (including micro ops) simulated +host_inst_rate 106543 # Simulator instruction rate (inst/s) +host_op_rate 106543 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3740252336 # Simulator tick rate (ticks/s) +host_mem_usage 320492 # Number of bytes of host memory used +host_seconds 497.30 # Real time elapsed on the host +sim_insts 52983264 # Number of instructions simulated +sim_ops 52983264 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 965120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24879104 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28496512 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 965120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 965120 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7515712 # Number of bytes written to this memory -system.physmem.bytes_written::total 7515712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15080 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388736 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445258 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117433 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117433 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 518834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13374624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1425829 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15319287 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 518834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4040331 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4040331 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4040331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 518834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13374624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1425829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19359618 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445258 # Number of read requests accepted -system.physmem.writeReqs 117433 # Number of write requests accepted -system.physmem.readBursts 445258 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117433 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28490432 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue -system.physmem.bytesWritten 7513664 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28496512 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7515712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 968512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24900352 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 25869824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 968512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 968512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4866048 # Number of bytes written to this memory +system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory +system.physmem.bytes_written::total 7525376 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15133 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 389068 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 404216 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 76032 # Number of write requests responded to by this memory +system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117584 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 520703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13387222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13908441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 520703 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 520703 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2616142 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1429739 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4045882 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2616142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 520703 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13387222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1430255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17954322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404216 # Number of read requests accepted +system.physmem.writeReqs 117584 # Number of write requests accepted +system.physmem.readBursts 404216 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117584 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25858752 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11072 # Total number of bytes read from write queue +system.physmem.bytesWritten 7523328 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25869824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7525376 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 173 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 176 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28223 # Per bank write bursts -system.physmem.perBankRdBursts::1 27968 # Per bank write bursts -system.physmem.perBankRdBursts::2 28292 # Per bank write bursts -system.physmem.perBankRdBursts::3 27927 # Per bank write bursts -system.physmem.perBankRdBursts::4 27805 # Per bank write bursts -system.physmem.perBankRdBursts::5 27242 # Per bank write bursts -system.physmem.perBankRdBursts::6 27352 # Per bank write bursts -system.physmem.perBankRdBursts::7 27274 # Per bank write bursts -system.physmem.perBankRdBursts::8 27691 # Per bank write bursts -system.physmem.perBankRdBursts::9 27508 # Per bank write bursts -system.physmem.perBankRdBursts::10 27933 # Per bank write bursts -system.physmem.perBankRdBursts::11 27527 # Per bank write bursts -system.physmem.perBankRdBursts::12 27552 # Per bank write bursts -system.physmem.perBankRdBursts::13 28225 # Per bank write bursts -system.physmem.perBankRdBursts::14 28330 # Per bank write bursts -system.physmem.perBankRdBursts::15 28314 # Per bank write bursts -system.physmem.perBankWrBursts::0 7932 # Per bank write bursts -system.physmem.perBankWrBursts::1 7496 # Per bank write bursts -system.physmem.perBankWrBursts::2 7821 # Per bank write bursts -system.physmem.perBankWrBursts::3 7427 # Per bank write bursts -system.physmem.perBankWrBursts::4 7353 # Per bank write bursts -system.physmem.perBankWrBursts::5 6703 # Per bank write bursts -system.physmem.perBankWrBursts::6 6854 # Per bank write bursts -system.physmem.perBankWrBursts::7 6665 # Per bank write bursts -system.physmem.perBankWrBursts::8 7118 # Per bank write bursts -system.physmem.perBankWrBursts::9 6889 # Per bank write bursts -system.physmem.perBankWrBursts::10 7323 # Per bank write bursts -system.physmem.perBankWrBursts::11 6981 # Per bank write bursts -system.physmem.perBankWrBursts::12 7116 # Per bank write bursts -system.physmem.perBankWrBursts::13 7874 # Per bank write bursts -system.physmem.perBankWrBursts::14 8055 # Per bank write bursts -system.physmem.perBankWrBursts::15 7794 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 213 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25622 # Per bank write bursts +system.physmem.perBankRdBursts::1 25451 # Per bank write bursts +system.physmem.perBankRdBursts::2 25608 # Per bank write bursts +system.physmem.perBankRdBursts::3 25528 # Per bank write bursts +system.physmem.perBankRdBursts::4 25399 # Per bank write bursts +system.physmem.perBankRdBursts::5 24757 # Per bank write bursts +system.physmem.perBankRdBursts::6 24940 # Per bank write bursts +system.physmem.perBankRdBursts::7 25074 # Per bank write bursts +system.physmem.perBankRdBursts::8 24966 # Per bank write bursts +system.physmem.perBankRdBursts::9 25053 # Per bank write bursts +system.physmem.perBankRdBursts::10 25586 # Per bank write bursts +system.physmem.perBankRdBursts::11 24884 # Per bank write bursts +system.physmem.perBankRdBursts::12 24485 # Per bank write bursts +system.physmem.perBankRdBursts::13 25285 # Per bank write bursts +system.physmem.perBankRdBursts::14 25789 # Per bank write bursts +system.physmem.perBankRdBursts::15 25616 # Per bank write bursts +system.physmem.perBankWrBursts::0 7925 # Per bank write bursts +system.physmem.perBankWrBursts::1 7509 # Per bank write bursts +system.physmem.perBankWrBursts::2 7974 # Per bank write bursts +system.physmem.perBankWrBursts::3 7525 # Per bank write bursts +system.physmem.perBankWrBursts::4 7335 # Per bank write bursts +system.physmem.perBankWrBursts::5 6682 # Per bank write bursts +system.physmem.perBankWrBursts::6 6769 # Per bank write bursts +system.physmem.perBankWrBursts::7 6701 # Per bank write bursts +system.physmem.perBankWrBursts::8 7135 # Per bank write bursts +system.physmem.perBankWrBursts::9 6719 # Per bank write bursts +system.physmem.perBankWrBursts::10 7431 # Per bank write bursts +system.physmem.perBankWrBursts::11 6970 # Per bank write bursts +system.physmem.perBankWrBursts::12 7113 # Per bank write bursts +system.physmem.perBankWrBursts::13 7882 # Per bank write bursts +system.physmem.perBankWrBursts::14 8065 # Per bank write bursts +system.physmem.perBankWrBursts::15 7817 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 1860166839000 # Total gap between requests +system.physmem.numWrRetry 9 # Number of times write queue was full causing retry +system.physmem.totGap 1860003602000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 445258 # Read request sizes (log2) +system.physmem.readPktSize::6 404216 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117433 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 38754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 44609 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9021 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2051 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1630 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1618 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1898 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 984 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 899 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117584 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 315071 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 37801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -148,282 +151,273 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1276 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6916 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 565.384925 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 351.672479 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 419.574374 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13299 20.88% 20.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10397 16.33% 37.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4628 7.27% 44.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2746 4.31% 48.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2553 4.01% 52.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1655 2.60% 55.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1376 2.16% 57.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1696 2.66% 60.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25330 39.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63680 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6888 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 64.625581 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 16.554610 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2544.325145 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 6885 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6888 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6888 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.044280 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.812634 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.762583 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5511 80.01% 80.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 31 0.45% 80.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 662 9.61% 90.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 220 3.19% 93.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 110 1.60% 94.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 25 0.36% 95.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 25 0.36% 95.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 91 1.32% 96.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 22 0.32% 97.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 31 0.45% 97.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 12 0.17% 97.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 22 0.32% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 6 0.09% 98.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 14 0.20% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.04% 98.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 16 0.23% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 12 0.17% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 7 0.10% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.01% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.01% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 3 0.04% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 4 0.06% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 4 0.06% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 4 0.06% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 6 0.09% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 3 0.04% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 3 0.04% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 7 0.10% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 2 0.03% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 1 0.01% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 2 0.03% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 2 0.03% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 1 0.01% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 1 0.01% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54 1 0.01% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 1 0.01% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 8 0.12% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 12 0.17% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6888 # Writes before turning the bus around for reads -system.physmem.totQLat 8740437500 # Total ticks spent queuing -system.physmem.totMemAccLat 17087243750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2225815000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19634.24 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 61090 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 546.434703 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 336.353089 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.871718 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13232 21.66% 21.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10443 17.09% 38.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4742 7.76% 46.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2710 4.44% 50.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2446 4.00% 54.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1597 2.61% 57.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1401 2.29% 59.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1610 2.64% 62.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22909 37.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61090 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5256 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.868151 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2912.510758 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5253 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5256 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5256 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.365297 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.103318 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.103778 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4494 85.50% 85.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 124 2.36% 87.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 9 0.17% 88.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 232 4.41% 92.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 40 0.76% 93.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 6 0.11% 93.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 12 0.23% 93.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.06% 93.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 27 0.51% 94.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.06% 94.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.02% 94.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.02% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 15 0.29% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.10% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.06% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 31 0.59% 95.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 8 0.15% 95.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 4 0.08% 95.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 5 0.10% 95.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 188 3.58% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 5 0.10% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.06% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.21% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.06% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 7 0.13% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 5 0.10% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5256 # Writes before turning the bus around for reads +system.physmem.totQLat 3626109250 # Total ticks spent queuing +system.physmem.totMemAccLat 11201915500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2020215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8974.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38384.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27724.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.91 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.05 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.65 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.75 # Average write queue length when enqueuing -system.physmem.readRowHits 403028 # Number of row buffer hits during reads -system.physmem.writeRowHits 95855 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.63 # Row buffer hit rate for writes -system.physmem.avgGap 3305840.75 # Average gap between requests -system.physmem.pageHitRate 88.68 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1761575145500 # Time in different power states -system.physmem.memoryStateTime::REF 62115040000 # Time in different power states +system.physmem.avgRdQLen 1.48 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing +system.physmem.readRowHits 364992 # Number of row buffer hits during reads +system.physmem.writeRowHits 95512 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.23 # Row buffer hit rate for writes +system.physmem.avgGap 3564591.03 # Average gap between requests +system.physmem.pageHitRate 88.28 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1761923491250 # Time in different power states +system.physmem.memoryStateTime::REF 62109580000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 36476358250 # Time in different power states +system.physmem.memoryStateTime::ACT 35970256750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 19402477 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 295985 # Transaction distribution -system.membus.trans_dist::ReadResp 295900 # Transaction distribution -system.membus.trans_dist::WriteReq 9597 # Transaction distribution -system.membus.trans_dist::WriteResp 9597 # Transaction distribution -system.membus.trans_dist::Writeback 117433 # Transaction distribution -system.membus.trans_dist::UpgradeReq 178 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 179 # Transaction distribution -system.membus.trans_dist::ReadExReq 156844 # Transaction distribution -system.membus.trans_dist::ReadExResp 156844 # Transaction distribution -system.membus.trans_dist::BadAddressError 85 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884181 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917405 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042084 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30703168 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30747308 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36056364 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36056364 # Total data (bytes) -system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29838500 # Layer occupancy (ticks) +system.membus.throughput 17983494 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296097 # Transaction distribution +system.membus.trans_dist::ReadResp 296008 # Transaction distribution +system.membus.trans_dist::WriteReq 9598 # Transaction distribution +system.membus.trans_dist::WriteResp 9598 # Transaction distribution +system.membus.trans_dist::Writeback 76032 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 207 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.membus.trans_dist::UpgradeResp 213 # Transaction distribution +system.membus.trans_dist::ReadExReq 115296 # Transaction distribution +system.membus.trans_dist::ReadExResp 115296 # Transaction distribution +system.membus.trans_dist::BadAddressError 89 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 178 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 918094 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1001386 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30734912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30779060 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 33439348 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 33439348 # Total data (bytes) +system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 29284000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1526200750 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1484965250 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 104500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 112000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3755175800 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3755505039 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376659242 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43151211 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.260971 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.268186 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710335831000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.260971 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078811 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078811 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1709354954000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.268186 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.079262 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.079262 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375525 # Number of tag accesses -system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.tags.tag_accesses 376037 # Number of tag accesses +system.iocache.tags.data_accesses 376037 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12441682213 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12441682213 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12462816596 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12462816596 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12462816596 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12462816596 # number of overall miss cycles +system.iocache.WriteInvalidateReq_misses::tsunami.ide 64 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 64 # number of WriteInvalidateReq misses +system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses +system.iocache.demand_misses::total 173 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 173 # number of overall misses +system.iocache.overall_misses::total 173 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41616 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41616 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.001538 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.001538 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299424.389031 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 299424.389031 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 298689.433098 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 298689.433098 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 298689.433098 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 298689.433098 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 366119 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28395 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.893784 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41512 # number of writebacks -system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10278710729 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10278710729 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10290848112 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10290848112 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10290848112 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10290848112 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2528134047 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2528134047 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.998462 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.998462 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247369.819239 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 247369.819239 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246635.065596 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 246635.065596 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246635.065596 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 246635.065596 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60842.656118 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60842.656118 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -437,36 +431,36 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13973676 # Number of BP lookups -system.cpu.branchPred.condPredicted 11739131 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 397652 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9590938 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5932533 # Number of BTB hits +system.cpu.branchPred.lookups 17833670 # Number of BP lookups +system.cpu.branchPred.condPredicted 15506350 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 381114 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12104225 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5926115 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.855608 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 905503 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 38808 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 48.959062 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 921355 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21398 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10112222 # DTB read hits -system.cpu.dtb.read_misses 41745 # DTB read misses -system.cpu.dtb.read_acv 542 # DTB read access violations -system.cpu.dtb.read_accesses 945441 # DTB read accesses -system.cpu.dtb.write_hits 6611008 # DTB write hits -system.cpu.dtb.write_misses 10791 # DTB write misses -system.cpu.dtb.write_acv 413 # DTB write access violations -system.cpu.dtb.write_accesses 339727 # DTB write accesses -system.cpu.dtb.data_hits 16723230 # DTB hits -system.cpu.dtb.data_misses 52536 # DTB misses -system.cpu.dtb.data_acv 955 # DTB access violations -system.cpu.dtb.data_accesses 1285168 # DTB accesses -system.cpu.itb.fetch_hits 1309723 # ITB hits -system.cpu.itb.fetch_misses 39683 # ITB misses -system.cpu.itb.fetch_acv 1073 # ITB acv -system.cpu.itb.fetch_accesses 1349406 # ITB accesses +system.cpu.dtb.read_hits 10317598 # DTB read hits +system.cpu.dtb.read_misses 42841 # DTB read misses +system.cpu.dtb.read_acv 498 # DTB read access violations +system.cpu.dtb.read_accesses 968680 # DTB read accesses +system.cpu.dtb.write_hits 6661505 # DTB write hits +system.cpu.dtb.write_misses 9470 # DTB write misses +system.cpu.dtb.write_acv 409 # DTB write access violations +system.cpu.dtb.write_accesses 342844 # DTB write accesses +system.cpu.dtb.data_hits 16979103 # DTB hits +system.cpu.dtb.data_misses 52311 # DTB misses +system.cpu.dtb.data_acv 907 # DTB access violations +system.cpu.dtb.data_accesses 1311524 # DTB accesses +system.cpu.itb.fetch_hits 1772041 # ITB hits +system.cpu.itb.fetch_misses 34420 # ITB misses +system.cpu.itb.fetch_acv 658 # ITB acv +system.cpu.itb.fetch_accesses 1806461 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -479,255 +473,256 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 121578156 # number of cpu cycles simulated +system.cpu.numCycles 118354133 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28154197 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 72069959 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13973676 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6838036 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13462286 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2111809 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 36504135 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32813 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 258219 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 367287 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 202 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8654218 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 283642 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80169891 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.898965 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.245398 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29610053 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 78304025 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17833670 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6847470 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80574615 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1256858 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1099 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 26263 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1650622 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 440507 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9057340 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 272482 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 112931823 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.693374 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.013486 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66707605 83.21% 83.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 850391 1.06% 84.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1701562 2.12% 86.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 829510 1.03% 87.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2814732 3.51% 90.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 566680 0.71% 91.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 649069 0.81% 92.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1061564 1.32% 93.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4988778 6.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 98319716 87.06% 87.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 938849 0.83% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1975725 1.75% 89.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 910849 0.81% 90.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2798510 2.48% 92.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 647409 0.57% 93.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 732146 0.65% 94.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1011734 0.90% 95.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5596885 4.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80169891 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.114936 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.592787 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 28969141 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36597720 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12749238 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 505228 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1348563 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 587502 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42619 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 70583559 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129875 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1348563 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 29902418 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12633582 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20046715 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11807818 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4430793 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 66640171 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8986 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 787429 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 47943 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1601274 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 44565634 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 80920867 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 80741427 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 166989 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38166970 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6398656 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1681821 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 238696 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9832739 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10696003 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7004082 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1336985 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 877203 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58981840 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2047452 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57223975 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 117650 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7712570 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4365148 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1386476 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80169891 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.713784 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.404933 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 112931823 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.150681 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.661608 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24101711 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 76820135 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9519710 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1904377 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 585889 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 591731 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42945 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68430953 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 130896 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 585889 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25024532 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 47243324 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20763433 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10413926 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8900717 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65988448 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 204336 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2037147 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 141186 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4759131 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 44017538 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79991288 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79809724 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 169111 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38182266 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5835264 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1692739 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 242112 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13540611 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10451547 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6960595 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1482211 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1061862 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58727790 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2141622 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57666213 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 56106 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7541795 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3548748 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1480432 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 112931823 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.510629 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.253101 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56166624 70.06% 70.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10391261 12.96% 83.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4679899 5.84% 88.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3142763 3.92% 92.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2796032 3.49% 96.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1647190 2.05% 98.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 895238 1.12% 99.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 353951 0.44% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 96933 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 89418441 79.18% 79.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10028401 8.88% 88.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4312192 3.82% 91.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 2973812 2.63% 94.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3078524 2.73% 97.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1589541 1.41% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1010242 0.89% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 396621 0.35% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 124049 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80169891 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 112931823 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 98738 11.92% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 400158 48.30% 60.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 329520 39.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 207021 18.24% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 552834 48.70% 66.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 375297 33.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38901419 67.98% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61759 0.11% 68.10% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10584317 18.50% 86.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6690891 11.69% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949060 1.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39135351 67.87% 67.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61883 0.11% 67.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38374 0.07% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10730394 18.61% 86.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6740242 11.69% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949047 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57223975 # Type of FU issued -system.cpu.iq.rate 0.470676 # Inst issue rate -system.cpu.iq.fu_busy_cnt 828416 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014477 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 194870458 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68419457 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55733530 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 693448 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 335810 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328249 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57682446 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 362659 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 614531 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57666213 # Type of FU issued +system.cpu.iq.rate 0.487234 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1135152 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019685 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 228740415 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 68094123 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55977641 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 715091 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336647 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 329707 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58410087 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 383992 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 639401 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1606237 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3745 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13777 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 627539 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1358213 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3975 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20004 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 581979 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18239 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 375591 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18257 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 542602 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1348563 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9312966 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 978337 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64604997 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 590069 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10696003 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 7004082 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1802911 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 468863 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 377382 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13777 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 204854 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411482 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 616336 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56685901 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10182131 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 538073 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 585889 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 44309531 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 608680 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64580146 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 145680 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10451547 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6960595 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1891521 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 42330 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 362520 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20004 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 191994 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411566 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 603560 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 57078103 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10388088 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 588109 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3575705 # number of nop insts executed -system.cpu.iew.exec_refs 16819167 # number of memory reference insts executed -system.cpu.iew.exec_branches 8947461 # Number of branches executed -system.cpu.iew.exec_stores 6637036 # Number of stores executed -system.cpu.iew.exec_rate 0.466251 # Inst execution rate -system.cpu.iew.wb_sent 56177988 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56061779 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28606216 # num instructions producing a value -system.cpu.iew.wb_consumers 39617780 # num instructions consuming a value +system.cpu.iew.exec_nop 3710734 # number of nop insts executed +system.cpu.iew.exec_refs 17074164 # number of memory reference insts executed +system.cpu.iew.exec_branches 8987700 # Number of branches executed +system.cpu.iew.exec_stores 6686076 # Number of stores executed +system.cpu.iew.exec_rate 0.482265 # Inst execution rate +system.cpu.iew.wb_sent 56446206 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56307348 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28961590 # num instructions producing a value +system.cpu.iew.wb_consumers 40346871 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.461117 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.722055 # average fanout of values written-back +system.cpu.iew.wb_rate 0.475753 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717815 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8325898 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660976 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 566478 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 78821328 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.712415 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.665597 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8290413 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661190 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 549582 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 111493844 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.503831 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.456125 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58682621 74.45% 74.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8193641 10.40% 84.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4257107 5.40% 90.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2319840 2.94% 93.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1767395 2.24% 95.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 615421 0.78% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 496583 0.63% 96.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 549859 0.70% 97.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1938861 2.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 91848046 82.38% 82.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7822356 7.02% 89.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4123652 3.70% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2157766 1.94% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1851713 1.66% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 614180 0.55% 97.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 473259 0.42% 97.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 509141 0.46% 98.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2093731 1.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 78821328 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56153459 # Number of instructions committed -system.cpu.commit.committedOps 56153459 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 111493844 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56174099 # Number of instructions committed +system.cpu.commit.committedOps 56174099 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15466309 # Number of memory references committed -system.cpu.commit.loads 9089766 # Number of loads committed -system.cpu.commit.membars 226357 # Number of memory barriers committed -system.cpu.commit.branches 8438044 # Number of branches committed -system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52003822 # Number of committed integer instructions. -system.cpu.commit.function_calls 740374 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3197313 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36218566 64.50% 70.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60658 0.11% 70.30% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.30% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 25607 0.05% 70.35% # Class of committed instruction +system.cpu.commit.refs 15471950 # Number of memory references committed +system.cpu.commit.loads 9093334 # Number of loads committed +system.cpu.commit.membars 226345 # Number of memory barriers committed +system.cpu.commit.branches 8441019 # Number of branches committed +system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. +system.cpu.commit.int_insts 52023449 # Number of committed integer instructions. +system.cpu.commit.function_calls 740634 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3198108 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36220301 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60671 0.11% 70.28% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 38087 0.07% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction @@ -753,30 +748,30 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9316123 16.59% 86.94% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6382496 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949060 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9319679 16.59% 86.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6384570 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949047 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56153459 # Class of committed instruction -system.cpu.commit.bw_lim_events 1938861 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 56174099 # Class of committed instruction +system.cpu.commit.bw_lim_events 2093731 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141112277 # The number of ROB reads -system.cpu.rob.rob_writes 130308588 # The number of ROB writes -system.cpu.timesIdled 1194216 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 41408265 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3598759795 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52963419 # Number of Instructions Simulated -system.cpu.committedOps 52963419 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.295512 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.295512 # CPI: Total CPI of All Threads -system.cpu.ipc 0.435633 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.435633 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74250743 # number of integer regfile reads -system.cpu.int_regfile_writes 40442410 # number of integer regfile writes -system.cpu.fp_regfile_reads 166399 # number of floating regfile reads -system.cpu.fp_regfile_writes 167429 # number of floating regfile writes -system.cpu.misc_regfile_reads 2028427 # number of misc regfile reads -system.cpu.misc_regfile_writes 938976 # number of misc regfile writes +system.cpu.rob.rob_reads 173614429 # The number of ROB reads +system.cpu.rob.rob_writes 130369620 # The number of ROB writes +system.cpu.timesIdled 576556 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5422310 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3601657297 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52983264 # Number of Instructions Simulated +system.cpu.committedOps 52983264 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.233802 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.233802 # CPI: Total CPI of All Threads +system.cpu.ipc 0.447667 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.447667 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74755796 # number of integer regfile reads +system.cpu.int_regfile_writes 40630218 # number of integer regfile writes +system.cpu.fp_regfile_reads 167440 # number of floating regfile reads +system.cpu.fp_regfile_writes 167913 # number of floating regfile writes +system.cpu.misc_regfile_reads 2030226 # number of misc regfile reads +system.cpu.misc_regfile_writes 939431 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -808,12 +803,13 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1454569 # Throughput (bytes/s) +system.iobus.throughput 1454701 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51149 # Transaction distribution -system.iobus.trans_dist::WriteResp 51149 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51086 # Transaction distribution +system.iobus.trans_dist::WriteResp 51150 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 64 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -825,11 +821,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33054 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116504 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20200 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -841,12 +837,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 44140 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2705748 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2705748 # Total data (bytes) -system.iobus.reqLayer0.occupancy 4661000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2705756 # Total data (bytes) +system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -868,245 +864,250 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380163354 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374510641 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43205758 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42014789 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.throughput 111909594 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2117185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2117083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 840753 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 342629 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301078 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 85 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2018148 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3678150 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5696298 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64577024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143586668 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 208163692 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 208153644 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 17472 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2479804999 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 114654995 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2149538 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2149432 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 845214 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41561 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 94 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 122 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 302210 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 302210 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 89 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2074480 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3693292 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5767772 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66377344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144210036 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 210587380 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 210577396 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 2681920 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2503268997 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1516964420 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1560084006 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2185370157 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2193039668 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 1008400 # number of replacements -system.cpu.icache.tags.tagsinuse 509.648597 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7589401 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1008908 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.522392 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 26586363250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.648597 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995407 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995407 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1036559 # number of replacements +system.cpu.icache.tags.tagsinuse 509.401978 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7968978 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1037067 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.684150 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 26427286250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.401978 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994926 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994926 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 136 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9663349 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9663349 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7589402 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7589402 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7589402 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7589402 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7589402 # number of overall hits -system.cpu.icache.overall_hits::total 7589402 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1064815 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1064815 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1064815 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1064815 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1064815 # number of overall misses -system.cpu.icache.overall_misses::total 1064815 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14788071318 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14788071318 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14788071318 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14788071318 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14788071318 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14788071318 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8654217 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8654217 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8654217 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8654217 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8654217 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8654217 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123040 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123040 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123040 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123040 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123040 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123040 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13887.925431 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13887.925431 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13887.925431 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13887.925431 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13887.925431 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13887.925431 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4640 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10094673 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10094673 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7968979 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7968979 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7968979 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7968979 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7968979 # number of overall hits +system.cpu.icache.overall_hits::total 7968979 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1088360 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1088360 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1088360 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1088360 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1088360 # number of overall misses +system.cpu.icache.overall_misses::total 1088360 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15140469933 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15140469933 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15140469933 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15140469933 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15140469933 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15140469933 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9057339 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9057339 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9057339 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9057339 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9057339 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9057339 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120163 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.120163 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.120163 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.120163 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.120163 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.120163 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13911.270106 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13911.270106 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13911.270106 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13911.270106 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13911.270106 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13911.270106 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4471 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 182 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 200 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 25.494505 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.355000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55683 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 55683 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 55683 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 55683 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 55683 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 55683 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009132 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1009132 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1009132 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1009132 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1009132 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1009132 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12130132326 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12130132326 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12130132326 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12130132326 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12130132326 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12130132326 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116606 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116606 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116606 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116606 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116606 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116606 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12020.362377 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12020.362377 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12020.362377 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12020.362377 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12020.362377 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12020.362377 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51026 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 51026 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 51026 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 51026 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 51026 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 51026 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1037334 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1037334 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1037334 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1037334 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1037334 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1037334 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12446794989 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12446794989 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12446794989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12446794989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12446794989 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12446794989 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114530 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.114530 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.114530 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.830646 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.830646 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.830646 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.830646 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.830646 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.830646 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 338319 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65340.875442 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2545143 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403486 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.307884 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5540956750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53842.334774 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5321.183862 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6177.356806 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.821569 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081195 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.094259 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997023 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3496 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3313 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2397 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55469 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26719739 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26719739 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 993934 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 827149 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1821083 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 840753 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 840753 # number of Writeback hits +system.cpu.l2cache.tags.replacements 338424 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65337.415563 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2581710 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 403590 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.396863 # 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average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39985.383039 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15298.706247 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15298.706247 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19000.500000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19000.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31585.487216 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31585.487216 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31585.487216 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31585.487216 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3437281 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 992 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 114395 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.047476 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 124 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 64006618 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 64006618 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7294645 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7294645 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4192085 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4192085 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186406 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186406 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215722 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215722 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11486730 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11486730 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11486730 # number of overall hits +system.cpu.dcache.overall_hits::total 11486730 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1781450 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1781450 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1956078 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1956078 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23435 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23435 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3737528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3737528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3737528 # number of overall misses +system.cpu.dcache.overall_misses::total 3737528 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 39460898751 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39460898751 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 77926098572 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 77926098572 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 366682499 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 366682499 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 440006 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 440006 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 117386997323 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117386997323 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117386997323 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117386997323 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9076095 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9076095 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6148163 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6148163 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209841 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209841 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215750 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215750 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15224258 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15224258 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15224258 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15224258 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.196279 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.196279 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318156 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.318156 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.245498 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.245498 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.245498 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.245498 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22150.999888 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22150.999888 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39837.930068 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39837.930068 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15646.788948 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15646.788948 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15714.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15714.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31407.656966 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31407.656966 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31407.656966 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31407.656966 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3974317 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2076 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 180350 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 21 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.036690 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 98.857143 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840753 # number of writebacks -system.cpu.dcache.writebacks::total 840753 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 705849 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 705849 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1648446 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1648446 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5839 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5839 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2354295 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2354295 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2354295 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2354295 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084028 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1084028 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300479 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300479 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17582 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17582 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384507 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384507 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384507 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384507 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27275332511 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27275332511 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11834545572 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11834545572 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200445001 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200445001 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 33999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 33999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39109878083 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 39109878083 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39109878083 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 39109878083 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424085500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424085500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997539998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997539998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421625498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421625498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120289 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120289 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048888 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048888 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084142 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084142 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091337 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091337 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25161.095941 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25161.095941 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39385.599566 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39385.599566 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11400.580196 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11400.580196 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16999.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16999.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28248.234269 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28248.234269 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28248.234269 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28248.234269 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 845214 # number of writebacks +system.cpu.dcache.writebacks::total 845214 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 683673 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 683673 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664672 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1664672 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5215 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5215 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2348345 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2348345 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2348345 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2348345 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1097777 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1097777 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291406 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 291406 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18220 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 18220 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1389183 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1389183 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1389183 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1389183 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27531600277 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27531600277 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11750999106 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11750999106 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 207629251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 207629251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 383994 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 383994 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39282599383 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 39282599383 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39282599383 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 39282599383 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423287000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423287000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997974498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997974498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421261498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421261498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120953 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120953 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047397 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047397 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086828 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086828 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091248 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091248 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091248 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091248 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25079.410734 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25079.410734 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40325.178981 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40325.178981 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11395.677881 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.677881 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13714.071429 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13714.071429 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28277.483516 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28277.483516 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28277.483516 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28277.483516 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1366,28 +1367,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211015 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74666 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211008 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105570 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182246 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73299 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105564 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182238 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73299 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148608 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817910535000 97.73% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64222000 0.00% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 554846000 0.03% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41641763000 2.24% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1860171366000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818262027500 97.76% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 61927000 0.00% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 526143500 0.03% 97.79% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41157993000 2.21% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860008091000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694317 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815425 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694328 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815434 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1423,32 +1424,32 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175131 91.23% 93.44% # number of callpals executed +system.cpu.kern.callpal::swpipl 175121 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191975 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches +system.cpu.kern.callpal::total 191967 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326496 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29515260500 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2703792500 0.15% 1.73% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827952305000 98.27% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394302 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29080060000 1.56% 1.56% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2655672500 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1828272350500 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index de36b122c..6a79f5850 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,147 +1,150 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.842688 # Number of seconds simulated -sim_ticks 1842688380000 # Number of ticks simulated -final_tick 1842688380000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841612 # Number of seconds simulated +sim_ticks 1841612285000 # Number of ticks simulated +final_tick 1841612285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 219315 # Simulator instruction rate (inst/s) -host_op_rate 219315 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5608158508 # Simulator tick rate (ticks/s) -host_mem_usage 303992 # Number of bytes of host memory used -host_seconds 328.57 # Real time elapsed on the host -sim_insts 72060922 # Number of instructions simulated -sim_ops 72060922 # Number of ops (including micro ops) simulated +host_inst_rate 168459 # Simulator instruction rate (inst/s) +host_op_rate 168459 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4750760669 # Simulator tick rate (ticks/s) +host_mem_usage 319468 # Number of bytes of host memory used +host_seconds 387.65 # Real time elapsed on the host +sim_insts 65302548 # Number of instructions simulated +sim_ops 65302548 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 480512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20113024 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2236096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 291264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2520128 # Number of bytes read from this memory -system.physmem.bytes_read::total 28440832 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 480512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 291264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 919232 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7466176 # Number of bytes written to this memory -system.physmem.bytes_written::total 7466176 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7508 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 314266 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2304 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 34939 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4551 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39377 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444388 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116659 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116659 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 260767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10915044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1439393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 80022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1213497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 158065 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1367637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15434423 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 260767 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 80022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 158065 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4051784 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4051784 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4051784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 260767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10915044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1439393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 80022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1213497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 158065 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1367637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19486207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 98062 # Number of read requests accepted -system.physmem.writeReqs 44473 # Number of write requests accepted -system.physmem.readBursts 98062 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 44473 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6274816 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1152 # Total number of bytes read from write queue -system.physmem.bytesWritten 2845184 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6275968 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2846272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 18 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu0.inst 475840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 19999104 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2248128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 298624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2645376 # Number of bytes read from this memory +system.physmem.bytes_read::total 25815040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 475840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 298624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 921472 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4825408 # Number of bytes written to this memory +system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory +system.physmem.bytes_written::total 7484736 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7435 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 312486 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 35127 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4666 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41334 # Number of read requests responded to by this memory +system.physmem.num_reads::total 403360 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 75397 # Number of write requests responded to by this memory +system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116949 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 258382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10859563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 79826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1220739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 162154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1436446 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14017630 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 258382 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 79826 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 162154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 500362 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2620208 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1444022 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4064230 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2620208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 258382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10859563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1444543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 79826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1220739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 162154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1436446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18081860 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 83439 # Number of read requests accepted +system.physmem.writeReqs 46740 # Number of write requests accepted +system.physmem.readBursts 83439 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 46740 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5337024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3072 # Total number of bytes read from write queue +system.physmem.bytesWritten 2989888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5340096 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2991360 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 48 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6096 # Per bank write bursts -system.physmem.perBankRdBursts::1 5927 # Per bank write bursts -system.physmem.perBankRdBursts::2 6222 # Per bank write bursts -system.physmem.perBankRdBursts::3 6258 # Per bank write bursts -system.physmem.perBankRdBursts::4 5693 # Per bank write bursts -system.physmem.perBankRdBursts::5 6247 # Per bank write bursts -system.physmem.perBankRdBursts::6 5971 # Per bank write bursts -system.physmem.perBankRdBursts::7 5980 # Per bank write bursts -system.physmem.perBankRdBursts::8 6426 # Per bank write bursts -system.physmem.perBankRdBursts::9 5994 # Per bank write bursts -system.physmem.perBankRdBursts::10 6527 # Per bank write bursts -system.physmem.perBankRdBursts::11 6117 # Per bank write bursts -system.physmem.perBankRdBursts::12 5881 # Per bank write bursts -system.physmem.perBankRdBursts::13 6322 # Per bank write bursts -system.physmem.perBankRdBursts::14 6340 # Per bank write bursts -system.physmem.perBankRdBursts::15 6043 # Per bank write bursts -system.physmem.perBankWrBursts::0 2729 # Per bank write bursts -system.physmem.perBankWrBursts::1 2556 # Per bank write bursts -system.physmem.perBankWrBursts::2 2841 # Per bank write bursts -system.physmem.perBankWrBursts::3 3001 # Per bank write bursts -system.physmem.perBankWrBursts::4 2678 # Per bank write bursts -system.physmem.perBankWrBursts::5 2962 # Per bank write bursts -system.physmem.perBankWrBursts::6 2867 # Per bank write bursts -system.physmem.perBankWrBursts::7 2601 # Per bank write bursts -system.physmem.perBankWrBursts::8 3150 # Per bank write bursts -system.physmem.perBankWrBursts::9 2533 # Per bank write bursts -system.physmem.perBankWrBursts::10 3049 # Per bank write bursts -system.physmem.perBankWrBursts::11 2640 # Per bank write bursts -system.physmem.perBankWrBursts::12 2384 # Per bank write bursts -system.physmem.perBankWrBursts::13 2771 # Per bank write bursts -system.physmem.perBankWrBursts::14 2950 # Per bank write bursts -system.physmem.perBankWrBursts::15 2744 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 52 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5256 # Per bank write bursts +system.physmem.perBankRdBursts::1 5087 # Per bank write bursts +system.physmem.perBankRdBursts::2 5115 # Per bank write bursts +system.physmem.perBankRdBursts::3 5179 # Per bank write bursts +system.physmem.perBankRdBursts::4 5173 # Per bank write bursts +system.physmem.perBankRdBursts::5 5205 # Per bank write bursts +system.physmem.perBankRdBursts::6 5267 # Per bank write bursts +system.physmem.perBankRdBursts::7 5273 # Per bank write bursts +system.physmem.perBankRdBursts::8 5423 # Per bank write bursts +system.physmem.perBankRdBursts::9 5013 # Per bank write bursts +system.physmem.perBankRdBursts::10 5464 # Per bank write bursts +system.physmem.perBankRdBursts::11 5273 # Per bank write bursts +system.physmem.perBankRdBursts::12 4813 # Per bank write bursts +system.physmem.perBankRdBursts::13 5124 # Per bank write bursts +system.physmem.perBankRdBursts::14 5602 # Per bank write bursts +system.physmem.perBankRdBursts::15 5124 # Per bank write bursts +system.physmem.perBankWrBursts::0 2825 # Per bank write bursts +system.physmem.perBankWrBursts::1 2787 # Per bank write bursts +system.physmem.perBankWrBursts::2 2858 # Per bank write bursts +system.physmem.perBankWrBursts::3 3069 # Per bank write bursts +system.physmem.perBankWrBursts::4 3024 # Per bank write bursts +system.physmem.perBankWrBursts::5 2822 # Per bank write bursts +system.physmem.perBankWrBursts::6 3224 # Per bank write bursts +system.physmem.perBankWrBursts::7 2821 # Per bank write bursts +system.physmem.perBankWrBursts::8 3331 # Per bank write bursts +system.physmem.perBankWrBursts::9 2683 # Per bank write bursts +system.physmem.perBankWrBursts::10 3131 # Per bank write bursts +system.physmem.perBankWrBursts::11 2953 # Per bank write bursts +system.physmem.perBankWrBursts::12 2475 # Per bank write bursts +system.physmem.perBankWrBursts::13 2748 # Per bank write bursts +system.physmem.perBankWrBursts::14 3227 # Per bank write bursts +system.physmem.perBankWrBursts::15 2739 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 1841676054500 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 1840600008500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 98062 # Read request sizes (log2) +system.physmem.readPktSize::6 83439 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 44473 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 65686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7740 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2064 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 855 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1814 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1004 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 871 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 653 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 645 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 766 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 872 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 494 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 362 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 46740 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 66354 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7773 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -153,400 +156,398 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 21822 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 417.926863 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 236.963090 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 396.574874 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 6839 31.34% 31.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4667 21.39% 52.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1650 7.56% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1022 4.68% 64.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 930 4.26% 69.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 496 2.27% 71.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 383 1.76% 73.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 375 1.72% 74.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5460 25.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 21822 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2614 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.504973 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 907.786867 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2612 99.92% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.04% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.04% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2614 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2614 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.006886 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.398766 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 4.165807 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 24 0.92% 0.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 7 0.27% 1.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 2 0.08% 1.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 1 0.04% 1.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 1 0.04% 1.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 3 0.11% 1.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 2 0.08% 1.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 1 0.04% 1.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 1 0.04% 1.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 1 0.04% 1.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1860 71.16% 72.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 26 0.99% 73.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 431 16.49% 90.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 74 2.83% 93.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 23 0.88% 93.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 9 0.34% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 11 0.42% 94.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 40 1.53% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 8 0.31% 96.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 18 0.69% 97.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 8 0.31% 97.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 7 0.27% 97.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 3 0.11% 97.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 5 0.19% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 6 0.23% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 9 0.34% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 5 0.19% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.04% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.04% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.04% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.04% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.04% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 4 0.15% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 3 0.11% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.08% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 1 0.04% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 1 0.04% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 4 0.15% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 1 0.04% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 1 0.04% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 3 0.11% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 2 0.08% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58 1 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2614 # Writes before turning the bus around for reads -system.physmem.totQLat 2880597750 # Total ticks spent queuing -system.physmem.totMemAccLat 4718922750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 490220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29380.66 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21530 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 386.758569 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 220.447203 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 381.120515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7019 32.60% 32.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4847 22.51% 55.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1849 8.59% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1051 4.88% 68.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 911 4.23% 72.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 506 2.35% 75.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 375 1.74% 76.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 418 1.94% 78.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4554 21.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21530 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2040 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 40.873529 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1027.655163 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2038 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.05% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 2040 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2040 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.900490 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.614282 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.575456 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 33 1.62% 1.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.34% 1.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.05% 2.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 5 0.25% 2.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 1695 83.09% 85.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 37 1.81% 87.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 5 0.25% 87.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 107 5.25% 92.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 7 0.34% 92.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.10% 93.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.05% 93.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.15% 93.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 8 0.39% 93.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.05% 93.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.05% 93.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 2 0.10% 93.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.05% 93.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.10% 94.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 2 0.10% 94.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 8 0.39% 94.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.15% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.15% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.10% 94.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 78 3.82% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.05% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.10% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.05% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.34% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.10% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.15% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.05% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.15% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.05% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 4 0.20% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2040 # Writes before turning the bus around for reads +system.physmem.totQLat 869064750 # Total ticks spent queuing +system.physmem.totMemAccLat 2432646000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 416955000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10421.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48130.66 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.41 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.41 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29171.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.62 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.62 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.05 # Average write queue length when enqueuing -system.physmem.readRowHits 85382 # Number of row buffer hits during reads -system.physmem.writeRowHits 35296 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.37 # Row buffer hit rate for writes -system.physmem.avgGap 12920868.94 # Average gap between requests -system.physmem.pageHitRate 84.68 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1767714784750 # Time in different power states -system.physmem.memoryStateTime::REF 61531340000 # Time in different power states +system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing +system.physmem.avgWrQLen 8.28 # Average write queue length when enqueuing +system.physmem.readRowHits 71609 # Number of row buffer hits during reads +system.physmem.writeRowHits 36969 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.87 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.09 # Row buffer hit rate for writes +system.physmem.avgGap 14138993.30 # Average gap between requests +system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1766589196000 # Time in different power states +system.physmem.memoryStateTime::REF 61495460000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 13440274000 # Time in different power states +system.physmem.memoryStateTime::ACT 13527240250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 19530148 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 44582 # Transaction distribution -system.membus.trans_dist::ReadResp 44547 # Transaction distribution -system.membus.trans_dist::WriteReq 3734 # Transaction distribution -system.membus.trans_dist::WriteResp 3734 # Transaction distribution -system.membus.trans_dist::Writeback 44473 # Transaction distribution -system.membus.trans_dist::UpgradeReq 43 # Transaction distribution -system.membus.trans_dist::UpgradeResp 43 # Transaction distribution -system.membus.trans_dist::ReadExReq 56556 # Transaction distribution -system.membus.trans_dist::ReadExResp 56556 # Transaction distribution -system.membus.trans_dist::BadAddressError 35 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13238 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 190124 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 70 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 203432 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 50712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 50712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 254144 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15652 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6962432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 6978084 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2159808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2159808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 9137892 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35977992 # Total data (bytes) -system.membus.snoop_data_through_bus 9984 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12394500 # Layer occupancy (ticks) +system.membus.throughput 18112095 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 44765 # Transaction distribution +system.membus.trans_dist::ReadResp 44760 # Transaction distribution +system.membus.trans_dist::WriteReq 3528 # Transaction distribution +system.membus.trans_dist::WriteResp 3528 # Transaction distribution +system.membus.trans_dist::Writeback 29460 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 17280 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 17280 # Transaction distribution +system.membus.trans_dist::UpgradeReq 50 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 52 # Transaction distribution +system.membus.trans_dist::ReadExReq 41656 # Transaction distribution +system.membus.trans_dist::ReadExResp 41656 # Transaction distribution +system.membus.trans_dist::BadAddressError 5 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 12900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 196412 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 209322 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 34645 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 34645 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 243967 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15792 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7224576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 7240368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 1106880 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 1106880 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 8347248 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 33351936 # Total data (bytes) +system.membus.snoop_data_through_bus 3520 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 11434500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 511002500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 517398750 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 45000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 6500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 763523207 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 783386948 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 153153250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 17911250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 337462 # number of replacements -system.l2c.tags.tagsinuse 65424.483078 # Cycle average of tags in use -system.l2c.tags.total_refs 2473806 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402625 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.144194 # Average number of references to valid blocks. +system.l2c.tags.replacements 337577 # number of replacements +system.l2c.tags.tagsinuse 65421.096735 # Cycle average of tags in use +system.l2c.tags.total_refs 2486717 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402739 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.174513 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54864.362424 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2329.333896 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2645.609154 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 576.513665 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 589.890909 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2235.608932 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2183.164099 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.837164 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.035543 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.040369 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008797 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034113 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.033312 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998298 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 54723.362784 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2335.935658 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2702.236553 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 571.913553 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 605.884543 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2280.035703 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2201.727940 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.835012 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.035644 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041233 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008727 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009245 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.034791 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.033596 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998247 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1028 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5611 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55380 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26155869 # Number of tag accesses -system.l2c.tags.data_accesses 26155869 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 519275 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 492761 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 124644 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 83355 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 294324 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 240703 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1755062 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835893 # number of Writeback hits -system.l2c.Writeback_hits::total 835893 # number of Writeback hits +system.l2c.tags.age_task_id_blocks_1024::1 1013 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5951 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2686 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55344 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 26259828 # Number of tag accesses +system.l2c.tags.data_accesses 26259828 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 505337 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 482025 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 122124 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 80194 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 322880 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 255461 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1768021 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835818 # number of Writeback hits +system.l2c.Writeback_hits::total 835818 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 3 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 7 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 92934 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 26300 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 67701 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186935 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 519275 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 585695 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 124644 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 109655 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 294324 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 308404 # number of demand (read+write) hits -system.l2c.demand_hits::total 1941997 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 519275 # number of overall hits -system.l2c.overall_hits::cpu0.data 585695 # number of overall hits -system.l2c.overall_hits::cpu1.inst 124644 # number of overall hits -system.l2c.overall_hits::cpu1.data 109655 # number of overall hits -system.l2c.overall_hits::cpu2.inst 294324 # number of overall hits -system.l2c.overall_hits::cpu2.data 308404 # number of overall hits -system.l2c.overall_hits::total 1941997 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 7508 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 238474 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2304 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 16794 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 4551 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 17979 # number of ReadReq misses -system.l2c.ReadReq_misses::total 287610 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 9 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 17 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # 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average ReadReq mshr uncacheable latency @@ -657,101 +666,93 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254888 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254802 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1694865618000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254888 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078431 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078431 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1693889914000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254802 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078425 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078425 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9303463 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9303463 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5047462530 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5047462530 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5056765993 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5056765993 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5056765993 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5056765993 # number of overall miss cycles +system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses +system.iocache.demand_misses::total 173 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 173 # number of overall misses +system.iocache.overall_misses::total 173 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 9417462 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9417462 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9417462 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9417462 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9417462 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9417462 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53777.242775 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 53777.242775 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 121473.395504 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 121473.395504 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 121192.714032 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 121192.714032 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 121192.714032 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 121192.714032 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 149207 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54436.196532 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 54436.196532 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 54436.196532 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 54436.196532 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11483 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.993730 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41512 # number of writebacks -system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 16896 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 16896 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 16965 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 16965 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 16965 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 16965 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5714463 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5714463 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4167935030 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4167935030 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 4173649493 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4173649493 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 4173649493 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4173649493 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.406623 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.406623 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.406591 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.406591 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82818.304348 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82818.304348 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 246681.760772 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 246681.760772 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246015.295785 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 246015.295785 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246015.295785 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 246015.295785 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17280 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 17280 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5776462 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5776462 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 1039320090 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1039320090 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5776462 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5776462 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5776462 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5776462 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 82520.885714 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60145.838542 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60145.838542 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -769,22 +770,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4913708 # DTB read hits -system.cpu0.dtb.read_misses 6100 # DTB read misses -system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 428235 # DTB read accesses -system.cpu0.dtb.write_hits 3510172 # DTB write hits -system.cpu0.dtb.write_misses 671 # DTB write misses -system.cpu0.dtb.write_acv 84 # DTB write access violations -system.cpu0.dtb.write_accesses 163990 # DTB write accesses -system.cpu0.dtb.data_hits 8423880 # DTB hits -system.cpu0.dtb.data_misses 6771 # DTB misses -system.cpu0.dtb.data_acv 210 # DTB access violations -system.cpu0.dtb.data_accesses 592225 # DTB accesses -system.cpu0.itb.fetch_hits 2758823 # ITB hits -system.cpu0.itb.fetch_misses 3034 # ITB misses -system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2761857 # ITB accesses +system.cpu0.dtb.read_hits 4820184 # DTB read hits +system.cpu0.dtb.read_misses 5970 # DTB read misses +system.cpu0.dtb.read_acv 109 # DTB read access violations +system.cpu0.dtb.read_accesses 427969 # DTB read accesses +system.cpu0.dtb.write_hits 3428698 # DTB write hits +system.cpu0.dtb.write_misses 674 # DTB write misses +system.cpu0.dtb.write_acv 81 # DTB write access violations +system.cpu0.dtb.write_accesses 164325 # DTB write accesses +system.cpu0.dtb.data_hits 8248882 # DTB hits +system.cpu0.dtb.data_misses 6644 # DTB misses +system.cpu0.dtb.data_acv 190 # DTB access violations +system.cpu0.dtb.data_accesses 592294 # DTB accesses +system.cpu0.itb.fetch_hits 2727685 # ITB hits +system.cpu0.itb.fetch_misses 3015 # ITB misses +system.cpu0.itb.fetch_acv 97 # ITB acv +system.cpu0.itb.fetch_accesses 2730700 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -797,87 +798,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928196841 # number of cpu cycles simulated +system.cpu0.numCycles 929885466 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 33463552 # Number of instructions committed -system.cpu0.committedOps 33463552 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 31328637 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 169756 # Number of float alu accesses -system.cpu0.num_func_calls 812549 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4574772 # number of instructions that are conditional controls -system.cpu0.num_int_insts 31328637 # number of integer instructions -system.cpu0.num_fp_insts 169756 # number of float instructions -system.cpu0.num_int_register_reads 43916482 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22873823 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 87693 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 89172 # number of times the floating registers were written -system.cpu0.num_mem_refs 8454037 # number of memory refs -system.cpu0.num_load_insts 4935095 # Number of load instructions -system.cpu0.num_store_insts 3518942 # Number of store instructions -system.cpu0.num_idle_cycles 904607153.884767 # Number of idle cycles -system.cpu0.num_busy_cycles 23589687.115233 # Number of busy cycles -system.cpu0.not_idle_fraction 0.025415 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.974585 # Percentage of idle cycles -system.cpu0.Branches 5650356 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1614853 4.82% 4.82% # Class of executed instruction -system.cpu0.op_class::IntAlu 22689020 67.79% 72.61% # Class of executed instruction -system.cpu0.op_class::IntMult 32419 0.10% 72.71% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 72.71% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12179 0.04% 72.75% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1606 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::MemRead 5069147 15.15% 87.90% # Class of executed instruction -system.cpu0.op_class::MemWrite 3522084 10.52% 98.42% # Class of executed instruction -system.cpu0.op_class::IprAccess 529225 1.58% 100.00% # Class of executed instruction +system.cpu0.committedInsts 30965233 # Number of instructions committed +system.cpu0.committedOps 30965233 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 28877959 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 164894 # Number of float alu accesses +system.cpu0.num_func_calls 798570 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3871145 # number of instructions that are conditional controls +system.cpu0.num_int_insts 28877959 # number of integer instructions +system.cpu0.num_fp_insts 164894 # number of float instructions +system.cpu0.num_int_register_reads 39995093 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21215374 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 85232 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 86749 # number of times the floating registers were written +system.cpu0.num_mem_refs 8278255 # number of memory refs +system.cpu0.num_load_insts 4840998 # Number of load instructions +system.cpu0.num_store_insts 3437257 # Number of store instructions +system.cpu0.num_idle_cycles 908001022.276160 # Number of idle cycles +system.cpu0.num_busy_cycles 21884443.723840 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023535 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976465 # Percentage of idle cycles +system.cpu0.Branches 4926958 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1578460 5.10% 5.10% # Class of executed instruction +system.cpu0.op_class::IntAlu 20418617 65.93% 71.02% # Class of executed instruction +system.cpu0.op_class::IntMult 31850 0.10% 71.13% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12902 0.04% 71.17% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1598 0.01% 71.17% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::MemRead 4971884 16.05% 87.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 3440357 11.11% 98.33% # Class of executed instruction +system.cpu0.op_class::IprAccess 516399 1.67% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 33470533 # Class of executed instruction +system.cpu0.op_class::total 30972067 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6420 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211388 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74806 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6423 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211353 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105697 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182585 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73439 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105680 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182555 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73439 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148960 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819515986000 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38828500 0.00% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 364353500 0.02% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22768442500 1.24% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842687610500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1818769989500 98.76% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39220500 0.00% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 357294000 0.02% 98.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22445011500 1.22% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841611515500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694807 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815839 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694805 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815836 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -913,33 +914,33 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175326 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175298 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192241 # number of callpals executed +system.cpu0.kern.callpal::total 192209 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1907 +system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1906 system.cpu0.kern.mode_good::user 1737 -system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches +system.cpu0.kern.mode_good::idle 169 +system.cpu0.kern.mode_switch_good::kernel 0.321851 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.390979 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29751992000 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2580511000 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810355103000 98.25% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4177 # number of times the context was actually changed +system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.390894 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29707694000 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2577107000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809326710000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -971,460 +972,459 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 110521342 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 787621 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 787571 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 3734 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 3734 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 372342 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 150591 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 133695 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 35 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 851659 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370714 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 2222373 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27252672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55368420 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 82621092 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 203645448 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 10944 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2139903500 # Layer occupancy (ticks) +system.toL2Bus.throughput 112481926 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 825463 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 825443 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 3528 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 3528 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 385263 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 17281 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 33 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 137914 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 137914 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 5 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 903973 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1415042 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 2319015 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 28925888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 57212080 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 86137968 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 204476224 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 2671872 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2218881500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1918103434 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2036319024 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2234598905 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2306325269 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1469149 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 2954 # Transaction distribution -system.iobus.trans_dist::ReadResp 2954 # Transaction distribution -system.iobus.trans_dist::WriteReq 20630 # Transaction distribution -system.iobus.trans_dist::WriteResp 20630 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2332 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 136 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8304 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2378 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 22 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 13238 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 33930 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 33930 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 47168 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9328 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 544 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1550 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 17 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 15652 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1082792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1082792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1098444 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2707184 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2201000 # Layer occupancy (ticks) +system.iobus.throughput 1470003 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 2992 # Transaction distribution +system.iobus.trans_dist::ReadResp 2992 # Transaction distribution +system.iobus.trans_dist::WriteReq 20808 # Transaction distribution +system.iobus.trans_dist::WriteResp 20808 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 7420 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2926 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 18 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 12900 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 34700 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 47600 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 55 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 3710 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 2083 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 16 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 15792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107376 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1123168 # 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Layer utilization (%) -system.iobus.reqLayer26.occupancy 13000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 154562743 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer29.occupancy 155677802 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9504000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9372000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17636750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17532750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 951958 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.193866 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 42822968 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 952469 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 44.959960 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10341081250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 254.383910 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 92.394710 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 164.415245 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.496844 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.180458 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.321124 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998426 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 964098 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.196429 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 40281211 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 964609 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 41.759108 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10190294250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 265.809335 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 64.640468 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 180.746626 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.519159 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.126251 # 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miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016660 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.121807 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.023774 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016557 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016660 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.121807 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.023774 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016557 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016660 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.121807 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.023774 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14266.221136 # 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mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.115793 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009724 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016401 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.115793 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009724 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12210.946592 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12223.711922 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12219.906389 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12210.946592 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12223.711922 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12219.906389 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12210.946592 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12223.711922 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12219.906389 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16160 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16160 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16160 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16160 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16160 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16160 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 124421 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 327585 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 452006 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 124421 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 327585 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 452006 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 124421 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 327585 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 452006 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1525261500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3997287463 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5522548963 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1525261500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3997287463 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5522548963 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1525261500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3997287463 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5522548963 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016660 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116081 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010954 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016660 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116081 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010954 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016660 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116081 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010954 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.875110 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12202.290895 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12217.866495 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.875110 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12202.290895 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12217.866495 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.875110 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12202.290895 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12217.866495 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1392214 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13295925 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1392726 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.546691 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1393139 # 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Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 260.896843 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 74.443174 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 176.657800 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.509564 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.145397 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.345035 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 267 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63306620 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63306620 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4076279 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1084544 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2409625 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7570448 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3214036 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 832568 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1295168 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5341772 # 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number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1130661 # number of overall misses -system.cpu0.dcache.overall_misses::total 2163760 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2236149750 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9408423500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11644573250 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1650986010 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18036124563 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19687110573 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28476000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 115371499 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 143847499 # 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number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8924184 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3383049 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 877063 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1891684 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6151796 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126730 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21487 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 54983 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203200 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126166 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21357 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 51770 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199293 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8180929 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2059597 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 4835454 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15075980 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8180929 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2059597 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 4835454 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15075980 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150400 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082864 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181449 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.151693 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049959 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050732 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.315336 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.131673 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076020 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100479 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.128185 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092721 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000019 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000010 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108865 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069181 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.233827 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.143524 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108865 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069181 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.233827 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.143524 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22820.183182 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17613.987775 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8601.805116 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37104.978312 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30235.776682 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 24304.354652 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13189.439555 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16369.395431 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7634.812324 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6500 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27281.017370 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24273.012037 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14480.202898 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27281.017370 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24273.012037 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14480.202898 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 642685 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 913 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 30067 # 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number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151074 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082508 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.183103 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.153289 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049890 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.051112 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.315634 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.136183 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075656 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100592 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130361 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094049 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000163 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000045 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109341 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069141 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.235171 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.146316 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109341 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069141 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.235171 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.146316 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23147.063783 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17394.983005 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 8764.089258 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37895.394695 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32350.284466 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 26271.400519 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13179.249763 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16519.708469 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8074.645116 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 15889.111111 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15889.111111 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27788.790498 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25280.859334 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15406.369391 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27788.790498 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25280.859334 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15406.369391 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 895030 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1251 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 63218 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.157835 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 113.727273 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 835893 # number of writebacks -system.cpu0.dcache.writebacks::total 835893 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 280644 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 280644 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 507552 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 507552 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1619 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1619 # 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number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6285455992 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1553735990 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2601199489 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4154935479 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24156000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66182251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90338251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3586353240 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6854038231 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10440391471 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3586353240 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6854038231 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10440391471 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 290678000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 312039500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 602717500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 359850500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 427676500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 787527000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 650528500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 739716000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1390244500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082864 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086114 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039386 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050732 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047029 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021694 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100479 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.098740 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037343 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069181 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070824 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032167 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069181 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070824 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032167 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20743.108991 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16776.418010 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17882.267233 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34919.339027 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29238.787476 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31132.673548 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11188.513201 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12190.504881 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.409989 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25170.040636 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20013.835665 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21528.799816 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25170.040636 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20013.835665 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21528.799816 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 835818 # number of writebacks +system.cpu0.dcache.writebacks::total 835818 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 296217 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 296217 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 534994 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 534994 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1640 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1640 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 831211 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 831211 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 831211 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 831211 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 94884 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 267717 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 362601 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43578 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 94069 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 137647 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2106 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6047 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8153 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 9 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 138462 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 361786 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 500248 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 138462 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 361786 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 500248 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1998980000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4480743134 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6479723134 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1555929490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2922490326 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4478419816 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 23542500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 72865001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96407501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 124998 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 124998 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3554909490 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7403233460 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10958142950 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3554909490 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7403233460 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10958142950 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 249968500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342709000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 592677500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 320834500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 419662000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 740496500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 570803000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 762371000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1333174000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082508 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086925 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040574 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051112 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047199 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022383 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100592 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.102549 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040011 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000163 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000045 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069141 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071318 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033159 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069141 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071318 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033159 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21067.619409 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16736.864428 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17870.119316 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35704.472211 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31067.517737 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32535.542482 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11178.774929 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12049.776914 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11824.788544 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 13888.666667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13888.666667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25674.260736 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20463.018083 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21905.420811 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25674.260736 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20463.018083 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21905.420811 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1439,22 +1439,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1201953 # DTB read hits -system.cpu1.dtb.read_misses 1367 # DTB read misses +system.cpu1.dtb.read_hits 1168812 # DTB read hits +system.cpu1.dtb.read_misses 1325 # DTB read misses system.cpu1.dtb.read_acv 34 # DTB read access violations -system.cpu1.dtb.read_accesses 142945 # DTB read accesses -system.cpu1.dtb.write_hits 898873 # DTB write hits -system.cpu1.dtb.write_misses 185 # DTB write misses -system.cpu1.dtb.write_acv 23 # DTB write access violations -system.cpu1.dtb.write_accesses 58321 # DTB write accesses -system.cpu1.dtb.data_hits 2100826 # DTB hits -system.cpu1.dtb.data_misses 1552 # DTB misses -system.cpu1.dtb.data_acv 57 # DTB access violations -system.cpu1.dtb.data_accesses 201266 # DTB accesses -system.cpu1.itb.fetch_hits 861128 # ITB hits -system.cpu1.itb.fetch_misses 693 # ITB misses -system.cpu1.itb.fetch_acv 30 # ITB acv -system.cpu1.itb.fetch_accesses 861821 # ITB accesses +system.cpu1.dtb.read_accesses 141647 # DTB read accesses +system.cpu1.dtb.write_hits 873733 # DTB write hits +system.cpu1.dtb.write_misses 170 # DTB write misses +system.cpu1.dtb.write_acv 22 # DTB write access violations +system.cpu1.dtb.write_accesses 57095 # DTB write accesses +system.cpu1.dtb.data_hits 2042545 # DTB hits +system.cpu1.dtb.data_misses 1495 # DTB misses +system.cpu1.dtb.data_acv 56 # DTB access violations +system.cpu1.dtb.data_accesses 198742 # DTB accesses +system.cpu1.itb.fetch_hits 849434 # ITB hits +system.cpu1.itb.fetch_misses 664 # ITB misses +system.cpu1.itb.fetch_acv 34 # ITB acv +system.cpu1.itb.fetch_accesses 850098 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1467,64 +1467,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953604102 # number of cpu cycles simulated +system.cpu1.numCycles 953402608 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7738659 # Number of instructions committed -system.cpu1.committedOps 7738659 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7195320 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 44971 # Number of float alu accesses -system.cpu1.num_func_calls 212104 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 948894 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7195320 # number of integer instructions -system.cpu1.num_fp_insts 44971 # number of float instructions -system.cpu1.num_int_register_reads 10028277 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5244710 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24303 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24579 # number of times the floating registers were written -system.cpu1.num_mem_refs 2108049 # number of memory refs -system.cpu1.num_load_insts 1206835 # Number of load instructions -system.cpu1.num_store_insts 901214 # Number of store instructions -system.cpu1.num_idle_cycles 922268722.786044 # Number of idle cycles -system.cpu1.num_busy_cycles 31335379.213956 # Number of busy cycles -system.cpu1.not_idle_fraction 0.032860 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.967140 # Percentage of idle cycles -system.cpu1.Branches 1227675 # Number of branches fetched -system.cpu1.op_class::No_OpClass 413043 5.34% 5.34% # Class of executed instruction -system.cpu1.op_class::IntAlu 5041451 65.13% 70.47% # Class of executed instruction -system.cpu1.op_class::IntMult 8548 0.11% 70.58% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.58% # Class of executed instruction -system.cpu1.op_class::FloatAdd 4999 0.06% 70.64% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 70.64% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 70.64% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 70.64% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 70.65% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::MemRead 1235944 15.97% 86.62% # Class of executed instruction -system.cpu1.op_class::MemWrite 902434 11.66% 98.28% # Class of executed instruction -system.cpu1.op_class::IprAccess 133039 1.72% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7466514 # Number of instructions committed +system.cpu1.committedOps 7466514 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 6940405 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 43972 # Number of float alu accesses +system.cpu1.num_func_calls 203873 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 905018 # number of instructions that are conditional controls +system.cpu1.num_int_insts 6940405 # number of integer instructions +system.cpu1.num_fp_insts 43972 # number of float instructions +system.cpu1.num_int_register_reads 9656232 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5062933 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 23750 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24129 # number of times the floating registers were written +system.cpu1.num_mem_refs 2049510 # number of memory refs +system.cpu1.num_load_insts 1173515 # Number of load instructions +system.cpu1.num_store_insts 875995 # Number of store instructions +system.cpu1.num_idle_cycles 923975227.132686 # Number of idle cycles +system.cpu1.num_busy_cycles 29427380.867314 # Number of busy cycles +system.cpu1.not_idle_fraction 0.030866 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.969134 # Percentage of idle cycles +system.cpu1.Branches 1173577 # Number of branches fetched +system.cpu1.op_class::No_OpClass 399506 5.35% 5.35% # Class of executed instruction +system.cpu1.op_class::IntAlu 4845173 64.88% 70.23% # Class of executed instruction +system.cpu1.op_class::IntMult 8216 0.11% 70.34% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.34% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5112 0.07% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 70.42% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::MemRead 1201694 16.09% 86.51% # Class of executed instruction +system.cpu1.op_class::MemWrite 877208 11.75% 98.25% # Class of executed instruction +system.cpu1.op_class::IprAccess 130346 1.75% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7740268 # Class of executed instruction +system.cpu1.op_class::total 7468065 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1542,35 +1542,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8997141 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8310458 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 125233 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7551874 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6369180 # Number of BTB hits +system.cpu2.branchPred.lookups 9007020 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8266685 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 125563 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 6913379 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 4889018 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 84.339066 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 284910 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 13175 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 70.718212 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 301119 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7670 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3232647 # DTB read hits -system.cpu2.dtb.read_misses 11674 # DTB read misses -system.cpu2.dtb.read_acv 117 # DTB read access violations -system.cpu2.dtb.read_accesses 217551 # DTB read accesses -system.cpu2.dtb.write_hits 2020818 # DTB write hits -system.cpu2.dtb.write_misses 2669 # DTB write misses -system.cpu2.dtb.write_acv 109 # DTB write access violations -system.cpu2.dtb.write_accesses 82591 # DTB write accesses -system.cpu2.dtb.data_hits 5253465 # DTB hits -system.cpu2.dtb.data_misses 14343 # DTB misses -system.cpu2.dtb.data_acv 226 # DTB access violations -system.cpu2.dtb.data_accesses 300142 # DTB accesses -system.cpu2.itb.fetch_hits 371576 # ITB hits -system.cpu2.itb.fetch_misses 5695 # ITB misses -system.cpu2.itb.fetch_acv 235 # ITB acv -system.cpu2.itb.fetch_accesses 377271 # ITB accesses +system.cpu2.dtb.read_hits 3485225 # DTB read hits +system.cpu2.dtb.read_misses 12620 # DTB read misses +system.cpu2.dtb.read_acv 152 # DTB read access violations +system.cpu2.dtb.read_accesses 227645 # DTB read accesses +system.cpu2.dtb.write_hits 2140940 # DTB write hits +system.cpu2.dtb.write_misses 2817 # DTB write misses +system.cpu2.dtb.write_acv 139 # DTB write access violations +system.cpu2.dtb.write_accesses 85106 # DTB write accesses +system.cpu2.dtb.data_hits 5626165 # DTB hits +system.cpu2.dtb.data_misses 15437 # DTB misses +system.cpu2.dtb.data_acv 291 # DTB access violations +system.cpu2.dtb.data_accesses 312751 # DTB accesses +system.cpu2.itb.fetch_hits 539657 # ITB hits +system.cpu2.itb.fetch_misses 5944 # ITB misses +system.cpu2.itb.fetch_acv 165 # ITB acv +system.cpu2.itb.fetch_accesses 545601 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1583,305 +1583,305 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 31002313 # number of cpu cycles simulated +system.cpu2.numCycles 29515720 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8393929 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 36824229 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8997141 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6654090 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8723757 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 635832 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9323842 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 10747 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1941 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 64126 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 88179 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 311 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2581223 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 87099 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27026118 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.362542 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.315525 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9404916 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 35474807 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 9007020 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 5190137 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 18003717 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 410566 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 517 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 9775 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1999 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 235781 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 98995 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 442 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2822037 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 92550 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27961187 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.268716 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.388099 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18302361 67.72% 67.72% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 270640 1.00% 68.72% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 435105 1.61% 70.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4809867 17.80% 88.13% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 769933 2.85% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 167503 0.62% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 192346 0.71% 92.31% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 444449 1.64% 93.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1633914 6.05% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 20241670 72.39% 72.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 312691 1.12% 73.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 474251 1.70% 75.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3278987 11.73% 86.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 837934 3.00% 89.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 194435 0.70% 90.63% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 239683 0.86% 91.48% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 437644 1.57% 93.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1943892 6.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27026118 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.290209 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.187790 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8441173 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9512814 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8253964 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 165145 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 407122 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 167309 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12818 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36409694 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 40311 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 407122 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 8734574 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2556870 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5774789 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 8067686 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1239186 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35224318 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 3572 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 388506 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 20310 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 316059 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 23620864 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 44017646 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 43961139 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 52746 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 21667069 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1953795 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 502665 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 59694 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 2961257 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3405802 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2124807 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 397929 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 274147 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32669106 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 622861 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 32140552 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 36002 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2321360 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1217953 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 439629 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27026118 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.189240 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.607686 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27961187 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.305160 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.201895 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7704419 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 13193149 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6090024 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 535254 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 192290 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 176132 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13346 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 32094888 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 42715 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 192290 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7987526 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4830275 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6354829 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 6312082 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2038145 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 31271508 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 68877 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 405466 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 55957 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 963204 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 20931686 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 38638449 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 38578281 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56251 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 19026086 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1905600 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 533120 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 63723 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3942739 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3510198 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2234995 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 462280 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 329256 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 28739879 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 680947 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 28391596 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 17529 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2438506 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1151582 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 487021 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27961187 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.015393 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.594251 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15119064 55.94% 55.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2962463 10.96% 66.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1396485 5.17% 72.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5591038 20.69% 92.76% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 885243 3.28% 96.03% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 550698 2.04% 98.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 348435 1.29% 99.36% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 154603 0.57% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18089 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17574861 62.85% 62.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2788082 9.97% 72.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1379347 4.93% 77.76% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4037262 14.44% 92.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1018579 3.64% 95.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 572705 2.05% 97.89% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 385941 1.38% 99.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 155733 0.56% 99.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 48677 0.17% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27026118 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27961187 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 38019 14.73% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 117677 45.59% 60.31% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 102444 39.69% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 82533 21.35% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 178965 46.29% 67.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 125088 32.36% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 26413495 82.18% 82.19% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20160 0.06% 82.25% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.25% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8429 0.03% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3362943 10.46% 92.74% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2042777 6.36% 99.10% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 289088 0.90% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 22261960 78.41% 78.42% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21111 0.07% 78.49% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 78.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20516 0.07% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3614417 12.73% 91.30% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2165470 7.63% 98.93% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 304438 1.07% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 32140552 # Type of FU issued -system.cpu2.iq.rate 1.036715 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 258140 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.008032 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 91366801 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 35502508 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 31706710 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 234563 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114868 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 110893 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 32274032 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 122220 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 191624 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 28391596 # Type of FU issued +system.cpu2.iq.rate 0.961914 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 386586 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.013616 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 84894790 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 31745632 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27810644 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 253704 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 119619 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 117118 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 28639647 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 136079 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206810 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 457264 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1199 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4154 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 177923 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 438537 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1486 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6057 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 183313 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4195 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 54966 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5003 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 177760 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 407122 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 1875775 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 219548 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 34577439 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 209711 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3405802 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2124807 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 553318 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 48768 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 120434 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4154 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 65270 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 127814 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 193084 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 31975437 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3252613 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 165115 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 192290 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4010862 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 349296 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 30806306 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 54542 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3510198 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2234995 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 606167 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 15566 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 285460 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6057 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 62858 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 135105 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 197963 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 28193561 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3506622 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 198035 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1285472 # number of nop insts executed -system.cpu2.iew.exec_refs 5280547 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7393667 # Number of branches executed -system.cpu2.iew.exec_stores 2027934 # Number of stores executed -system.cpu2.iew.exec_rate 1.031389 # Inst execution rate -system.cpu2.iew.wb_sent 31851458 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 31817603 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 18729651 # num instructions producing a value -system.cpu2.iew.wb_consumers 22311181 # num instructions consuming a value +system.cpu2.iew.exec_nop 1385480 # number of nop insts executed +system.cpu2.iew.exec_refs 5655108 # number of memory reference insts executed +system.cpu2.iew.exec_branches 5954900 # Number of branches executed +system.cpu2.iew.exec_stores 2148486 # Number of stores executed +system.cpu2.iew.exec_rate 0.955205 # Inst execution rate +system.cpu2.iew.wb_sent 27969918 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27927762 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15888662 # num instructions producing a value +system.cpu2.iew.wb_consumers 19538696 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.026298 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.839474 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.946200 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.813189 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2502130 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 183232 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 177866 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26618996 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.203206 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.875540 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2672008 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 193926 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 180997 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 27494343 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.021637 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.858517 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16042703 60.27% 60.27% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2256116 8.48% 68.74% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1167560 4.39% 73.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5327635 20.01% 93.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 518833 1.95% 95.09% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 187130 0.70% 95.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 168998 0.63% 96.43% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 171142 0.64% 97.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 778879 2.93% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18377188 66.84% 66.84% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2251123 8.19% 75.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1180007 4.29% 79.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 3743706 13.62% 92.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 543464 1.98% 94.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 201872 0.73% 95.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 166281 0.60% 96.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 179533 0.65% 96.90% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 851169 3.10% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26618996 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 32028137 # Number of instructions committed -system.cpu2.commit.committedOps 32028137 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 27494343 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 28089240 # Number of instructions committed +system.cpu2.commit.committedOps 28089240 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4895422 # Number of memory references committed -system.cpu2.commit.loads 2948538 # Number of loads committed -system.cpu2.commit.membars 64184 # Number of memory barriers committed -system.cpu2.commit.branches 7237241 # Number of branches committed -system.cpu2.commit.fp_insts 109664 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 30577389 # Number of committed integer instructions. -system.cpu2.commit.function_calls 229570 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1171866 3.66% 3.66% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 25576585 79.86% 83.52% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 19753 0.06% 83.58% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.58% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 8429 0.03% 83.60% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.60% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.60% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.60% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3012722 9.41% 93.01% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 1948474 6.08% 99.10% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 289088 0.90% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5123343 # Number of memory references committed +system.cpu2.commit.loads 3071661 # Number of loads committed +system.cpu2.commit.membars 68272 # Number of memory barriers committed +system.cpu2.commit.branches 5784239 # Number of branches committed +system.cpu2.commit.fp_insts 115390 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 26574373 # Number of committed integer instructions. +system.cpu2.commit.function_calls 240380 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1220895 4.35% 4.35% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 21328709 75.93% 80.28% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20651 0.07% 80.35% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 80.35% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20067 0.07% 80.42% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 80.42% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 80.42% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 80.42% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1228 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3139933 11.18% 91.61% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2053319 7.31% 98.92% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 304438 1.08% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 32028137 # Class of committed instruction -system.cpu2.commit.bw_lim_events 778879 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 28089240 # Class of committed instruction +system.cpu2.commit.bw_lim_events 851169 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 60296509 # The number of ROB reads -system.cpu2.rob.rob_writes 69467378 # The number of ROB writes -system.cpu2.timesIdled 246541 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3976195 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1746763449 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 30858711 # Number of Instructions Simulated -system.cpu2.committedOps 30858711 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.004654 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.004654 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.995368 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.995368 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 42053824 # number of integer regfile reads -system.cpu2.int_regfile_writes 22390255 # number of integer regfile writes -system.cpu2.fp_regfile_reads 67731 # number of floating regfile reads -system.cpu2.fp_regfile_writes 68085 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5172203 # number of misc regfile reads -system.cpu2.misc_regfile_writes 258202 # number of misc regfile writes +system.cpu2.rob.rob_reads 57327258 # The number of ROB reads +system.cpu2.rob.rob_writes 61989353 # The number of ROB writes +system.cpu2.timesIdled 175568 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1554533 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1746289037 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 26870801 # Number of Instructions Simulated +system.cpu2.committedOps 26870801 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.098431 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.098431 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.910389 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.910389 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 36957190 # number of integer regfile reads +system.cpu2.int_regfile_writes 19824047 # number of integer regfile writes +system.cpu2.fp_regfile_reads 70953 # number of floating regfile reads +system.cpu2.fp_regfile_writes 70972 # number of floating regfile writes +system.cpu2.misc_regfile_reads 3637810 # number of misc regfile reads +system.cpu2.misc_regfile_writes 273227 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed |