diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | 4908 |
1 files changed, 2460 insertions, 2448 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 9d2732791..605ec955f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,162 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.848878 # Number of seconds simulated -sim_ticks 2848878048000 # Number of ticks simulated -final_tick 2848878048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.847227 # Number of seconds simulated +sim_ticks 2847227406000 # Number of ticks simulated +final_tick 2847227406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 186843 # Simulator instruction rate (inst/s) -host_op_rate 226247 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4196685224 # Simulator tick rate (ticks/s) -host_mem_usage 620168 # Number of bytes of host memory used -host_seconds 678.84 # Real time elapsed on the host -sim_insts 126836472 # Number of instructions simulated -sim_ops 153585571 # Number of ops (including micro ops) simulated +host_inst_rate 172654 # Simulator instruction rate (inst/s) +host_op_rate 209070 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3861033235 # Simulator tick rate (ticks/s) +host_mem_usage 617124 # Number of bytes of host memory used +host_seconds 737.43 # Real time elapsed on the host +sim_insts 127319545 # Number of instructions simulated +sim_ops 154173476 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 8960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 7488 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1701632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1345580 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8578560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 207872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 624532 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 336128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1647744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1317552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8353536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 217280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 643604 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 446720 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12804992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1701632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 207872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1909504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8865600 # Number of bytes written to this memory +system.physmem.bytes_read::total 12635780 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1647744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 217280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1865024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8874176 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8883164 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 140 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8891740 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 117 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26588 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21546 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134040 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3248 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9779 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5252 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25746 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21109 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 130524 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3395 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6980 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 200620 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138525 # Number of write requests responded to by this memory +system.physmem.num_reads::total 197977 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138659 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142916 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3145 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 143050 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2630 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 597299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 472319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3011206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 247 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 72966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 219220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 117986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 578719 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 462749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2933919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 292 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 76313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 226046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 156896 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4494749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 597299 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 72966 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 670265 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3111962 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4437924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 578719 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 76313 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 655032 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3116778 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6155 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3118127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3111962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3122947 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3116778 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2630 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 597299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 478470 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3011206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 247 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 72966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 219234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 117986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 578719 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 468904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2933919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 76313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 226060 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 156896 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7612876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 200620 # Number of read requests accepted -system.physmem.writeReqs 142916 # Number of write requests accepted -system.physmem.readBursts 200620 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 142916 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12829952 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9728 # Total number of bytes read from write queue -system.physmem.bytesWritten 8896256 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12804992 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8883164 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7560871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 197977 # Number of read requests accepted +system.physmem.writeReqs 143050 # Number of write requests accepted +system.physmem.readBursts 197977 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 143050 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12661056 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue +system.physmem.bytesWritten 8904256 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12635780 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8891740 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12282 # Per bank write bursts -system.physmem.perBankRdBursts::1 12615 # Per bank write bursts -system.physmem.perBankRdBursts::2 13546 # Per bank write bursts -system.physmem.perBankRdBursts::3 12896 # Per bank write bursts -system.physmem.perBankRdBursts::4 15667 # Per bank write bursts -system.physmem.perBankRdBursts::5 12734 # Per bank write bursts -system.physmem.perBankRdBursts::6 12682 # Per bank write bursts -system.physmem.perBankRdBursts::7 12950 # Per bank write bursts -system.physmem.perBankRdBursts::8 12070 # Per bank write bursts -system.physmem.perBankRdBursts::9 12307 # Per bank write bursts -system.physmem.perBankRdBursts::10 11595 # Per bank write bursts -system.physmem.perBankRdBursts::11 10656 # Per bank write bursts -system.physmem.perBankRdBursts::12 11845 # Per bank write bursts -system.physmem.perBankRdBursts::13 12839 # Per bank write bursts -system.physmem.perBankRdBursts::14 12069 # Per bank write bursts -system.physmem.perBankRdBursts::15 11715 # Per bank write bursts -system.physmem.perBankWrBursts::0 8801 # Per bank write bursts -system.physmem.perBankWrBursts::1 9221 # Per bank write bursts -system.physmem.perBankWrBursts::2 9816 # Per bank write bursts -system.physmem.perBankWrBursts::3 9124 # Per bank write bursts -system.physmem.perBankWrBursts::4 8304 # Per bank write bursts -system.physmem.perBankWrBursts::5 8866 # Per bank write bursts -system.physmem.perBankWrBursts::6 8953 # Per bank write bursts -system.physmem.perBankWrBursts::7 8983 # Per bank write bursts -system.physmem.perBankWrBursts::8 8497 # Per bank write bursts -system.physmem.perBankWrBursts::9 8715 # Per bank write bursts -system.physmem.perBankWrBursts::10 8212 # Per bank write bursts -system.physmem.perBankWrBursts::11 7775 # Per bank write bursts -system.physmem.perBankWrBursts::12 8513 # Per bank write bursts -system.physmem.perBankWrBursts::13 8820 # Per bank write bursts -system.physmem.perBankWrBursts::14 8499 # Per bank write bursts -system.physmem.perBankWrBursts::15 7905 # Per bank write bursts +system.physmem.perBankRdBursts::0 11990 # Per bank write bursts +system.physmem.perBankRdBursts::1 12090 # Per bank write bursts +system.physmem.perBankRdBursts::2 12710 # Per bank write bursts +system.physmem.perBankRdBursts::3 12556 # Per bank write bursts +system.physmem.perBankRdBursts::4 14859 # Per bank write bursts +system.physmem.perBankRdBursts::5 12263 # Per bank write bursts +system.physmem.perBankRdBursts::6 12121 # Per bank write bursts +system.physmem.perBankRdBursts::7 12401 # Per bank write bursts +system.physmem.perBankRdBursts::8 11839 # Per bank write bursts +system.physmem.perBankRdBursts::9 11973 # Per bank write bursts +system.physmem.perBankRdBursts::10 12288 # Per bank write bursts +system.physmem.perBankRdBursts::11 11633 # Per bank write bursts +system.physmem.perBankRdBursts::12 12418 # Per bank write bursts +system.physmem.perBankRdBursts::13 12730 # Per bank write bursts +system.physmem.perBankRdBursts::14 11938 # Per bank write bursts +system.physmem.perBankRdBursts::15 12020 # Per bank write bursts +system.physmem.perBankWrBursts::0 8637 # Per bank write bursts +system.physmem.perBankWrBursts::1 8726 # Per bank write bursts +system.physmem.perBankWrBursts::2 9304 # Per bank write bursts +system.physmem.perBankWrBursts::3 8986 # Per bank write bursts +system.physmem.perBankWrBursts::4 8078 # Per bank write bursts +system.physmem.perBankWrBursts::5 8592 # Per bank write bursts +system.physmem.perBankWrBursts::6 8645 # Per bank write bursts +system.physmem.perBankWrBursts::7 8770 # Per bank write bursts +system.physmem.perBankWrBursts::8 8363 # Per bank write bursts +system.physmem.perBankWrBursts::9 8478 # Per bank write bursts +system.physmem.perBankWrBursts::10 8927 # Per bank write bursts +system.physmem.perBankWrBursts::11 8795 # Per bank write bursts +system.physmem.perBankWrBursts::12 9084 # Per bank write bursts +system.physmem.perBankWrBursts::13 8813 # Per bank write bursts +system.physmem.perBankWrBursts::14 8578 # Per bank write bursts +system.physmem.perBankWrBursts::15 8353 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 24 # Number of times write queue was full causing retry -system.physmem.totGap 2848877502000 # Total gap between requests +system.physmem.numWrRetry 38 # Number of times write queue was full causing retry +system.physmem.totGap 2847226871000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 552 # Read request sizes (log2) +system.physmem.readPktSize::2 553 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 200040 # Read request sizes (log2) +system.physmem.readPktSize::6 197396 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 138525 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 88667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 138659 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 85811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9476 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6090 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4527 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 718 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -184,160 +184,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 169 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 68 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 83 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 92501 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 234.874693 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.252552 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 298.003949 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50468 54.56% 54.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17746 19.18% 73.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6298 6.81% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3474 3.76% 84.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2881 3.11% 87.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1488 1.61% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 938 1.01% 90.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 959 1.04% 91.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8249 8.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 92501 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6731 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.782499 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 569.000641 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6729 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::60 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 145 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 92332 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 233.562015 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.589518 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 297.350425 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50532 54.73% 54.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17809 19.29% 74.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6200 6.71% 80.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3503 3.79% 84.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2794 3.03% 87.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1407 1.52% 89.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 909 0.98% 90.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 989 1.07% 91.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8189 8.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 92332 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6903 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.657830 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 561.171003 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6902 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6731 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6731 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.651315 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.819444 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.992190 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5609 83.33% 83.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 487 7.24% 90.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 91 1.35% 91.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 48 0.71% 92.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 35 0.52% 93.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 15 0.22% 93.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 45 0.67% 94.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 18 0.27% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 127 1.89% 96.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 10 0.15% 96.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.12% 96.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 12 0.18% 96.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 75 1.11% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 97.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.04% 97.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 23 0.34% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 82 1.22% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.48% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6903 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6903 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.154860 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.644326 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.603874 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5813 84.21% 84.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 373 5.40% 89.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 70 1.01% 90.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 58 0.84% 91.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 265 3.84% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 25 0.36% 95.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 18 0.26% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 26 0.38% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 14 0.20% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 9 0.13% 96.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.04% 96.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.12% 96.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 153 2.22% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.09% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 5 0.07% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 5 0.07% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.04% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.04% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.04% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.48% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 1 0.01% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 5 0.07% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.12% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 9 0.13% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6731 # Writes before turning the bus around for reads -system.physmem.totQLat 5345988099 # Total ticks spent queuing -system.physmem.totMemAccLat 9104763099 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1002340000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26667.54 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::108-111 8 0.12% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 9 0.13% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 6 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6903 # Writes before turning the bus around for reads +system.physmem.totQLat 5250518808 # Total ticks spent queuing +system.physmem.totMemAccLat 8959812558 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 989145000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26540.69 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45417.54 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.50 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.49 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 45290.69 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.45 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.13 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.44 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.22 # Average write queue length when enqueuing -system.physmem.readRowHits 166512 # Number of row buffer hits during reads -system.physmem.writeRowHits 80458 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.06 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.88 # Row buffer hit rate for writes -system.physmem.avgGap 8292806.29 # Average gap between requests -system.physmem.pageHitRate 72.75 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 369525240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 201625875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 821901600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 467000640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186074475600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 85037796405 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634728846500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1907701171860 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.633786 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2719381991131 # Time in different power states -system.physmem_0.memoryStateTime::REF 95130100000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.07 # Average write queue length when enqueuing +system.physmem.readRowHits 164412 # Number of row buffer hits during reads +system.physmem.writeRowHits 80213 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.64 # Row buffer hit rate for writes +system.physmem.avgGap 8348977.86 # Average gap between requests +system.physmem.pageHitRate 72.59 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 354957120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 193677000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 787722000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 451902240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185966660880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83190012300 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1635359290500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1906304222040 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.531375 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2720439936839 # Time in different power states +system.physmem_0.memoryStateTime::REF 95074980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34360263869 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31706739411 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 329782320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179940750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 741741000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 433745280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186074475600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 83868136740 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635754863750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1907382685440 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.521992 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2721101495830 # Time in different power states -system.physmem_1.memoryStateTime::REF 95130100000 # Time in different power states +system.physmem_1.actEnergy 343072800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 187192500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 755336400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 449653680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185966660880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82901008620 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635612802500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1906215727380 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.500294 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2720864046511 # Time in different power states +system.physmem_1.memoryStateTime::REF 95074980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32646289170 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31288281989 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory @@ -363,19 +365,19 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 36258885 # Number of BP lookups -system.cpu0.branchPred.condPredicted 17779541 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1788671 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 20741460 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 11048316 # Number of BTB hits +system.cpu0.branchPred.lookups 20737076 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13605991 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1017313 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13202297 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 8722072 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 53.266819 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 11219024 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 931479 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4153759 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 3951203 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 202556 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 105471 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 66.064807 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3399643 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 216094 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 760668 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 581758 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 178910 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 99353 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -406,59 +408,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 71829 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 71829 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46722 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 25107 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 71829 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 71829 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 71829 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 7556 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12351.641080 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11368.840758 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 8528.588507 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 7496 99.21% 99.21% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 51 0.67% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 5 0.07% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 1 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 7556 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 581987000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 581987000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 581987000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5875 77.75% 77.75% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1681 22.25% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 7556 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71829 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 68420 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 68420 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46092 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22328 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 68420 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 68420 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 68420 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6777 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12395.971669 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11546.443771 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5803.014677 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6374 94.05% 94.05% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 345 5.09% 99.14% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 47 0.69% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 6 0.09% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.06% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6777 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 338010000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 338010000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 338010000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5225 77.10% 77.10% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1552 22.90% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6777 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 68420 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71829 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7556 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 68420 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6777 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7556 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 79385 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6777 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 75197 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 24842790 # DTB read hits -system.cpu0.dtb.read_misses 65179 # DTB read misses -system.cpu0.dtb.write_hits 18502994 # DTB write hits -system.cpu0.dtb.write_misses 6650 # DTB write misses +system.cpu0.dtb.read_hits 17339980 # DTB read hits +system.cpu0.dtb.read_misses 61941 # DTB read misses +system.cpu0.dtb.write_hits 14540399 # DTB write hits +system.cpu0.dtb.write_misses 6479 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3814 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1457 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2027 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3513 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1354 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1959 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 602 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24907969 # DTB read accesses -system.cpu0.dtb.write_accesses 18509644 # DTB write accesses +system.cpu0.dtb.perms_faults 521 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17401921 # DTB read accesses +system.cpu0.dtb.write_accesses 14546878 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 43345784 # DTB hits -system.cpu0.dtb.misses 71829 # DTB misses -system.cpu0.dtb.accesses 43417613 # DTB accesses +system.cpu0.dtb.hits 31880379 # DTB hits +system.cpu0.dtb.misses 68420 # DTB misses +system.cpu0.dtb.accesses 31948799 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -488,38 +489,40 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 4265 # Table walker walks requested -system.cpu0.itb.walker.walksShort 4265 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 325 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3940 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 4265 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 4265 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 4265 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2684 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12705.663189 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11959.550432 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5173.129128 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 2444 91.06% 91.06% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 221 8.23% 99.29% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 17 0.63% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2684 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 581277500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 581277500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 581277500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2364 88.08% 88.08% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 320 11.92% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2684 # Table walker page sizes translated +system.cpu0.itb.walker.walks 3977 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3977 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 304 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3673 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3977 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3977 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3977 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2411 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12713.811696 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 12041.525578 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 4752.572139 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 358 14.85% 14.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1847 76.61% 91.46% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 161 6.68% 98.13% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 17 0.71% 98.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 26 1.08% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2411 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 337545500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 337545500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 337545500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2112 87.60% 87.60% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 299 12.40% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2411 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4265 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4265 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3977 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3977 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2684 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2684 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6949 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 71322502 # ITB inst hits -system.cpu0.itb.inst_misses 4265 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2411 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2411 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6388 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 38606266 # ITB inst hits +system.cpu0.itb.inst_misses 3977 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -528,762 +531,773 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2459 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2216 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7664 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 6955 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 71326767 # ITB inst accesses -system.cpu0.itb.hits 71322502 # DTB hits -system.cpu0.itb.misses 4265 # DTB misses -system.cpu0.itb.accesses 71326767 # DTB accesses -system.cpu0.numCycles 248723849 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 38610243 # ITB inst accesses +system.cpu0.itb.hits 38606266 # DTB hits +system.cpu0.itb.misses 3977 # DTB misses +system.cpu0.itb.accesses 38610243 # DTB accesses +system.cpu0.numCycles 167224982 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 112829406 # Number of instructions committed -system.cpu0.committedOps 136421013 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 8883957 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1865 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5449058541 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.204424 # CPI: cycles per instruction -system.cpu0.ipc 0.453633 # IPC: instructions per cycle -system.cpu0.op_class_0::No_OpClass 2315 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 92785256 68.01% 68.02% # Class of committed instruction -system.cpu0.op_class_0::IntMult 112251 0.08% 68.10% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 8279 0.01% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 68.10% # Class of committed instruction -system.cpu0.op_class_0::MemRead 24255979 17.78% 85.88% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 19256933 14.12% 100.00% # Class of committed instruction +system.cpu0.committedInsts 79715648 # Number of instructions committed +system.cpu0.committedOps 95927461 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 5237247 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1849 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5527254348 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.097769 # CPI: cycles per instruction +system.cpu0.ipc 0.476697 # IPC: instructions per cycle +system.cpu0.op_class_0::No_OpClass 2273 0.00% 0.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 63730677 66.44% 66.44% # Class of committed instruction +system.cpu0.op_class_0::IntMult 92076 0.10% 66.53% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 8115 0.01% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::MemRead 16811055 17.52% 84.07% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 15283265 15.93% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 136421013 # Class of committed instruction +system.cpu0.op_class_0::total 95927461 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1871 # number of quiesce instructions executed -system.cpu0.tickCycles 199772172 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 48951677 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 757698 # number of replacements -system.cpu0.dcache.tags.tagsinuse 497.510170 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 41768211 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 758210 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.087919 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 600550000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.510170 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971700 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.971700 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1852 # number of quiesce instructions executed +system.cpu0.tickCycles 128530134 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 38694848 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 715130 # number of replacements +system.cpu0.dcache.tags.tagsinuse 500.249385 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 30394668 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 715642 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 42.471890 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 356009000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.249385 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977050 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.977050 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 86683357 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 86683357 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 23240588 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23240588 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 17340312 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 17340312 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 329150 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 329150 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374937 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 374937 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370987 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 370987 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 40580900 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 40580900 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 40910050 # number of overall hits -system.cpu0.dcache.overall_hits::total 40910050 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 491866 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 491866 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 603751 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 603751 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141943 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 141943 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21447 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21447 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20439 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20439 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1095617 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1095617 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1237560 # number of overall misses -system.cpu0.dcache.overall_misses::total 1237560 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6971329500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6971329500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12451928500 # 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number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 41676517 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 41676517 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 42147610 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 42147610 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.020725 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.020725 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033646 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.033646 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301306 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301306 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054107 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054107 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052217 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052217 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026289 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026289 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029363 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029363 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14173.229091 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14173.229091 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20624.278055 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20624.278055 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15415.186273 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15415.186273 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25958.657469 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25958.657469 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63780149 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63780149 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15810331 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15810331 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 13424811 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 13424811 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320440 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 320440 # 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number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30279766 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30279766 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30736689 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30736689 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028495 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028495 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041476 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.041476 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298700 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298700 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055123 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055123 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053890 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053890 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034499 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.034499 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038427 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.038427 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13334.744017 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13334.744017 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17757.543884 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17757.543884 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15101.445534 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15101.445534 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24211.236447 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24211.236447 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17728.145876 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 17728.145876 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15694.801060 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15694.801060 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15794.202029 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15794.202029 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13969.100598 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13969.100598 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 757698 # number of writebacks -system.cpu0.dcache.writebacks::total 757698 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 75572 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 75572 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266010 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 266010 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14891 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14891 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 341582 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 341582 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 341582 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 341582 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 416294 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 416294 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337741 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 337741 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 108342 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 108342 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6556 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6556 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20439 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20439 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 754035 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 754035 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 862377 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 862377 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32042 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32042 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28724 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28724 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60766 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60766 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5289052500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5289052500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7033138500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7033138500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1803466000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1803466000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104788000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104788000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 510140000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 510140000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 641500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 641500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12322191000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12322191000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14125657000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 14125657000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6702357000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6702357000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6702357000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6702357000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017541 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017541 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018822 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018822 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.229980 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.229980 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016540 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016540 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052217 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052217 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018093 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.018093 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020461 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020461 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12705.089432 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12705.089432 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20824.058968 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20824.058968 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16646.046778 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16646.046778 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15983.526541 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15983.526541 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24959.146729 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24959.146729 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 715130 # number of writebacks +system.cpu0.dcache.writebacks::total 715130 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 71798 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 71798 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255281 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 255281 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14780 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14780 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 327079 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 327079 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 327079 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 327079 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 391925 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 391925 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325620 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 325620 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103078 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 103078 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6527 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6527 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20567 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20567 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 717545 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 717545 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 820623 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 820623 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20575 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20575 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19271 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19271 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39846 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4674150000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4674150000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5703236000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5703236000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1673631500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1673631500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101407500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101407500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 477391500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 477391500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 223500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 223500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10377386000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10377386000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12051017500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12051017500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4615609000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4615609000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4615609000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4615609000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024083 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024083 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023249 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023249 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225592 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225592 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016886 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016886 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053890 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053890 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023697 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023697 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026698 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026698 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11926.133827 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11926.133827 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17515.005221 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17515.005221 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16236.553872 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16236.553872 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15536.617129 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15536.617129 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23211.528176 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23211.528176 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16341.669816 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16341.669816 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16379.909251 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16379.909251 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209174.115224 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209174.115224 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110297.814567 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110297.814567 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 2042425 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.725794 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 69271608 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 2042937 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 33.907853 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6975620000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.725794 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999464 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999464 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14462.348703 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14462.348703 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14685.205630 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14685.205630 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 224330.935601 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 224330.935601 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115836.194348 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115836.194348 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 1962004 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.774944 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36636559 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1962516 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.668158 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6612168000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774944 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999560 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999560 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 144672089 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 144672089 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 69271608 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 69271608 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 69271608 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 69271608 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 69271608 # number of overall hits -system.cpu0.icache.overall_hits::total 69271608 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 2042958 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2042958 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 2042958 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2042958 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 2042958 # number of overall misses -system.cpu0.icache.overall_misses::total 2042958 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20578821000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 20578821000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 20578821000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 20578821000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 20578821000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 20578821000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 71314566 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 71314566 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 71314566 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 71314566 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 71314566 # 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average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10073.051428 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10073.051428 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 79160710 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 79160710 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 36636559 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36636559 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36636559 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36636559 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36636559 # number of overall hits +system.cpu0.icache.overall_hits::total 36636559 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1962531 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1962531 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1962531 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1962531 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1962531 # number of overall misses +system.cpu0.icache.overall_misses::total 1962531 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18757498000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18757498000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18757498000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18757498000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18757498000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18757498000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 38599090 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 38599090 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 38599090 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 38599090 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 38599090 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 38599090 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050844 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050844 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050844 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050844 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050844 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050844 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9557.809787 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9557.809787 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9557.809787 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9557.809787 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9557.809787 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9557.809787 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 2042425 # number of writebacks -system.cpu0.icache.writebacks::total 2042425 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2042958 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 2042958 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 2042958 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 2042958 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 2042958 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 2042958 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3917 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 3917 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3917 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 3917 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19557342500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 19557342500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19557342500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 19557342500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19557342500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 19557342500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 557356500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 557356500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 557356500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 557356500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028647 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028647 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028647 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028647 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028647 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028647 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9573.051673 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9573.051673 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9573.051673 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927381 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1927559 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 155 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.writebacks::writebacks 1962004 # number of writebacks +system.cpu0.icache.writebacks::total 1962004 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1962531 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1962531 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1962531 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1962531 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1962531 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1962531 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3449 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 3449 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3449 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 3449 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17776233000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17776233000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17776233000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17776233000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17776233000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17776233000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 319470000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 319470000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 319470000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 319470000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050844 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.050844 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.050844 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9057.810042 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9057.810042 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9057.810042 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9057.810042 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9057.810042 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9057.810042 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92626.848362 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92626.848362 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1841200 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1841258 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 51 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 244697 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 304900 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16120.127106 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 4899871 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 321020 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 15.263445 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 233630 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 298119 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16125.660847 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 4682482 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 314209 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 14.902444 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14747.855464 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 65.322901 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.062340 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1306.886401 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.900138 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003987 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_blocks::writebacks 14756.008973 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.059574 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.057522 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1311.534778 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.900635 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003544 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.079766 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.983894 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 987 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.080050 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.984232 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 965 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15123 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 320 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 459 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 198 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 370 # 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number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 100249 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 100249 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 856 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 128 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 68340 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 144267 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 213591 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 856 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 128 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 68340 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 144267 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 258926 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 472517 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3449 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20575 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 24024 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19271 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19271 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3449 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 43295 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 23631000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2229000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 25860000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14017177372 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14017177372 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1114674000 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1114674000 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 322353500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 322353500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 176499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 176499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1755037000 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1755037000 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2929882500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2929882500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2420870995 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2420870995 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 23631000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2229000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2929882500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4175907995 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 7131650495 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 23631000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2229000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2929882500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4175907995 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14017177372 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 21148827867 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 291877500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4450889000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4742766500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 291877500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4450889000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4742766500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010241 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.023084 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.011040 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150478 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150478 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034232 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034232 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.188570 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.188570 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034232 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.175382 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.072306 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034232 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.175382 # mshr miss rate for overall accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.163708 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163708 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034822 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034822 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.199889 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.199889 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010241 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.023084 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034822 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.187261 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075686 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010241 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.023084 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034822 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.187261 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.161933 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 39501.170960 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79624.255077 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 79624.255077 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26001.258151 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26001.258151 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17421.547042 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17421.547042 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57646.697534 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57646.697534 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 58632.110275 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29121.138899 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29121.138899 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37595.250453 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44500.623571 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37595.250453 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79624.255077 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63941.054222 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201170.042444 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193884.994021 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 106077.255373 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 107785.824714 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 5755490 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2900081 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44333 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 350983 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 345970 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5013 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 141142 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2764242 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28724 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28724 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 743774 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 2294086 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 245615 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 332229 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 86791 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42912 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 113818 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 300259 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 296935 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2042958 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 604813 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3110 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6136174 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2759564 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14116 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 185351 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 9095205 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 261715136 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104822354 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 23644 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 353660 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 366914794 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1076546 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4066304 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.104124 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.309432 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.167436 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26280.487805 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54135.843337 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 54135.843337 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19643.217143 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19643.217143 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15674.098026 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15674.098026 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 176499 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 176499 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39870.893725 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39870.893725 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42872.146620 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42872.146620 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24148.579986 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24148.579986 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42872.146620 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28945.690941 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33389.283701 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42872.146620 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28945.690941 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54135.843337 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44757.813723 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84626.703392 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 216325.103281 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197417.852980 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84626.703392 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111702.278773 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109545.363206 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 5508026 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2775137 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42660 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 346625 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 340732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5893 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 122459 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2635557 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19271 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19271 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 716131 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 2195168 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 240019 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 309687 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 88590 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43220 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114518 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 14 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 288089 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284462 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1962531 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 586533 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3131 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5893963 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2592135 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13195 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 174334 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 8673627 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 251390912 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99322292 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22180 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 334344 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 351069728 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1056913 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3897709 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.106693 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.313582 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3647917 89.71% 89.71% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 413374 10.17% 99.88% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 5013 0.12% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3487742 89.48% 89.48% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 404074 10.37% 99.85% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 5893 0.15% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4066304 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 5765624998 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3897709 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 5501303494 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115477021 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115667783 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 3070848423 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2949460514 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1304480252 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1225261932 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 8215479 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7656487 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 96957457 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 90771952 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 3600044 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2023819 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 196135 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2284720 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1344428 # Number of BTB hits +system.cpu1.branchPred.lookups 19337823 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6215951 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 910078 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 9913117 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3669706 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 58.844322 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 748131 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 53981 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 144785 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 107908 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 36877 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 17103 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 37.018689 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8699112 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 707232 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3579063 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 3516137 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 62926 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 23615 # Number of mispredicted indirect branches. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1313,58 +1327,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 22955 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 22955 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18858 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4097 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 22955 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 22955 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 22955 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1846 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11730.498375 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11025.049339 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6418.983235 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 1704 92.31% 92.31% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 130 7.04% 99.35% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-49151 9 0.49% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-65535 1 0.05% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1846 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1572230032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1572230032 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1572230032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1316 71.29% 71.29% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 530 28.71% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1846 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 22955 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 26974 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 26974 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20087 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6887 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 26974 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 26974 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 26974 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2714 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11914.148858 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11049.041659 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5760.245338 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 673 24.80% 24.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1844 67.94% 92.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 118 4.35% 97.09% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.06% 99.15% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 13 0.48% 99.63% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 4 0.15% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.04% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.07% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 2 0.07% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2714 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -2024068032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -2024068032 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -2024068032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1997 73.58% 73.58% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 717 26.42% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2714 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26974 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 22955 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1846 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26974 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2714 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1846 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 24801 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2714 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 29688 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3573471 # DTB read hits -system.cpu1.dtb.read_misses 21372 # DTB read misses -system.cpu1.dtb.write_hits 2968093 # DTB write hits -system.cpu1.dtb.write_misses 1583 # DTB write misses +system.cpu1.dtb.read_hits 11185393 # DTB read hits +system.cpu1.dtb.read_misses 25019 # DTB read misses +system.cpu1.dtb.write_hits 6992115 # DTB write hits +system.cpu1.dtb.write_misses 1955 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1717 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 261 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2060 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 164 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 367 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3594843 # DTB read accesses -system.cpu1.dtb.write_accesses 2969676 # DTB write accesses +system.cpu1.dtb.perms_faults 283 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 11210412 # DTB read accesses +system.cpu1.dtb.write_accesses 6994070 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6541564 # DTB hits -system.cpu1.dtb.misses 22955 # DTB misses -system.cpu1.dtb.accesses 6564519 # DTB accesses +system.cpu1.dtb.hits 18177508 # DTB hits +system.cpu1.dtb.misses 26974 # DTB misses +system.cpu1.dtb.accesses 18204482 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1394,44 +1412,45 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 2082 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2082 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 151 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1931 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2082 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2082 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2082 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 843 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11844.009490 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11365.721789 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4291.658656 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 129 15.30% 15.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 559 66.31% 81.61% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 106 12.57% 94.19% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 28 3.32% 97.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.24% 97.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 9 1.07% 98.81% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 1 0.12% 98.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.24% 99.17% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.59% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.12% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.12% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 843 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1573105532 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1573105532 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1573105532 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 703 83.39% 83.39% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 140 16.61% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 843 # Table walker page sizes translated +system.cpu1.itb.walker.walks 2420 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2420 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2239 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2420 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2420 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2420 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1133 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12165.931156 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11504.985007 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4742.932714 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 196 17.30% 17.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 640 56.49% 73.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 219 19.33% 93.12% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 41 3.62% 96.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 96.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 1.32% 98.23% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.71% 98.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.26% 99.21% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.44% 99.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1133 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -2024645532 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -2024645532 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -2024645532 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 964 85.08% 85.08% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 169 14.92% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1133 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2082 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2082 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2420 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2420 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 843 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 843 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 2925 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 6880260 # ITB inst hits -system.cpu1.itb.inst_misses 2082 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1133 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1133 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3553 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 39602800 # ITB inst hits +system.cpu1.itb.inst_misses 2420 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1440,759 +1459,748 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 907 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1166 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1103 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1819 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6882342 # ITB inst accesses -system.cpu1.itb.hits 6880260 # DTB hits -system.cpu1.itb.misses 2082 # DTB misses -system.cpu1.itb.accesses 6882342 # DTB accesses -system.cpu1.numCycles 40344479 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 39605220 # ITB inst accesses +system.cpu1.itb.hits 39602800 # DTB hits +system.cpu1.itb.misses 2420 # DTB misses +system.cpu1.itb.accesses 39605220 # DTB accesses +system.cpu1.numCycles 115435582 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 14007066 # Number of instructions committed -system.cpu1.committedOps 17164558 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1348197 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2750 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5656772716 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.880295 # CPI: cycles per instruction -system.cpu1.ipc 0.347187 # IPC: instructions per cycle -system.cpu1.op_class_0::No_OpClass 24 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 10609725 61.81% 61.81% # Class of committed instruction -system.cpu1.op_class_0::IntMult 25154 0.15% 61.96% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 61.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 3180 0.02% 61.98% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 61.98% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 61.98% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 61.98% # Class of committed instruction -system.cpu1.op_class_0::MemRead 3461168 20.16% 82.14% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 3065307 17.86% 100.00% # Class of committed instruction +system.cpu1.committedInsts 47603897 # Number of instructions committed +system.cpu1.committedOps 58246015 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 5049538 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2772 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5578401245 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.424919 # CPI: cycles per instruction +system.cpu1.ipc 0.412385 # IPC: instructions per cycle +system.cpu1.op_class_0::No_OpClass 66 0.00% 0.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 40076529 68.81% 68.81% # Class of committed instruction +system.cpu1.op_class_0::IntMult 45752 0.08% 68.88% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.88% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 3347 0.01% 68.89% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.89% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.89% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.89% # Class of committed instruction +system.cpu1.op_class_0::MemRead 11012402 18.91% 87.80% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 7107919 12.20% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 17164558 # Class of committed instruction +system.cpu1.op_class_0::total 58246015 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2755 # number of quiesce instructions executed -system.cpu1.tickCycles 27219778 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 13124701 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 155125 # number of replacements -system.cpu1.dcache.tags.tagsinuse 474.675908 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6200474 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 155475 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.880843 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 91637729500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.675908 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.927101 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.927101 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 281 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 69 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.683594 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 13156233 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 13156233 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3254524 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3254524 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2729726 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2729726 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42620 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 42620 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70434 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 70434 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61835 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 61835 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5984250 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5984250 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6026870 # number of overall hits -system.cpu1.dcache.overall_hits::total 6026870 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 133031 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 133031 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 121759 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 121759 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24466 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 24466 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16570 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16570 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23417 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23417 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 254790 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 254790 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 279256 # number of overall misses -system.cpu1.dcache.overall_misses::total 279256 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2166796500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2166796500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4455024500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4455024500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320532500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 320532500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 635944000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 635944000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1106500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1106500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6621821000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6621821000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6621821000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6621821000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3387555 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3387555 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2851485 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2851485 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 67086 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 67086 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87004 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 87004 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85252 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 85252 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 6239040 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 6239040 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 6306126 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 6306126 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039271 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.039271 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.042700 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.042700 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.364696 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.364696 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190451 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190451 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274680 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274680 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040838 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.040838 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044283 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044283 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16287.906578 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16287.906578 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36588.872280 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 36588.872280 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19344.146047 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19344.146047 # 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Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920136 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.920136 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 36398755 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 36398755 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 10795076 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10795076 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6704752 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6704752 # 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number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 145538 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 31004 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 31004 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16960 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16960 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23795 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23795 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 305260 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 305260 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 336264 # number of overall misses +system.cpu1.dcache.overall_misses::total 336264 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2429598500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2429598500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3913148500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3913148500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317482500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 317482500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 583924500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 583924500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 387500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 387500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6342747000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6342747000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6342747000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6342747000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 10954798 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 10954798 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6850290 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6850290 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81354 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 81354 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97131 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97131 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95328 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95328 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 17805088 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 17805088 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 17886442 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 17886442 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.014580 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.014580 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021246 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.021246 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381100 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381100 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174610 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174610 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249612 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249612 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.017145 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.017145 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018800 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.018800 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15211.420468 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15211.420468 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26887.469252 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26887.469252 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18719.487028 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18719.487028 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24539.798277 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24539.798277 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25989.328467 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 25989.328467 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23712.367863 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23712.367863 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20778.179257 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20778.179257 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18862.402755 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18862.402755 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 155125 # number of writebacks -system.cpu1.dcache.writebacks::total 155125 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 12753 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 12753 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 42136 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 42136 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11686 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11686 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 54889 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 54889 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 54889 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 54889 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 120278 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 120278 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79623 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 79623 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23936 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 23936 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4884 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4884 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23417 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23417 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 199901 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 199901 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 223837 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 223837 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2973 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2973 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2311 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2311 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5284 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5284 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1843019500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1843019500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2713747500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2713747500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 448609500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 448609500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89247000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89247000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 612539000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 612539000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1094500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1094500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4556767000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4556767000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5005376500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5005376500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 389467000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 389467000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 389467000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 389467000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035506 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035506 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027923 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027923 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.356796 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.356796 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056135 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056135 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274680 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274680 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032040 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.032040 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035495 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035495 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15322.997556 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15322.997556 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34082.457330 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34082.457330 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18742.041277 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18742.041277 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18273.341523 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18273.341523 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26157.876756 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26157.876756 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 196286 # number of writebacks +system.cpu1.dcache.writebacks::total 196286 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16292 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 16292 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52982 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 52982 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12069 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12069 # 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number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23795 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23795 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 235986 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 235986 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 266082 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 266082 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14424 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14424 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11758 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11758 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26182 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26182 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2041290000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2041290000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2380409500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2380409500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 535271500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 535271500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82814000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82814000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 560137500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 560137500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 379500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 379500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4421699500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4421699500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4956971000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4956971000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2479783500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2479783500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2479783500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2479783500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013093 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013093 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013511 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013511 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369939 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369939 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050355 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050355 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249612 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249612 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013254 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.013254 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014876 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.014876 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14231.959841 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14231.959841 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25718.586585 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25718.586585 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17785.469830 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17785.469830 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16931.915764 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16931.915764 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23540.134482 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23540.134482 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22795.118584 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22795.118584 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22361.702936 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22361.702936 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131001.345442 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 131001.345442 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 73706.850871 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 73706.850871 # average overall mshr uncacheable latency -system.cpu1.icache.tags.replacements 856657 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.135889 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6021932 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 857169 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 7.025373 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 73312939000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.135889 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974875 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974875 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18737.126355 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18737.126355 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18629.486399 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18629.486399 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171920.653078 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171920.653078 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94713.295394 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 94713.295394 # average overall mshr uncacheable latency +system.cpu1.icache.tags.replacements 946364 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.210861 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 38654025 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 946876 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.822690 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 72815756000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.210861 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975021 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975021 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 50 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 14615371 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 14615371 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 6021932 # 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average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8791.747811 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8791.747811 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8791.747811 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 856657 # number of writebacks -system.cpu1.icache.writebacks::total 856657 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 857169 # 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number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 946876 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7161455000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7161455000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7161455000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7161455000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7161455000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7161455000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15471500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15471500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15471500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 15471500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.124605 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.124605 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.124605 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.124605 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.124605 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.124605 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8354.776013 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8354.776013 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8354.776013 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 138138.392857 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 138138.392857 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.num_hwpf_issued 119555 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 119603 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 42 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7851257000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7851257000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7851257000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7851257000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7851257000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7851257000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10474500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10474500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10474500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10474500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023910 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023910 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023910 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023910 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023910 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023910 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8291.747811 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8291.747811 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8291.747811 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 93522.321429 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 93522.321429 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.num_hwpf_issued 199879 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 199934 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 48 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 49365 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 38167 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15174.819793 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1843147 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 53515 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 34.441689 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 58626 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 53638 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15286.424872 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 2058198 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 68366 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 30.105579 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14738.835731 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 34.198599 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.090889 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 401.694574 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.899587 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002087 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.024517 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.926197 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 877 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14388 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 49 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 826 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 60 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 344 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2130 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11914 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.053528 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.878174 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 34225299 # 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number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 241 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 904 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29265 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29265 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23415 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23415 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32287 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 32287 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 12866 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 12866 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 66621 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 66621 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 663 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 241 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 12866 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 98908 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 112678 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 663 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 241 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 12866 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 98908 # number of overall misses -system.cpu1.l2cache.overall_misses::total 112678 # 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number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 14913000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4829500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 739774500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3309806996 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 4069323996 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 24985 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2983 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 27968 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 94449 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 94449 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 899051 # 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number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 857169 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 149096 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 149096 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 24985 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2983 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 857169 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 199456 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1084593 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 24985 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2983 # 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mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.014999 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014999 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.446571 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.446571 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026536 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.080791 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.014999 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.494490 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103624 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026536 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.080791 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.014999 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.494490 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.548003 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.548003 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.021165 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.021165 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.402142 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402142 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020262 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.068351 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.021165 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.439994 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103862 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020262 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.068351 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.021165 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.439994 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.122054 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15839.048673 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48141.089849 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48141.089849 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20158.858671 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20158.858671 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18611.232116 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18611.232116 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 500499.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 500499.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46505.975598 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46505.975598 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 51500.038889 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18067.826079 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18067.826079 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27308.083789 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29983.303639 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27308.083789 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48141.089849 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32725.097946 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122984.695594 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123244.408428 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 69196.347464 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 70461.267606 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 2128285 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1071677 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18282 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 177050 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 175620 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1430 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 34150 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1077374 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2311 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2311 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 124900 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 917333 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 97527 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 24473 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 71017 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41707 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 84949 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 57470 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 55019 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 857169 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 232907 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 41 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2571219 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 743876 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6996 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 52037 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3374128 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 109692032 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25376564 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11932 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 99940 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 135180468 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 380471 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1449236 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.140738 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.350577 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.125170 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16289.319249 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38663.269819 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38663.269819 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16840.104566 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16840.104566 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15989.010296 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15989.010296 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33124.908799 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33124.908799 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33723.067711 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33723.067711 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17377.391964 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17377.391964 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33723.067711 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22467.178825 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24203.219649 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33723.067711 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22467.178825 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38663.269819 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26664.802502 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85522.321429 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163916.909318 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163312.878371 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85522.321429 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90303.930181 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90283.562790 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 2394243 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1206431 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20164 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 192169 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 190372 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1797 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 53056 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1216172 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11758 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11758 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 154274 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 1024857 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 118852 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 31456 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 74303 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42261 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86315 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 14 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 69975 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 67112 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 946876 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 270105 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 65 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2840340 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 913098 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8024 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 64559 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3826021 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121174528 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30799564 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13460 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 122792 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 152110344 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 428107 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1655199 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.135380 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.345288 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1246703 86.02% 86.02% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 201103 13.88% 99.90% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1430 0.10% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1432915 86.57% 86.57% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 220487 13.32% 99.89% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1797 0.11% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1449236 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2091716493 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1655199 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2373087991 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 78610365 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79906669 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1286047248 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1420645672 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 331216893 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 410383006 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4013000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4659998 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 27068966 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 33872477 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31009 # Transaction distribution -system.iobus.trans_dist::ReadResp 31009 # Transaction distribution -system.iobus.trans_dist::WriteReq 59425 # Transaction distribution -system.iobus.trans_dist::WriteResp 59425 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31003 # Transaction distribution +system.iobus.trans_dist::ReadResp 31003 # Transaction distribution +system.iobus.trans_dist::WriteReq 59422 # Transaction distribution +system.iobus.trans_dist::WriteResp 59422 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -2211,11 +2219,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -2234,63 +2242,63 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48277500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48463001 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 326500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 29000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 88000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 84000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 577000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 574000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 19000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6148000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6138000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33110001 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33143500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187086234 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187679851 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36433 # number of replacements -system.iocache.tags.tagsinuse 14.469289 # Cycle average of tags in use +system.iocache.tags.replacements 36449 # number of replacements +system.iocache.tags.tagsinuse 14.476064 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 272370801000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.469289 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.904331 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.904331 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 271175186000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.476064 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904754 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904754 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2304,14 +2312,14 @@ system.iocache.demand_misses::realview.ide 36467 # system.iocache.demand_misses::total 36467 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36467 # number of overall misses system.iocache.overall_misses::total 36467 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31660877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31660877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4578259357 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4578259357 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4609920234 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4609920234 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4609920234 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4609920234 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 31712877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31712877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4301380974 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4301380974 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4333093851 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4333093851 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4333093851 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4333093851 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2328,22 +2336,22 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 130291.674897 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 130291.674897 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126387.460165 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126387.460165 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 126413.476129 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126413.476129 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 126413.476129 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126413.476129 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 130505.666667 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 130505.666667 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118743.953567 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118743.953567 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118822.328434 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118822.328434 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118822.328434 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118822.328434 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 152 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 16.888889 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.writebacks::writebacks 36206 # number of writebacks +system.iocache.writebacks::total 36206 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses @@ -2352,14 +2360,14 @@ system.iocache.demand_mshr_misses::realview.ide 36467 system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19510877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19510877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2765398414 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2765398414 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2784909291 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2784909291 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2784909291 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2784909291 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19562877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19562877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2487893822 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2487893822 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2507456699 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2507456699 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2507456699 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2507456699 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2368,565 +2376,569 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80291.674897 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 80291.674897 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76341.608160 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76341.608160 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76367.929662 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76367.929662 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76367.929662 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76367.929662 # average overall mshr miss latency -system.l2c.tags.replacements 132278 # number of replacements -system.l2c.tags.tagsinuse 63284.055151 # Cycle average of tags in use -system.l2c.tags.total_refs 475189 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 196356 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.420038 # Average number of references to valid blocks. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80505.666667 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 80505.666667 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68680.814432 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68680.814432 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68759.610031 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68759.610031 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency +system.l2c.tags.replacements 131721 # number of replacements +system.l2c.tags.tagsinuse 63119.316885 # Cycle average of tags in use +system.l2c.tags.total_refs 480965 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 195649 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.458305 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13432.084830 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 86.256901 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.025522 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 9264.781047 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2924.876995 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33297.808041 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.154929 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1918.631510 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 571.851499 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1782.583876 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.204957 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001316 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.141369 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.044630 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.508084 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000079 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.029276 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008726 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027200 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.965638 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 29131 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 62 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 34885 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 127 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5182 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 23822 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 62 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 413 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3378 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 31070 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.444504 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000946 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.532303 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6384287 # Number of tag accesses -system.l2c.tags.data_accesses 6384287 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 266285 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 266285 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 34059 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2216 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 36275 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2214 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 916 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3130 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4440 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1284 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5724 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 468 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 93 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 47246 # 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average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 59101.307139 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 94714.260374 # average overall mshr uncacheable latency -system.membus.trans_dist::ReadReq 39041 # Transaction distribution -system.membus.trans_dist::ReadResp 216336 # Transaction distribution -system.membus.trans_dist::WriteReq 31035 # Transaction distribution -system.membus.trans_dist::WriteResp 31035 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138525 # Transaction distribution -system.membus.trans_dist::CleanEvict 18214 # Transaction distribution -system.membus.trans_dist::UpgradeReq 73002 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40704 # Transaction distribution -system.membus.trans_dist::UpgradeResp 16 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # 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mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.200686 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.014286 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.326431 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.161404 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.728637 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.087248 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.164463 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.153794 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.559699 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.495784 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.200686 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.014286 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.326431 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.276692 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.728637 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.087248 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.164463 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.463027 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.559699 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.513955 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.200686 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.014286 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.326431 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.276692 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.728637 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.087248 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.164463 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.463027 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.559699 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.513955 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23958.421959 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23070.102751 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23750.504267 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25792.503347 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24699.277978 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25082.317073 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89437.214305 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73128.741306 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 82502.962494 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76089.743590 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71235.812444 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78696.563606 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90675.441472 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 88884.615385 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72902.761226 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82897.365532 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117781.479799 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88189.814683 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76089.743590 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71235.812444 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84452.805313 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90675.441472 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 88884.615385 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72902.761226 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74895.335186 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117781.479799 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 87621.682669 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76089.743590 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71235.812444 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84452.805313 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90675.441472 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 88884.615385 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72902.761226 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74895.335186 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117781.479799 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 87621.682669 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63626.703392 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 198323.110571 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64517.857143 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145946.883087 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166295.938507 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63626.703392 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102406.715856 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64517.857143 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80396.501050 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92143.139439 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 526346 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 301567 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 567 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 38557 # Transaction distribution +system.membus.trans_dist::ReadResp 213679 # Transaction distribution +system.membus.trans_dist::WriteReq 31029 # Transaction distribution +system.membus.trans_dist::WriteResp 31029 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138659 # Transaction distribution +system.membus.trans_dist::CleanEvict 18543 # Transaction distribution +system.membus.trans_dist::UpgradeReq 76988 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41072 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 39665 # Transaction distribution +system.membus.trans_dist::ReadExResp 19299 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 175122 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14218 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664863 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 787057 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72915 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72915 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 859972 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664223 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 786371 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 859302 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28436 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19371036 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19563630 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21880750 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 120342 # Total snoops (count) -system.membus.snoop_fanout::samples 593889 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28380 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19209376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19401896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21720040 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123861 # Total snoops (count) +system.membus.snoop_fanout::samples 438659 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011132 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.104918 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 593889 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 433776 98.89% 98.89% # Request fanout histogram +system.membus.snoop_fanout::1 4883 1.11% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 593889 # Request fanout histogram -system.membus.reqLayer0.occupancy 88806999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 438659 # Request fanout histogram +system.membus.reqLayer0.occupancy 89013499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12293000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12314999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1011120672 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1002605728 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1148583006 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1133893717 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1341627 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1318131 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2969,52 +2981,52 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 1040507 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 561217 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 153026 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 21153 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 20199 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 954 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 39044 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 500503 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31035 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 404834 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 139205 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 109172 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43834 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 153006 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 22 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50921 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50921 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 461474 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1330590 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 273408 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1603998 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36819910 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4347048 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 41166958 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 447482 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 940492 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.338468 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.475327 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 1068358 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 578478 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 169754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 19773 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 18732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1041 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 38560 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 513452 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31029 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31029 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 371703 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 144260 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 113415 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 44348 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 157763 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 14 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51662 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51662 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 474894 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4314 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1271960 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 368625 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1640585 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36024040 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5855360 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 41879400 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 387762 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 889983 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.383411 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.488617 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 623120 66.25% 66.25% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 316418 33.64% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 954 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 549795 61.78% 61.78% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 339147 38.11% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1041 0.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 940492 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 900307645 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 889983 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 926156147 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 342123 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 342619 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 690598933 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 669727799 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 213088139 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 257138606 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |