diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | 4386 |
1 files changed, 2216 insertions, 2170 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 57022429e..c733baa00 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,160 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.846001 # Number of seconds simulated -sim_ticks 2846001096000 # Number of ticks simulated -final_tick 2846001096000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.846097 # Number of seconds simulated +sim_ticks 2846097440000 # Number of ticks simulated +final_tick 2846097440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163513 # Simulator instruction rate (inst/s) -host_op_rate 197998 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3697981305 # Simulator tick rate (ticks/s) -host_mem_usage 648920 # Number of bytes of host memory used -host_seconds 769.61 # Real time elapsed on the host -sim_insts 125841424 # Number of instructions simulated -sim_ops 152380857 # Number of ops (including micro ops) simulated +host_inst_rate 101530 # Simulator instruction rate (inst/s) +host_op_rate 122947 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2278332577 # Simulator tick rate (ticks/s) +host_mem_usage 584920 # Number of bytes of host memory used +host_seconds 1249.20 # Real time elapsed on the host +sim_insts 126830911 # Number of instructions simulated +sim_ops 153585651 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 9664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1676864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1253436 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8602112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 9344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1671232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1335292 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8458880 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 217536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 601248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 396864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 217280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 606496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 432576 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12760092 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1676864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 217536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1894400 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8825856 # Number of bytes written to this memory +system.physmem.bytes_read::total 12733532 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1671232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 217280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1888512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8840256 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8843600 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 151 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26201 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20110 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134408 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8858000 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 146 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26113 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21389 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 132170 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3399 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9418 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6201 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3395 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9500 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6759 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 199925 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 137904 # Number of write requests responded to by this memory +system.physmem.num_reads::total 199510 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138129 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142340 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 589200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 440420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3022526 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 142565 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3283 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 587201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 469166 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2972098 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 76436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 211261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 139446 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 76343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 213097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 151989 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4483516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 589200 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 76436 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 665636 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3101143 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4474032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 587201 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 76343 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 663544 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3106097 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6220 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3107378 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3101143 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 589200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 446641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3022526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3112332 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3106097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3283 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 587201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 475386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2972098 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 76436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 211275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 139446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 76343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 213111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 151989 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7590894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 199925 # Number of read requests accepted -system.physmem.writeReqs 178564 # Number of write requests accepted -system.physmem.readBursts 199925 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 178564 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12787648 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue -system.physmem.bytesWritten 9914112 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12760092 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11161936 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23627 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14395 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11804 # Per bank write bursts -system.physmem.perBankRdBursts::1 12403 # Per bank write bursts -system.physmem.perBankRdBursts::2 13173 # Per bank write bursts -system.physmem.perBankRdBursts::3 12915 # Per bank write bursts -system.physmem.perBankRdBursts::4 15440 # Per bank write bursts -system.physmem.perBankRdBursts::5 12419 # Per bank write bursts -system.physmem.perBankRdBursts::6 12541 # Per bank write bursts -system.physmem.perBankRdBursts::7 12439 # Per bank write bursts -system.physmem.perBankRdBursts::8 12804 # Per bank write bursts -system.physmem.perBankRdBursts::9 13107 # Per bank write bursts -system.physmem.perBankRdBursts::10 11847 # Per bank write bursts -system.physmem.perBankRdBursts::11 11130 # Per bank write bursts -system.physmem.perBankRdBursts::12 12155 # Per bank write bursts -system.physmem.perBankRdBursts::13 12699 # Per bank write bursts -system.physmem.perBankRdBursts::14 11526 # Per bank write bursts -system.physmem.perBankRdBursts::15 11405 # Per bank write bursts -system.physmem.perBankWrBursts::0 9464 # Per bank write bursts -system.physmem.perBankWrBursts::1 9978 # Per bank write bursts -system.physmem.perBankWrBursts::2 10476 # Per bank write bursts -system.physmem.perBankWrBursts::3 10111 # Per bank write bursts -system.physmem.perBankWrBursts::4 9384 # Per bank write bursts -system.physmem.perBankWrBursts::5 9602 # Per bank write bursts -system.physmem.perBankWrBursts::6 9874 # Per bank write bursts -system.physmem.perBankWrBursts::7 9552 # Per bank write bursts -system.physmem.perBankWrBursts::8 9896 # Per bank write bursts -system.physmem.perBankWrBursts::9 10357 # Per bank write bursts -system.physmem.perBankWrBursts::10 9473 # Per bank write bursts -system.physmem.perBankWrBursts::11 9143 # Per bank write bursts -system.physmem.perBankWrBursts::12 9886 # Per bank write bursts -system.physmem.perBankWrBursts::13 9717 # Per bank write bursts -system.physmem.perBankWrBursts::14 9232 # Per bank write bursts -system.physmem.perBankWrBursts::15 8763 # Per bank write bursts +system.physmem.bw_total::total 7586364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 199510 # Number of read requests accepted +system.physmem.writeReqs 178789 # Number of write requests accepted +system.physmem.readBursts 199510 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 178789 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12761024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue +system.physmem.bytesWritten 9911424 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12733532 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11176336 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23895 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14191 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12377 # Per bank write bursts +system.physmem.perBankRdBursts::1 12507 # Per bank write bursts +system.physmem.perBankRdBursts::2 12921 # Per bank write bursts +system.physmem.perBankRdBursts::3 12944 # Per bank write bursts +system.physmem.perBankRdBursts::4 15059 # Per bank write bursts +system.physmem.perBankRdBursts::5 12345 # Per bank write bursts +system.physmem.perBankRdBursts::6 13163 # Per bank write bursts +system.physmem.perBankRdBursts::7 13279 # Per bank write bursts +system.physmem.perBankRdBursts::8 12255 # Per bank write bursts +system.physmem.perBankRdBursts::9 12304 # Per bank write bursts +system.physmem.perBankRdBursts::10 12058 # Per bank write bursts +system.physmem.perBankRdBursts::11 11233 # Per bank write bursts +system.physmem.perBankRdBursts::12 11543 # Per bank write bursts +system.physmem.perBankRdBursts::13 12301 # Per bank write bursts +system.physmem.perBankRdBursts::14 11677 # Per bank write bursts +system.physmem.perBankRdBursts::15 11425 # Per bank write bursts +system.physmem.perBankWrBursts::0 9896 # Per bank write bursts +system.physmem.perBankWrBursts::1 10159 # Per bank write bursts +system.physmem.perBankWrBursts::2 10174 # Per bank write bursts +system.physmem.perBankWrBursts::3 9995 # Per bank write bursts +system.physmem.perBankWrBursts::4 9156 # Per bank write bursts +system.physmem.perBankWrBursts::5 9568 # Per bank write bursts +system.physmem.perBankWrBursts::6 10283 # Per bank write bursts +system.physmem.perBankWrBursts::7 10373 # Per bank write bursts +system.physmem.perBankWrBursts::8 9590 # Per bank write bursts +system.physmem.perBankWrBursts::9 9571 # Per bank write bursts +system.physmem.perBankWrBursts::10 9719 # Per bank write bursts +system.physmem.perBankWrBursts::11 9542 # Per bank write bursts +system.physmem.perBankWrBursts::12 9254 # Per bank write bursts +system.physmem.perBankWrBursts::13 9350 # Per bank write bursts +system.physmem.perBankWrBursts::14 9412 # Per bank write bursts +system.physmem.perBankWrBursts::15 8824 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 62 # Number of times write queue was full causing retry -system.physmem.totGap 2846000520000 # Total gap between requests +system.physmem.numWrRetry 38 # Number of times write queue was full causing retry +system.physmem.totGap 2846096933500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 559 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 199338 # Read request sizes (log2) +system.physmem.readPktSize::6 198923 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 174128 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 99213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 47252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 818 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 174353 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 98295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47940 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7837 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6409 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5336 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 765 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -184,162 +184,160 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1868 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 2527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 117 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90945 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 249.620056 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.134877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 309.994619 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47499 52.23% 52.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17879 19.66% 71.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6335 6.97% 78.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3699 4.07% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2819 3.10% 86.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1518 1.67% 87.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 969 1.07% 88.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1044 1.15% 89.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9183 10.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90945 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6522 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.635388 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 556.912572 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6520 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::41 1779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 90716 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 249.927069 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.222601 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 310.362875 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47359 52.21% 52.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17889 19.72% 71.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6289 6.93% 78.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3581 3.95% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2839 3.13% 85.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1568 1.73% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 985 1.09% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1019 1.12% 89.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9187 10.13% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90716 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6524 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.562538 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 556.578248 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6523 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6522 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6522 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.751610 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.656400 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 41.548658 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 6178 94.73% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 86 1.32% 96.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 19 0.29% 96.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 12 0.18% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 33 0.51% 97.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 33 0.51% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 29 0.44% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 13 0.20% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 13 0.20% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 4 0.06% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 22 0.34% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 18 0.28% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 8 0.12% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 6 0.09% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 3 0.05% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 3 0.05% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 5 0.08% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 5 0.08% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 7 0.11% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 9 0.14% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 2 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 2 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::896-911 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6522 # Writes before turning the bus around for reads -system.physmem.totQLat 5658505376 # Total ticks spent queuing -system.physmem.totMemAccLat 9404886626 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 999035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28319.86 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6524 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6524 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.737891 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.670801 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 40.283485 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 6175 94.65% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 90 1.38% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 23 0.35% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 12 0.18% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 26 0.40% 96.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 32 0.49% 97.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 26 0.40% 97.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 10 0.15% 98.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 20 0.31% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 5 0.08% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 20 0.31% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 23 0.35% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 7 0.11% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 7 0.11% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.02% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.05% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.03% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 5 0.08% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.06% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 4 0.06% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 14 0.21% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.03% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.05% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6524 # Writes before turning the bus around for reads +system.physmem.totQLat 5679096455 # Total ticks spent queuing +system.physmem.totMemAccLat 9417677705 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 996955000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28482.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47069.86 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 47232.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.48 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.48 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.92 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.47 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.33 # Average write queue length when enqueuing -system.physmem.readRowHits 166469 # Number of row buffer hits during reads -system.physmem.writeRowHits 97300 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.31 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.80 # Row buffer hit rate for writes -system.physmem.avgGap 7519374.46 # Average gap between requests -system.physmem.pageHitRate 74.35 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 351842400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 191977500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 804437400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 508297680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185886816960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83070715860 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634730471750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1905544559550 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.552036 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2719396100671 # Time in different power states -system.physmem_0.memoryStateTime::REF 95034160000 # Time in different power states +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.18 # Average write queue length when enqueuing +system.physmem.readRowHits 166067 # Number of row buffer hits during reads +system.physmem.writeRowHits 97473 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.29 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.93 # Row buffer hit rate for writes +system.physmem.avgGap 7523405.91 # Average gap between requests +system.physmem.pageHitRate 74.39 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 359115120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 195945750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 815841000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 515833920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185892919680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83249453610 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634629745250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1905658854330 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.570214 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2719227401175 # Time in different power states +system.physmem_0.memoryStateTime::REF 95037280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31570722329 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31827968825 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 335701800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 183170625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 754049400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 495506160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185886816960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82302536835 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635404313000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1905362094780 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.487923 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2720522847414 # Time in different power states -system.physmem_1.memoryStateTime::REF 95034160000 # Time in different power states +system.physmem_1.actEnergy 326697840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 178257750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 739401000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 487697760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185892919680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82096607520 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635641013750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1905362595300 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.466120 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2720918284391 # Time in different power states +system.physmem_1.memoryStateTime::REF 95037280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30442207586 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30141762609 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory @@ -365,15 +363,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 20635824 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13602989 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1045571 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 13187813 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 9323038 # Number of BTB hits +system.cpu0.branchPred.lookups 20630955 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13593557 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1040069 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13124579 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 9315197 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 70.694345 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3366354 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 208367 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 70.975206 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3367508 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 204886 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -404,59 +402,59 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 68383 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 68383 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 45560 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22823 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 68383 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 68383 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 68383 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6747 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 9430.747147 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 8234.841596 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6251.099816 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6572 97.41% 97.41% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 158 2.34% 99.75% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.10% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::114688-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6747 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 69457 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 69457 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46535 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22922 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 69457 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 69457 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 69457 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6849 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9469.922616 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 8283.824538 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6457.338241 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6642 96.98% 96.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 191 2.79% 99.77% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.10% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6849 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 328505000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 328505000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 328505000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5180 76.77% 76.77% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1567 23.23% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6747 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 68383 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5259 76.78% 76.78% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1590 23.22% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6849 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69457 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 68383 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6747 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69457 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6849 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6747 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 75130 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6849 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 76306 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17310932 # DTB read hits -system.cpu0.dtb.read_misses 62315 # DTB read misses -system.cpu0.dtb.write_hits 14537397 # DTB write hits -system.cpu0.dtb.write_misses 6068 # DTB write misses +system.cpu0.dtb.read_hits 17312533 # DTB read hits +system.cpu0.dtb.read_misses 63301 # DTB read misses +system.cpu0.dtb.write_hits 14536158 # DTB write hits +system.cpu0.dtb.write_misses 6156 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1366 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1946 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3522 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1254 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1942 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 545 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17373247 # DTB read accesses -system.cpu0.dtb.write_accesses 14543465 # DTB write accesses +system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17375834 # DTB read accesses +system.cpu0.dtb.write_accesses 14542314 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31848329 # DTB hits -system.cpu0.dtb.misses 68383 # DTB misses -system.cpu0.dtb.accesses 31916712 # DTB accesses +system.cpu0.dtb.hits 31848691 # DTB hits +system.cpu0.dtb.misses 69457 # DTB misses +system.cpu0.dtb.accesses 31918148 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -486,38 +484,38 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3838 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3838 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3532 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3838 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3838 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3838 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2413 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 9817.861169 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 8667.312532 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5173.169908 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 854 35.39% 35.39% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1509 62.54% 97.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 3 0.12% 98.05% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 46 1.91% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 3833 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3833 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3526 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3833 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3833 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3833 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2419 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 9485.117817 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 8378.584027 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 4911.792845 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 918 37.95% 37.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1466 60.60% 98.55% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 5 0.21% 98.76% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 29 1.20% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2413 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2419 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 328041000 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 328041000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 328041000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2114 87.61% 87.61% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 299 12.39% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2413 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2119 87.60% 87.60% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 300 12.40% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2419 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3838 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3838 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3833 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3833 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2413 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2413 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6251 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 38726658 # ITB inst hits -system.cpu0.itb.inst_misses 3838 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2419 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2419 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6252 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 38694088 # ITB inst hits +system.cpu0.itb.inst_misses 3833 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -526,123 +524,131 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2219 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2222 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7377 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7309 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 38730496 # ITB inst accesses -system.cpu0.itb.hits 38726658 # DTB hits -system.cpu0.itb.misses 3838 # DTB misses -system.cpu0.itb.accesses 38730496 # DTB accesses -system.cpu0.numCycles 164623207 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 38697921 # ITB inst accesses +system.cpu0.itb.hits 38694088 # DTB hits +system.cpu0.itb.misses 3833 # DTB misses +system.cpu0.itb.accesses 38697921 # DTB accesses +system.cpu0.numCycles 164664294 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 79533802 # Number of instructions committed -system.cpu0.committedOps 95718607 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 5045973 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1856 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5527394503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.069852 # CPI: cycles per instruction -system.cpu0.ipc 0.483126 # IPC: instructions per cycle +system.cpu0.committedInsts 79545676 # Number of instructions committed +system.cpu0.committedOps 95726645 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 5037895 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1845 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5527555817 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.070060 # CPI: cycles per instruction +system.cpu0.ipc 0.483078 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1858 # number of quiesce instructions executed -system.cpu0.tickCycles 128554371 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 36068836 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 714653 # number of replacements -system.cpu0.dcache.tags.tagsinuse 500.517650 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 30439123 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 715165 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 42.562378 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1847 # number of quiesce instructions executed +system.cpu0.tickCycles 127989646 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 36674648 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 713904 # number of replacements +system.cpu0.dcache.tags.tagsinuse 500.482804 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 30358451 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 714416 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 42.494080 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 348749500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.517650 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977574 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.977574 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.482804 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977505 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.977505 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63710880 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63710880 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 16167111 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 16167111 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 13468154 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 13468154 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 380067 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 380067 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361342 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361342 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 29635265 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 29635265 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 29635265 # number of overall hits -system.cpu0.dcache.overall_hits::total 29635265 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 537159 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 537159 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 529716 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 529716 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6447 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6447 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20264 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20264 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1066875 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1066875 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1066875 # number of overall misses -system.cpu0.dcache.overall_misses::total 1066875 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6690812322 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6690812322 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8678584493 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8678584493 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104630740 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 104630740 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 454305285 # 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miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.032157 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.037843 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.037843 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016680 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016680 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053102 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053102 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034749 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.034749 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034749 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.034749 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12455.925195 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12455.925195 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16383.466788 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 16383.466788 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16229.368699 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16229.368699 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22419.329106 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22419.329106 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63703980 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63703980 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15781686 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15781686 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 13418199 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 13418199 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 321521 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 321521 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365596 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365596 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361488 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361488 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 29199885 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 29199885 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 29521406 # number of overall hits +system.cpu0.dcache.overall_hits::total 29521406 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 463568 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 463568 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 577310 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 577310 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 136519 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 136519 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21073 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21073 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20283 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20283 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1040878 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1040878 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1177397 # number of overall misses +system.cpu0.dcache.overall_misses::total 1177397 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6134841542 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6134841542 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9140419725 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 9140419725 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 317623227 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 317623227 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453858268 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 453858268 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 454500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 454500 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386669 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381771 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381771 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30240763 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30240763 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30698803 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30698803 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028536 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028536 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041250 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.041250 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298050 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298050 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054499 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054499 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053129 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053129 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034420 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.034420 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038353 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.038353 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13233.962530 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13233.962530 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15832.775675 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15832.775675 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15072.520619 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15072.520619 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22376.288912 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22376.288912 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14405.995843 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14405.995843 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14405.995843 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14405.995843 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14675.361826 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14675.361826 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12973.755893 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12973.755893 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -651,74 +657,84 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 516062 # number of writebacks -system.cpu0.dcache.writebacks::total 516062 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 42087 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 42087 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 229086 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 229086 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 271173 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 271173 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 271173 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 271173 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 495072 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 495072 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 300630 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 300630 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6447 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6447 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20264 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20264 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 795702 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 795702 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 795702 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 795702 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5420342985 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5420342985 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4742244244 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4742244244 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94933760 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94933760 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 423201715 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 423201715 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 147000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 147000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10162587229 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10162587229 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10162587229 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10162587229 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4276747000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4276747000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3261903001 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3261903001 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7538650001 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7538650001 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029637 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029637 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.021477 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021477 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016680 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016680 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053102 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053102 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025917 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025917 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025917 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025917 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10948.595326 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10948.595326 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15774.354669 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15774.354669 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14725.261362 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14725.261362 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20884.411518 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20884.411518 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 513522 # number of writebacks +system.cpu0.dcache.writebacks::total 513522 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 72271 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 72271 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 253439 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 253439 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14656 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14656 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 325710 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 325710 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 325710 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 325710 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 391297 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 391297 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323871 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 323871 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103394 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 103394 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6417 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6417 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20283 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20283 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 715168 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 715168 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 818562 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 818562 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4428376943 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4428376943 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4906976685 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4906976685 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1616801678 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1616801678 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 95832009 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95832009 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 422721232 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 422721232 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 436500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 436500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9335353628 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9335353628 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10952155306 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10952155306 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4276481750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4276481750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3261665000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3261665000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7538146750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7538146750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024087 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024087 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023141 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023141 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225731 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225731 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016596 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016596 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053129 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053129 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023649 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023649 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026664 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026664 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11317.175810 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11317.175810 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15151.022120 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15151.022120 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15637.287251 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15637.287251 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14934.082749 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14934.082749 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20841.159197 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20841.159197 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12771.850805 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12771.850805 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12771.850805 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12771.850805 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13053.371555 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13053.371555 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13379.750472 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13379.750472 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -726,58 +742,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # 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Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6455779250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.783924 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999578 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 230 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # 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number of overall misses -system.cpu0.icache.overall_misses::total 1970661 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18596838762 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18596838762 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18596838762 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18596838762 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18596838762 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18596838762 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 38718926 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 38718926 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 38718926 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 38718926 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 38718926 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 38718926 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050897 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050897 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050897 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050897 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050897 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050897 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9436.853300 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9436.853300 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9436.853300 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9436.853300 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9436.853300 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9436.853300 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 79342579 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 79342579 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 36716761 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36716761 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36716761 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36716761 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36716761 # number of overall hits +system.cpu0.icache.overall_hits::total 36716761 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1969686 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1969686 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1969686 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1969686 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1969686 # number of overall misses +system.cpu0.icache.overall_misses::total 1969686 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18594001543 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18594001543 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18594001543 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18594001543 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18594001543 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18594001543 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 38686447 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 38686447 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 38686447 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 38686447 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 38686447 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 38686447 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050914 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050914 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050914 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050914 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050914 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050914 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9440.084127 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9440.084127 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9440.084127 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9440.084127 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9440.084127 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9440.084127 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -786,358 +802,356 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1970661 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1970661 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1970661 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1970661 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1970661 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1970661 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16616813240 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 16616813240 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16616813240 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 16616813240 # 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mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050897 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.050897 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8432.101330 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8432.101330 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8432.101330 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8432.101330 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8432.101330 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8432.101330 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1969686 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1969686 # 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average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29850.706714 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16070.247934 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39588.437872 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29885.177687 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53498.080753 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45630.907306 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163120 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23400.009493 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30053.081217 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58459.199979 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58459.199979 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20172.381963 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20172.381963 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14669.747940 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14669.747940 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 345999 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 345999 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38178.292804 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38178.292804 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27791.679436 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31655.164692 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27791.679436 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58459.199979 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45977.272768 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1147,65 +1161,65 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 2704309 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2644372 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19133 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19133 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 516061 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 357573 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36265 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 65952 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43054 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 89535 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 298181 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284517 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3948091 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2342949 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11777 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 172611 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6475428 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126338880 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86633336 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17628 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 325620 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 213315464 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 705686 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3997625 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 3.147566 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.354669 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 2703667 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2643606 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19130 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19130 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 513519 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 304285 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 88848 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42983 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113085 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 297594 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284124 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3946133 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2385460 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11633 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 174179 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6517405 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126276224 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86385120 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17096 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 327200 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 213005640 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 651207 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3963380 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.135029 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.341755 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 3407711 85.24% 85.24% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 589914 14.76% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 3428208 86.50% 86.50% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 535172 13.50% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3997625 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2250942493 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3963380 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2258643996 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 117029497 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 116241999 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2966538511 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2965047043 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1219549045 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1230256203 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7373994 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7364491 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 91216246 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 92392742 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 18670420 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6078179 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 807720 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 9612678 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 6998038 # Number of BTB hits +system.cpu1.branchPred.lookups 18842889 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6205402 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 629106 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 9920552 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 7177439 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 72.800088 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 8300224 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 592338 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.349190 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8245946 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 413041 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1235,59 +1249,60 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 26198 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 26198 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19047 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7151 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 26198 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 26198 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 26198 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2710 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 9322.699631 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 8294.308784 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5681.860876 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1066 39.34% 39.34% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1510 55.72% 95.06% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 65 2.40% 97.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 58 2.14% 99.59% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 6 0.22% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 3 0.11% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2710 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1205143764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1205143764 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1205143764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 2001 73.84% 73.84% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 709 26.16% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2710 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26198 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 26188 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 26188 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19132 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7056 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 26188 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 26188 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 26188 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2719 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9780.159618 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8826.212048 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5631.617808 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 919 33.80% 33.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1662 61.13% 94.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 68 2.50% 97.43% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 62 2.28% 99.71% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.11% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 2 0.07% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2719 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1631340764 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1631340764 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1631340764 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 2011 73.96% 73.96% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 708 26.04% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2719 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26188 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26198 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2710 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26188 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2719 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2710 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 28908 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2719 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 28907 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10899944 # DTB read hits -system.cpu1.dtb.read_misses 24664 # DTB read misses -system.cpu1.dtb.write_hits 6857896 # DTB write hits -system.cpu1.dtb.write_misses 1534 # DTB write misses +system.cpu1.dtb.read_hits 11112548 # DTB read hits +system.cpu1.dtb.read_misses 24192 # DTB read misses +system.cpu1.dtb.write_hits 6961122 # DTB write hits +system.cpu1.dtb.write_misses 1996 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2060 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 145 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 340 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2061 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 148 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 422 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 279 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10924608 # DTB read accesses -system.cpu1.dtb.write_accesses 6859430 # DTB write accesses +system.cpu1.dtb.perms_faults 278 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 11136740 # DTB read accesses +system.cpu1.dtb.write_accesses 6963118 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 17757840 # DTB hits -system.cpu1.dtb.misses 26198 # DTB misses -system.cpu1.dtb.accesses 17784038 # DTB accesses +system.cpu1.dtb.hits 18073670 # DTB hits +system.cpu1.dtb.misses 26188 # DTB misses +system.cpu1.dtb.accesses 18099858 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1317,41 +1332,41 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 2253 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2253 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 177 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2076 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2253 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2253 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2253 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 2252 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2252 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2071 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2252 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2252 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2252 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 1119 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 9627.345845 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8644.762201 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4978.900312 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 184 16.44% 16.44% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 161 14.39% 30.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 501 44.77% 75.60% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 236 21.09% 96.69% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 96.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 13 1.16% 97.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.88% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 9763.181412 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8935.720507 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4528.605471 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 139 12.42% 12.42% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 170 15.19% 27.61% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 525 46.92% 74.53% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 253 22.61% 97.14% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 2 0.18% 97.32% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 1.88% 99.20% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 7 0.63% 99.82% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 1119 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1204569264 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1204569264 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1204569264 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 955 85.34% 85.34% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 164 14.66% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walksPending::samples 1630766264 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1630766264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1630766264 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 951 84.99% 84.99% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 168 15.01% 100.00% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::total 1119 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2253 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2253 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2252 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2252 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1119 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1119 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3372 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 39818327 # ITB inst hits -system.cpu1.itb.inst_misses 2253 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin::total 3371 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 39781680 # ITB inst hits +system.cpu1.itb.inst_misses 2252 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1364,118 +1379,126 @@ system.cpu1.itb.flush_entries 1157 # Nu system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1840 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1899 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 39820580 # ITB inst accesses -system.cpu1.itb.hits 39818327 # DTB hits -system.cpu1.itb.misses 2253 # DTB misses -system.cpu1.itb.accesses 39820580 # DTB accesses -system.cpu1.numCycles 115094455 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 39783932 # ITB inst accesses +system.cpu1.itb.hits 39781680 # DTB hits +system.cpu1.itb.misses 2252 # DTB misses +system.cpu1.itb.accesses 39783932 # DTB accesses +system.cpu1.numCycles 114623988 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 46307622 # Number of instructions committed -system.cpu1.committedOps 56662250 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 4905736 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2805 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5576292649 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.485432 # CPI: cycles per instruction -system.cpu1.ipc 0.402345 # IPC: instructions per cycle +system.cpu1.committedInsts 47285235 # Number of instructions committed +system.cpu1.committedOps 57859006 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 5005620 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2776 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5576963738 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.424097 # CPI: cycles per instruction +system.cpu1.ipc 0.412525 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2806 # number of quiesce instructions executed -system.cpu1.tickCycles 98408596 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 16685859 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 195662 # number of replacements -system.cpu1.dcache.tags.tagsinuse 474.092793 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 17323078 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 195999 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 88.383502 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 90082708500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.092793 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.925962 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.925962 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 88 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.658203 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 35540406 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 35540406 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 10562839 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10562839 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6561699 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6561699 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 92378 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 92378 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71754 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71754 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 17124538 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 17124538 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 17124538 # number of overall hits -system.cpu1.dcache.overall_hits::total 17124538 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 188265 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 188265 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 144615 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 144615 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4906 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4906 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23743 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23743 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 332880 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 332880 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 332880 # number of overall misses -system.cpu1.dcache.overall_misses::total 332880 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2782453534 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2782453534 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3892497330 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3892497330 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 87637747 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 87637747 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 559501111 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 559501111 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 370500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 370500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6674950864 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6674950864 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6674950864 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6674950864 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 10751104 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 10751104 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6706314 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6706314 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97284 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 97284 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95497 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95497 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 17457418 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 17457418 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 17457418 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 17457418 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.017511 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.017511 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021564 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.021564 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050430 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.050430 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248626 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248626 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.019068 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.019068 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.019068 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.019068 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14779.452017 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14779.452017 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26916.276527 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 26916.276527 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17863.380962 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17863.380962 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23564.886956 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23564.886956 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2776 # number of quiesce instructions executed +system.cpu1.tickCycles 97884766 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 16739222 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 194739 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.948438 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 17633406 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 195100 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 90.381374 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 90504077500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.948438 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923727 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.923727 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 55 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.705078 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 36178407 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 36178407 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 10725883 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10725883 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6668052 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6668052 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49984 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49984 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80051 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 80051 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71499 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71499 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 17393935 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 17393935 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 17443919 # number of overall hits +system.cpu1.dcache.overall_hits::total 17443919 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 157968 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 157968 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 144726 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 144726 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30816 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30816 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16919 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16919 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23678 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23678 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 302694 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 302694 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 333510 # number of overall misses +system.cpu1.dcache.overall_misses::total 333510 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2315952429 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2315952429 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3861386324 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3861386324 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 316030492 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 316030492 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557062155 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 557062155 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 124000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 124000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6177338753 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6177338753 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6177338753 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6177338753 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 10883851 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 10883851 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6812778 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6812778 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80800 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 80800 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96970 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96970 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95177 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95177 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 17696629 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 17696629 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 17777429 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 17777429 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.014514 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.014514 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021243 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.021243 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381386 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381386 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174477 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174477 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248779 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248779 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.017105 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.017105 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018760 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.018760 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14660.896061 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14660.896061 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26680.667772 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26680.667772 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18679.029021 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18679.029021 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23526.571290 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23526.571290 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20052.123480 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20052.123480 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20052.123480 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20052.123480 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20407.866535 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20407.866535 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18522.199493 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18522.199493 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1484,74 +1507,84 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 120164 # number of writebacks -system.cpu1.dcache.writebacks::total 120164 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 15759 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 15759 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52033 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 52033 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 67792 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 67792 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 67792 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 67792 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172506 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 172506 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92582 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 92582 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4906 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4906 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23743 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23743 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 265088 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 265088 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 265088 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 265088 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2304438945 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2304438945 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2314812844 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2314812844 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 80267253 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 80267253 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 522512389 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 522512389 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 358500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 358500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4619251789 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4619251789 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4619251789 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4619251789 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2322402500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2322402500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1844154499 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1844154499 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4166556999 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4166556999 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016045 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.016045 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013805 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013805 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050430 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050430 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248626 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248626 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.015185 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.015185 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015185 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.015185 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13358.601701 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13358.601701 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25002.839040 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25002.839040 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16361.038117 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16361.038117 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22007.007918 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22007.007918 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 119475 # number of writebacks +system.cpu1.dcache.writebacks::total 119475 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16075 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 16075 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52265 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 52265 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12035 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12035 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 68340 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 68340 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 68340 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 68340 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 141893 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 141893 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92461 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 92461 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29935 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29935 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4884 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4884 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23678 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23678 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 234354 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 234354 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 264289 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 264289 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1871458583 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1871458583 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2300176813 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2300176813 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 487265761 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 487265761 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79878753 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 79878753 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 520207345 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 520207345 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 119500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 119500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4171635396 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4171635396 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4658901157 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4658901157 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2322015751 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2322015751 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1843986000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1843986000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4166001751 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4166001751 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013037 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013037 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013572 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013572 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.370483 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.370483 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050366 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050366 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248779 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248779 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013243 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.013243 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014867 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.014867 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13189.224155 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13189.224155 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24877.265150 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24877.265150 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16277.459863 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16277.459863 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16355.191032 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16355.191032 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21970.071163 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21970.071163 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17425.352294 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17425.352294 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17425.352294 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17425.352294 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17800.572621 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17800.572621 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17628.055488 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17628.055488 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1559,57 +1592,57 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 948962 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.398770 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 38866849 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 949474 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.935138 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 71724827500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.398770 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975388 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975388 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 947666 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.322678 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 38831450 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 948178 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.953756 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 72138919500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.322678 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975240 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975240 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 459 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 53 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 80582120 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 80582120 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 38866849 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 38866849 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 38866849 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 38866849 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 38866849 # number of overall hits -system.cpu1.icache.overall_hits::total 38866849 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 949474 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 949474 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 949474 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 949474 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 949474 # number of overall misses -system.cpu1.icache.overall_misses::total 949474 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8197479438 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8197479438 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8197479438 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8197479438 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8197479438 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8197479438 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 39816323 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 39816323 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 39816323 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 39816323 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 39816323 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 39816323 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023846 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023846 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023846 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023846 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023846 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023846 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8633.706071 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8633.706071 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8633.706071 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8633.706071 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8633.706071 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8633.706071 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 80507434 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 80507434 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 38831450 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 38831450 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 38831450 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 38831450 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 38831450 # number of overall hits +system.cpu1.icache.overall_hits::total 38831450 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 948178 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 948178 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 948178 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 948178 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 948178 # number of overall misses +system.cpu1.icache.overall_misses::total 948178 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8186316171 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8186316171 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8186316171 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8186316171 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8186316171 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8186316171 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 39779628 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 39779628 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 39779628 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 39779628 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 39779628 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 39779628 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023836 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.023836 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023836 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.023836 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023836 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.023836 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8633.733509 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8633.733509 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8633.733509 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8633.733509 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8633.733509 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8633.733509 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1618,344 +1651,354 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 949474 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 949474 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 949474 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 949474 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 949474 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 949474 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7246706562 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7246706562 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7246706562 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7246706562 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7246706562 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7246706562 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10208000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10208000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10208000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10208000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023846 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023846 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023846 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.023846 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023846 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023846 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7632.338076 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7632.338076 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7632.338076 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7632.338076 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7632.338076 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7632.338076 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 948178 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 948178 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 948178 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 948178 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 948178 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 948178 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7236829829 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7236829829 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7236829829 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7236829829 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7236829829 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7236829829 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10429000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10429000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10429000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10429000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023836 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023836 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023836 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023836 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023836 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023836 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7632.353660 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7632.353660 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7632.353660 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7632.353660 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7632.353660 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7632.353660 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 263000 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 263018 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 198185 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 198250 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 56 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 69926 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 55260 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15340.181807 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1180273 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 70026 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 16.854783 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 58438 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 54866 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15346.205956 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1177923 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 69767 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 16.883670 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 7920.573124 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 36.864575 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.107624 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4396.054830 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2144.688544 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 841.893110 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.483433 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002250 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.268314 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.130901 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051385 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.936290 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2047 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 49 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 12670 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 77 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 853 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1117 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5605 # 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number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 595509510 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2226971556 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2836308809 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 10825243 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3002500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 595509510 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2226971556 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1009576164 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3845884973 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9469000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2205184749 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2214653749 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1754353500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1754353500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9469000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3959538249 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3969007249 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022542 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.078037 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.022093 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.401845 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.080252 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.949225 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.949225 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.960241 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.960241 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.559621 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.559621 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022388 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.079186 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.021988 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.428848 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.102090 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022388 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.079186 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.021988 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.428848 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.947996 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.947996 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.958863 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.958863 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.546801 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.546801 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022542 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.078037 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.022093 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.439737 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.104183 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022542 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.078037 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.022093 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.439737 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.124466 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17238.010819 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13646.788991 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28575.933563 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15397.298227 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18475.608133 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35413.300077 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35413.300077 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15957.484300 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15957.484300 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15100.211457 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15100.211457 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32362.948722 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32362.948722 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17238.010819 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13646.788991 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28575.933563 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21170.759053 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22377.297493 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17238.010819 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13646.788991 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28575.933563 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21170.759053 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35413.300077 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24720.789733 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.123779 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15573.986058 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18476.484941 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42252.287771 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 42252.287771 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15940.014772 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15940.014772 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15081.828305 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15081.828305 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 97000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 97000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32781.531259 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32781.531259 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21167.321458 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22327.514398 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21167.321458 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42252.287771 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25481.924738 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1965,58 +2008,58 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1549513 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1217389 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11941 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11941 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 120163 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 34752 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36265 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 76638 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42182 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86369 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 85047 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 67036 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1899176 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 835933 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7082 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62248 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2804439 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60773632 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25876936 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11012 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 115596 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 86777176 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 610005 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1929839 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 3.274006 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.446012 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1546268 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1215347 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11936 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11936 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 119475 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 29668 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 76508 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42110 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86467 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 85086 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 67037 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1896584 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 833808 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7155 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62301 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2799848 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60690688 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25792980 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11328 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 116228 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 86611224 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 603822 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1920664 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.272089 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.445035 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 1401052 72.60% 72.60% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 528787 27.40% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 1398073 72.79% 72.79% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 522591 27.21% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1929839 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 840003478 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1920664 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 837814982 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80148998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80458500 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1425055438 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1423116171 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 412471555 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 410915491 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4329500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4323500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 33365476 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 33252737 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31015 # Transaction distribution -system.iobus.trans_dist::ReadResp 31015 # Transaction distribution +system.iobus.trans_dist::ReadReq 31003 # Transaction distribution +system.iobus.trans_dist::ReadResp 31003 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution system.iobus.trans_dist::WriteResp 23198 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution @@ -2042,9 +2085,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -2067,9 +2110,9 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) @@ -2110,52 +2153,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 199065929 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198973953 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36796533 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36786758 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.480362 # Cycle average of tags in use +system.iocache.tags.replacements 36449 # number of replacements +system.iocache.tags.tagsinuse 14.479940 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270133806000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.480362 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.905023 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.905023 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270378265000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.479940 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904996 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904996 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328311 # Number of tag accesses -system.iocache.tags.data_accesses 328311 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses -system.iocache.ReadReq_misses::total 255 # number of ReadReq misses +system.iocache.tags.tag_accesses 328203 # Number of tag accesses +system.iocache.tags.data_accesses 328203 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses +system.iocache.ReadReq_misses::total 243 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses -system.iocache.demand_misses::total 255 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 255 # number of overall misses -system.iocache.overall_misses::total 255 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32660377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32660377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6669320019 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6669320019 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32660377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32660377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32660377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32660377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses +system.iocache.demand_misses::total 243 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 243 # number of overall misses +system.iocache.overall_misses::total 243 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31380127 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31380127 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6638963068 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6638963068 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31380127 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31380127 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31380127 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31380127 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses @@ -2164,40 +2207,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128079.909804 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128079.909804 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 184113.295578 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 184113.295578 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128079.909804 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128079.909804 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128079.909804 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128079.909804 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 23275 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129136.325103 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129136.325103 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183275.261374 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183275.261374 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 129136.325103 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129136.325103 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 129136.325103 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129136.325103 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22458 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3594 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3415 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.476071 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.576281 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36206 # number of writebacks +system.iocache.writebacks::total 36206 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19371377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19371377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4785606085 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4785606085 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19371377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 19371377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 19371377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 19371377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18685627 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18685627 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4755299084 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4755299084 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18685627 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18685627 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18685627 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18685627 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2206,304 +2249,304 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75966.184314 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75966.184314 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 132111.475403 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 132111.475403 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75966.184314 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75966.184314 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75966.184314 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75966.184314 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76895.584362 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76895.584362 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131274.820119 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131274.820119 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76895.584362 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76895.584362 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76895.584362 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76895.584362 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 135784 # number of replacements -system.l2c.tags.tagsinuse 63989.836026 # Cycle average of tags in use -system.l2c.tags.total_refs 379813 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 200303 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.896192 # Average number of references to valid blocks. +system.l2c.tags.replacements 135638 # number of replacements +system.l2c.tags.tagsinuse 64035.864385 # Cycle average of tags in use +system.l2c.tags.total_refs 380564 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 200114 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.901736 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12166.183008 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 73.341692 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030170 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8672.913636 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2762.328324 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35676.457886 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.004073 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2139.434191 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 561.920463 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1923.222583 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.185641 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001119 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.132338 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042150 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.544380 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000214 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.032645 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008574 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.029346 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.976407 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31538 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 56 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32925 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 124 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5437 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 25977 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 12087.017372 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 77.160254 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.033685 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8509.496822 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2877.165248 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35676.414678 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 13.500349 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2186.391247 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 567.991773 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2040.692959 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.184433 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001177 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.129845 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043902 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.544379 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000206 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.033362 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008667 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.031139 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.977110 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 30037 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 48 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 34391 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 135 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4776 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 25126 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 55 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3182 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29429 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.481232 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.502396 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5287676 # Number of tag accesses -system.l2c.tags.data_accesses 5287676 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 420 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 71 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 47985 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 21581 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 76019 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 126 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 31 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 17578 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 7426 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7556 # number of ReadReq hits -system.l2c.ReadReq_hits::total 178793 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 232242 # number of Writeback hits -system.l2c.Writeback_hits::total 232242 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3124 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 764 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3888 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 164 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 156 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 320 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4039 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1693 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5732 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 420 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 71 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 47985 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 25620 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 76019 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 126 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 31 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 17578 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 9119 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 7556 # number of demand (read+write) hits -system.l2c.demand_hits::total 184525 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 420 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 71 # number of overall hits -system.l2c.overall_hits::cpu0.inst 47985 # number of overall hits -system.l2c.overall_hits::cpu0.data 25620 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 76019 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 126 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 31 # number of overall hits -system.l2c.overall_hits::cpu1.inst 17578 # number of overall hits -system.l2c.overall_hits::cpu1.data 9119 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 7556 # number of overall hits -system.l2c.overall_hits::total 184525 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 151 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 22827 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 8447 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 134637 # number of ReadReq misses +system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 3317 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 30762 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.458328 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.524765 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5287806 # Number of tag accesses +system.l2c.tags.data_accesses 5287806 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 444 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 48461 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 49558 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 47653 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 127 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 25 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 17654 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 9320 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 5533 # number of ReadReq hits +system.l2c.ReadReq_hits::total 178838 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 232835 # number of Writeback hits +system.l2c.Writeback_hits::total 232835 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 3130 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 650 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3780 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 173 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 165 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 338 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4192 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1733 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5925 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 444 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 48461 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 53750 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 47653 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 127 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 25 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 17654 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 11053 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 5533 # number of demand (read+write) hits +system.l2c.demand_hits::total 184763 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 444 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits +system.l2c.overall_hits::cpu0.inst 48461 # number of overall hits +system.l2c.overall_hits::cpu0.data 53750 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 47653 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 127 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 25 # number of overall hits +system.l2c.overall_hits::cpu1.inst 17654 # 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average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69691.543041 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 75064.022094 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78696.917808 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68037.082888 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77774.611639 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90758.632025 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 96976.190476 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71159.233546 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70237.067771 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119715.576446 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 86401.318914 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77008.278146 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68207.465922 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77572.664185 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90812.054018 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76892.857143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70560.885515 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70775.623552 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122229.036396 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 86523.829726 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78696.917808 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68037.082888 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77774.611639 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90758.632025 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 96976.190476 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71159.233546 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70237.067771 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119715.576446 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 86401.318914 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68207.465922 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77572.664185 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90812.054018 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76892.857143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70560.885515 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70775.623552 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122229.036396 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 86523.829726 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2706,58 +2752,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 215369 # Transaction distribution -system.membus.trans_dist::ReadResp 215369 # Transaction distribution -system.membus.trans_dist::WriteReq 31074 # Transaction distribution -system.membus.trans_dist::WriteResp 31074 # Transaction distribution -system.membus.trans_dist::Writeback 137904 # Transaction distribution +system.membus.trans_dist::ReadReq 214962 # Transaction distribution +system.membus.trans_dist::ReadResp 214962 # Transaction distribution +system.membus.trans_dist::WriteReq 31066 # Transaction distribution +system.membus.trans_dist::WriteResp 31066 # Transaction distribution +system.membus.trans_dist::Writeback 138129 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 77019 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40910 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14411 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 39992 # Transaction distribution -system.membus.trans_dist::ReadExResp 19617 # Transaction distribution +system.membus.trans_dist::UpgradeReq 76255 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40796 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14193 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 40018 # Transaction distribution +system.membus.trans_dist::ReadExResp 19540 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14196 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 663493 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 785643 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 894551 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661851 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 783963 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 892875 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28392 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19286572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19478976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24114432 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 124537 # Total snoops (count) -system.membus.snoop_fanout::samples 508980 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28316 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19273388 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19465716 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24102196 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123912 # Total snoops (count) +system.membus.snoop_fanout::samples 507941 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 508980 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 507941 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 508980 # Request fanout histogram -system.membus.reqLayer0.occupancy 88720999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 507941 # Request fanout histogram +system.membus.reqLayer0.occupancy 88612000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12492999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12528499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1167594605 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1167691410 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1174957130 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1172073016 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37546467 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 37476242 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2790,44 +2836,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 518257 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 518242 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31074 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31074 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 232242 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36265 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 80802 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41230 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 122032 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51798 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51798 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1084621 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 339731 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1424352 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34113464 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5575752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 39689216 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 290726 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 922102 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.039605 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.195030 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 516720 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 516705 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31066 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31066 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 232835 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 79932 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41134 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 121066 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51762 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51762 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1083099 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 338756 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1421855 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34093856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5618324 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 39712180 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 288702 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 920160 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.039660 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.195160 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 885582 96.04% 96.04% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36520 3.96% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 883666 96.03% 96.03% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36494 3.97% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 922102 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 794355306 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 920160 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 787000770 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 342000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 683518313 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 681574777 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 260405210 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 259216519 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |