diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | 3991 |
1 files changed, 2072 insertions, 1919 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 9cf124dc2..16f8b652d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,152 +1,152 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.844427 # Number of seconds simulated -sim_ticks 2844427140500 # Number of ticks simulated -final_tick 2844427140500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.845843 # Number of seconds simulated +sim_ticks 2845842660500 # Number of ticks simulated +final_tick 2845842660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 150296 # Simulator instruction rate (inst/s) -host_op_rate 181972 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3416553864 # Simulator tick rate (ticks/s) -host_mem_usage 612172 # Number of bytes of host memory used -host_seconds 832.54 # Real time elapsed on the host -sim_insts 125127935 # Number of instructions simulated -sim_ops 151499394 # Number of ops (including micro ops) simulated +host_inst_rate 164712 # Simulator instruction rate (inst/s) +host_op_rate 199442 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3743328799 # Simulator tick rate (ticks/s) +host_mem_usage 646452 # Number of bytes of host memory used +host_seconds 760.24 # Real time elapsed on the host +sim_insts 125221621 # Number of instructions simulated +sim_ops 151624712 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 10304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 10368 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1349820 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 10836800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 503456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1120064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3007420 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8732480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 774240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 399936 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 13821980 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 416640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 27264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 443904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9404288 # Number of bytes written to this memory +system.physmem.bytes_read::total 12926236 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1722304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 153024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1875328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8977344 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 9422032 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 161 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8995088 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 162 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 21616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 169325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7890 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 17501 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 47516 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 136445 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 12121 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6249 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 216517 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 146942 # Number of write requests responded to by this memory +system.physmem.num_reads::total 202521 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 140271 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 151378 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 474549 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3809836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 176997 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 393775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4859319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 146476 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 9585 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 156061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3306215 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.inst 6224 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 144707 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 1056777 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3068504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 270 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 272060 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 140533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4542147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 605200 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53771 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 658971 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3154547 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.inst 6221 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3312453 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3306215 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 480773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3809836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 180 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 177011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 393775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 8171773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 216517 # Number of read requests accepted -system.physmem.writeReqs 187602 # Number of write requests accepted -system.physmem.readBursts 216517 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 187602 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13846784 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10304 # Total number of bytes read from write queue -system.physmem.bytesWritten 11642944 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 13821980 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11740368 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5664 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 13644 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 13513 # Per bank write bursts -system.physmem.perBankRdBursts::1 13311 # Per bank write bursts -system.physmem.perBankRdBursts::2 14548 # Per bank write bursts -system.physmem.perBankRdBursts::3 14027 # Per bank write bursts -system.physmem.perBankRdBursts::4 15548 # Per bank write bursts -system.physmem.perBankRdBursts::5 13123 # Per bank write bursts -system.physmem.perBankRdBursts::6 13508 # Per bank write bursts -system.physmem.perBankRdBursts::7 14039 # Per bank write bursts -system.physmem.perBankRdBursts::8 13183 # Per bank write bursts -system.physmem.perBankRdBursts::9 13181 # Per bank write bursts -system.physmem.perBankRdBursts::10 13142 # Per bank write bursts -system.physmem.perBankRdBursts::11 11743 # Per bank write bursts -system.physmem.perBankRdBursts::12 13238 # Per bank write bursts -system.physmem.perBankRdBursts::13 14181 # Per bank write bursts -system.physmem.perBankRdBursts::14 13272 # Per bank write bursts -system.physmem.perBankRdBursts::15 12799 # Per bank write bursts -system.physmem.perBankWrBursts::0 11429 # Per bank write bursts -system.physmem.perBankWrBursts::1 11725 # Per bank write bursts -system.physmem.perBankWrBursts::2 12190 # Per bank write bursts -system.physmem.perBankWrBursts::3 11854 # Per bank write bursts -system.physmem.perBankWrBursts::4 10909 # Per bank write bursts -system.physmem.perBankWrBursts::5 11199 # Per bank write bursts -system.physmem.perBankWrBursts::6 11528 # Per bank write bursts -system.physmem.perBankWrBursts::7 11643 # Per bank write bursts -system.physmem.perBankWrBursts::8 11026 # Per bank write bursts -system.physmem.perBankWrBursts::9 11436 # Per bank write bursts -system.physmem.perBankWrBursts::10 11468 # Per bank write bursts -system.physmem.perBankWrBursts::11 11022 # Per bank write bursts -system.physmem.perBankWrBursts::12 11525 # Per bank write bursts -system.physmem.perBankWrBursts::13 11398 # Per bank write bursts -system.physmem.perBankWrBursts::14 10974 # Per bank write bursts -system.physmem.perBankWrBursts::15 10595 # Per bank write bursts +system.physmem.bw_write::total 3160782 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3154547 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3643 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 1062998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3068504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 272074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 140533 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7702929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 202521 # Number of read requests accepted +system.physmem.writeReqs 180931 # Number of write requests accepted +system.physmem.readBursts 202521 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 180931 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12951936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue +system.physmem.bytesWritten 11206784 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12926236 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11313424 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5797 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 13571 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12806 # Per bank write bursts +system.physmem.perBankRdBursts::1 12696 # Per bank write bursts +system.physmem.perBankRdBursts::2 13455 # Per bank write bursts +system.physmem.perBankRdBursts::3 13223 # Per bank write bursts +system.physmem.perBankRdBursts::4 15141 # Per bank write bursts +system.physmem.perBankRdBursts::5 12251 # Per bank write bursts +system.physmem.perBankRdBursts::6 12720 # Per bank write bursts +system.physmem.perBankRdBursts::7 12666 # Per bank write bursts +system.physmem.perBankRdBursts::8 12396 # Per bank write bursts +system.physmem.perBankRdBursts::9 12410 # Per bank write bursts +system.physmem.perBankRdBursts::10 12030 # Per bank write bursts +system.physmem.perBankRdBursts::11 11077 # Per bank write bursts +system.physmem.perBankRdBursts::12 12224 # Per bank write bursts +system.physmem.perBankRdBursts::13 12978 # Per bank write bursts +system.physmem.perBankRdBursts::14 12239 # Per bank write bursts +system.physmem.perBankRdBursts::15 12062 # Per bank write bursts +system.physmem.perBankWrBursts::0 11243 # Per bank write bursts +system.physmem.perBankWrBursts::1 11520 # Per bank write bursts +system.physmem.perBankWrBursts::2 11868 # Per bank write bursts +system.physmem.perBankWrBursts::3 11342 # Per bank write bursts +system.physmem.perBankWrBursts::4 10753 # Per bank write bursts +system.physmem.perBankWrBursts::5 10659 # Per bank write bursts +system.physmem.perBankWrBursts::6 11197 # Per bank write bursts +system.physmem.perBankWrBursts::7 10854 # Per bank write bursts +system.physmem.perBankWrBursts::8 10720 # Per bank write bursts +system.physmem.perBankWrBursts::9 10780 # Per bank write bursts +system.physmem.perBankWrBursts::10 10917 # Per bank write bursts +system.physmem.perBankWrBursts::11 10553 # Per bank write bursts +system.physmem.perBankWrBursts::12 10892 # Per bank write bursts +system.physmem.perBankWrBursts::13 10850 # Per bank write bursts +system.physmem.perBankWrBursts::14 10512 # Per bank write bursts +system.physmem.perBankWrBursts::15 10446 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2844424796500 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 2845842079500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 559 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 215930 # Read request sizes (log2) +system.physmem.readPktSize::6 201934 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 183166 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 79055 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63481 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12216 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10702 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 7427 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6415 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 303 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 92 # What read queue length does an incoming req see +system.physmem.writePktSize::6 176495 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 98520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 50579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9843 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5553 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 735 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -176,173 +176,159 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 13080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 12741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 12428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 12228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 12238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 12014 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 93322 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 273.137395 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 151.655882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.256113 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45588 48.85% 48.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18736 20.08% 68.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6915 7.41% 76.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3558 3.81% 80.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3108 3.33% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2062 2.21% 85.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1352 1.45% 87.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1057 1.13% 88.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10946 11.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 93322 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7762 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.873744 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 521.384620 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7761 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7762 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7762 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.437387 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.920909 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.626862 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6141 79.12% 79.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 490 6.31% 85.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 77 0.99% 86.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 208 2.68% 89.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 144 1.86% 90.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 54 0.70% 91.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 53 0.68% 92.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 34 0.44% 92.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 115 1.48% 94.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 15 0.19% 94.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 16 0.21% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 14 0.18% 94.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 31 0.40% 95.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 17 0.22% 95.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 9 0.12% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 24 0.31% 95.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 61 0.79% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 9 0.12% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.05% 96.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 7 0.09% 96.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 74 0.95% 97.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.15% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 8 0.10% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 21 0.27% 98.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 7 0.09% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 12 0.15% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 7 0.09% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 28 0.36% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 9 0.12% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.04% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 9 0.12% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 8 0.10% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.04% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 7 0.09% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.04% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.06% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 3 0.04% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 3 0.04% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 3 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-243 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7762 # Writes before turning the bus around for reads -system.physmem.totQLat 7644398000 # Total ticks spent queuing -system.physmem.totMemAccLat 11701073000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1081780000 # Total ticks spent in databus transfers -system.physmem.avgQLat 35332.50 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 94139 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 256.627498 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 142.457232 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 317.924062 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 48795 51.83% 51.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18347 19.49% 71.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6488 6.89% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3770 4.00% 82.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2738 2.91% 85.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1619 1.72% 86.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 964 1.02% 87.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1076 1.14% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10342 10.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 94139 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7479 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.058430 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 520.327968 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7478 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7479 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7479 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.413023 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.870843 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.578889 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 6390 85.44% 85.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 248 3.32% 88.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 198 2.65% 91.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 77 1.03% 92.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 144 1.93% 94.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 30 0.40% 94.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 35 0.47% 95.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 33 0.44% 95.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 72 0.96% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 21 0.28% 96.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 96 1.28% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 18 0.24% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 22 0.29% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 12 0.16% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 35 0.47% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 4 0.05% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 12 0.16% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 4 0.05% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 8 0.11% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 2 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.05% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 3 0.04% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 2 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7479 # Writes before turning the bus around for reads +system.physmem.totQLat 5783977250 # Total ticks spent queuing +system.physmem.totMemAccLat 9578489750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1011870000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28580.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 54082.50 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.87 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.86 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.13 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47330.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.54 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.98 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.07 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.94 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.48 # Average write queue length when enqueuing -system.physmem.readRowHits 183280 # Number of row buffer hits during reads -system.physmem.writeRowHits 121675 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.88 # Row buffer hit rate for writes -system.physmem.avgGap 7038582.19 # Average gap between requests -system.physmem.pageHitRate 76.57 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2710525028500 # Time in different power states -system.physmem.memoryStateTime::REF 94981640000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 38919724000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 365533560 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 339980760 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 199447875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 185505375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 870612600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 816964200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 599250960 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 579597120 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 185784087840 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 185784087840 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 82151193285 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 81119552850 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1634593377000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1635498324750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1904563503120 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1904324012895 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.577359 # Core power per rank (mW) -system.physmem.averagePower::1 669.493163 # Core power per rank (mW) +system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing +system.physmem.readRowHits 168404 # Number of row buffer hits during reads +system.physmem.writeRowHits 114936 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.21 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.63 # Row buffer hit rate for writes +system.physmem.avgGap 7421638.38 # Average gap between requests +system.physmem.pageHitRate 75.06 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 372813840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 203420250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 818672400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 579545280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185876137200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83421293220 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634324841000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1905596723190 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.608836 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2718714861000 # Time in different power states +system.physmem_0.memoryStateTime::REF 95028700000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32092142750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 338877000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 184903125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 759837000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 555141600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185876137200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82372109895 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635245177250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1905332183070 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.515879 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2720254769500 # Time in different power states +system.physmem_1.memoryStateTime::REF 95028700000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30559102000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory @@ -352,31 +338,39 @@ system.realview.nvmem.bytes_inst_read::total 1216 system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 158 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 157 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 428 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 158 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 427 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 157 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 428 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 158 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 427 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 157 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 428 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 427 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 35736686 # Number of BP lookups -system.cpu0.branchPred.condPredicted 17706973 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1707657 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 20554340 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 14845557 # Number of BTB hits +system.cpu0.branchPred.lookups 35059389 # Number of BP lookups +system.cpu0.branchPred.condPredicted 17250705 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1579435 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 20094508 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 14609065 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.225900 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 10924417 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 815226 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.701780 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 10810171 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 733013 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -398,27 +392,66 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 67889 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 67889 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44852 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23037 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 67889 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 67889 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 67889 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6673 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 8598.195564 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 7320.525431 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6106.619536 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6491 97.27% 97.27% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 168 2.52% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 6 0.09% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6673 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 287368000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 287368000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 287368000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5164 77.39% 77.39% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1509 22.61% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6673 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67889 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67889 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6673 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6673 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 74562 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 24607000 # DTB read hits -system.cpu0.dtb.read_misses 66402 # DTB read misses -system.cpu0.dtb.write_hits 18455953 # DTB write hits -system.cpu0.dtb.write_misses 6655 # DTB write misses +system.cpu0.dtb.read_hits 23969568 # DTB read hits +system.cpu0.dtb.read_misses 61820 # DTB read misses +system.cpu0.dtb.write_hits 17946825 # DTB write hits +system.cpu0.dtb.write_misses 6069 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3808 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1234 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2108 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3496 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1251 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2004 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 615 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24673402 # DTB read accesses -system.cpu0.dtb.write_accesses 18462608 # DTB write accesses +system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 24031388 # DTB read accesses +system.cpu0.dtb.write_accesses 17952894 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 43062953 # DTB hits -system.cpu0.dtb.misses 73057 # DTB misses -system.cpu0.dtb.accesses 43136010 # DTB accesses +system.cpu0.dtb.hits 41916393 # DTB hits +system.cpu0.dtb.misses 67889 # DTB misses +system.cpu0.dtb.accesses 41984282 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -440,8 +473,38 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 71661808 # ITB inst hits -system.cpu0.itb.inst_misses 4142 # ITB inst misses +system.cpu0.itb.walker.walks 3825 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3825 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3518 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3825 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3825 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3825 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2419 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 8874.535345 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 7628.532351 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 4888.994435 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 1491 61.64% 61.64% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 888 36.71% 98.35% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 4 0.17% 98.51% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2419 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 286941000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 286941000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 286941000 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2119 87.60% 87.60% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 300 12.40% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2419 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3825 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3825 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2419 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2419 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6244 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 70462798 # ITB inst hits +system.cpu0.itb.inst_misses 3825 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -450,123 +513,123 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2456 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2222 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 8241 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7291 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 71665950 # ITB inst accesses -system.cpu0.itb.hits 71661808 # DTB hits -system.cpu0.itb.misses 4142 # DTB misses -system.cpu0.itb.accesses 71665950 # DTB accesses -system.cpu0.numCycles 235973632 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 70466623 # ITB inst accesses +system.cpu0.itb.hits 70462798 # DTB hits +system.cpu0.itb.misses 3825 # DTB misses +system.cpu0.itb.accesses 70466623 # DTB accesses +system.cpu0.numCycles 234985394 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 111703770 # Number of instructions committed -system.cpu0.committedOps 135097839 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 8562554 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1855 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5452894525 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.112495 # CPI: cycles per instruction -system.cpu0.ipc 0.473374 # IPC: instructions per cycle +system.cpu0.committedInsts 109265327 # Number of instructions committed +system.cpu0.committedOps 132114239 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 8364757 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1821 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5456715361 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.150594 # CPI: cycles per instruction +system.cpu0.ipc 0.464988 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1855 # number of quiesce instructions executed -system.cpu0.tickCycles 199544848 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 36428784 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 751860 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.262864 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 41566353 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 752372 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.247076 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 306713000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 494.262864 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.965357 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.965357 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1824 # number of quiesce instructions executed +system.cpu0.tickCycles 195318282 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 39667112 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 718541 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.305697 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 40476936 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 719053 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 56.292006 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 306903000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.inst 494.305697 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.965441 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.965441 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 86104149 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 86104149 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 23403701 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23403701 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 17336391 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 17336391 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 390425 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 390425 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 371566 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 371566 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.inst 40740092 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 40740092 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.inst 40740092 # number of overall hits -system.cpu0.dcache.overall_hits::total 40740092 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.inst 564897 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 564897 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 554409 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 554409 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6644 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6644 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20340 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20340 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 1119306 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1119306 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 1119306 # number of overall misses -system.cpu0.dcache.overall_misses::total 1119306 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6887885459 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6887885459 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8219762503 # 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average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9401.011692 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9401.011692 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9401.011692 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -710,313 +773,323 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2070970 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 2070970 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 2070970 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 2070970 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 2070970 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 2070970 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 14149699520 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 14149699520 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 14149699520 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 14149699520 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 14149699520 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 14149699520 # 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number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1982967 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1982967 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 15657207046 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 15657207046 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 15657207046 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 15657207046 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 15657207046 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 15657207046 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 278031000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 278031000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 278031000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 278031000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028145 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028145 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028145 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028145 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028145 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028145 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7895.848517 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7895.848517 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7895.848517 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7895.848517 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7895.848517 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7895.848517 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 18115074 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 431506 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 17132776 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9283 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6596 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 534910 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1383846 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 428439 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16212.256950 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3152645 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 444682 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 7.089662 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2824980212500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4226.197620 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 50.775812 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.065487 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2187.555983 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.662049 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.257947 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003099 # Average percentage of cache occupancy +system.cpu0.l2cache.prefetcher.num_hwpf_issued 2292717 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 2293221 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 436 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu0.l2cache.prefetcher.pfSpanPage 284211 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 303376 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16141.726832 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2969035 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 319611 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 9.289527 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 2825848630000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 6310.295058 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.412646 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.063392 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 7791.524761 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1981.430976 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.385150 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003565 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.133518 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.594950 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.989518 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8981 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7254 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 61 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 111 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2870 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5529 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 410 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.475557 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.120937 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.985213 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1941 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14280 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 509 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 923 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 497 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 272 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3049 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3651 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 230 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.548157 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.442749 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 57799798 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 57799798 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 84149 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4243 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2500411 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 2588803 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 541643 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 541643 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4674 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 4674 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2411 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 2411 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 234433 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 234433 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 84149 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4243 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 2734844 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 2823236 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 84149 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4243 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 2734844 # number of overall hits -system.cpu0.l2cache.overall_hits::total 2823236 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 906 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 138 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 97001 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 98045 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 27960 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 27960 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 17929 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 17929 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 46525 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 46525 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 906 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 138 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 143526 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 144570 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 906 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 138 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 143526 # number of overall misses -system.cpu0.l2cache.overall_misses::total 144570 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 31530500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3231999 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2954004148 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 2988766647 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 497244183 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 497244183 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 356127296 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 356127296 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 112000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 112000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 1936152477 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 1936152477 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 31530500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3231999 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4890156625 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 4924919124 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 31530500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3231999 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4890156625 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 4924919124 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 85055 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4381 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2597412 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 2686848 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 541643 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 541643 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 32634 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 32634 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 20340 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 20340 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 280958 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 280958 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 85055 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4381 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 2878370 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 2967806 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 85055 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4381 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 2878370 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 2967806 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010652 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031500 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.037345 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.036491 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.856775 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.856775 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.881465 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.881465 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.165594 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.165594 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010652 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.031500 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.049864 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.048713 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010652 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.031500 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.049864 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.048713 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34801.876380 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23420.282609 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30453.337058 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30483.621266 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17784.126717 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17784.126717 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19863.199063 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19863.199063 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst inf # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 41615.313853 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 41615.313853 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34801.876380 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23420.282609 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34071.573269 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 34065.982735 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34801.876380 # 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number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1685499 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 4279514975 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4305290474 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15488924735 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15488924735 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 449600763 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 449600763 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 240569359 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 240569359 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 219000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 219000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1467254248 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1467254248 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 24090000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1685499 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 5746769223 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 5772544722 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 24090000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1685499 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 5746769223 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15488924735 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 21261469457 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6177076991 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6177076991 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4588309497 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4588309497 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10765386488 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10765386488 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.057106 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.055577 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.856775 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.856775 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.881465 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.881465 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.154795 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154795 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010652 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031500 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.045921 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.044889 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010652 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031500 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.045921 # mshr miss rate for overall accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.846699 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.846699 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.905006 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.905006 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.150831 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150831 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.066304 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.064643 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.066304 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.225125 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24365.159010 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24387.417709 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40472.031944 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40472.031944 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17220.066452 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17220.066452 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13307.710748 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13307.710748 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27564.673910 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27564.673910 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25417.914804 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25424.656953 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27779.801325 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16420.282609 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25417.914804 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40472.031944 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37471.664733 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163393 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30134.034017 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30110.716552 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55165.489205 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17026.462281 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17026.462281 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13360.510885 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13360.510885 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 109500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 109500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 35947.135948 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 35947.135948 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31431.794167 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31406.834216 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31431.794167 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45765.812883 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1024,67 +1097,75 @@ system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 2861093 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2792980 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28855 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28855 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 541643 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 731101 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 2726808 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2669763 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28813 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28813 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 523100 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 388140 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 68486 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42622 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 93982 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 302729 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 293421 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 4148051 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2491359 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12339 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 183942 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6835691 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 132737600 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 90757533 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17524 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 340220 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 223852877 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1093341 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4548807 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.213001 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.409428 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::UpgradeReq 64720 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42432 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 88655 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 13 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 299964 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 286773 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3972081 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2399294 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11788 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 172273 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6555436 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 127106560 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 87442327 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17780 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 325388 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 214892055 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 732010 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4046250 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.152317 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.359328 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 3579907 78.70% 78.70% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 968900 21.30% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 3429939 84.77% 84.77% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 616311 15.23% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4548807 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2378574445 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 4046250 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2284841999 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 119537998 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 117254000 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 3112636730 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2984852953 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1291088389 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1241569539 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7963988 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7347491 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 98908477 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 90940738 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 3448752 # Number of BP lookups -system.cpu1.branchPred.condPredicted 1941981 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 196391 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2221819 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1396869 # Number of BTB hits +system.cpu1.branchPred.lookups 4088735 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2366310 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 253216 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2663045 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1651600 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 62.870513 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 715789 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 52420 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 62.019230 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 809555 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 58673 # Number of incorrect RAS predictions. +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1106,27 +1187,66 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 25571 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 25571 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18521 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7050 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 25571 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 25571 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 25571 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2708 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 8701.256278 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 7631.681902 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5745.938863 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 2093 77.29% 77.29% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 481 17.76% 95.05% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 65 2.40% 97.45% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.07% 99.52% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 9 0.33% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-90111 4 0.15% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2708 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1108722264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1108722264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1108722264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1997 73.74% 73.74% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 711 26.26% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2708 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 25571 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 25571 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2708 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2708 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 28279 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3432223 # DTB read hits -system.cpu1.dtb.read_misses 19764 # DTB read misses -system.cpu1.dtb.write_hits 2826731 # DTB write hits -system.cpu1.dtb.write_misses 1392 # DTB write misses +system.cpu1.dtb.read_hits 4075725 # DTB read hits +system.cpu1.dtb.read_misses 23546 # DTB read misses +system.cpu1.dtb.write_hits 3346999 # DTB write hits +system.cpu1.dtb.write_misses 2025 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1674 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 101 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2069 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 121 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 325 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 209 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3451987 # DTB read accesses -system.cpu1.dtb.write_accesses 2828123 # DTB write accesses +system.cpu1.dtb.perms_faults 279 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 4099271 # DTB read accesses +system.cpu1.dtb.write_accesses 3349024 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6258954 # DTB hits -system.cpu1.dtb.misses 21156 # DTB misses -system.cpu1.dtb.accesses 6280110 # DTB accesses +system.cpu1.dtb.hits 7422724 # DTB hits +system.cpu1.dtb.misses 25571 # DTB misses +system.cpu1.dtb.accesses 7448295 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1148,8 +1268,42 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 6653879 # ITB inst hits -system.cpu1.itb.inst_misses 1856 # ITB inst misses +system.cpu1.itb.walker.walks 2243 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2243 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2062 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2243 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2243 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2243 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1122 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 8831.106061 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 7825.020839 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4777.823788 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 160 14.26% 14.26% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 676 60.25% 74.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 3 0.27% 74.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 248 22.10% 96.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 96.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 13 1.16% 98.13% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.69% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1122 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1108154264 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1108154264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1108154264 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 954 85.03% 85.03% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 168 14.97% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1122 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2243 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2243 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1122 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1122 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3365 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 7772051 # ITB inst hits +system.cpu1.itb.inst_misses 2243 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1158,122 +1312,122 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 882 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1160 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1128 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1845 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6655735 # ITB inst accesses -system.cpu1.itb.hits 6653879 # DTB hits -system.cpu1.itb.misses 1856 # DTB misses -system.cpu1.itb.accesses 6655735 # DTB accesses -system.cpu1.numCycles 36145472 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7774294 # ITB inst accesses +system.cpu1.itb.hits 7772051 # DTB hits +system.cpu1.itb.misses 2243 # DTB misses +system.cpu1.itb.accesses 7774294 # DTB accesses +system.cpu1.numCycles 42246986 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13424165 # Number of instructions committed -system.cpu1.committedOps 16401555 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1287407 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2767 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5652095397 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.692568 # CPI: cycles per instruction -system.cpu1.ipc 0.371393 # IPC: instructions per cycle +system.cpu1.committedInsts 15956294 # Number of instructions committed +system.cpu1.committedOps 19510473 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1491389 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2792 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5648821854 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.647669 # CPI: cycles per instruction +system.cpu1.ipc 0.377691 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2770 # number of quiesce instructions executed -system.cpu1.tickCycles 26236459 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 9909013 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 149765 # number of replacements -system.cpu1.dcache.tags.tagsinuse 476.829408 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 5935391 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 150124 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.536590 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 107725830000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 476.829408 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.931307 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.931307 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 12574886 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 12574886 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 3167382 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3167382 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.inst 2587127 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2587127 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 79870 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 79870 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 60510 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 60510 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 5754509 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5754509 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 5754509 # number of overall hits -system.cpu1.dcache.overall_hits::total 5754509 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 151161 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 151161 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 116953 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 116953 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5079 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5079 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 22818 # 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average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 19850.536233 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 19850.536233 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1282,74 +1436,74 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 93707 # number of writebacks -system.cpu1.dcache.writebacks::total 93707 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 11593 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 11593 # 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average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 24008.093807 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24008.093807 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16359.716480 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16359.716480 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21379.314664 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21379.314664 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 113901 # number of writebacks +system.cpu1.dcache.writebacks::total 113901 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15137 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 15137 # 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number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1417,310 +1570,307 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 827664 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 827664 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 827664 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 827664 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 827664 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 827664 # 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number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.124412 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.124412 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.124412 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.124412 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6605.980830 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6605.980830 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6605.980830 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6605.980830 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 908528 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 908528 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 908528 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 908528 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 908528 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 908528 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6381932762 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6381932762 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6381932762 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6381932762 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6381932762 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6381932762 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10331250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10331250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10331250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10331250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.116927 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.116927 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.116927 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.116927 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.116927 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.116927 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7024.475593 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7024.475593 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7024.475593 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7024.475593 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7024.475593 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7024.475593 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6453687 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 29592 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6340817 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 898 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2376 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 80004 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 668025 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 52740 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15520.178150 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1029232 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 68128 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 15.107327 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.num_hwpf_issued 255012 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 255045 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 26 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 67427 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 54264 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15327.785502 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1131516 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 69292 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 16.329677 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 6901.586978 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.255538 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.084140 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2337.993929 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6253.257565 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.421239 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001664 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000005 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.142700 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.381669 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.947276 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8859 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 87 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6442 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 153 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1624 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 7082 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 8763.818423 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 26.824644 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.109281 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5323.780218 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1213.252936 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.534901 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001637 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000007 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.324938 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.074051 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.935534 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2056 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 45 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 12927 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 84 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 880 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1092 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 51 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 256 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1161 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5025 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.540710 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005310 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.393188 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 19285639 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 19285639 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 22569 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2289 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 905837 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 930695 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 93707 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 93707 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1549 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1549 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 533 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 533 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 18299 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 18299 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 22569 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2289 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 924136 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 948994 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 22569 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2289 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 924136 # number of overall hits -system.cpu1.l2cache.overall_hits::total 948994 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 704 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 245 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 66474 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 67423 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 27781 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 27781 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22285 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22285 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 30137 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 30137 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 704 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 245 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 96611 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 97560 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 704 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 245 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 96611 # number of overall misses -system.cpu1.l2cache.overall_misses::total 97560 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 14471499 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4810998 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1464118881 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1483401378 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 523592810 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 523592810 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 437167020 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 437167020 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 97500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 97500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1078871611 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1078871611 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 14471499 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4810998 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2542990492 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 2562272989 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 14471499 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4810998 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2542990492 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 2562272989 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 23273 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2534 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 972311 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 998118 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 93707 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 93707 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 29330 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29330 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 22818 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 22818 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 48436 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 48436 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 23273 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2534 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 1020747 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1046554 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 23273 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2534 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 1020747 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1046554 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.030250 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.096685 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.068367 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.067550 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.947187 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.947187 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.976641 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.976641 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.622202 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.622202 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.030250 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.096685 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.094647 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.093220 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.030250 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.096685 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.094647 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.093220 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20556.106534 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19636.726531 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22025.436727 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22001.414621 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18847.154890 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18847.154890 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19617.097599 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19617.097599 # average SCUpgradeReq miss latency +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 271 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5756 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 6900 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.125488 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002747 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.789001 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 21629208 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 21629208 # 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number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28133 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22540 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22540 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 34750 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 34750 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 614 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 219 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 120608 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 121441 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 614 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 219 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 120608 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25785 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 147226 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 8818750 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2802498 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1423893692 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1435514940 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1025770621 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1025770621 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 399929245 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 399929245 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 306606785 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306606785 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 145000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 145000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 1042779776 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1042779776 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 8818750 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2802498 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 2466673468 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2478294716 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 8818750 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2802498 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 2466673468 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1025770621 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3504065337 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 316947250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 316947250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 187186000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 187186000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 504133250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 504133250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.079507 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.077996 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.947187 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.947187 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.976641 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.976641 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.616112 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.616112 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.030250 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.096685 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.093428 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.092031 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.030250 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.096685 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.093428 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.946124 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.946124 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.962220 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962220 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.579041 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.579041 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.105806 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103663 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.105806 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168476 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14982.124672 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14958.362583 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31527.335258 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31527.335258 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14260.643677 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14260.643677 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13734.519273 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13734.519273 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.125673 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 16584.286753 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16558.984670 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39781.680085 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14215.662923 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14215.662923 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13602.785492 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13602.785492 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27861.741773 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27861.741773 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19012.424082 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18956.313492 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13554.688920 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12636.726531 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19012.424082 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31527.335258 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24660.361413 # average overall mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30008.051108 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30008.051108 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20451.988823 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20407.397139 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20451.988823 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23800.587783 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -1728,64 +1878,64 @@ system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1502965 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1041469 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2098 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2098 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 93707 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 114724 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadReq 1492249 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1157222 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2126 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2126 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 113900 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 36842 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 83933 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40744 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 84523 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 65298 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 52790 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1655558 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 667978 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6105 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 48641 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2378282 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 52977856 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 21039827 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10136 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 93092 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 74120911 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 816365 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1934720 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.382054 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.485890 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeReq 74786 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41424 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85596 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 13 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 82199 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 64364 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1817284 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 767101 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7150 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 61380 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2652915 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 58153088 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24793955 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11380 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 115036 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 83073459 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 610470 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1874725 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.283158 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.450533 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1195552 61.79% 61.79% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 739168 38.21% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1343882 71.68% 71.68% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 530843 28.32% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1934720 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 695166718 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1874725 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 789561722 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 78719500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79017500 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1243267482 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1364909988 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 322631890 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 381206023 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 3571998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4307495 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 25370995 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 32623745 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31020 # Transaction distribution -system.iobus.trans_dist::ReadResp 31020 # Transaction distribution -system.iobus.trans_dist::WriteReq 59447 # Transaction distribution -system.iobus.trans_dist::WriteResp 23223 # Transaction distribution +system.iobus.trans_dist::ReadReq 31012 # Transaction distribution +system.iobus.trans_dist::ReadResp 31012 # Transaction distribution +system.iobus.trans_dist::WriteReq 59440 # Transaction distribution +system.iobus.trans_dist::WriteResp 23216 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56686 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1806,11 +1956,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 108000 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71630 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1831,11 +1981,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40158000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484026 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1875,23 +2025,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347075142 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347036169 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84777000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36822606 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36822569 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36433 # number of replacements -system.iocache.tags.tagsinuse 0.995239 # Cycle average of tags in use +system.iocache.tags.replacements 36417 # number of replacements +system.iocache.tags.tagsinuse 0.997930 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36433 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 269184120000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.995239 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062202 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062202 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 269849823000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.997930 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062371 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062371 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1905,14 +2055,14 @@ system.iocache.demand_misses::realview.ide 243 # system.iocache.demand_misses::total 243 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 243 # number of overall misses system.iocache.overall_misses::total 243 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 30315377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 30315377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9644186159 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9644186159 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 30315377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 30315377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 30315377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 30315377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 30354377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 30354377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9625347223 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9625347223 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 30354377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 30354377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 30354377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 30354377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1929,24 +2079,24 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124754.637860 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124754.637860 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 266237.471262 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 266237.471262 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124754.637860 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124754.637860 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124754.637860 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124754.637860 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 57278 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124915.131687 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124915.131687 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265717.403462 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 265717.403462 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124915.131687 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124915.131687 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124915.131687 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124915.131687 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 56938 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7269 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7266 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.879763 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.836224 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.writebacks::writebacks 36174 # number of writebacks +system.iocache.writebacks::total 36174 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses @@ -1955,14 +2105,14 @@ system.iocache.demand_mshr_misses::realview.ide 243 system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17678377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17678377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7760326371 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7760326371 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17678377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17678377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17678377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17678377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17717377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17717377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7741561361 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7741561361 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17717377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17717377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17717377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17717377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1971,264 +2121,264 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72750.522634 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72750.522634 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 214231.624641 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214231.624641 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72750.522634 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72750.522634 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72750.522634 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72750.522634 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72911.016461 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72911.016461 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213713.597642 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213713.597642 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72911.016461 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72911.016461 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72911.016461 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72911.016461 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 150396 # number of replacements -system.l2c.tags.tagsinuse 64479.883220 # Cycle average of tags in use -system.l2c.tags.total_refs 522727 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 215317 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.427709 # Average number of references to valid blocks. +system.l2c.tags.replacements 139153 # number of replacements +system.l2c.tags.tagsinuse 64176.379405 # Cycle average of tags in use +system.l2c.tags.total_refs 380612 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 203608 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.869337 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12469.492368 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 93.733463 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999899 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3818.005633 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42810.602787 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.718540 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 732.215158 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4549.115372 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.190269 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001430 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.058258 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.653238 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000087 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011173 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.069414 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983885 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 47457 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 17396 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 475 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6086 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 40896 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 11502.485032 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 90.401142 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.038214 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 12425.194881 # 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number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 413866750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10030002248 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.315304 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.121800 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.500587 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.753275 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.806014 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.764967 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.813158 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.871062 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.850353 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.750795 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.866906 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.796500 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.371905 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.321463 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.520232 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.371905 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.321463 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.520232 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72653.539979 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71955.443699 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 94058.618584 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10210.646555 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10096.708166 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10189.046358 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10290.366224 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10019.530478 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10101.512349 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72733.404219 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61713.292114 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 67445.428348 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62521.611524 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64927.927628 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 85997.063536 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10229.922408 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10070.488296 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10192.679340 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10210.542071 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10022.864592 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10087.050913 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 69789.055983 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61107.769940 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 66069.790875 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72684.079012 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63480.953024 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 92386.824795 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67254.658385 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64428.461113 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62167.333916 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 83971.580069 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72684.079012 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95357.230196 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63480.953024 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 97196.158162 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 92386.824795 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64428.461113 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62167.333916 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 83971.580069 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2396,57 +2549,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 238185 # Transaction distribution -system.membus.trans_dist::ReadResp 238185 # Transaction distribution -system.membus.trans_dist::WriteReq 30953 # Transaction distribution -system.membus.trans_dist::WriteResp 30953 # Transaction distribution -system.membus.trans_dist::Writeback 146942 # Transaction distribution +system.membus.trans_dist::ReadReq 217279 # Transaction distribution +system.membus.trans_dist::ReadResp 217279 # Transaction distribution +system.membus.trans_dist::WriteReq 30939 # Transaction distribution +system.membus.trans_dist::WriteResp 30939 # Transaction distribution +system.membus.trans_dist::Writeback 140271 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 78292 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 39832 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13662 # Transaction distribution -system.membus.trans_dist::ReadExReq 30241 # Transaction distribution -system.membus.trans_dist::ReadExResp 13298 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 108000 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 75080 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40217 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13603 # Transaction distribution +system.membus.trans_dist::ReadExReq 40948 # Transaction distribution +system.membus.trans_dist::ReadExResp 20159 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13634 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 701758 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 823430 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108896 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108896 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 932326 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13590 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 668031 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 789629 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108880 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108880 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 898509 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27268 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 20926892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 21118256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25753712 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 122070 # Total snoops (count) -system.membus.snoop_fanout::samples 531658 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27180 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19605228 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19796474 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4634432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4634432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24430906 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123136 # Total snoops (count) +system.membus.snoop_fanout::samples 511969 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 531658 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 511969 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 531658 # Request fanout histogram -system.membus.reqLayer0.occupancy 88755994 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 511969 # Request fanout histogram +system.membus.reqLayer0.occupancy 88887000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11894500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11855500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1935574499 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1869891749 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 2123782192 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2005520473 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38517394 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38480431 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2479,44 +2632,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 658320 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 658305 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30953 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30953 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 250431 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 516876 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 516861 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30939 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30939 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 234152 # Transaction distribution system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 90455 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40208 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 130663 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 6 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 38633 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 38633 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1411505 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 304961 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1716466 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 43486557 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5753747 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 49240304 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 287552 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1076220 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.033884 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.180932 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeReq 78584 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40535 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 119119 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 13 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51536 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51536 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1131248 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 290761 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1422009 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34509719 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5415139 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 39924858 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 285546 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 919868 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.039644 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.195121 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1039753 96.61% 96.61% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36467 3.39% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 883401 96.04% 96.04% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36467 3.96% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1076220 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1573537018 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 919868 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1489301846 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2438104006 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1891845782 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 680349684 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 645358377 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |