diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | 4904 |
1 files changed, 2454 insertions, 2450 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index c0e015b81..37e31e615 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,163 +1,163 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.848927 # Number of seconds simulated -sim_ticks 2848926718000 # Number of ticks simulated -final_tick 2848926718000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.848913 # Number of seconds simulated +sim_ticks 2848912955000 # Number of ticks simulated +final_tick 2848912955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 263408 # Simulator instruction rate (inst/s) -host_op_rate 318982 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5866973599 # Simulator tick rate (ticks/s) -host_mem_usage 626336 # Number of bytes of host memory used -host_seconds 485.59 # Real time elapsed on the host -sim_insts 127907365 # Number of instructions simulated -sim_ops 154893549 # Number of ops (including micro ops) simulated +host_inst_rate 258856 # Simulator instruction rate (inst/s) +host_op_rate 313468 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5762698171 # Simulator tick rate (ticks/s) +host_mem_usage 627144 # Number of bytes of host memory used +host_seconds 494.37 # Real time elapsed on the host +sim_insts 127970828 # Number of instructions simulated +sim_ops 154969713 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 9536 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 9408 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1676224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1355764 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8486720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 229952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 664980 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 417216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1675840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1349948 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8501504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 229824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 661012 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 405952 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12842440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1676224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 229952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1906176 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9074368 # Number of bytes written to this memory +system.physmem.bytes_read::total 12835728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1675840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 229824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1905664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9061888 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 9091932 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 149 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 9079452 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 147 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26191 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21707 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 132605 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3593 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10411 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6519 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26185 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21618 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 132836 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3591 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10349 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6343 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 201207 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 141787 # Number of write requests responded to by this memory +system.physmem.num_reads::total 201104 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 141592 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 146178 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3347 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 145983 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3302 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 588370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 475886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2978918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 80715 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 233414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 146447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 588238 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 473847 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2984122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 427 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 80671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 232023 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 142494 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4507817 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 588370 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 80715 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 669086 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3185188 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4505483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 588238 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 80671 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 668909 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3180823 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3191353 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3185188 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3186988 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3180823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3302 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 588370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 482037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2978918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 80715 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 233428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 146447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 588238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 479998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2984122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 80671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 232037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 142494 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7699170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 201207 # Number of read requests accepted -system.physmem.writeReqs 146178 # Number of write requests accepted -system.physmem.readBursts 201207 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 146178 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12868352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue -system.physmem.bytesWritten 9104640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12842440 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9091932 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7692471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 201104 # Number of read requests accepted +system.physmem.writeReqs 145983 # Number of write requests accepted +system.physmem.readBursts 201104 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 145983 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12861056 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue +system.physmem.bytesWritten 9091968 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12835728 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9079452 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12387 # Per bank write bursts -system.physmem.perBankRdBursts::1 12818 # Per bank write bursts -system.physmem.perBankRdBursts::2 13574 # Per bank write bursts -system.physmem.perBankRdBursts::3 13051 # Per bank write bursts -system.physmem.perBankRdBursts::4 15332 # Per bank write bursts -system.physmem.perBankRdBursts::5 12655 # Per bank write bursts -system.physmem.perBankRdBursts::6 12896 # Per bank write bursts -system.physmem.perBankRdBursts::7 13054 # Per bank write bursts -system.physmem.perBankRdBursts::8 12485 # Per bank write bursts -system.physmem.perBankRdBursts::9 12494 # Per bank write bursts -system.physmem.perBankRdBursts::10 11451 # Per bank write bursts -system.physmem.perBankRdBursts::11 10701 # Per bank write bursts -system.physmem.perBankRdBursts::12 11947 # Per bank write bursts -system.physmem.perBankRdBursts::13 12784 # Per bank write bursts -system.physmem.perBankRdBursts::14 11815 # Per bank write bursts -system.physmem.perBankRdBursts::15 11624 # Per bank write bursts -system.physmem.perBankWrBursts::0 9013 # Per bank write bursts +system.physmem.perBankRdBursts::0 12429 # Per bank write bursts +system.physmem.perBankRdBursts::1 12794 # Per bank write bursts +system.physmem.perBankRdBursts::2 13696 # Per bank write bursts +system.physmem.perBankRdBursts::3 13190 # Per bank write bursts +system.physmem.perBankRdBursts::4 15337 # Per bank write bursts +system.physmem.perBankRdBursts::5 12894 # Per bank write bursts +system.physmem.perBankRdBursts::6 12741 # Per bank write bursts +system.physmem.perBankRdBursts::7 13088 # Per bank write bursts +system.physmem.perBankRdBursts::8 12333 # Per bank write bursts +system.physmem.perBankRdBursts::9 12486 # Per bank write bursts +system.physmem.perBankRdBursts::10 11357 # Per bank write bursts +system.physmem.perBankRdBursts::11 10671 # Per bank write bursts +system.physmem.perBankRdBursts::12 11888 # Per bank write bursts +system.physmem.perBankRdBursts::13 12773 # Per bank write bursts +system.physmem.perBankRdBursts::14 11762 # Per bank write bursts +system.physmem.perBankRdBursts::15 11515 # Per bank write bursts +system.physmem.perBankWrBursts::0 8987 # Per bank write bursts system.physmem.perBankWrBursts::1 9459 # Per bank write bursts -system.physmem.perBankWrBursts::2 10048 # Per bank write bursts -system.physmem.perBankWrBursts::3 9447 # Per bank write bursts -system.physmem.perBankWrBursts::4 8653 # Per bank write bursts -system.physmem.perBankWrBursts::5 8898 # Per bank write bursts -system.physmem.perBankWrBursts::6 9273 # Per bank write bursts -system.physmem.perBankWrBursts::7 9228 # Per bank write bursts -system.physmem.perBankWrBursts::8 8869 # Per bank write bursts -system.physmem.perBankWrBursts::9 8977 # Per bank write bursts -system.physmem.perBankWrBursts::10 8270 # Per bank write bursts -system.physmem.perBankWrBursts::11 7926 # Per bank write bursts -system.physmem.perBankWrBursts::12 8743 # Per bank write bursts -system.physmem.perBankWrBursts::13 8906 # Per bank write bursts -system.physmem.perBankWrBursts::14 8530 # Per bank write bursts -system.physmem.perBankWrBursts::15 8020 # Per bank write bursts +system.physmem.perBankWrBursts::2 10102 # Per bank write bursts +system.physmem.perBankWrBursts::3 9553 # Per bank write bursts +system.physmem.perBankWrBursts::4 8641 # Per bank write bursts +system.physmem.perBankWrBursts::5 9022 # Per bank write bursts +system.physmem.perBankWrBursts::6 9160 # Per bank write bursts +system.physmem.perBankWrBursts::7 9289 # Per bank write bursts +system.physmem.perBankWrBursts::8 8726 # Per bank write bursts +system.physmem.perBankWrBursts::9 8906 # Per bank write bursts +system.physmem.perBankWrBursts::10 8219 # Per bank write bursts +system.physmem.perBankWrBursts::11 7897 # Per bank write bursts +system.physmem.perBankWrBursts::12 8731 # Per bank write bursts +system.physmem.perBankWrBursts::13 8920 # Per bank write bursts +system.physmem.perBankWrBursts::14 8491 # Per bank write bursts +system.physmem.perBankWrBursts::15 7959 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 92 # Number of times write queue was full causing retry -system.physmem.totGap 2848926179000 # Total gap between requests +system.physmem.numWrRetry 98 # Number of times write queue was full causing retry +system.physmem.totGap 2848912399000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 554 # Read request sizes (log2) +system.physmem.readPktSize::2 556 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 200625 # Read request sizes (log2) +system.physmem.readPktSize::6 200520 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 141787 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 84607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6758 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5703 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3992 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 136 # What read queue length does an incoming req see +system.physmem.writePktSize::6 141592 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 84624 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11856 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6722 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5707 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4943 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1053 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 127 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -185,178 +185,178 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 295 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 89804 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 244.676495 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.021398 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 301.276619 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45910 51.12% 51.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18733 20.86% 71.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6663 7.42% 79.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3737 4.16% 83.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2991 3.33% 86.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1528 1.70% 88.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 943 1.05% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1048 1.17% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8251 9.19% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89804 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7084 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.382976 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 553.950604 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7082 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4499 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 296 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 89688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 244.770315 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.172635 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 301.083170 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45750 51.01% 51.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18787 20.95% 71.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6651 7.42% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3758 4.19% 83.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2958 3.30% 86.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1568 1.75% 88.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1004 1.12% 89.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1009 1.13% 90.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8203 9.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 89688 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7073 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.410010 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 554.388606 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7071 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7084 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7084 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.081875 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.511113 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.183489 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5975 84.35% 84.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 419 5.91% 90.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 68 0.96% 91.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 50 0.71% 91.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 261 3.68% 95.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.30% 95.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 13 0.18% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 17 0.24% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 10 0.14% 96.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.08% 96.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.11% 96.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.13% 96.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 144 2.03% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 9 0.13% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.07% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 4 0.06% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 8 0.11% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.03% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 5 0.07% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 9 0.13% 99.46% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7073 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7073 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.085112 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.515707 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.383837 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5944 84.04% 84.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 432 6.11% 90.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 82 1.16% 91.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 52 0.74% 92.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 255 3.61% 95.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 25 0.35% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 15 0.21% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.10% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 13 0.18% 96.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 9 0.13% 96.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.10% 96.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 148 2.09% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 11 0.16% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.08% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.04% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 9 0.13% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.04% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.06% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 6 0.08% 99.46% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 2 0.03% 99.49% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::116-119 3 0.04% 99.53% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::120-123 1 0.01% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.04% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.16% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 4 0.06% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 3 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7084 # Writes before turning the bus around for reads -system.physmem.totQLat 9521946881 # Total ticks spent queuing -system.physmem.totMemAccLat 13291971881 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1005340000 # Total ticks spent in databus transfers -system.physmem.avgQLat 47356.85 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 6 0.08% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.04% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.06% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.04% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.06% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7073 # Writes before turning the bus around for reads +system.physmem.totQLat 9366475580 # Total ticks spent queuing +system.physmem.totMemAccLat 13134363080 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1004770000 # Total ticks spent in databus transfers +system.physmem.avgQLat 46610.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 66106.85 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.52 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.20 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 65360.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.51 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.19 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.51 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.19 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.49 # Average write queue length when enqueuing -system.physmem.readRowHits 166479 # Number of row buffer hits during reads -system.physmem.writeRowHits 87044 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.80 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.18 # Row buffer hit rate for writes -system.physmem.avgGap 8201062.74 # Average gap between requests -system.physmem.pageHitRate 73.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 339864000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 180642000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 755176380 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 386379180 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5802201600.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5394350610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 323555040 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 11564942040 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8568107520 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 670261966035 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 703579433835 # Total energy per rank (pJ) -system.physmem_0.averagePower 246.962980 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2836248193267 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 586826713 # Time in different power states -system.physmem_0.memoryStateTime::REF 2465512000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2788574898250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 22312648073 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9624892520 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 25361940444 # Time in different power states -system.physmem_1.actEnergy 301343700 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 160164180 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 680449140 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 356218020 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5736435120.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5416162800 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 310781280 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10711678260 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 8807078880 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 670588805775 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 703071916065 # Total energy per rank (pJ) -system.physmem_1.averagePower 246.784837 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2836233678907 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 556712196 # Time in different power states -system.physmem_1.memoryStateTime::REF 2438058000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2789808007000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 22935120354 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9698204397 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 23490616053 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.20 # Average write queue length when enqueuing +system.physmem.readRowHits 166422 # Number of row buffer hits during reads +system.physmem.writeRowHits 86905 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.16 # Row buffer hit rate for writes +system.physmem.avgGap 8208064.26 # Average gap between requests +system.physmem.pageHitRate 73.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 341813220 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 181678035 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 758046660 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 387391860 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5805889440.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5444775090 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 308095680 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 11642068740 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8562690720 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 670190772435 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 703626055650 # Total energy per rank (pJ) +system.physmem_0.averagePower 246.980538 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2836051939093 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 546109733 # Time in different power states +system.physmem_0.memoryStateTime::REF 2466940000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2788334468750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 22298648785 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9735828674 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 25530959058 # Time in different power states +system.physmem_1.actEnergy 298566240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 158687925 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 676764900 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 354171780 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5707547040.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5348415450 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 325299360 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10595992200 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8817735360 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 670663868775 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 702949735620 # Total energy per rank (pJ) +system.physmem_1.averagePower 246.743143 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2836330915238 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 596946927 # Time in different power states +system.physmem_1.memoryStateTime::REF 2425844000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2790131179750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 22962884806 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9559167335 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 23236932182 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory @@ -375,30 +375,30 @@ system.realview.nvmem.bw_inst_read::total 472 # I system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 20832099 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13651765 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1014112 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 13085676 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 8745572 # Number of BTB hits +system.cpu0.branchPred.lookups 20830846 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13649526 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1014386 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13197369 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 8753451 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.833169 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3412344 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 213562 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 762387 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 580471 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 181916 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 99152 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 66.327243 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3414506 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 211257 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 762629 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 580306 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 182323 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 100148 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -428,58 +428,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 65584 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 65584 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44931 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20653 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 65584 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 65584 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 65584 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6815 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12330.961115 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11272.043541 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 9573.930789 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 6808 99.90% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 5 0.07% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6815 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 66699 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 66699 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 45954 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20745 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 66699 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 66699 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 66699 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6786 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12503.831418 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11414.396725 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6634.903581 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6272 92.43% 92.43% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 416 6.13% 98.56% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 85 1.25% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 5 0.07% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 5 0.07% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::114688-131071 2 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6786 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 338892000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 338892000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 338892000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5268 77.30% 77.30% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1547 22.70% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6815 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65584 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5256 77.45% 77.45% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1530 22.55% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6786 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66699 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65584 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6815 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66699 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6786 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6815 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 72399 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6786 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 73485 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17333612 # DTB read hits -system.cpu0.dtb.read_misses 59171 # DTB read misses -system.cpu0.dtb.write_hits 14536785 # DTB write hits -system.cpu0.dtb.write_misses 6413 # DTB write misses +system.cpu0.dtb.read_hits 17337178 # DTB read hits +system.cpu0.dtb.read_misses 60105 # DTB read misses +system.cpu0.dtb.write_hits 14536732 # DTB write hits +system.cpu0.dtb.write_misses 6594 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3455 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1366 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1951 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3451 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1375 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1930 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 521 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17392783 # DTB read accesses -system.cpu0.dtb.write_accesses 14543198 # DTB write accesses +system.cpu0.dtb.perms_faults 524 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17397283 # DTB read accesses +system.cpu0.dtb.write_accesses 14543326 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31870397 # DTB hits -system.cpu0.dtb.misses 65584 # DTB misses -system.cpu0.dtb.accesses 31935981 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 31873910 # DTB hits +system.cpu0.dtb.misses 66699 # DTB misses +system.cpu0.dtb.accesses 31940609 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -509,41 +512,40 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 3993 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3993 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 304 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3689 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3993 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3993 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3993 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2420 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12562.190083 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11733.706609 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5199.448662 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 453 18.72% 18.72% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1764 72.89% 91.61% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 139 5.74% 97.36% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 98.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 27 1.12% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 4013 # Table walker walks requested +system.cpu0.itb.walker.walksShort 4013 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 305 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3708 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 4013 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 4013 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 4013 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2436 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12745.689655 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11895.862443 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5321.422543 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 433 17.78% 17.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1791 73.52% 91.30% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 138 5.67% 96.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 37 1.52% 98.48% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 36 1.48% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2420 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2436 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 338263500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 338263500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 338263500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2121 87.64% 87.64% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 299 12.36% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2420 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2136 87.68% 87.68% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 300 12.32% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2436 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3993 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3993 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4013 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4013 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2420 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2420 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6413 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 38722571 # ITB inst hits -system.cpu0.itb.inst_misses 3993 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2436 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2436 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6449 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 38740955 # ITB inst hits +system.cpu0.itb.inst_misses 4013 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -552,804 +554,798 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2172 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7056 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7050 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 38726564 # ITB inst accesses -system.cpu0.itb.hits 38722571 # DTB hits -system.cpu0.itb.misses 3993 # DTB misses -system.cpu0.itb.accesses 38726564 # DTB accesses -system.cpu0.numPwrStateTransitions 3692 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1846 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1496527734.232936 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23959432114.332718 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1066 57.75% 57.75% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 773 41.87% 99.62% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 38744968 # ITB inst accesses +system.cpu0.itb.hits 38740955 # DTB hits +system.cpu0.itb.misses 4013 # DTB misses +system.cpu0.itb.accesses 38744968 # DTB accesses +system.cpu0.numPwrStateTransitions 3702 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1851 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1492467740.212318 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23926618307.518574 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1069 57.75% 57.75% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 775 41.87% 99.62% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499963466540 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1846 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 86336520606 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2762590197394 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 172675597 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499963002708 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1851 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 86355167867 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2762557787133 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 172712897 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 79702454 # Number of instructions committed -system.cpu0.committedOps 95912008 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 5263315 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1846 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5525206368 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.166503 # CPI: cycles per instruction -system.cpu0.ipc 0.461573 # IPC: instructions per cycle +system.cpu0.committedInsts 79713377 # Number of instructions committed +system.cpu0.committedOps 95922535 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 5281292 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1851 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5525141996 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.166674 # CPI: cycles per instruction +system.cpu0.ipc 0.461537 # IPC: instructions per cycle system.cpu0.op_class_0::No_OpClass 2273 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 63720470 66.44% 66.44% # Class of committed instruction -system.cpu0.op_class_0::IntMult 92091 0.10% 66.53% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatMultAcc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatMisc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 8071 0.01% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::MemRead 16805556 17.52% 84.07% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 15273907 15.92% 99.99% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 63731011 66.44% 66.44% # Class of committed instruction +system.cpu0.op_class_0::IntMult 92142 0.10% 66.54% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::FloatMultAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::FloatMisc 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 8073 0.01% 66.55% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.55% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.55% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.55% # Class of committed instruction +system.cpu0.op_class_0::MemRead 16805807 17.52% 84.07% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 15273589 15.92% 99.99% # Class of committed instruction system.cpu0.op_class_0::FloatMemRead 2256 0.00% 99.99% # Class of committed instruction system.cpu0.op_class_0::FloatMemWrite 7384 0.01% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 95912008 # Class of committed instruction +system.cpu0.op_class_0::total 95922535 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1846 # number of quiesce instructions executed -system.cpu0.tickCycles 120803038 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 51872559 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 716043 # number of replacements -system.cpu0.dcache.tags.tagsinuse 497.070686 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 30430864 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 716555 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 42.468288 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1851 # number of quiesce instructions executed +system.cpu0.tickCycles 120871852 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 51841045 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 716918 # number of replacements +system.cpu0.dcache.tags.tagsinuse 495.671066 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 30432435 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 717430 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 42.418682 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 356904000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.070686 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970841 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.970841 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.671066 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968108 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.968108 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 74 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63800570 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63800570 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 15847676 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15847676 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 13422923 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 13422923 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320765 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 320765 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365692 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365692 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361178 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361178 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 29270599 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 29270599 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 29591364 # number of overall hits -system.cpu0.dcache.overall_hits::total 29591364 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 438302 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 438302 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 581071 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 581071 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 135874 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 135874 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20748 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20748 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20391 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20391 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1019373 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1019373 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1155247 # number of overall misses -system.cpu0.dcache.overall_misses::total 1155247 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6426011500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6426011500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11337499000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 11337499000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330321500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 330321500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 481265000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 481265000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 655500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 655500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 17763510500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 17763510500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 17763510500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 17763510500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16285978 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16285978 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 14003994 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 14003994 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456639 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 456639 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386440 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386440 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381569 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381569 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30289972 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30289972 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30746611 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30746611 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026913 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.026913 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041493 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.041493 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.297552 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.297552 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053690 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053690 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053440 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053440 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033654 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.033654 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037573 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.037573 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14661.150303 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14661.150303 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19511.383291 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19511.383291 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15920.642954 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15920.642954 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23601.834143 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23601.834143 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63807329 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63807329 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 15850504 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15850504 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 13422208 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 13422208 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320804 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 320804 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365505 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365505 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361161 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361161 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 29272712 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 29272712 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 29593516 # number of overall hits +system.cpu0.dcache.overall_hits::total 29593516 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 439135 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 439135 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 581157 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 581157 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 135756 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 135756 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20923 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20923 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20396 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20396 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1020292 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1020292 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1156048 # number of overall misses +system.cpu0.dcache.overall_misses::total 1156048 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6443435000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6443435000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11283390500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 11283390500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 333090000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 333090000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 482408000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 482408000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 637500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 637500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 17726825500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 17726825500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 17726825500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 17726825500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16289639 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16289639 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 14003365 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 14003365 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456560 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 456560 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386428 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386428 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381557 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381557 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30293004 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30293004 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30749564 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30749564 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026958 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.026958 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041501 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.041501 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.297345 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.297345 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054145 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054145 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053455 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053455 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033681 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.033681 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037596 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.037596 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14673.016271 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14673.016271 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19415.391194 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19415.391194 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15919.801176 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15919.801176 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23652.088645 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23652.088645 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17425.918187 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 17425.918187 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15376.374490 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15376.374490 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17374.266877 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 17374.266877 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15333.987430 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15333.987430 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 716044 # number of writebacks -system.cpu0.dcache.writebacks::total 716044 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44411 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 44411 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255478 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 255478 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14411 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14411 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 299889 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 299889 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 299889 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 299889 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 393891 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 393891 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325593 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 325593 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102318 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 102318 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6337 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6337 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20391 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20391 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 719484 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 719484 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 821802 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 821802 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20577 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20577 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.writebacks::writebacks 716918 # number of writebacks +system.cpu0.dcache.writebacks::total 716918 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44597 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 44597 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255598 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 255598 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14548 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14548 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 300195 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 300195 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 300195 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 300195 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 394538 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 394538 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325559 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 325559 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102257 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 102257 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6375 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6375 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20396 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20396 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 720097 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 720097 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 822354 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 822354 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20581 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20581 # number of ReadReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19270 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19270 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39847 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39847 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5265212000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5265212000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6193589500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6193589500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1698431500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1698431500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 100630000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100630000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 460892000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 460892000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 637500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 637500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11458801500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11458801500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13157233000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13157233000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4606601500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4606601500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4606601500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4606601500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024186 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024186 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023250 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023250 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224068 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224068 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016398 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016398 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053440 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053440 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023753 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023753 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026728 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026728 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13367.180261 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13367.180261 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19022.489734 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19022.489734 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16599.537716 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16599.537716 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15879.753827 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15879.753827 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22602.716885 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22602.716885 # average StoreCondReq mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39851 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39851 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5273598500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5273598500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6168960000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6168960000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1704833000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1704833000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102845500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102845500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 462030000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 462030000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 619500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 619500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11442558500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11442558500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13147391500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13147391500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4607502500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4607502500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4607502500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4607502500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024220 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024220 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023249 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023249 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223973 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223973 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016497 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016497 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053455 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053455 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023771 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023771 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026744 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026744 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13366.516026 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13366.516026 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18948.823408 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18948.823408 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16672.042012 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16672.042012 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16132.627451 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16132.627451 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22652.971171 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22652.971171 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15926.416015 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15926.416015 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16010.222657 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16010.222657 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223871.385528 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223871.385528 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115607.235175 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115607.235175 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1964076 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.773099 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36750687 # 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Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 36750687 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36750687 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36750687 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36750687 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36750687 # number of overall hits -system.cpu0.icache.overall_hits::total 36750687 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1964601 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1964601 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1964601 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1964601 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1964601 # number of overall misses -system.cpu0.icache.overall_misses::total 1964601 # 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number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 234570 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 289188 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15635.373554 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2589127 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 304798 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 8.494567 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 235148 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 289262 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15626.234267 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2591525 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 304855 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 8.500845 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14528.592543 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 65.479311 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.075767 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1041.225933 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.886755 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003997 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063551 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.954307 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 228 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15366 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 19 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 147 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 59 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1155 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7305 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5549 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1111 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.013916 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000977 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.937866 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 91385031 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 91385031 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77639 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5220 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 82859 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 481305 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 481305 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 2156745 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 2156745 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 222879 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 222879 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1872794 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1872794 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 388786 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 388786 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77639 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5220 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1872794 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 611665 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 2567318 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77639 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5220 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1872794 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 611665 # number of overall hits -system.cpu0.l2cache.overall_hits::total 2567318 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 934 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 150 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1084 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 56829 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 56829 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20390 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 20390 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45892 # 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number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 91807 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 159646 # number of overall misses -system.cpu0.l2cache.overall_misses::total 252537 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 44624500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3518000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 48142500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 45750500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 45750500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9568000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9568000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 607499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 607499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2923141000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2923141000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4535079000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4535079000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3749547498 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3749547498 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 44624500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3518000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4535079000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 6672688498 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 11255909998 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 44624500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3518000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4535079000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 6672688498 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 11255909998 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78573 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5370 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 83943 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 481305 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 481305 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 2156745 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 2156745 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56829 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 56829 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20390 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 20390 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 268771 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 268771 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1964601 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1964601 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 502540 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 502540 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78573 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5370 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1964601 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 771311 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 2819855 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78573 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5370 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1964601 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 771311 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 2819855 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.011887 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.027933 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.012914 # miss rate for ReadReq accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 14514.282419 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 66.020594 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.070348 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1045.860906 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.885881 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004030 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063834 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.953750 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 230 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15349 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 21 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 121 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 83 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1192 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7258 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5558 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1085 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.014038 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.936829 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 91498325 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 91498325 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 78219 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5306 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 83525 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 481785 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 481785 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 2159151 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 2159151 # 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average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38435.364728 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63655.903730 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63655.903730 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17349.847789 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17349.847789 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15060.200981 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15060.200981 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 499499 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 499499 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50864.680672 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50864.680672 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43407.069133 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43407.069133 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26866.440514 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26866.440514 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41808.681672 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17453.333333 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43407.069133 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33432.804868 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37131.537597 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41808.681672 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17453.333333 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43407.069133 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33432.804868 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63655.903730 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50784.937791 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.182218 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34078.086672 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63097.730550 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63097.730550 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17308.922663 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17308.922663 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15108.575211 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15108.575211 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50274.240208 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50274.240208 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43245.133621 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26883.323189 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26883.323189 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33282.312155 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36948.799964 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33282.312155 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63097.730550 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50415.402160 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215865.626671 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198689.234510 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215866.308731 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198692.702657 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111473.059452 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109904.763009 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 5514708 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2778846 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42068 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 220650 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 216436 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4214 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 117829 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2634124 # Transaction distribution +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111483.889990 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109914.916064 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 5521359 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2782090 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 221607 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 217384 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4223 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 119065 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2638335 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 19270 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 19270 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 714129 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 2198813 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 105915 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 313152 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 88836 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42982 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114292 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 287887 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284399 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1964601 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 602822 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3087 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5899831 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2594741 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13052 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 164810 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 8672434 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 251644992 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99451448 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 21480 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314292 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 351432212 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 940964 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 19090924 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 3779220 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.076318 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.269673 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::WritebackDirty 714834 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 2201699 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 105895 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 314040 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 88690 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43009 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113952 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 288266 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284716 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1967094 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 603225 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3100 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 13 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5907309 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2596679 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13203 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 166718 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 8683909 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 251964032 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99557768 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 21928 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 317096 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 351860824 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 942421 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 19099824 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3784720 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.076642 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.270185 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3495013 92.48% 92.48% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 279993 7.41% 99.89% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4214 0.11% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3498873 92.45% 92.45% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 281624 7.44% 99.89% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4223 0.11% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3779220 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 5504902494 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3784720 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 5512121494 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115882925 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115701354 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2952081467 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2955829450 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1226789533 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1228012492 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7686990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7726489 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 86252968 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 87463960 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 19393527 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6185527 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 769783 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 9956759 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3606289 # Number of BTB hits +system.cpu1.branchPred.lookups 19376501 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6203106 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 800498 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 9925818 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3621861 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 36.219507 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 8702764 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 566393 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3646067 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 3582470 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 63597 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 23601 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 36.489295 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8664248 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 596452 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3651980 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 3587973 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 64007 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 23614 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1379,58 +1375,63 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 26638 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 26638 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20208 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6430 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 26638 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 26638 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 26638 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2684 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12533.532042 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11490.379150 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 8690.810286 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 2656 98.96% 98.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 26 0.97% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2684 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1849661032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1849661032 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1849661032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1998 74.44% 74.44% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 686 25.56% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2684 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26638 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 26236 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 26236 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19848 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6388 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 26236 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 26236 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 26236 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2697 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12386.911383 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11389.033391 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6251.379906 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 628 23.29% 23.29% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1805 66.93% 90.21% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 172 6.38% 96.59% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.08% 98.67% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 26 0.96% 99.63% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 2 0.07% 99.70% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 3 0.11% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.07% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 3 0.11% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2697 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1855739032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1855739032 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1855739032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 2013 74.64% 74.64% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 684 25.36% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2697 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26236 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26638 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2684 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26236 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2697 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2684 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 29322 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2697 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 28933 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 11320530 # DTB read hits -system.cpu1.dtb.read_misses 24586 # DTB read misses -system.cpu1.dtb.write_hits 7061626 # DTB write hits -system.cpu1.dtb.write_misses 2052 # DTB write misses +system.cpu1.dtb.read_hits 11335471 # DTB read hits +system.cpu1.dtb.read_misses 23997 # DTB read misses +system.cpu1.dtb.write_hits 7067505 # DTB write hits +system.cpu1.dtb.write_misses 2239 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1992 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 148 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 300 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1990 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 147 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 359 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 11345116 # DTB read accesses -system.cpu1.dtb.write_accesses 7063678 # DTB write accesses +system.cpu1.dtb.perms_faults 265 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 11359468 # DTB read accesses +system.cpu1.dtb.write_accesses 7069744 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 18382156 # DTB hits -system.cpu1.dtb.misses 26638 # DTB misses -system.cpu1.dtb.accesses 18408794 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 18402976 # DTB hits +system.cpu1.dtb.misses 26236 # DTB misses +system.cpu1.dtb.accesses 18429212 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1460,45 +1461,45 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 2499 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2499 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 2445 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2445 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 180 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2319 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2499 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2499 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2499 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1128 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12699.024823 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11989.496313 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4984.320484 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 166 14.72% 14.72% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 634 56.21% 70.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 206 18.26% 89.18% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.34% 93.53% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 22 1.95% 95.48% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.48% 97.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.42% 99.38% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 99.65% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 2 0.18% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2265 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2445 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2445 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2445 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1122 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12500.891266 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11818.240424 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4741.770571 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 15.60% 15.60% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 626 55.79% 71.39% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 208 18.54% 89.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.37% 94.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 21 1.87% 96.17% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 29 2.58% 98.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 9 0.80% 99.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.18% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.82% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1128 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1850303532 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1850303532 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1850303532 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 963 85.37% 85.37% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 165 14.63% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1128 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 1122 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1856356532 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1856356532 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1856356532 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 957 85.29% 85.29% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 165 14.71% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1122 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2499 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2499 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2445 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2445 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1128 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1128 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3627 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 39699373 # ITB inst hits -system.cpu1.itb.inst_misses 2499 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1122 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1122 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3567 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 39707544 # ITB inst hits +system.cpu1.itb.inst_misses 2445 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1507,45 +1508,45 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1101 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1094 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1838 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1860 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 39701872 # ITB inst accesses -system.cpu1.itb.hits 39699373 # DTB hits -system.cpu1.itb.misses 2499 # DTB misses -system.cpu1.itb.accesses 39701872 # DTB accesses -system.cpu1.numPwrStateTransitions 5523 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2762 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1010212132.618392 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25718871891.755051 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1964 71.11% 71.11% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 794 28.75% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 39709989 # ITB inst accesses +system.cpu1.itb.hits 39707544 # DTB hits +system.cpu1.itb.misses 2445 # DTB misses +system.cpu1.itb.accesses 39709989 # DTB accesses +system.cpu1.numPwrStateTransitions 5531 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2766 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1008751457.310195 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25700289930.408852 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1968 71.15% 71.15% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 794 28.71% 99.86% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 949979704076 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2762 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 58720807708 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2790205910292 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 117445100 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 949980202104 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2766 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 58706424080 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2790206530920 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 117416330 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48204911 # Number of instructions committed -system.cpu1.committedOps 58981541 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 5132548 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2762 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5579768700 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.436372 # CPI: cycles per instruction -system.cpu1.ipc 0.410446 # IPC: instructions per cycle +system.cpu1.committedInsts 48257451 # Number of instructions committed +system.cpu1.committedOps 59047178 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 5145755 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2766 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5579767080 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.433123 # CPI: cycles per instruction +system.cpu1.ipc 0.410994 # IPC: instructions per cycle system.cpu1.op_class_0::No_OpClass 66 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 40607989 68.85% 68.85% # Class of committed instruction -system.cpu1.op_class_0::IntMult 45709 0.08% 68.93% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 40655660 68.85% 68.85% # Class of committed instruction +system.cpu1.op_class_0::IntMult 45723 0.08% 68.93% # Class of committed instruction system.cpu1.op_class_0::IntDiv 0 0.00% 68.93% # Class of committed instruction system.cpu1.op_class_0::FloatAdd 0 0.00% 68.93% # Class of committed instruction system.cpu1.op_class_0::FloatCmp 0 0.00% 68.93% # Class of committed instruction @@ -1571,715 +1572,721 @@ system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.93% # Cl system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.93% # Class of committed instruction system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.93% # Class of committed instruction system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 3353 0.01% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::MemRead 11146731 18.90% 87.83% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 7175909 12.17% 100.00% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 3341 0.01% 68.94% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.94% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.94% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.94% # Class of committed instruction +system.cpu1.op_class_0::MemRead 11158922 18.90% 87.83% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 7181682 12.16% 100.00% # Class of committed instruction system.cpu1.op_class_0::FloatMemRead 516 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::FloatMemWrite 1268 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 58981541 # Class of committed instruction +system.cpu1.op_class_0::total 59047178 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2762 # number of quiesce instructions executed -system.cpu1.tickCycles 94223774 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 23221326 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 197231 # number of replacements -system.cpu1.dcache.tags.tagsinuse 476.160023 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 17961880 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 197583 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 90.908023 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 91326739500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 476.160023 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.930000 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.930000 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 69 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 36815018 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 36815018 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 10942799 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10942799 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6773317 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6773317 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50710 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50710 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80304 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 80304 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71747 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71747 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 17716116 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 17716116 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 17766826 # number of overall hits -system.cpu1.dcache.overall_hits::total 17766826 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 150509 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 150509 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 145770 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 145770 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30651 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30651 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16960 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16960 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23697 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23697 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 296279 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 296279 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 326930 # number of overall misses -system.cpu1.dcache.overall_misses::total 326930 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2503108000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2503108000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4131089000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4131089000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325863000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 325863000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557327500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 557327500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 612000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 612000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6634197000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6634197000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6634197000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6634197000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11093308 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11093308 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6919087 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6919087 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81361 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 81361 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97264 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 97264 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95444 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95444 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 18012395 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 18012395 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 18093756 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 18093756 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013568 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.013568 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021068 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.021068 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.376728 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.376728 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174371 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174371 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248282 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248282 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.016449 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.016449 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018069 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.018069 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16630.952302 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16630.952302 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28339.774988 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 28339.774988 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19213.620283 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19213.620283 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23518.905347 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23518.905347 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed +system.cpu1.tickCycles 94212752 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 23203578 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 197406 # number of replacements +system.cpu1.dcache.tags.tagsinuse 475.838335 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 17978253 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 197762 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 90.908531 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 91321339500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 475.838335 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.929372 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.929372 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 356 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 284 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.695312 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 36857417 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 36857417 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 10958654 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10958654 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6778912 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6778912 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50538 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50538 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80236 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 80236 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71701 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71701 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 17737566 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 17737566 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 17788104 # number of overall hits +system.cpu1.dcache.overall_hits::total 17788104 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 149954 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 149954 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 146295 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 146295 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30728 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30728 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16950 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16950 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23669 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23669 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 296249 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 296249 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 326977 # number of overall misses +system.cpu1.dcache.overall_misses::total 326977 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2480923500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2480923500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4141245000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4141245000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 326364000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 326364000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557050500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 557050500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 662000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 662000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6622168500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6622168500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6622168500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6622168500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11108608 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11108608 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6925207 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6925207 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81266 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 81266 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97186 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97186 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95370 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95370 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 18033815 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 18033815 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 18115081 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 18115081 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013499 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.013499 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021125 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.021125 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.378116 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.378116 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174408 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174408 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248181 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248181 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.016427 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.016427 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018050 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.018050 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16544.563666 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16544.563666 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28307.495130 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 28307.495130 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19254.513274 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19254.513274 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23535.024716 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23535.024716 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22391.721992 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 22391.721992 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20292.408161 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20292.408161 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22353.386847 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 22353.386847 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20252.704319 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20252.704319 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 197231 # number of writebacks -system.cpu1.dcache.writebacks::total 197231 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 5831 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 5831 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53065 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 53065 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12062 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12062 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 58896 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 58896 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 58896 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 58896 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 144678 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 144678 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92705 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 92705 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29814 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29814 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4898 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4898 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23697 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23697 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 237383 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 237383 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 267197 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 267197 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14423 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14423 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11756 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11756 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26179 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26179 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2254716500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2254716500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2475419500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2475419500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 516532000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 516532000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86654500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86654500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 533644500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 533644500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 598000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 598000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4730136000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4730136000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5246668000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5246668000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2493280000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2493280000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2493280000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2493280000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013042 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013042 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013398 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013398 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.366441 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.366441 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050358 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050358 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248282 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248282 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013179 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.013179 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014767 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.014767 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15584.377030 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15584.377030 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26702.114233 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26702.114233 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17325.149259 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17325.149259 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17691.812985 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17691.812985 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22519.496139 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22519.496139 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 197406 # number of writebacks +system.cpu1.dcache.writebacks::total 197406 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 5638 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 5638 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53221 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 53221 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12059 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12059 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 58859 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 58859 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 58859 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 58859 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 144316 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 144316 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 93074 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 93074 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29900 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29900 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4891 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4891 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23669 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23669 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 237390 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 237390 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 267290 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 267290 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14424 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14424 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11757 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11757 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26181 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26181 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2239010000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2239010000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2480218000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2480218000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 521766000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 521766000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86789500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86789500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 533397500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 533397500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 646000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 646000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4719228000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4719228000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5240994000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5240994000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2492996500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2492996500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2492996500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2492996500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.012991 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.012991 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013440 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013440 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.367928 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.367928 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050326 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050326 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248181 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248181 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013164 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.013164 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014755 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.014755 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15514.634552 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15514.634552 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26647.807121 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26647.807121 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17450.367893 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17450.367893 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17744.735228 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17744.735228 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22535.700706 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22535.700706 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19926.178370 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19926.178370 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19635.953996 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19635.953996 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172868.335298 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172868.335298 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95239.695939 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95239.695939 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 951926 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.186802 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 38745002 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 952438 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.679815 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 73025806000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.186802 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974974 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974974 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19879.641097 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19879.641097 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19607.894048 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19607.894048 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172836.695785 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172836.695785 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95221.591994 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95221.591994 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 951563 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.187738 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 38753540 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 952075 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.704293 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 73017738000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.187738 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974976 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974976 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 466 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 80347318 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 80347318 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 38745002 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 38745002 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 38745002 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 38745002 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 38745002 # number of overall hits -system.cpu1.icache.overall_hits::total 38745002 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 952438 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 952438 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 952438 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 952438 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 952438 # 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number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 39697440 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 39697440 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023992 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023992 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023992 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023992 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023992 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023992 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9256.581531 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9256.581531 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9256.581531 # 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mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023978 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023978 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023978 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023978 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023978 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8756.166268 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8756.166268 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8756.166268 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98183.035714 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 98183.035714 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98183.035714 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 98183.035714 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 202046 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 202062 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # 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Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 53261 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14759.472479 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1060224 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 67460 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 15.716336 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14396.977583 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 38.648393 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.118214 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 333.751919 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.878722 # 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Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14399.124814 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 38.202581 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.100138 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 322.044945 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.878853 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002332 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.019656 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.900847 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 251 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13906 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 79 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 172 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1305 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7821 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4855 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017029 # 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number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 354728500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 526000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 526000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1277222000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1277222000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 1145765500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 1145765500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1434909495 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1434909495 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 11857500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3693000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1145765500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2712131495 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3873447495 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 11857500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3693000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1145765500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2712131495 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 965321170 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4838768665 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10100500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2377583500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2387684000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10100500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2377583500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2387684000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023144 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.077191 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028810 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.552707 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.552707 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.037198 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.037198 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.420854 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.420854 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023488 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.078896 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.037198 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454998 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119351 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023488 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.078896 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.037198 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454998 # mshr miss rate for overall accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.551761 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.551761 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.037404 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.037404 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.420927 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.420927 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023144 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.077191 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.037404 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454980 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119570 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023144 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.077191 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.037404 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454980 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.140779 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 20529.957204 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14116.607774 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18685.467480 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37862.608886 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37862.608886 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15343.782271 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15343.782271 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14959.003249 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14959.003249 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36706.222761 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36706.222761 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32360.255723 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32360.255723 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 19121.057698 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 19121.057698 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 20529.957204 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14116.607774 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32360.255723 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24652.663722 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26475.848939 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 20529.957204 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14116.607774 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32360.255723 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24652.663722 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37862.608886 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28209.001949 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91379.464286 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164866.601955 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164300.343997 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91379.464286 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90831.238779 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90833.574227 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 2407842 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1213344 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20026 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 118526 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 110630 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 7896 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 52421 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1221670 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11756 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11756 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 155519 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 1031415 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 35412 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 31701 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 73485 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42116 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86132 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 18 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 69767 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 67286 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 952438 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295145 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 55 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2857026 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 915642 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8405 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62913 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3843986 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121886464 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30908928 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14348 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 119380 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 152929120 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 368607 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 5126040 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1602092 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.097939 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.313375 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.140992 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16420.802534 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36722.378742 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36722.378742 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15370.915685 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15370.915685 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14987.683792 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14987.683792 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 526000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 526000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36731.335557 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36731.335557 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32174.482604 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 19032.901739 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 19032.901739 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24619.259597 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26400.089251 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24619.259597 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36722.378742 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27968.467730 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90183.035714 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164835.239878 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164260.044029 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90183.035714 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90813.318819 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90810.634009 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 2407036 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1212847 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20197 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 118681 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 110741 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 7940 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 51870 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1220498 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11757 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11757 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 156434 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 1031137 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 35507 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 31472 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 73789 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42123 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86153 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 70267 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 67627 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 952075 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295896 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 106 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2855937 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 915985 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8156 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62049 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3842127 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121840000 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30925576 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13784 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 117700 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 152897060 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 370911 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 5180924 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1603484 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.097889 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.313386 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1453081 90.70% 90.70% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 141115 8.81% 99.51% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 7896 0.49% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1454460 90.71% 90.71% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 141084 8.80% 99.50% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 7940 0.50% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1602092 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2385821492 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1603484 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2385111494 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79306117 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79363429 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1428899351 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1428355849 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 412338887 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 412276680 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4820495 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4711996 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 33080974 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 32634978 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31015 # Transaction distribution system.iobus.trans_dist::ReadResp 31015 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution @@ -2330,58 +2337,58 @@ system.iobus.pkt_size_system.bridge.master::total 162796 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48391001 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 48355001 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 111500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 334500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 333000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 92500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 622500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 611500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 20000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 47000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6378000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6349500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38950500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38550000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187782564 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187836280 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36461 # number of replacements -system.iocache.tags.tagsinuse 14.472132 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.472129 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 272036828000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.472132 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 272035829000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.472129 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.904508 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.904508 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -2389,7 +2396,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328311 # Number of tag accesses system.iocache.tags.data_accesses 328311 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2398,14 +2405,14 @@ system.iocache.demand_misses::realview.ide 36479 # system.iocache.demand_misses::total 36479 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36479 # number of overall misses system.iocache.overall_misses::total 36479 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 33219876 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 33219876 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4376166688 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4376166688 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4409386564 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4409386564 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4409386564 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4409386564 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 33894626 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 33894626 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4361652654 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4361652654 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4395547280 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4395547280 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4395547280 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4395547280 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2422,19 +2429,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 130274.023529 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 130274.023529 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120808.488516 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120808.488516 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120874.655665 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120874.655665 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120874.655665 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120874.655665 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 3 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 132920.101961 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 132920.101961 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120407.813991 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120407.813991 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120495.278928 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120495.278928 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120495.278928 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120495.278928 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.600000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks @@ -2446,14 +2453,14 @@ system.iocache.demand_mshr_misses::realview.ide 36479 system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 20469876 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 20469876 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2562591001 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2562591001 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2583060877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2583060877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2583060877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2583060877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 21144626 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 21144626 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2548533560 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2548533560 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2569678186 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2569678186 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2569678186 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2569678186 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2462,591 +2469,587 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80274.023529 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 80274.023529 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70742.905284 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70742.905284 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70809.530881 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70809.530881 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70809.530881 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70809.530881 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 145308 # number of replacements -system.l2c.tags.tagsinuse 65153.014694 # Cycle average of tags in use -system.l2c.tags.total_refs 608197 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 210799 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.885199 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 94570968000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 6725.818981 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 88.835717 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.039308 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8741.022578 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6775.934473 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34864.204134 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 12.618119 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2235.319135 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3466.513349 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2242.708901 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.102628 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001356 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.133377 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.103393 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.531986 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000193 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.034108 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.052895 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034221 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994156 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31590 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 60 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 33841 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 126 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4772 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 26692 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 58 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1899 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 31836 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.482025 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000916 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.516373 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6845829 # Number of tag accesses -system.l2c.tags.data_accesses 6845829 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 269041 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 269041 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 43018 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5569 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 48587 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2756 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2348 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 5104 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4245 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1488 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5733 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 501 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 88 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 68822 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 63059 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47426 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 132 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 22 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 31931 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 13672 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5861 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 231514 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 501 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 88 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 68822 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 67304 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 47426 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 132 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 22 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 31931 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 15160 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5861 # number of demand (read+write) hits -system.l2c.demand_hits::total 237247 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 501 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 88 # number of overall hits -system.l2c.overall_hits::cpu0.inst 68822 # number of overall hits -system.l2c.overall_hits::cpu0.data 67304 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 47426 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 132 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 22 # number of overall hits -system.l2c.overall_hits::cpu1.inst 31931 # number of overall hits -system.l2c.overall_hits::cpu1.data 15160 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5861 # number of overall hits -system.l2c.overall_hits::total 237247 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 567 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 233 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 800 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 71 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 57 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 128 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11330 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8671 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 20001 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 149 # number of ReadSharedReq misses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 82920.101961 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 82920.101961 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70354.835468 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70354.835468 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70442.670742 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70442.670742 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70442.670742 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70442.670742 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 144965 # number of replacements +system.l2c.tags.tagsinuse 65152.937424 # Cycle average of tags in use +system.l2c.tags.total_refs 609190 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 210433 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.894936 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 94596333000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 6623.641464 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 83.873340 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030778 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8717.297780 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6753.906827 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34978.887881 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.032858 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2236.963584 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3439.697056 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2304.605856 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.101069 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001280 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.133015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.103056 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.533735 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000214 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.034133 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.052486 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.035165 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994155 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 31624 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 33792 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 150 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4711 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 26763 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 52 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 93 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1870 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 31828 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.482544 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.515625 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6850011 # Number of tag accesses +system.l2c.tags.data_accesses 6850011 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 269158 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 269158 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 42928 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 5622 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 48550 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2743 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 2305 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 5048 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4279 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1522 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5801 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 596 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 96 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 68829 # 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number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 19 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 3492 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1704 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6343 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 177568 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 147 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 22928 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 21339 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 132762 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3498 # 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number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 147 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 22928 # number of overall misses -system.l2c.overall_misses::cpu0.data 21339 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 132762 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3498 # number of overall misses -system.l2c.overall_misses::cpu1.data 10400 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 6519 # number of overall misses -system.l2c.overall_misses::total 197612 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 7996500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 709500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 8706000 # 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average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21982.532751 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22086.097946 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26283.018868 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24371.951220 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25449.468085 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128231.592920 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 86156.358582 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 110007.574997 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 135547.619048 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 91370.054526 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 109547.806974 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110307.425762 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 237906.250000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100532.198054 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 151834.587045 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124331.046173 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108593.359665 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 152187.919463 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 110524.278677 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 149876.760563 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 107807.640087 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 135547.619048 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 91370.054526 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 120250.527204 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110307.425762 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 237906.250000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100532.198054 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96418.509808 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124331.046173 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 108784.734956 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 152187.919463 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 119941.732951 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96659.315148 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 108029.684262 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 135547.619048 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 91370.054526 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 120250.527204 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110307.425762 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 237906.250000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100532.198054 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96418.509808 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124331.046173 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 108784.734956 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 119941.732951 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96659.315148 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 108029.684262 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197862.516402 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70379.464286 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146895.873786 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167414.851769 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197863.927895 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69183.035714 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146864.503155 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167402.972051 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102176.249153 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70379.464286 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80922.925581 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 92583.220481 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 519453 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 291586 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 583 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102186.582520 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69183.035714 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80905.072962 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92580.706733 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 519148 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 291431 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 639 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 38386 # Transaction distribution -system.membus.trans_dist::ReadResp 216245 # Transaction distribution -system.membus.trans_dist::WriteReq 31026 # Transaction distribution -system.membus.trans_dist::WriteResp 31026 # Transaction distribution -system.membus.trans_dist::WritebackDirty 141787 # Transaction distribution -system.membus.trans_dist::CleanEvict 20009 # Transaction distribution -system.membus.trans_dist::UpgradeReq 64008 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 38952 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 38391 # Transaction distribution +system.membus.trans_dist::ReadResp 216211 # Transaction distribution +system.membus.trans_dist::WriteReq 31027 # Transaction distribution +system.membus.trans_dist::WriteResp 31027 # Transaction distribution +system.membus.trans_dist::WritebackDirty 141592 # Transaction distribution +system.membus.trans_dist::CleanEvict 19995 # Transaction distribution +system.membus.trans_dist::UpgradeReq 63966 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38983 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 40468 # Transaction distribution -system.membus.trans_dist::ReadExResp 19978 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 177859 # Transaction distribution +system.membus.trans_dist::ReadExReq 40431 # Transaction distribution +system.membus.trans_dist::ReadExResp 19912 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 177820 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 4302 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14184 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 782434 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14192 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 659894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 782044 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72955 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72955 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 855389 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 854999 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28368 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19616228 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19808736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19597036 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19789560 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22126880 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123082 # Total snoops (count) +system.membus.pkt_size::total 22107704 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 127509 # Total snoops (count) system.membus.snoopTraffic 37120 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 426925 # Request fanout histogram -system.membus.snoop_fanout::mean 0.011573 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.106956 # Request fanout histogram +system.membus.snoop_fanout::samples 426843 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011580 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.106987 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 421984 98.84% 98.84% # Request fanout histogram -system.membus.snoop_fanout::1 4941 1.16% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 421900 98.84% 98.84% # Request fanout histogram +system.membus.snoop_fanout::1 4943 1.16% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 426925 # Request fanout histogram -system.membus.reqLayer0.occupancy 95052999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 426843 # Request fanout histogram +system.membus.reqLayer0.occupancy 94581999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12480499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12496000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1015492813 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1014639485 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1151697269 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1151195264 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1408128 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 6864902 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3078,77 +3081,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1122951 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 592347 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 209143 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 29689 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 28433 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1256 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 38389 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 568851 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31026 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31026 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 374622 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 155080 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 112572 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 44056 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 156628 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51647 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51647 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 530464 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4356 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1342563 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 408877 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1751440 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 38341228 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7151796 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45493024 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 399228 # Total snoops (count) -system.toL2Bus.snoopTraffic 16183244 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 957878 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.406657 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.493872 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1123711 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 579018 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 224775 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 30515 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 29083 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1432 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 38394 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 569470 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31027 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31027 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 374544 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 155002 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 112494 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 44031 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 156525 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 34 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51717 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51717 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 531080 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4357 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 3099 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1346867 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 408809 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1755676 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 38391932 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7144124 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45536056 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 402215 # Total snoops (count) +system.toL2Bus.snoopTraffic 16179148 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 958128 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.409221 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.494721 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 569606 59.47% 59.47% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 387016 40.40% 99.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1256 0.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 567474 59.23% 59.23% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 389222 40.62% 99.85% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1432 0.15% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 957878 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 953761642 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 958128 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 954442443 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 360622 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1977326 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 722683237 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 723838248 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 286574903 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 286417681 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |