diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | 5091 |
1 files changed, 2553 insertions, 2538 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 43f49bfd8..14253ba3e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,161 +1,161 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.647778 # Number of seconds simulated -sim_ticks 2647778082500 # Number of ticks simulated -final_tick 2647778082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.848172 # Number of seconds simulated +sim_ticks 2848172284000 # Number of ticks simulated +final_tick 2848172284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109262 # Simulator instruction rate (inst/s) -host_op_rate 132319 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2267003011 # Simulator tick rate (ticks/s) -host_mem_usage 618500 # Number of bytes of host memory used -host_seconds 1167.96 # Real time elapsed on the host -sim_insts 127613917 # Number of instructions simulated -sim_ops 154544077 # Number of ops (including micro ops) simulated +host_inst_rate 135409 # Simulator instruction rate (inst/s) +host_op_rate 163982 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3007675070 # Simulator tick rate (ticks/s) +host_mem_usage 625764 # Number of bytes of host memory used +host_seconds 946.97 # Real time elapsed on the host +sim_insts 128228197 # Number of instructions simulated +sim_ops 155285827 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 8192 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 8960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1505216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1244784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8319232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 374976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 749140 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 607232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1677760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1343340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8401088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 221184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 660436 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 438272 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12811716 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1505216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 374976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1880192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9040448 # Number of bytes written to this memory +system.physmem.bytes_read::total 12753472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1677760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 221184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1898944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9008896 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 9058012 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 128 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 9026460 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 140 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 23519 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 19972 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 129988 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 30 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11726 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 9488 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21511 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 131267 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10340 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6848 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 200726 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 141257 # Number of write requests responded to by this memory +system.physmem.num_reads::total 199815 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 140764 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 145648 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 568483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 470124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3141967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 141619 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 282932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 229336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4838667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 568483 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 141619 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 710102 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3414353 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6618 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3420986 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3414353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 568483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 476742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3141967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 141619 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 282947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 229336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 8259653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 200726 # Number of read requests accepted -system.physmem.writeReqs 145648 # Number of write requests accepted -system.physmem.readBursts 200726 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 145648 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12837568 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue -system.physmem.bytesWritten 9070080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12811716 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9058012 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_writes::total 145155 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 589065 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 471650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2949642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 77658 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 231881 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 153878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4477774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 589065 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 77658 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 666724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3163045 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6153 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3169211 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3163045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 589065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 477803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2949642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 77658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 231895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 153878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7646985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 199815 # Number of read requests accepted +system.physmem.writeReqs 145155 # Number of write requests accepted +system.physmem.readBursts 199815 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 145155 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12777984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue +system.physmem.bytesWritten 9038976 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12753472 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9026460 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12684 # Per bank write bursts -system.physmem.perBankRdBursts::1 12558 # Per bank write bursts -system.physmem.perBankRdBursts::2 12677 # Per bank write bursts -system.physmem.perBankRdBursts::3 12470 # Per bank write bursts -system.physmem.perBankRdBursts::4 15173 # Per bank write bursts -system.physmem.perBankRdBursts::5 12439 # Per bank write bursts -system.physmem.perBankRdBursts::6 12705 # Per bank write bursts -system.physmem.perBankRdBursts::7 12895 # Per bank write bursts -system.physmem.perBankRdBursts::8 12483 # Per bank write bursts -system.physmem.perBankRdBursts::9 12862 # Per bank write bursts -system.physmem.perBankRdBursts::10 12103 # Per bank write bursts -system.physmem.perBankRdBursts::11 11319 # Per bank write bursts -system.physmem.perBankRdBursts::12 11938 # Per bank write bursts -system.physmem.perBankRdBursts::13 12281 # Per bank write bursts -system.physmem.perBankRdBursts::14 12069 # Per bank write bursts -system.physmem.perBankRdBursts::15 11931 # Per bank write bursts -system.physmem.perBankWrBursts::0 9144 # Per bank write bursts -system.physmem.perBankWrBursts::1 9177 # Per bank write bursts -system.physmem.perBankWrBursts::2 9224 # Per bank write bursts -system.physmem.perBankWrBursts::3 8920 # Per bank write bursts -system.physmem.perBankWrBursts::4 8442 # Per bank write bursts -system.physmem.perBankWrBursts::5 8744 # Per bank write bursts -system.physmem.perBankWrBursts::6 9263 # Per bank write bursts -system.physmem.perBankWrBursts::7 9163 # Per bank write bursts -system.physmem.perBankWrBursts::8 8908 # Per bank write bursts -system.physmem.perBankWrBursts::9 9183 # Per bank write bursts -system.physmem.perBankWrBursts::10 8711 # Per bank write bursts -system.physmem.perBankWrBursts::11 8187 # Per bank write bursts -system.physmem.perBankWrBursts::12 8717 # Per bank write bursts -system.physmem.perBankWrBursts::13 8673 # Per bank write bursts -system.physmem.perBankWrBursts::14 8851 # Per bank write bursts -system.physmem.perBankWrBursts::15 8413 # Per bank write bursts +system.physmem.perBankRdBursts::0 12196 # Per bank write bursts +system.physmem.perBankRdBursts::1 12508 # Per bank write bursts +system.physmem.perBankRdBursts::2 12943 # Per bank write bursts +system.physmem.perBankRdBursts::3 12617 # Per bank write bursts +system.physmem.perBankRdBursts::4 14662 # Per bank write bursts +system.physmem.perBankRdBursts::5 11885 # Per bank write bursts +system.physmem.perBankRdBursts::6 12499 # Per bank write bursts +system.physmem.perBankRdBursts::7 12704 # Per bank write bursts +system.physmem.perBankRdBursts::8 12537 # Per bank write bursts +system.physmem.perBankRdBursts::9 12319 # Per bank write bursts +system.physmem.perBankRdBursts::10 11826 # Per bank write bursts +system.physmem.perBankRdBursts::11 10998 # Per bank write bursts +system.physmem.perBankRdBursts::12 12485 # Per bank write bursts +system.physmem.perBankRdBursts::13 13119 # Per bank write bursts +system.physmem.perBankRdBursts::14 12369 # Per bank write bursts +system.physmem.perBankRdBursts::15 11989 # Per bank write bursts +system.physmem.perBankWrBursts::0 8816 # Per bank write bursts +system.physmem.perBankWrBursts::1 9166 # Per bank write bursts +system.physmem.perBankWrBursts::2 9495 # Per bank write bursts +system.physmem.perBankWrBursts::3 9136 # Per bank write bursts +system.physmem.perBankWrBursts::4 8038 # Per bank write bursts +system.physmem.perBankWrBursts::5 8411 # Per bank write bursts +system.physmem.perBankWrBursts::6 8988 # Per bank write bursts +system.physmem.perBankWrBursts::7 8984 # Per bank write bursts +system.physmem.perBankWrBursts::8 9026 # Per bank write bursts +system.physmem.perBankWrBursts::9 8762 # Per bank write bursts +system.physmem.perBankWrBursts::10 8598 # Per bank write bursts +system.physmem.perBankWrBursts::11 8287 # Per bank write bursts +system.physmem.perBankWrBursts::12 9114 # Per bank write bursts +system.physmem.perBankWrBursts::13 9118 # Per bank write bursts +system.physmem.perBankWrBursts::14 8888 # Per bank write bursts +system.physmem.perBankWrBursts::15 8407 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 30 # Number of times write queue was full causing retry -system.physmem.totGap 2647777471000 # Total gap between requests +system.physmem.numWrRetry 34 # Number of times write queue was full causing retry +system.physmem.totGap 2848171745000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 553 # Read request sizes (log2) +system.physmem.readPktSize::2 552 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 200145 # Read request sizes (log2) +system.physmem.readPktSize::6 199235 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 141257 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 87468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7877 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 140764 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 87471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3767 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -185,165 +185,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 90 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 94963 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 230.695997 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 131.239554 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 294.689609 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 52509 55.29% 55.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18085 19.04% 74.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6234 6.56% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3686 3.88% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2895 3.05% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1483 1.56% 89.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 908 0.96% 90.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1023 1.08% 91.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8140 8.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 94963 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7063 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.398839 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 555.406402 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7061 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 88 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 88570 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 246.323767 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 141.050118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 301.878369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 44937 50.74% 50.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18529 20.92% 71.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6585 7.43% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3856 4.35% 83.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3004 3.39% 86.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1517 1.71% 88.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 921 1.04% 89.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1037 1.17% 90.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8184 9.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88570 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7038 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.368144 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 555.266808 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7037 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7063 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7063 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.065128 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.613340 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.212436 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5945 84.17% 84.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 392 5.55% 89.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 71 1.01% 90.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 48 0.68% 91.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 279 3.95% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 27 0.38% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 19 0.27% 96.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 25 0.35% 96.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 16 0.23% 96.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 12 0.17% 96.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.04% 96.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.10% 96.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 160 2.27% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.08% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.07% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 7 0.10% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 4 0.06% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.04% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.01% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.11% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.01% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7038 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7038 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.067349 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.571017 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.392738 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5944 84.46% 84.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 388 5.51% 89.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 60 0.85% 90.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 46 0.65% 91.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 266 3.78% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.30% 95.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 22 0.31% 95.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 25 0.36% 96.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 15 0.21% 96.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 13 0.18% 96.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 13 0.18% 96.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 149 2.12% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.07% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.10% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 11 0.16% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.09% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.06% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 7 0.10% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 9 0.13% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.11% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 4 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7063 # Writes before turning the bus around for reads -system.physmem.totQLat 5391615341 # Total ticks spent queuing -system.physmem.totMemAccLat 9152621591 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1002935000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26879.19 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::176-179 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7038 # Writes before turning the bus around for reads +system.physmem.totQLat 5532611303 # Total ticks spent queuing +system.physmem.totMemAccLat 9276161303 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 998280000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27710.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45629.19 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.85 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.43 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.42 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46460.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.48 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.36 # Average write queue length when enqueuing -system.physmem.readRowHits 166580 # Number of row buffer hits during reads -system.physmem.writeRowHits 80763 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 56.97 # Row buffer hit rate for writes -system.physmem.avgGap 7644273.16 # Average gap between requests -system.physmem.pageHitRate 72.25 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 370341720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 202071375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 808080000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 467058960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 172939896480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 79567681680 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1518869897250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1773225027465 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.703351 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2526645938707 # Time in different power states -system.physmem_0.memoryStateTime::REF 88415080000 # Time in different power states +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.18 # Average write queue length when enqueuing +system.physmem.readRowHits 165300 # Number of row buffer hits during reads +system.physmem.writeRowHits 87019 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.79 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.60 # Row buffer hit rate for writes +system.physmem.avgGap 8256288.21 # Average gap between requests +system.physmem.pageHitRate 74.01 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 339738840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 185373375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 795709200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 460300320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186028705200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83305465515 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1635827969250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1906943261700 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.532441 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2721218544299 # Time in different power states +system.physmem_0.memoryStateTime::REF 95106700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32716967293 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31846334451 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 347578560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 189651000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 756490800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 451286640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 172939896480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 78874475895 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1519477980750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1773037360125 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.632470 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2527659145749 # Time in different power states -system.physmem_1.memoryStateTime::REF 88415080000 # Time in different power states +system.physmem_1.actEnergy 329850360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179977875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 761599800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 454896000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186028705200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82993384530 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1636101724500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1906850138265 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.499746 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2721674822130 # Time in different power states +system.physmem_1.memoryStateTime::REF 95106700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31702650501 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31390664370 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory @@ -353,39 +350,39 @@ system.realview.nvmem.bytes_inst_read::total 1344 system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 193 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 314 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 508 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 193 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 314 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 508 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 193 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 314 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 508 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 34732065 # Number of BP lookups -system.cpu0.branchPred.condPredicted 16497595 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1496295 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 19609177 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 10269070 # Number of BTB hits +system.cpu0.branchPred.lookups 20844041 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13655604 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1017556 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13118749 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 8767800 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 52.368695 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 11117365 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 739154 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4170441 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 3984607 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 185834 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 94839 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 66.834117 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3422259 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 208349 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 764708 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 581484 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 183224 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 100888 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -415,61 +412,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 65243 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 65243 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44492 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20751 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 65243 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 65243 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 65243 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6699 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12206.821914 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11332.778692 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5808.192470 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6323 94.39% 94.39% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 330 4.93% 99.31% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 32 0.48% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 7 0.10% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6699 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 67283 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 67283 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46446 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20837 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 67283 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 67283 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 67283 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6844 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12453.243717 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11569.675575 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5895.982503 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6363 92.97% 92.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 412 6.02% 98.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 59 0.86% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 3 0.04% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.07% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6844 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 338010000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 338010000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 338010000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5176 77.27% 77.27% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1523 22.73% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6699 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65243 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5263 76.90% 76.90% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1581 23.10% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6844 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67283 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65243 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6699 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67283 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6844 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6699 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 71942 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6844 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 74127 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 23418517 # DTB read hits -system.cpu0.dtb.read_misses 59363 # DTB read misses -system.cpu0.dtb.write_hits 17357852 # DTB write hits -system.cpu0.dtb.write_misses 5880 # DTB write misses +system.cpu0.dtb.read_hits 17352300 # DTB read hits +system.cpu0.dtb.read_misses 60872 # DTB read misses +system.cpu0.dtb.write_hits 14551648 # DTB write hits +system.cpu0.dtb.write_misses 6411 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1178 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1722 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3450 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1427 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1946 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 516 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 23477880 # DTB read accesses -system.cpu0.dtb.write_accesses 17363732 # DTB write accesses +system.cpu0.dtb.perms_faults 519 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17413172 # DTB read accesses +system.cpu0.dtb.write_accesses 14558059 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 40776369 # DTB hits -system.cpu0.dtb.misses 65243 # DTB misses -system.cpu0.dtb.accesses 40841612 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 31903948 # DTB hits +system.cpu0.dtb.misses 67283 # DTB misses +system.cpu0.dtb.accesses 31971231 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -499,41 +496,42 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 4001 # Table walker walks requested -system.cpu0.itb.walker.walksShort 4001 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 3992 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3992 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3695 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 4001 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 4001 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 4001 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2427 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12648.125258 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11968.911523 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 4734.087286 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 373 15.37% 15.37% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1885 77.67% 93.04% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 118 4.86% 97.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 27 1.11% 99.01% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 22 0.91% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3686 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3992 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3992 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3992 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2438 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12900.533224 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 12073.120538 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5370.959057 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 392 16.08% 16.08% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1803 73.95% 90.03% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 168 6.89% 96.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 38 1.56% 98.48% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 34 1.39% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2427 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2438 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 337545500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 337545500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 337545500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2126 87.60% 87.60% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 301 12.40% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2427 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2137 87.65% 87.65% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 301 12.35% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2438 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4001 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4001 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3992 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3992 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2427 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2427 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6428 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 68314752 # ITB inst hits -system.cpu0.itb.inst_misses 4001 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2438 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2438 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6430 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 38811638 # ITB inst hits +system.cpu0.itb.inst_misses 3992 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -542,795 +540,802 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2164 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2175 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7135 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7061 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 68318753 # ITB inst accesses -system.cpu0.itb.hits 68314752 # DTB hits -system.cpu0.itb.misses 4001 # DTB misses -system.cpu0.itb.accesses 68318753 # DTB accesses -system.cpu0.numPwrStateTransitions 4126 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 2063 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1227700157.144935 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 21500702795.368797 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1198 58.07% 58.07% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 860 41.69% 99.76% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.81% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.05% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 3 0.15% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 38815630 # ITB inst accesses +system.cpu0.itb.hits 38811638 # DTB hits +system.cpu0.itb.misses 3992 # DTB misses +system.cpu0.itb.accesses 38815630 # DTB accesses +system.cpu0.numPwrStateTransitions 3698 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1849 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1494392801.532720 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23960009045.887756 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1074 58.09% 58.09% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 768 41.54% 99.62% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.68% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.05% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499984309000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 2063 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 115032658310 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2532745424190 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 230068064 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499963441540 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1849 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 85039993966 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2763132290034 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 170082548 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 106706103 # Number of instructions committed -system.cpu0.committedOps 129024022 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 8506641 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 2063 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5065528558 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.156091 # CPI: cycles per instruction -system.cpu0.ipc 0.463802 # IPC: instructions per cycle -system.cpu0.op_class_0::No_OpClass 2272 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 87919988 68.14% 68.14% # Class of committed instruction -system.cpu0.op_class_0::IntMult 105727 0.08% 68.23% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 7151 0.01% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::MemRead 22900542 17.75% 85.98% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 18088342 14.02% 100.00% # Class of committed instruction +system.cpu0.committedInsts 79775908 # Number of instructions committed +system.cpu0.committedOps 96002231 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 5290576 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1849 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5526291371 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.132004 # CPI: cycles per instruction +system.cpu0.ipc 0.469042 # IPC: instructions per cycle +system.cpu0.op_class_0::No_OpClass 2273 0.00% 0.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 63778191 66.43% 66.44% # Class of committed instruction +system.cpu0.op_class_0::IntMult 92152 0.10% 66.53% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 8115 0.01% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::MemRead 16825163 17.53% 84.07% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 15296337 15.93% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 129024022 # Class of committed instruction +system.cpu0.op_class_0::total 96002231 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 2063 # number of quiesce instructions executed -system.cpu0.tickCycles 178511666 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 51556398 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 681177 # number of replacements -system.cpu0.dcache.tags.tagsinuse 487.337065 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 39381714 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 681689 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 57.770793 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1849 # number of quiesce instructions executed +system.cpu0.tickCycles 121004168 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 49078380 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 716277 # number of replacements +system.cpu0.dcache.tags.tagsinuse 496.364938 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 30460734 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 716789 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 42.496096 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 356009000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 487.337065 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.951830 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.951830 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.364938 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.969463 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.969463 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 81578447 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 81578447 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 21978387 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 21978387 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 16273218 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16273218 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 306177 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 306177 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 357355 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 357355 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352292 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 352292 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 38251605 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 38251605 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 38557782 # number of overall hits -system.cpu0.dcache.overall_hits::total 38557782 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 418335 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 418335 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 561531 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 561531 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131453 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 131453 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20802 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20802 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21460 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 21460 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 979866 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 979866 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1111319 # number of overall misses -system.cpu0.dcache.overall_misses::total 1111319 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5562272000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5562272000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10028849500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10028849500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 328076000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 328076000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 523772000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 523772000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 516000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 516000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 15591121500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 15591121500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 15591121500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 15591121500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 22396722 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 22396722 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16834749 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16834749 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 437630 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 437630 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378157 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 378157 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 373752 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 373752 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 39231471 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 39231471 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 39669101 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 39669101 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.018678 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.018678 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033355 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.033355 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300375 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300375 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055009 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055009 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.057418 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.057418 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024977 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.024977 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028015 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.028015 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13296.214756 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13296.214756 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17859.832316 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17859.832316 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15771.368138 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15771.368138 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24406.896552 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24406.896552 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63863131 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63863131 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 15863909 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15863909 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 13436402 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 13436402 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320993 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 320993 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365530 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365530 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361278 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361278 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 29300311 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 29300311 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 29621304 # number of overall hits +system.cpu0.dcache.overall_hits::total 29621304 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 439369 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 439369 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 580672 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 580672 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 135956 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 135956 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21086 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21086 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20448 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20448 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1020041 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1020041 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1155997 # number of overall misses +system.cpu0.dcache.overall_misses::total 1155997 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6148409000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6148409000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10121621500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10121621500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 324178500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 324178500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 483049500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 483049500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 688000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 688000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 16270030500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 16270030500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 16270030500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 16270030500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16303278 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16303278 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 14017074 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 14017074 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456949 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 456949 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386616 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386616 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381726 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381726 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30320352 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30320352 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30777301 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30777301 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026950 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.026950 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041426 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.041426 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.297530 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.297530 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054540 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054540 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053567 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053567 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033642 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.033642 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037560 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.037560 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13993.725092 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13993.725092 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17430.875778 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17430.875778 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15374.110784 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15374.110784 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23623.312793 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23623.312793 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15911.483305 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15911.483305 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14029.384452 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14029.384452 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15950.369152 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15950.369152 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14074.457373 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14074.457373 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 681177 # number of writebacks -system.cpu0.dcache.writebacks::total 681177 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44450 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 44450 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 246335 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 246335 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14695 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14695 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 290785 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 290785 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 290785 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 290785 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 373885 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 373885 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 315196 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 315196 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98829 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 98829 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6107 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6107 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21460 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 21460 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 689081 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 689081 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 787910 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 787910 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29629 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29629 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26357 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26357 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 55986 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 55986 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4452451000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4452451000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5571993500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5571993500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1619437000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1619437000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94023500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94023500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 502325000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 502325000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 503000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 503000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10024444500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10024444500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11643881500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11643881500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6101487500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6101487500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6101487500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6101487500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016694 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016694 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018723 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018723 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225828 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225828 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016149 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016149 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.057418 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.057418 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017564 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.017564 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019862 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.019862 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11908.610937 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11908.610937 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17677.868691 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17677.868691 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16386.253023 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16386.253023 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15396.020960 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15396.020960 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23407.502330 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23407.502330 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 716277 # number of writebacks +system.cpu0.dcache.writebacks::total 716277 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44943 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 44943 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255413 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 255413 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14625 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14625 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 300356 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 300356 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 300356 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 300356 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 394426 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 394426 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325259 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 325259 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102388 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 102388 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6461 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6461 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20448 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20448 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 719685 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 719685 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 822073 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 822073 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20384 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20384 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19085 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19085 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39469 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39469 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5005155000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5005155000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5561809000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5561809000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1663563000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1663563000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98784500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98784500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 462621500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 462621500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 668000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 668000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10566964000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10566964000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12230527000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12230527000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4556252000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4556252000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4556252000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4556252000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024193 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024193 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023204 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023204 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224069 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224069 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016712 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016712 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053567 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053567 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023736 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023736 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026710 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026710 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12689.718731 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12689.718731 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17099.631371 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17099.631371 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16247.636442 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16247.636442 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15289.351494 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15289.351494 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22624.290884 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22624.290884 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14547.556093 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14547.556093 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14778.187230 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14778.187230 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 205929.579129 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205929.579129 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 108982.379523 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 108982.379523 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1887196 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.757846 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 66419655 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1887708 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.185344 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6638125000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.757846 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999527 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999527 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14682.762598 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14682.762598 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14877.665365 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14877.665365 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223520.996860 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223520.996860 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115438.749398 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115438.749398 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1970602 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.774874 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36833218 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1971114 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.686498 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6638665000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774874 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999560 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999560 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 138502472 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 138502472 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 66419655 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 66419655 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 66419655 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 66419655 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 66419655 # number of overall hits -system.cpu0.icache.overall_hits::total 66419655 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1887721 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1887721 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1887721 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1887721 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1887721 # 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average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9448.674354 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9448.674354 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9448.674354 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 79579816 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 79579816 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 36833218 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36833218 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36833218 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36833218 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36833218 # number of overall hits +system.cpu0.icache.overall_hits::total 36833218 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1971127 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1971127 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1971127 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1971127 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1971127 # number of overall misses +system.cpu0.icache.overall_misses::total 1971127 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 19380486500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 19380486500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 19380486500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 19380486500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 19380486500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 19380486500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 38804345 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 38804345 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 38804345 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 38804345 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 38804345 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 38804345 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050797 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050797 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050797 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050797 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050797 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050797 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9832.185597 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9832.185597 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9832.185597 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9832.185597 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9832.185597 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9832.185597 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1887196 # number of writebacks -system.cpu0.icache.writebacks::total 1887196 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1887721 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1887721 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1887721 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1887721 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1887721 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1887721 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1970602 # number of writebacks +system.cpu0.icache.writebacks::total 1970602 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1971127 # 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number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16892601000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 16892601000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16892601000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 16892601000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 18394923500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 18394923500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 18394923500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 18394923500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 18394923500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 18394923500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 319413000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 319413000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 319413000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 319413000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027636 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027636 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027636 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.027636 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027636 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.027636 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8948.674619 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8948.674619 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8948.674619 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8948.674619 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8948.674619 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8948.674619 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050797 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050797 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050797 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.050797 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050797 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.050797 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9332.185851 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9332.185851 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9332.185851 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9332.185851 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9332.185851 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9332.185851 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92637.180974 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92637.180974 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92637.180974 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92637.180974 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1767222 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1767306 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 74 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1842994 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1843099 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 91 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 225214 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 281957 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16020.304669 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 4495555 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 298080 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 15.081706 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 234669 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 289615 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15618.929391 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2598682 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 305234 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 8.513737 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15153.098614 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.898882 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.073768 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 805.233405 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.924872 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003778 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.049148 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.977802 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1000 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15110 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 18 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 315 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 390 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 277 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14506.516440 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 65.609020 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.093662 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1046.710270 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.885407 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004004 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063886 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.953304 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 240 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15363 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 27 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 131 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 75 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 335 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4038 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7911 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2755 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061035 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922241 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 85783129 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 85783129 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77844 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5474 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 83318 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 465182 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 465182 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 2062277 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 2062277 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 213330 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 213330 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1827339 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1827339 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 378100 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 378100 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77844 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5474 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1827339 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 591430 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 2502087 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77844 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5474 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1827339 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 591430 # number of overall hits -system.cpu0.l2cache.overall_hits::total 2502087 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 760 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 121 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 881 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 57605 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 57605 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 21456 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 21456 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44266 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 44266 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 60382 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 60382 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 100716 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 100716 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 760 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 121 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 60382 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 144982 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 206245 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 760 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 121 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 60382 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 144982 # number of overall misses -system.cpu0.l2cache.overall_misses::total 206245 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 27717500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2799500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 30517000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 116554500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 116554500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 30031000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 30031000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 482498 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 482498 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2238448000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2238448000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2969526500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2969526500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2950737493 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2950737493 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 27717500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2799500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2969526500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 5189185493 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 8189228993 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 27717500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2799500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2969526500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 5189185493 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 8189228993 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78604 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5595 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 84199 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 465182 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 465182 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 2062277 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 2062277 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 57605 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 57605 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21456 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 21456 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 257596 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 257596 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1887721 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1887721 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 478816 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 478816 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78604 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5595 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1887721 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 736412 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 2708332 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78604 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5595 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1887721 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 736412 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 2708332 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009669 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.021626 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.010463 # miss rate for ReadReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 299 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1118 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7270 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5493 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1183 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.014648 # 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mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192817 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.163902 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163902 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.046599 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.046599 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.226148 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.226148 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.011434 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.032736 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.046599 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.204489 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.088642 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.011434 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.032736 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.046599 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.204489 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.166430 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28639.046538 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56558.077101 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56558.077101 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19461.965107 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19461.965107 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15860.109060 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15860.109060 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 101124.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 101124.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40772.358309 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40772.358309 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43199.340284 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43199.340284 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23209.032047 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23209.032047 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43199.340284 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28359.545844 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32766.548688 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43199.340284 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28359.545844 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56558.077101 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45832.549870 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.181851 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29462.621885 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17290.055249 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27466.938406 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54426.267559 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 54426.267559 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17296.446835 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17296.446835 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15079.795510 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15079.795510 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 515999 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 515999 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39199.922757 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39199.922757 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38321.366749 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38321.366749 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24124.678165 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24124.678165 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29462.621885 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17290.055249 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38321.366749 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28328.993195 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31984.995219 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29462.621885 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17290.055249 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38321.366749 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28328.993195 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54426.267559 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43487.383325 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197926.474063 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 186117.014844 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215516.311813 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196580.794730 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 104746.963527 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103580.315981 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 5292246 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2668157 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 40914 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 334901 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 330475 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4426 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 126809 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2542571 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 26357 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26357 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 693110 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 2103191 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 223137 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 294264 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 92982 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43850 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 116200 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 275510 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 272175 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1887721 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 569608 # Transaction distribution +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111304.682156 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109162.185148 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 5528539 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2785631 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 220679 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 216467 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4212 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 119671 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2643248 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19085 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19085 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 716138 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 2204203 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 105351 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 312801 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 88645 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43001 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114336 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 287716 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284337 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1971127 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 603215 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateReq 3113 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5669533 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2525108 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13291 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 164598 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 8372530 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 241815296 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 94996751 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22380 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314416 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 337148843 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1025467 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 18711896 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 3771293 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.106316 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.312026 # Request fanout histogram +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5919751 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2595390 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13207 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 168847 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 8697195 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 252491264 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99508828 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22116 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 322908 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 352345116 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 940127 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 19140516 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3787201 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.076346 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.269706 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3374771 89.49% 89.49% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 392096 10.40% 99.88% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4426 0.12% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3502276 92.48% 92.48% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 280713 7.41% 99.89% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4212 0.11% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3771293 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 5293903990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3787201 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 5519275492 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 114422325 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 116183079 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2837181638 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2962129461 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1188012916 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1227256511 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7701489 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7683988 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 86027432 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 88134970 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 5469499 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3374978 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 316517 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 3346860 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 2136825 # Number of BTB hits +system.cpu1.branchPred.lookups 19426531 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6224342 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 651829 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 10038478 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3634441 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 63.845664 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 972408 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 68961 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 195238 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 132437 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 62801 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 28788 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 36.205100 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8674574 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 447731 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3678807 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 3614078 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 64729 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 23620 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1360,59 +1365,66 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 30404 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 30404 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 23807 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6597 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 30404 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 30404 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 30404 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2736 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12207.419591 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11247.456123 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 8821.385005 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 2714 99.20% 99.20% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 14 0.51% 99.71% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 4 0.15% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 3 0.11% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2736 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1954228032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1954228032 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1954228032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 2033 74.31% 74.31% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 703 25.69% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2736 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30404 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 27735 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 27735 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 21301 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6434 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 27735 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 27735 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 27735 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2744 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12429.118076 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11482.413236 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6276.586572 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 644 23.47% 23.47% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1820 66.33% 89.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 198 7.22% 97.01% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 63 2.30% 99.31% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 9 0.33% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 4 0.15% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.04% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.04% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2744 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1939283032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1939283032 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1939283032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 2036 74.20% 74.20% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 708 25.80% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2744 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 27735 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30404 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2736 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 27735 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2744 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2736 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 33140 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2744 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 30479 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5173966 # DTB read hits -system.cpu1.dtb.read_misses 27871 # DTB read misses -system.cpu1.dtb.write_hits 4222414 # DTB write hits -system.cpu1.dtb.write_misses 2533 # DTB write misses +system.cpu1.dtb.read_hits 11374009 # DTB read hits +system.cpu1.dtb.read_misses 25676 # DTB read misses +system.cpu1.dtb.write_hits 7084428 # DTB write hits +system.cpu1.dtb.write_misses 2059 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2009 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 306 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 555 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1996 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 172 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 434 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5201837 # DTB read accesses -system.cpu1.dtb.write_accesses 4224947 # DTB write accesses +system.cpu1.dtb.perms_faults 262 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 11399685 # DTB read accesses +system.cpu1.dtb.write_accesses 7086487 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 9396380 # DTB hits -system.cpu1.dtb.misses 30404 # DTB misses -system.cpu1.dtb.accesses 9426784 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 18458437 # DTB hits +system.cpu1.dtb.misses 27735 # DTB misses +system.cpu1.dtb.accesses 18486172 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1442,44 +1454,46 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 2488 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2488 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 182 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2306 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2488 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2488 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2488 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1135 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12427.312775 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11760.899210 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5007.072010 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 4 0.35% 0.35% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 156 13.74% 14.10% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 686 60.44% 74.54% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 210 18.50% 93.04% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 30 2.64% 95.68% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 95.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 1.85% 97.71% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.70% 98.41% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 15 1.32% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.26% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1135 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1954817532 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1954817532 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1954817532 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 965 85.02% 85.02% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 170 14.98% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1135 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 2480 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2480 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 180 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2300 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2480 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2480 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2480 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1130 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12659.734513 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11853.270475 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5315.711785 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 183 16.19% 16.19% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 614 54.34% 70.53% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 213 18.85% 89.38% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 45 3.98% 93.36% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 23 2.04% 95.40% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.48% 97.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 15 1.33% 99.20% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.18% 99.38% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 4 0.35% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::53248-57343 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1130 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1939872532 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1939872532 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1939872532 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 965 85.40% 85.40% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 165 14.60% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1130 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2488 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2488 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2480 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2480 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1135 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1135 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3623 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 10174079 # ITB inst hits -system.cpu1.itb.inst_misses 2488 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1130 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1130 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3610 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 39704875 # ITB inst hits +system.cpu1.itb.inst_misses 2480 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1488,778 +1502,777 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1107 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1100 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1891 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1840 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 10176567 # ITB inst accesses -system.cpu1.itb.hits 10174079 # DTB hits -system.cpu1.itb.misses 2488 # DTB misses -system.cpu1.itb.accesses 10176567 # DTB accesses -system.cpu1.numPwrStateTransitions 5445 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2723 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 962192053.212266 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 19383110303.670654 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1861 68.34% 68.34% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 855 31.40% 99.74% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 3 0.11% 99.85% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 4 0.15% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 39707355 # ITB inst accesses +system.cpu1.itb.hits 39704875 # DTB hits +system.cpu1.itb.misses 2480 # DTB misses +system.cpu1.itb.accesses 39707355 # DTB accesses +system.cpu1.numPwrStateTransitions 5533 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2767 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1008221990.514637 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25700822378.312321 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1966 71.05% 71.05% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 797 28.80% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 499966911836 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2723 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 27729121603 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2620048960897 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 55461727 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 949980874116 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2767 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 58422036246 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2789750247754 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 116847616 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 20907814 # Number of instructions committed -system.cpu1.committedOps 25520055 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1855956 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2723 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5239453402 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.652679 # CPI: cycles per instruction -system.cpu1.ipc 0.376977 # IPC: instructions per cycle -system.cpu1.op_class_0::No_OpClass 67 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 16137166 63.23% 63.23% # Class of committed instruction -system.cpu1.op_class_0::IntMult 34169 0.13% 63.37% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 4083 0.02% 63.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 63.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 63.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 63.38% # Class of committed instruction -system.cpu1.op_class_0::MemRead 4989153 19.55% 82.93% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 4355417 17.07% 100.00% # Class of committed instruction +system.cpu1.committedInsts 48452289 # Number of instructions committed +system.cpu1.committedOps 59283596 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 5163197 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2767 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5578862239 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.411602 # CPI: cycles per instruction +system.cpu1.ipc 0.414662 # IPC: instructions per cycle +system.cpu1.op_class_0::No_OpClass 66 0.00% 0.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 40834570 68.88% 68.88% # Class of committed instruction +system.cpu1.op_class_0::IntMult 45625 0.08% 68.96% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 3333 0.01% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::MemRead 11200779 18.89% 87.86% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 7199223 12.14% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 25520055 # Class of committed instruction +system.cpu1.op_class_0::total 59283596 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2723 # number of quiesce instructions executed -system.cpu1.tickCycles 37036327 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 18425400 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 231690 # number of replacements -system.cpu1.dcache.tags.tagsinuse 479.724430 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 8932333 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 232024 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 38.497453 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 109862994000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.724430 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.936962 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.936962 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 334 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 70 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.652344 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 18884551 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 18884551 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 4750067 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 4750067 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3901959 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3901959 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65733 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 65733 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87399 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 87399 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79392 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 79392 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 8652026 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 8652026 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 8717759 # number of overall hits -system.cpu1.dcache.overall_hits::total 8717759 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 172325 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 172325 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 169730 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 169730 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34831 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 34831 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17668 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17668 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23402 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23402 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 342055 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 342055 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 376886 # number of overall misses -system.cpu1.dcache.overall_misses::total 376886 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2622225500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2622225500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4369952500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4369952500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 333352000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 333352000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 570866500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 570866500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 547000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 547000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6992178000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6992178000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6992178000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6992178000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 4922392 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 4922392 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4071689 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4071689 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 100564 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 100564 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105067 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 105067 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102794 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 102794 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 8994081 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 8994081 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 9094645 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 9094645 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035008 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035008 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.041685 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.041685 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.346357 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.346357 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.168159 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.168159 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.227659 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.227659 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038031 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.038031 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041440 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.041440 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15216.744523 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15216.744523 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25746.494432 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25746.494432 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18867.557165 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18867.557165 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24393.919323 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24393.919323 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2767 # number of quiesce instructions executed +system.cpu1.tickCycles 94150450 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 22697166 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 195596 # number of replacements +system.cpu1.dcache.tags.tagsinuse 473.279573 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 18031187 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 195963 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 92.013222 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 91237126000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.279573 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.924374 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.924374 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 57 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.716797 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 36965565 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 36965565 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 10998874 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10998874 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6796614 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6796614 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50142 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50142 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80008 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 80008 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71567 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71567 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 17795488 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 17795488 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 17845630 # number of overall hits +system.cpu1.dcache.overall_hits::total 17845630 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 148727 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 148727 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 145387 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 145387 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30687 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30687 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16966 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16966 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23611 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23611 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 294114 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 294114 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 324801 # number of overall misses +system.cpu1.dcache.overall_misses::total 324801 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2356620500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2356620500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3915884500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3915884500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 322199000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 322199000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 556849500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 556849500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 389000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 389000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6272505000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6272505000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6272505000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6272505000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11147601 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11147601 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6942001 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6942001 # 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number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 507235000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 507235000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82984000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82984000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 533247500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 533247500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 380000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 380000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4478001000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4478001000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4985236000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4985236000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2537758000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2537758000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2537758000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2537758000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.012829 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.012829 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013326 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013326 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369409 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369409 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050364 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050364 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248072 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248072 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013020 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.013020 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014605 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.014605 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14789.437619 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14789.437619 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25542.223375 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25542.223375 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16987.675408 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16987.675408 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16990.990991 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16990.990991 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22584.706281 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22584.706281 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18331.529533 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18331.529533 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18150.376751 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18150.376751 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184285.238007 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184285.238007 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 98539.764286 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 98539.764286 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 1038587 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.233977 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 9132995 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 1039099 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 8.789341 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 72888333000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.233977 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973113 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973113 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19012.847893 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19012.847893 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18784.990806 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18784.990806 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173878.588558 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173878.588558 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95681.408589 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95681.408589 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 948026 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.199607 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 38754409 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 948538 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.856991 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 72914784000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.199607 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974999 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974999 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 461 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 21383287 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 21383287 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 9132995 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 9132995 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 9132995 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 9132995 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 9132995 # number of overall hits -system.cpu1.icache.overall_hits::total 9132995 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 1039099 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 1039099 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 1039099 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 1039099 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 1039099 # number of overall misses -system.cpu1.icache.overall_misses::total 1039099 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9377315500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 9377315500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 9377315500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 9377315500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 9377315500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 9377315500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 10172094 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 10172094 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 10172094 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 10172094 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 10172094 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 10172094 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.102152 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.102152 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.102152 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.102152 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.102152 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.102152 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9024.467832 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9024.467832 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9024.467832 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9024.467832 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9024.467832 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9024.467832 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 80354432 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 80354432 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 38754409 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 38754409 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 38754409 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 38754409 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 38754409 # number of overall hits +system.cpu1.icache.overall_hits::total 38754409 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 948538 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 948538 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 948538 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 948538 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 948538 # number of overall misses +system.cpu1.icache.overall_misses::total 948538 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8680888000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8680888000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8680888000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8680888000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8680888000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8680888000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 39702947 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 39702947 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 39702947 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 39702947 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 39702947 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 39702947 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023891 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.023891 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023891 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.023891 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023891 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.023891 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9151.861075 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9151.861075 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9151.861075 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9151.861075 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9151.861075 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9151.861075 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 1038587 # number of writebacks -system.cpu1.icache.writebacks::total 1038587 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 1039099 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 1039099 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 1039099 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 1039099 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 1039099 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 1039099 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 948026 # number of writebacks +system.cpu1.icache.writebacks::total 948026 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 948538 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 948538 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 948538 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 948538 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 948538 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 948538 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8857766000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8857766000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8857766000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8857766000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8857766000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8857766000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10704000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10704000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10704000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10704000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.102152 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.102152 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.102152 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.102152 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.102152 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.102152 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8524.467832 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8524.467832 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8524.467832 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8524.467832 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8524.467832 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8524.467832 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95571.428571 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95571.428571 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95571.428571 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95571.428571 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 276399 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 276459 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 53 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8206619000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8206619000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8206619000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8206619000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8206619000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8206619000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10719000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10719000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10719000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10719000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023891 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023891 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023891 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023891 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023891 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023891 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8651.861075 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8651.861075 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8651.861075 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8651.861075 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8651.861075 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8651.861075 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95705.357143 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95705.357143 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95705.357143 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95705.357143 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 199515 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 199547 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 69493 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 70219 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15563.656432 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 2283330 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 85023 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 26.855439 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 59237 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 51581 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14798.019682 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1058904 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 65844 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 16.082012 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14385.822816 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 54.124799 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.170471 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1123.538345 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.878041 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003304 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000010 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.068575 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.949930 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1056 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14409.418299 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 42.207150 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.101777 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 346.292455 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.879481 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002576 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.021136 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.903199 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 289 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13706 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 291 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 761 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13932 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 101 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 185 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 19 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5206 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 8191 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.064453 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1267 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7924 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4741 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017639 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.836548 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 42757972 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 42757972 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 32984 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 3253 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 36237 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 134317 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 134317 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 1113970 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 1113970 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 37754 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 37754 # 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number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 167842 # number of overall hits -system.cpu1.l2cache.overall_hits::total 1216531 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 703 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 237 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 940 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 31976 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 31976 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23401 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23401 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36794 # 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number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14707 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11928 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11928 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10097 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10209 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 13702000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3438500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 17140500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1312457547 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1312457547 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 566974500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 566974500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 370291999 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 370291999 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 461000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 461000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1222094000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1222094000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 987020000 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 987020000 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1373517992 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1373517992 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 13702000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3438500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 987020000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2595611992 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 3599772492 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 13702000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3438500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 987020000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2595611992 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1312457547 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 4912230039 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9808000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 951737000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 961545000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9808000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 951737000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 961545000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020869 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.067908 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025284 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26523 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26635 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 12503500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4198500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 16702000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 979860887 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 979860887 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 459895000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 459895000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 354696000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 354696000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 312500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 312500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1165426499 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1165426499 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 1042424000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 1042424000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1304028987 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1304028987 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 12503500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4198500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1042424000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2469455486 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3528581486 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 12503500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4198500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1042424000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2469455486 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 979860887 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4508442373 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9823000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2420981000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2430804000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9823000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2420981000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2430804000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023300 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.084289 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029517 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.489121 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.489121 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.025623 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.025623 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.364724 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.364724 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020869 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.067908 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.025623 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.397900 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.102366 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020869 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.067908 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.025623 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.397900 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.551439 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.551439 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.037418 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.037418 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.421225 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.421225 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023300 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.084289 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.037418 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.455149 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119294 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023300 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.084289 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.037418 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.455149 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.130971 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18234.574468 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33841.925300 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33841.925300 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17731.251564 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17731.251564 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15823.768172 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15823.768172 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 461000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 461000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33516.002523 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33516.002523 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 37071.173709 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 37071.173709 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18372.364794 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18372.364794 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 37071.173709 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23337.007561 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25937.202726 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 37071.173709 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23337.007561 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33841.925300 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27663.625832 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87571.428571 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176280.237081 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174477.408819 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87571.428571 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 94259.383975 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 94186.012342 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 2654318 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1335711 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 21986 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 212975 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 211032 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1943 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 47306 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1331970 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 4698 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 4698 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 177822 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 1135956 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 137781 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 47279 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 75014 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42924 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 89713 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 82844 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 80563 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1039099 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 293637 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3117009 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1002647 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8284 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70688 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 4198628 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 132979072 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 35729427 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13960 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 134748 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 168857207 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 473910 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 5785960 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1814338 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.136111 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.346015 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.140483 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17462.988827 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14280.612245 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16536.633663 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37807.650847 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37807.650847 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15389.853763 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15389.853763 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15022.489518 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15022.489518 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33746.242913 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33746.242913 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29370.675082 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29370.675082 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17415.614768 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17415.614768 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17462.988827 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14280.612245 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29370.675082 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22570.243538 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24182.610894 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17462.988827 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14280.612245 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29370.675082 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22570.243538 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37807.650847 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26237.654282 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87705.357143 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165877.423775 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165282.110560 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87705.357143 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91278.550692 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91263.525436 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 2396557 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1207646 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20286 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 118595 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 110586 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8009 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 53656 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1217922 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11928 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11928 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 153983 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 1025852 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 34704 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 31184 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 74094 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41981 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86038 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 20 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 69927 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 67092 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 948538 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295426 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 64 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2845326 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 911410 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8268 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 64898 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3829902 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121387264 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30723028 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13952 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 122916 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 152247160 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 369470 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 5053360 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1597738 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.098519 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.314386 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1569330 86.50% 86.50% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 243065 13.40% 99.89% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1943 0.11% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1448339 90.65% 90.65% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 141390 8.85% 99.50% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 8009 0.50% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1814338 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2620766990 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1597738 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2375408982 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 87124018 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79990687 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1558968196 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 456771923 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1423068313 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 409788212 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4794998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4783493 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 37016968 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 34178481 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 31014 # Transaction distribution -system.iobus.trans_dist::ReadResp 31014 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 31003 # Transaction distribution +system.iobus.trans_dist::ReadResp 31003 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution system.iobus.trans_dist::WriteResp 59422 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) @@ -2268,7 +2281,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2281,17 +2294,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180872 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2304,94 +2317,94 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48375000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48331500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 113500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 329000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 333000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 27500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 13000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 88500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 619500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 620000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 45500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 47000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6358000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6355500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38893000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 39060500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187720844 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187669353 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36784000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36462 # number of replacements -system.iocache.tags.tagsinuse 14.359878 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 36449 # number of replacements +system.iocache.tags.tagsinuse 14.473969 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36478 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 271405535000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.359878 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.897492 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.897492 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 271637878000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.473969 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904623 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904623 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328320 # Number of tag accesses -system.iocache.tags.data_accesses 328320 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 256 # number of ReadReq misses -system.iocache.ReadReq_misses::total 256 # number of ReadReq misses +system.iocache.tags.tag_accesses 328203 # Number of tag accesses +system.iocache.tags.data_accesses 328203 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses +system.iocache.ReadReq_misses::total 243 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36480 # number of demand (read+write) misses -system.iocache.demand_misses::total 36480 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36480 # number of overall misses -system.iocache.overall_misses::total 36480 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 33042377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 33042377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4307289467 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4307289467 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4340331844 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4340331844 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4340331844 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4340331844 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 256 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 256 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses +system.iocache.demand_misses::total 36467 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36467 # number of overall misses +system.iocache.overall_misses::total 36467 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31680877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31680877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4302277476 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4302277476 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4333958353 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4333958353 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4333958353 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4333958353 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36480 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36480 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36480 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36480 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36467 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36467 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36467 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36467 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2400,38 +2413,38 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129071.785156 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129071.785156 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118907.063466 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118907.063466 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118978.394846 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118978.394846 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118978.394846 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118978.394846 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 130373.979424 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 130373.979424 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118768.702407 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118768.702407 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118846.034853 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118846.034853 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118846.034853 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118846.034853 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.666667 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 4.166667 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 256 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 256 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36480 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36480 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36480 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36480 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 20242377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 20242377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2493740476 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2493740476 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2513982853 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2513982853 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2513982853 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2513982853 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 36467 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19530877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19530877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2488777487 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2488777487 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2508308364 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2508308364 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2508308364 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2508308364 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2440,590 +2453,592 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79071.785156 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 79071.785156 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68842.217204 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68842.217204 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68914.003646 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68914.003646 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68914.003646 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68914.003646 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 135113 # number of replacements -system.l2c.tags.tagsinuse 63251.941629 # Cycle average of tags in use -system.l2c.tags.total_refs 475115 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 198978 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.387777 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 14216.048080 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 74.910809 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.033810 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7426.792759 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2102.106662 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29896.915616 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 20.238831 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3811.016358 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1509.520853 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4194.357849 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.216920 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001143 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80373.979424 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 80373.979424 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68705.208895 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68705.208895 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68782.964434 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68782.964434 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68782.964434 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68782.964434 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 143192 # number of replacements +system.l2c.tags.tagsinuse 65154.235518 # Cycle average of tags in use +system.l2c.tags.total_refs 608270 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 208652 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.915237 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 94157771000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 6329.103935 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 78.467327 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.034862 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8953.646572 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6857.938638 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35058.708510 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 16.060603 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2144.069552 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3463.562714 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2252.642806 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.096574 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001197 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.113324 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.032076 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.456191 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000309 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.058151 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.023033 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.064001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.965148 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 27324 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 89 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 36452 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 105 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4822 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 22394 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 88 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 417 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3262 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 32736 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.416931 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.001358 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.556213 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6444953 # Number of tag accesses -system.l2c.tags.data_accesses 6444953 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 270033 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 270033 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 32996 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 3857 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 36853 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2004 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1040 # 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number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 8223 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 174583 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 357 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 67 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 40247 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 51329 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 44871 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 179 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 29 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 20863 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14295 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 8223 # number of demand (read+write) hits -system.l2c.demand_hits::total 180460 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74516.612069 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116100.999562 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 88935.335554 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63637.035963 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179924.347835 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66571.428571 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158365.363232 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166188.791033 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197515.134419 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66705.357143 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147906.284265 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166371.405958 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63637.035963 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 95219.849641 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66571.428571 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 84658.163265 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 92079.185841 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 535318 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 308111 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 583 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102007.866934 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66705.357143 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81381.919306 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92183.762527 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 516977 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 290556 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 569 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 38585 # Transaction distribution -system.membus.trans_dist::ReadResp 215902 # Transaction distribution -system.membus.trans_dist::WriteReq 31055 # Transaction distribution -system.membus.trans_dist::WriteResp 31055 # Transaction distribution -system.membus.trans_dist::WritebackDirty 141257 # Transaction distribution -system.membus.trans_dist::CleanEvict 18818 # Transaction distribution -system.membus.trans_dist::UpgradeReq 79128 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41795 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 38536 # Transaction distribution +system.membus.trans_dist::ReadResp 214874 # Transaction distribution +system.membus.trans_dist::WriteReq 31013 # Transaction distribution +system.membus.trans_dist::WriteResp 31013 # Transaction distribution +system.membus.trans_dist::WritebackDirty 140764 # Transaction distribution +system.membus.trans_dist::CleanEvict 19586 # Transaction distribution +system.membus.trans_dist::UpgradeReq 64644 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38971 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 40708 # Transaction distribution -system.membus.trans_dist::ReadExResp 19870 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 177317 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 40377 # Transaction distribution +system.membus.trans_dist::ReadExResp 19925 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 176338 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14304 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 675920 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 798178 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72957 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72957 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 871135 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 656690 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 778768 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 851699 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19551584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19744330 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19461788 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19654168 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22062474 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 126237 # Total snoops (count) -system.membus.snoopTraffic 37184 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 444815 # Request fanout histogram -system.membus.snoop_fanout::mean 0.011558 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.106883 # Request fanout histogram +system.membus.pkt_size::total 21972312 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123613 # Total snoops (count) +system.membus.snoopTraffic 36288 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 426105 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011500 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.106618 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 439674 98.84% 98.84% # Request fanout histogram -system.membus.snoop_fanout::1 5141 1.16% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 421205 98.85% 98.85% # Request fanout histogram +system.membus.snoop_fanout::1 4900 1.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 444815 # Request fanout histogram -system.membus.reqLayer0.occupancy 94951000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 426105 # Request fanout histogram +system.membus.reqLayer0.occupancy 95080500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12539499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12459499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1031011447 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1008366249 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1149570495 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1144784655 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1412877 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1337127 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3055,77 +3070,77 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1073312 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 580718 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 172518 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 20634 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 19568 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1066 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 38588 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 515387 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31055 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 375084 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 144219 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 115852 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 44839 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 160691 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51833 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51833 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 476801 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4556 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1253209 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 392983 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1646192 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34630659 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7267527 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 41898186 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 395888 # Total snoops (count) -system.toL2Bus.snoopTraffic 16395788 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 898686 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.386698 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.489423 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1122676 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 592030 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 210689 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 28909 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 27742 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1167 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 38539 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 569123 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31013 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31013 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 372658 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 153621 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 113203 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 44029 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 157232 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 29 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51954 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51954 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 530586 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4329 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1344687 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 405982 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1750669 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 38363344 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7028808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45392152 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 398871 # Total snoops (count) +system.toL2Bus.snoopTraffic 16195724 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 956902 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.408687 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.494066 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 552232 61.45% 61.45% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 345388 38.43% 99.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1066 0.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 566996 59.25% 59.25% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 388739 40.62% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1167 0.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 898686 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 930017339 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 956902 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 952868265 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 361623 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 342123 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 658710189 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 724877328 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 272587474 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 285789223 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |