diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | 4685 |
1 files changed, 2374 insertions, 2311 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index c733baa00..bb4196597 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,160 +1,164 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.846097 # Number of seconds simulated -sim_ticks 2846097440000 # Number of ticks simulated -final_tick 2846097440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.846145 # Number of seconds simulated +sim_ticks 2846145040000 # Number of ticks simulated +final_tick 2846145040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101530 # Simulator instruction rate (inst/s) -host_op_rate 122947 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2278332577 # Simulator tick rate (ticks/s) -host_mem_usage 584920 # Number of bytes of host memory used -host_seconds 1249.20 # Real time elapsed on the host -sim_insts 126830911 # Number of instructions simulated -sim_ops 153585651 # Number of ops (including micro ops) simulated +host_inst_rate 162017 # Simulator instruction rate (inst/s) +host_op_rate 196203 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3671761280 # Simulator tick rate (ticks/s) +host_mem_usage 648900 # Number of bytes of host memory used +host_seconds 775.14 # Real time elapsed on the host +sim_insts 125586921 # Number of instructions simulated +sim_ops 152085297 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 9344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1671232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1335292 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8458880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 217280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 606496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 432576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 8320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1497984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1248876 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8305216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 2560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 388800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 684240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 582144 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12733532 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1671232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 217280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1888512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8840256 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory +system.physmem.bytes_read::total 12719228 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1497984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 388800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1886784 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8861888 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8858000 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 146 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26113 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21389 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 132170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9500 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6759 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8879452 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 130 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 23406 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20035 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 129769 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 40 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6075 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10711 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 9096 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 199510 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138129 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory +system.physmem.num_reads::total 199279 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138467 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142565 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3283 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 587201 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 469166 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2972098 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 76343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 213097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 151989 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 142858 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 526320 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 438796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2918058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 136606 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 240409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 204538 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4474032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 587201 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 76343 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 663544 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3106097 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6220 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4468932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 526320 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 136606 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 662926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3113646 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6157 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3112332 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3106097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3283 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 587201 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 475386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2972098 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 76343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 213111 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 151989 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3119817 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3113646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 526320 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 444953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2918058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 136606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 240423 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 204538 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7586364 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 199510 # Number of read requests accepted -system.physmem.writeReqs 178789 # Number of write requests accepted -system.physmem.readBursts 199510 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 178789 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12761024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue -system.physmem.bytesWritten 9911424 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12733532 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11176336 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23895 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14191 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12377 # Per bank write bursts -system.physmem.perBankRdBursts::1 12507 # Per bank write bursts -system.physmem.perBankRdBursts::2 12921 # Per bank write bursts -system.physmem.perBankRdBursts::3 12944 # Per bank write bursts -system.physmem.perBankRdBursts::4 15059 # Per bank write bursts -system.physmem.perBankRdBursts::5 12345 # Per bank write bursts -system.physmem.perBankRdBursts::6 13163 # Per bank write bursts -system.physmem.perBankRdBursts::7 13279 # Per bank write bursts -system.physmem.perBankRdBursts::8 12255 # Per bank write bursts -system.physmem.perBankRdBursts::9 12304 # Per bank write bursts -system.physmem.perBankRdBursts::10 12058 # Per bank write bursts -system.physmem.perBankRdBursts::11 11233 # Per bank write bursts -system.physmem.perBankRdBursts::12 11543 # Per bank write bursts -system.physmem.perBankRdBursts::13 12301 # Per bank write bursts -system.physmem.perBankRdBursts::14 11677 # Per bank write bursts -system.physmem.perBankRdBursts::15 11425 # Per bank write bursts -system.physmem.perBankWrBursts::0 9896 # Per bank write bursts -system.physmem.perBankWrBursts::1 10159 # Per bank write bursts -system.physmem.perBankWrBursts::2 10174 # Per bank write bursts -system.physmem.perBankWrBursts::3 9995 # Per bank write bursts -system.physmem.perBankWrBursts::4 9156 # Per bank write bursts -system.physmem.perBankWrBursts::5 9568 # Per bank write bursts -system.physmem.perBankWrBursts::6 10283 # Per bank write bursts -system.physmem.perBankWrBursts::7 10373 # Per bank write bursts -system.physmem.perBankWrBursts::8 9590 # Per bank write bursts -system.physmem.perBankWrBursts::9 9571 # Per bank write bursts -system.physmem.perBankWrBursts::10 9719 # Per bank write bursts -system.physmem.perBankWrBursts::11 9542 # Per bank write bursts -system.physmem.perBankWrBursts::12 9254 # Per bank write bursts -system.physmem.perBankWrBursts::13 9350 # Per bank write bursts -system.physmem.perBankWrBursts::14 9412 # Per bank write bursts -system.physmem.perBankWrBursts::15 8824 # Per bank write bursts +system.physmem.bw_total::total 7588749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 199279 # Number of read requests accepted +system.physmem.writeReqs 179082 # Number of write requests accepted +system.physmem.readBursts 199279 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 179082 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12747712 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue +system.physmem.bytesWritten 9932032 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12719228 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11197788 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23866 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14978 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12467 # Per bank write bursts +system.physmem.perBankRdBursts::1 12549 # Per bank write bursts +system.physmem.perBankRdBursts::2 12590 # Per bank write bursts +system.physmem.perBankRdBursts::3 12626 # Per bank write bursts +system.physmem.perBankRdBursts::4 14976 # Per bank write bursts +system.physmem.perBankRdBursts::5 12125 # Per bank write bursts +system.physmem.perBankRdBursts::6 13379 # Per bank write bursts +system.physmem.perBankRdBursts::7 13505 # Per bank write bursts +system.physmem.perBankRdBursts::8 12274 # Per bank write bursts +system.physmem.perBankRdBursts::9 12440 # Per bank write bursts +system.physmem.perBankRdBursts::10 11813 # Per bank write bursts +system.physmem.perBankRdBursts::11 11246 # Per bank write bursts +system.physmem.perBankRdBursts::12 11354 # Per bank write bursts +system.physmem.perBankRdBursts::13 11924 # Per bank write bursts +system.physmem.perBankRdBursts::14 11833 # Per bank write bursts +system.physmem.perBankRdBursts::15 12082 # Per bank write bursts +system.physmem.perBankWrBursts::0 9603 # Per bank write bursts +system.physmem.perBankWrBursts::1 9871 # Per bank write bursts +system.physmem.perBankWrBursts::2 10084 # Per bank write bursts +system.physmem.perBankWrBursts::3 9904 # Per bank write bursts +system.physmem.perBankWrBursts::4 9385 # Per bank write bursts +system.physmem.perBankWrBursts::5 9666 # Per bank write bursts +system.physmem.perBankWrBursts::6 10609 # Per bank write bursts +system.physmem.perBankWrBursts::7 10482 # Per bank write bursts +system.physmem.perBankWrBursts::8 9764 # Per bank write bursts +system.physmem.perBankWrBursts::9 9386 # Per bank write bursts +system.physmem.perBankWrBursts::10 9428 # Per bank write bursts +system.physmem.perBankWrBursts::11 9248 # Per bank write bursts +system.physmem.perBankWrBursts::12 9294 # Per bank write bursts +system.physmem.perBankWrBursts::13 9689 # Per bank write bursts +system.physmem.perBankWrBursts::14 9592 # Per bank write bursts +system.physmem.perBankWrBursts::15 9183 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 38 # Number of times write queue was full causing retry -system.physmem.totGap 2846096933500 # Total gap between requests +system.physmem.numWrRetry 107 # Number of times write queue was full causing retry +system.physmem.totGap 2846144533500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 559 # Read request sizes (log2) +system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 198923 # Read request sizes (log2) +system.physmem.readPktSize::6 198700 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 4436 # Write request sizes (log2) +system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 174353 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 98295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 47940 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7837 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6409 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5336 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4702 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 765 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 174691 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 98289 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7835 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4763 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 766 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 286 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -184,160 +188,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1868 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90716 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 249.927069 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.222601 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 310.362875 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47359 52.21% 52.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17889 19.72% 71.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6289 6.93% 78.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3581 3.95% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2839 3.13% 85.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1568 1.73% 87.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 985 1.09% 88.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1019 1.12% 89.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9187 10.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90716 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6524 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.562538 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 556.578248 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6523 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 536 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 91273 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 248.481807 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 139.408554 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 309.811796 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47817 52.39% 52.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18099 19.83% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6231 6.83% 79.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3556 3.90% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2836 3.11% 86.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1554 1.70% 87.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 946 1.04% 88.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1020 1.12% 89.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9214 10.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 91273 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6574 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.298296 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 554.918828 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6572 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6524 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6524 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.737891 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.670801 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 40.283485 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 6175 94.65% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 90 1.38% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 23 0.35% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 12 0.18% 96.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 26 0.40% 96.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 32 0.49% 97.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 26 0.40% 97.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 10 0.15% 98.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 20 0.31% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 5 0.08% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 20 0.31% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 23 0.35% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 7 0.11% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 7 0.11% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 1 0.02% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 3 0.05% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 2 0.03% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 5 0.08% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 4 0.06% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 4 0.06% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 14 0.21% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 2 0.03% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.05% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6524 # Writes before turning the bus around for reads -system.physmem.totQLat 5679096455 # Total ticks spent queuing -system.physmem.totMemAccLat 9417677705 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 996955000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28482.21 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6574 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6574 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.606328 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.587470 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 41.316435 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 6233 94.81% 94.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 88 1.34% 96.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 20 0.30% 96.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 23 0.35% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 27 0.41% 97.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 26 0.40% 97.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 23 0.35% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 19 0.29% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 11 0.17% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 6 0.09% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 17 0.26% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 19 0.29% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 5 0.08% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 3 0.05% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.03% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.03% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 3 0.05% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 5 0.08% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 6 0.09% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 6 0.09% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 9 0.14% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 2 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.05% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.03% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 3 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 2 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6574 # Writes before turning the bus around for reads +system.physmem.totQLat 5766362365 # Total ticks spent queuing +system.physmem.totMemAccLat 9501043615 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 995915000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28950.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47232.21 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 47700.07 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.48 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 3.49 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.47 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.18 # Average write queue length when enqueuing -system.physmem.readRowHits 166067 # Number of row buffer hits during reads -system.physmem.writeRowHits 97473 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.93 # Row buffer hit rate for writes -system.physmem.avgGap 7523405.91 # Average gap between requests -system.physmem.pageHitRate 74.39 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 359115120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 195945750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 815841000 # Energy for read commands per rank (pJ) +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.19 # Average write queue length when enqueuing +system.physmem.readRowHits 165729 # Number of row buffer hits during reads +system.physmem.writeRowHits 97368 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.73 # Row buffer hit rate for writes +system.physmem.avgGap 7522298.90 # Average gap between requests +system.physmem.pageHitRate 74.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 359432640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 196119000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 812892600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 515833920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185892919680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83249453610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634629745250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1905658854330 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.570214 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2719227401175 # Time in different power states -system.physmem_0.memoryStateTime::REF 95037280000 # Time in different power states +system.physmem_0.refreshEnergy 185895971040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83250586485 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634656782000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1905687617685 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.569329 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2719272584266 # Time in different power states +system.physmem_0.memoryStateTime::REF 95038840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31827968825 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31827943234 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 326697840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 178257750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 739401000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 487697760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185892919680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82096607520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635641013750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1905362595300 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.466120 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2720918284391 # Time in different power states -system.physmem_1.memoryStateTime::REF 95037280000 # Time in different power states +system.physmem_1.actEnergy 330591240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 180382125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 740727000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 489784320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185895971040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82231883055 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635550381500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1905419720280 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.475203 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2720770086744 # Time in different power states +system.physmem_1.memoryStateTime::REF 95038840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30141762609 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30336000256 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory @@ -363,15 +371,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 20630955 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13593557 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1040069 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 13124579 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 9315197 # Number of BTB hits +system.cpu0.branchPred.lookups 33812647 # Number of BP lookups +system.cpu0.branchPred.condPredicted 16331756 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1585484 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 19439562 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 14041669 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 70.975206 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3367508 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 204886 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.232435 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 10663467 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 792082 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -402,59 +410,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 69457 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 69457 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46535 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22922 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 69457 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 69457 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 69457 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6849 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 9469.922616 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 8283.824538 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6457.338241 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6642 96.98% 96.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 191 2.79% 99.77% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.10% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6849 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 65253 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 65253 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 42795 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22458 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 65253 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 65253 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 65253 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6648 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9627.369284 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 8488.785540 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6159.752779 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6446 96.96% 96.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 188 2.83% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 4 0.06% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.11% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6648 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 328505000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 328505000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 328505000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5259 76.78% 76.78% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1590 23.22% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6849 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69457 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5136 77.26% 77.26% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1512 22.74% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6648 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65253 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69457 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6849 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65253 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6648 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6849 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 76306 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6648 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 71901 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17312533 # DTB read hits -system.cpu0.dtb.read_misses 63301 # DTB read misses -system.cpu0.dtb.write_hits 14536158 # DTB write hits -system.cpu0.dtb.write_misses 6156 # DTB write misses +system.cpu0.dtb.read_hits 22995822 # DTB read hits +system.cpu0.dtb.read_misses 59685 # DTB read misses +system.cpu0.dtb.write_hits 17147924 # DTB write hits +system.cpu0.dtb.write_misses 5568 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3522 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1254 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1942 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1156 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1615 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17375834 # DTB read accesses -system.cpu0.dtb.write_accesses 14542314 # DTB write accesses +system.cpu0.dtb.perms_faults 564 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 23055507 # DTB read accesses +system.cpu0.dtb.write_accesses 17153492 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31848691 # DTB hits -system.cpu0.dtb.misses 69457 # DTB misses -system.cpu0.dtb.accesses 31918148 # DTB accesses +system.cpu0.dtb.hits 40143746 # DTB hits +system.cpu0.dtb.misses 65253 # DTB misses +system.cpu0.dtb.accesses 40208999 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -484,38 +491,39 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3833 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3833 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3526 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3833 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3833 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3833 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2419 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 9485.117817 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 8378.584027 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 4911.792845 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 918 37.95% 37.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1466 60.60% 98.55% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 5 0.21% 98.76% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 29 1.20% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 3866 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3866 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3560 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3866 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3866 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3866 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2421 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 9944.030566 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 8839.286720 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5045.849413 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 802 33.13% 33.13% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1572 64.93% 98.06% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 10 0.41% 98.47% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2419 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2421 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 328041000 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 328041000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 328041000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2119 87.60% 87.60% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 300 12.40% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2419 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2122 87.65% 87.65% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 299 12.35% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2421 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3833 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3833 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3866 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3866 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2419 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2419 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6252 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 38694088 # ITB inst hits -system.cpu0.itb.inst_misses 3833 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2421 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2421 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6287 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 68390761 # ITB inst hits +system.cpu0.itb.inst_misses 3866 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -524,131 +532,131 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2222 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2224 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7309 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7604 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 38697921 # ITB inst accesses -system.cpu0.itb.hits 38694088 # DTB hits -system.cpu0.itb.misses 3833 # DTB misses -system.cpu0.itb.accesses 38697921 # DTB accesses -system.cpu0.numCycles 164664294 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 68394627 # ITB inst accesses +system.cpu0.itb.hits 68390761 # DTB hits +system.cpu0.itb.misses 3866 # DTB misses +system.cpu0.itb.accesses 68394627 # DTB accesses +system.cpu0.numCycles 225488562 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 79545676 # Number of instructions committed -system.cpu0.committedOps 95726645 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 5037895 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1845 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5527555817 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.070060 # CPI: cycles per instruction -system.cpu0.ipc 0.483078 # IPC: instructions per cycle +system.cpu0.committedInsts 104715622 # Number of instructions committed +system.cpu0.committedOps 126599996 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 8092675 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 2098 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5466839701 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.153342 # CPI: cycles per instruction +system.cpu0.ipc 0.464394 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1847 # number of quiesce instructions executed -system.cpu0.tickCycles 127989646 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 36674648 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 713904 # number of replacements -system.cpu0.dcache.tags.tagsinuse 500.482804 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 30358451 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 714416 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 42.494080 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 348749500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.482804 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977505 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.977505 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 2103 # number of quiesce instructions executed +system.cpu0.tickCycles 187544415 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 37944147 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 678004 # number of replacements +system.cpu0.dcache.tags.tagsinuse 485.290770 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 38699274 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 678516 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 57.035168 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 346166500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.290770 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947834 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.947834 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63703980 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63703980 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15781686 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15781686 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 13418199 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 13418199 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 321521 # 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number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95832009 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 422721232 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 422721232 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 436500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 436500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9335353628 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9335353628 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10952155306 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10952155306 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4276481750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4276481750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3261665000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3261665000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7538146750 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7538146750 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024087 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024087 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023141 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023141 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225731 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225731 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016596 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016596 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053129 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053129 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023649 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023649 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026664 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026664 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11317.175810 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11317.175810 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15151.022120 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15151.022120 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15637.287251 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15637.287251 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14934.082749 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14934.082749 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20841.159197 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20841.159197 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 490183 # number of writebacks +system.cpu0.dcache.writebacks::total 490183 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 69583 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 69583 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 243174 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 243174 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14803 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14803 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 312757 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 312757 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 312757 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 312757 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 371857 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 371857 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312047 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 312047 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99536 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 99536 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6041 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6041 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21317 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 21317 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 683904 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 683904 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 783440 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 783440 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29433 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29433 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26165 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26165 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 55598 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 55598 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4208861714 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4208861714 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4793451106 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4793451106 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1567109691 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1567109691 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 90045006 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90045006 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 448833841 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 448833841 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 579500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 579500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9002312820 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9002312820 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10569422511 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10569422511 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5627001499 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5627001499 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4261635500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4261635500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9888636999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9888636999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016940 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016940 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018780 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018780 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226570 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226570 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.015961 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.015961 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056988 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056988 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017733 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.017733 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020085 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.020085 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11318.495319 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11318.495319 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15361.311296 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15361.311296 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15744.149765 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15744.149765 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14905.645754 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14905.645754 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21055.206689 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21055.206689 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13053.371555 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13053.371555 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13379.750472 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13379.750472 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13163.123509 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13163.123509 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13491.042723 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13491.042723 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191180.018992 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191180.018992 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162875.425186 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162875.425186 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177859.581262 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177859.581262 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1969157 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.783924 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36716761 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1969669 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 18.641082 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6455779250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.783924 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999578 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1884730 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.784347 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 66497574 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1885242 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 35.272699 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6453364250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.784347 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999579 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999579 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 79342579 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 79342579 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 36716761 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36716761 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36716761 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36716761 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36716761 # number of overall hits -system.cpu0.icache.overall_hits::total 36716761 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1969686 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1969686 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1969686 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1969686 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1969686 # number of overall misses -system.cpu0.icache.overall_misses::total 1969686 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18594001543 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18594001543 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18594001543 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18594001543 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18594001543 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18594001543 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 38686447 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 38686447 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 38686447 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 38686447 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 38686447 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 38686447 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050914 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050914 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050914 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050914 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050914 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050914 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9440.084127 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9440.084127 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9440.084127 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9440.084127 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9440.084127 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9440.084127 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 138650918 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 138650918 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 66497574 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 66497574 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 66497574 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 66497574 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 66497574 # number of overall hits +system.cpu0.icache.overall_hits::total 66497574 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1885257 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1885257 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1885257 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1885257 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1885257 # number of overall misses +system.cpu0.icache.overall_misses::total 1885257 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17590953808 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 17590953808 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 17590953808 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 17590953808 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 17590953808 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 17590953808 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 68382831 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 68382831 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 68382831 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 68382831 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 68382831 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 68382831 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.027569 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.027569 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.027569 # 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Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15217 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 322 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 428 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 273 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 280 # 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mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.915650 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.915650 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157671 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157671 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010905 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.026439 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036152 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.185051 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075961 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010905 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.026439 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036152 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.185051 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158018 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158018 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010033 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.027480 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.033826 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192590 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.076207 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010033 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.027480 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.033826 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192590 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163120 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23400.009493 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30053.081217 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58459.199979 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58459.199979 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20172.381963 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20172.381963 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14669.747940 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14669.747940 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 345999 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 345999 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38178.292804 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38178.292804 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27791.679436 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31655.164692 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27791.679436 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58459.199979 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45977.272768 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.162550 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 38954.865391 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22316.905255 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28750.735065 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60961.827767 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60961.827767 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19582.360065 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19582.360065 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14803.678348 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14803.678348 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 466499 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 466499 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39187.808209 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39187.808209 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38954.865391 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27143.872318 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30798.654503 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38954.865391 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27143.872318 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60961.827767 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46820.715114 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183171.261849 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172970.251524 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155364.532773 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155364.532773 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 170085.124465 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 165157.928432 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 2703667 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2643606 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19130 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19130 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 513519 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 304285 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 88848 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42983 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 113085 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 297594 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284124 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3946133 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2385460 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11633 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 174179 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6517405 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126276224 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86385120 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17096 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 327200 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 213005640 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 651207 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3963380 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 3.135029 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.341755 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 2622296 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2539595 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26165 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 490181 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 288086 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 93335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43761 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114801 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 284088 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 269989 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3777247 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2323391 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11902 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 166252 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6278792 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120871872 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82524675 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17904 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314164 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 203728615 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 661406 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3889209 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.165588 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.371711 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 3428208 86.50% 86.50% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 535172 13.50% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 3245202 83.44% 83.44% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 644007 16.56% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3963380 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2258643996 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 3889209 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2173439238 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 116241999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 113551498 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2965047043 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2837827806 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1230256203 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1188833142 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7364491 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7429994 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 92392742 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 87720745 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 18842889 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6205402 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 629106 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 9920552 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 7177439 # Number of BTB hits +system.cpu1.branchPred.lookups 5430284 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3355584 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 331008 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 3397877 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 2268406 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 72.349190 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 8245946 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 413041 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 66.759509 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 972543 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 68492 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1249,60 +1275,60 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 26188 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 26188 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19132 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7056 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 26188 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 26188 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 26188 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2719 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 9780.159618 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 8826.212048 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5631.617808 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 919 33.80% 33.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1662 61.13% 94.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 68 2.50% 97.43% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 62 2.28% 99.71% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.11% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 2 0.07% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2719 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1631340764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1631340764 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1631340764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 2011 73.96% 73.96% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 708 26.04% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2719 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26188 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 30040 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 30040 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 22353 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7687 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 30040 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 30040 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 30040 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2702 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9799.871947 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8761.915074 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6575.386381 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 913 33.79% 33.79% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1652 61.14% 94.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 67 2.48% 97.41% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.07% 99.48% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.56% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 5 0.19% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 6 0.22% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2702 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1622459264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1622459264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1622459264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 2019 74.72% 74.72% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 683 25.28% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2702 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30040 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26188 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2719 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30040 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2702 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2719 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 28907 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2702 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 32742 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 11112548 # DTB read hits -system.cpu1.dtb.read_misses 24192 # DTB read misses -system.cpu1.dtb.write_hits 6961122 # DTB write hits -system.cpu1.dtb.write_misses 1996 # DTB write misses +system.cpu1.dtb.read_hits 5155380 # DTB read hits +system.cpu1.dtb.read_misses 27847 # DTB read misses +system.cpu1.dtb.write_hits 4232538 # DTB write hits +system.cpu1.dtb.write_misses 2193 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2061 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 148 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 422 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2049 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 312 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 511 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 278 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 11136740 # DTB read accesses -system.cpu1.dtb.write_accesses 6963118 # DTB write accesses +system.cpu1.dtb.perms_faults 285 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 5183227 # DTB read accesses +system.cpu1.dtb.write_accesses 4234731 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 18073670 # DTB hits -system.cpu1.dtb.misses 26188 # DTB misses -system.cpu1.dtb.accesses 18099858 # DTB accesses +system.cpu1.dtb.hits 9387918 # DTB hits +system.cpu1.dtb.misses 30040 # DTB misses +system.cpu1.dtb.accesses 9417958 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1332,41 +1358,40 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 2252 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2252 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2071 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2252 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2252 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2252 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1119 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 9763.181412 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8935.720507 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4528.605471 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 139 12.42% 12.42% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 170 15.19% 27.61% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 525 46.92% 74.53% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 253 22.61% 97.14% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 2 0.18% 97.32% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 1.88% 99.20% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 7 0.63% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1119 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1630766264 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1630766264 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1630766264 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 951 84.99% 84.99% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 168 15.01% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1119 # Table walker page sizes translated +system.cpu1.itb.walker.walks 2268 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2268 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 178 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2090 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2268 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2268 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2268 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1115 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 9869.507623 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8954.185655 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5421.941384 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 302 27.09% 27.09% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 778 69.78% 96.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 3 0.27% 97.13% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 27 2.42% 99.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 1 0.09% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.27% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1115 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1621868264 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1621868264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1621868264 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 950 85.20% 85.20% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 165 14.80% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1115 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2252 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2252 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2268 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2268 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1119 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1119 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3371 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 39781680 # ITB inst hits -system.cpu1.itb.inst_misses 2252 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1115 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1115 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3383 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 10199097 # ITB inst hits +system.cpu1.itb.inst_misses 2268 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1375,130 +1400,130 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1157 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1153 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1899 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1907 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 39783932 # ITB inst accesses -system.cpu1.itb.hits 39781680 # DTB hits -system.cpu1.itb.misses 2252 # DTB misses -system.cpu1.itb.accesses 39783932 # DTB accesses -system.cpu1.numCycles 114623988 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 10201365 # ITB inst accesses +system.cpu1.itb.hits 10199097 # DTB hits +system.cpu1.itb.misses 2268 # DTB misses +system.cpu1.itb.accesses 10201365 # DTB accesses +system.cpu1.numCycles 54377537 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 47285235 # Number of instructions committed -system.cpu1.committedOps 57859006 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 5005620 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2776 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5576963738 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.424097 # CPI: cycles per instruction -system.cpu1.ipc 0.412525 # IPC: instructions per cycle +system.cpu1.committedInsts 20871299 # Number of instructions committed +system.cpu1.committedOps 25485301 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1815368 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2715 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5637293692 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.605374 # CPI: cycles per instruction +system.cpu1.ipc 0.383822 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2776 # number of quiesce instructions executed -system.cpu1.tickCycles 97884766 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 16739222 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 194739 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.948438 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 17633406 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 195100 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 90.381374 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 90504077500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.948438 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923727 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.923727 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 55 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.705078 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 36178407 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 36178407 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 10725883 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10725883 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6668052 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6668052 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49984 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 49984 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80051 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 80051 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71499 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71499 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 17393935 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 17393935 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 17443919 # number of overall hits -system.cpu1.dcache.overall_hits::total 17443919 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 157968 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 157968 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 144726 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 144726 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30816 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30816 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16919 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16919 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23678 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23678 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 302694 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 302694 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 333510 # number of overall misses -system.cpu1.dcache.overall_misses::total 333510 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2315952429 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2315952429 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3861386324 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3861386324 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 316030492 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 316030492 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557062155 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 557062155 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 124000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 124000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6177338753 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6177338753 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6177338753 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6177338753 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 10883851 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 10883851 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6812778 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6812778 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80800 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 80800 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96970 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96970 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95177 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95177 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 17696629 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 17696629 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 17777429 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 17777429 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.014514 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.014514 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021243 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.021243 # 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average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14660.896061 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26680.667772 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 26680.667772 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18679.029021 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18679.029021 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23526.571290 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23526.571290 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2716 # number of quiesce instructions executed +system.cpu1.tickCycles 38719894 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 15657643 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 231595 # 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number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 550485715 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 359500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 359500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6866916728 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6866916728 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6866916728 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6866916728 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4898499 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4898499 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4074313 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4074313 # 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number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1507,142 +1532,148 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 119475 # number of writebacks -system.cpu1.dcache.writebacks::total 119475 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16075 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 16075 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52265 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 52265 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12035 # 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number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4171635396 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4658901157 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4658901157 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2322015751 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2322015751 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1843986000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1843986000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4166001751 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4166001751 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013037 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013037 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013572 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013572 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.370483 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.370483 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050366 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050366 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248779 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248779 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013243 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.013243 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014867 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.014867 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13189.224155 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13189.224155 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24877.265150 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24877.265150 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16277.459863 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16277.459863 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16355.191032 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16355.191032 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21970.071163 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21970.071163 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 138038 # number of writebacks +system.cpu1.dcache.writebacks::total 138038 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18091 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 18091 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62532 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 62532 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12272 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12272 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 80623 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 80623 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 80623 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 80623 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164874 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 164874 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105876 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 105876 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 34136 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 34136 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5441 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5441 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23494 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23494 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 270750 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 270750 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 304886 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 304886 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5716 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5716 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5010 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5010 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10726 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10726 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2161886054 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2161886054 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2482626291 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2482626291 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 533136002 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 533136002 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89692006 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89692006 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 513974285 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 513974285 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 347500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 347500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4644512345 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4644512345 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5177648347 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5177648347 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 978236749 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 978236749 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 848797501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 848797501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1827034250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1827034250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033658 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033658 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025986 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025986 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.337897 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.337897 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051407 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051407 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.226809 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.226809 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030174 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030174 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033601 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033601 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13112.352791 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13112.352791 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23448.432988 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23448.432988 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15617.998652 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15617.998652 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16484.470869 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16484.470869 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21876.831744 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21876.831744 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17800.572621 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17800.572621 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17628.055488 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17628.055488 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17154.246888 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17154.246888 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16982.243681 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16982.243681 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171140.089048 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171140.089048 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169420.658882 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169420.658882 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170336.961589 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170336.961589 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 947666 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.322678 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 38831450 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 948178 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.953756 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 72138919500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.322678 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975240 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975240 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 1038832 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.324542 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 9157675 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 1039344 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 8.811014 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 72123856500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.324542 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975243 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975243 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 459 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 53 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 80507434 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 80507434 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 38831450 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 38831450 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 38831450 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 38831450 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 38831450 # number of overall hits -system.cpu1.icache.overall_hits::total 38831450 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 948178 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 948178 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 948178 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 948178 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 948178 # number of overall misses -system.cpu1.icache.overall_misses::total 948178 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8186316171 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8186316171 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8186316171 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8186316171 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8186316171 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8186316171 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 39779628 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 39779628 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 39779628 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 39779628 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 39779628 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 39779628 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023836 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023836 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023836 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023836 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023836 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023836 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8633.733509 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8633.733509 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8633.733509 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8633.733509 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8633.733509 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8633.733509 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 21433382 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21433382 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 9157675 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 9157675 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 9157675 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 9157675 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 9157675 # number of overall hits +system.cpu1.icache.overall_hits::total 9157675 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 1039344 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 1039344 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 1039344 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 1039344 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 1039344 # number of overall misses +system.cpu1.icache.overall_misses::total 1039344 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9221968883 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 9221968883 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 9221968883 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 9221968883 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 9221968883 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 9221968883 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 10197019 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 10197019 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 10197019 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 10197019 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 10197019 # 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average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8872.874508 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8872.874508 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1651,415 +1682,415 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 948178 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 948178 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 948178 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 948178 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 948178 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 948178 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7236829829 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7236829829 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7236829829 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7236829829 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7236829829 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7236829829 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10429000 # 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average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7632.353660 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7632.353660 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7632.353660 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7632.353660 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7632.353660 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 1039344 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 1039344 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 1039344 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 1039344 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 1039344 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 1039344 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8180244117 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8180244117 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8180244117 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8180244117 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8180244117 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8180244117 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10330000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10330000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10330000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10330000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.101926 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.101926 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.101926 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.101926 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.101926 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.101926 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7870.583865 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7870.583865 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7870.583865 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7870.583865 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7870.583865 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7870.583865 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92232.142857 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92232.142857 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92232.142857 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92232.142857 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 198185 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 198250 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 56 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 272919 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 272954 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 58438 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 54866 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15346.205956 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1177923 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 69767 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 16.883670 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 68790 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 69865 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15664.735857 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1313161 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 84814 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 15.482833 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 7899.614060 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 43.616627 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.093163 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4379.239024 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2180.842140 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 842.800943 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.482154 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002662 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.267288 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.133108 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051440 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.936658 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1047 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13803 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 662 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 384 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6041 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7452 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.063904 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.842468 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 22495354 # 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number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 20977 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 71094 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 92947 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28365 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28365 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22703 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22703 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34428 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 34428 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 655 # 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mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.358901 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.079449 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.947996 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.947996 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.958863 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.958863 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # 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mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.439737 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.936976 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.936976 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.955691 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.955691 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.482035 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.482035 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020897 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.075936 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026391 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.391744 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.101546 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020897 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.075936 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026391 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.391744 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.123779 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15573.986058 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18476.484941 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42252.287771 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 42252.287771 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15940.014772 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15940.014772 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15081.828305 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15081.828305 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 97000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 97000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32781.531259 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32781.531259 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21167.321458 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22327.514398 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16527.088550 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13585.972851 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28427.988829 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21167.321458 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42252.287771 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25481.924738 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.127580 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16899.951851 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21182.658462 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36122.588756 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36122.588756 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16664.330725 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16664.330725 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15034.151160 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15034.151160 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32245.566240 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32245.566240 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21936.337984 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24065.183685 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21936.337984 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36122.588756 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26525.578216 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83821.428571 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163134.141008 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161609.943377 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161902.894012 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161902.894012 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83821.428571 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162559.038691 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161745.363443 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1546268 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1215347 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11936 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11936 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 119475 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 29668 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 76508 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42110 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86467 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 85086 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 67037 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1896584 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 833808 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7155 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62301 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2799848 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60690688 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25792980 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11328 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 116228 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 86611224 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 603822 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1920664 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 3.272089 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.445035 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1679463 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1332654 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5010 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 138038 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 44141 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 76606 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42998 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 89660 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 97798 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 80302 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2078912 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 908693 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7242 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 71512 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3066359 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66525184 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29710243 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11536 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 135140 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 96382103 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 669363 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2146516 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.290923 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.454188 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 1398073 72.79% 72.79% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 522591 27.21% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 1522045 70.91% 70.91% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 624471 29.09% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1920664 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 837814982 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 2146516 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 922622470 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80458500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 87676498 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1423116171 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1560397383 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 410915491 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 459276108 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4323500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4359499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 33252737 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 37739490 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31003 # Transaction distribution -system.iobus.trans_dist::ReadResp 31003 # Transaction distribution +system.iobus.trans_dist::ReadReq 30987 # Transaction distribution +system.iobus.trans_dist::ReadResp 30987 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution system.iobus.trans_dist::WriteResp 23198 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution @@ -2068,7 +2099,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2084,16 +2115,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72906 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72906 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180818 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2109,10 +2140,10 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2483858 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) @@ -2123,7 +2154,7 @@ system.iobus.reqLayer3.occupancy 12000 # La system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 504000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2153,52 +2184,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198973953 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198858516 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36786758 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36733518 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36449 # number of replacements -system.iocache.tags.tagsinuse 14.479940 # Cycle average of tags in use +system.iocache.tags.replacements 36403 # number of replacements +system.iocache.tags.tagsinuse 1.010559 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36419 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270378265000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.479940 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.904996 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.904996 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270375766000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.010559 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.063160 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.063160 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328203 # Number of tag accesses -system.iocache.tags.data_accesses 328203 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses -system.iocache.ReadReq_misses::total 243 # number of ReadReq misses +system.iocache.tags.tag_accesses 328077 # Number of tag accesses +system.iocache.tags.data_accesses 328077 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 229 # number of ReadReq misses +system.iocache.ReadReq_misses::total 229 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses -system.iocache.demand_misses::total 243 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 243 # number of overall misses -system.iocache.overall_misses::total 243 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31380127 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31380127 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6638963068 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6638963068 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31380127 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31380127 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31380127 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31380127 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 229 # number of demand (read+write) misses +system.iocache.demand_misses::total 229 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 229 # number of overall misses +system.iocache.overall_misses::total 229 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 29476377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29476377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6677842621 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6677842621 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29476377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29476377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29476377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29476377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 229 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 229 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 229 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 229 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 229 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 229 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses @@ -2207,40 +2238,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129136.325103 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129136.325103 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183275.261374 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183275.261374 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 129136.325103 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 129136.325103 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 129136.325103 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 129136.325103 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22458 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128717.803493 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128717.803493 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 184348.570589 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 184348.570589 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128717.803493 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128717.803493 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128717.803493 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128717.803493 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 23020 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3415 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3484 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.576281 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.607348 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36206 # number of writebacks -system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36174 # number of writebacks +system.iocache.writebacks::total 36174 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 229 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 229 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18685627 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18685627 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4755299084 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4755299084 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18685627 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18685627 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18685627 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18685627 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 229 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 229 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 229 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 229 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17561377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17561377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4794158657 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4794158657 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17561377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17561377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17561377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17561377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2249,561 +2280,593 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76895.584362 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76895.584362 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131274.820119 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131274.820119 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76895.584362 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76895.584362 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76895.584362 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76895.584362 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76687.235808 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76687.235808 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 132347.577766 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 132347.577766 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76687.235808 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76687.235808 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76687.235808 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76687.235808 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 135638 # number of replacements -system.l2c.tags.tagsinuse 64035.864385 # Cycle average of tags in use -system.l2c.tags.total_refs 380564 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 200114 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.901736 # Average number of references to valid blocks. +system.l2c.tags.replacements 136197 # number of replacements +system.l2c.tags.tagsinuse 64163.282922 # Cycle average of tags in use +system.l2c.tags.total_refs 379817 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 200471 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.894623 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12087.017372 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 77.160254 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.033685 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8509.496822 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2877.165248 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35676.414678 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 13.500349 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2186.391247 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 567.991773 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2040.692959 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.184433 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001177 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.129845 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043902 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.544379 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000206 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.033362 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008667 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.031139 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.977110 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 30037 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 48 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 34391 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 135 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4776 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 25126 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 4 # 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average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17771.948923 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17815.447505 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79077.135895 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69691.543041 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 75064.022094 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78696.917808 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67786.821886 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75518.687414 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91740.464995 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73037.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70300.124184 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77572.373631 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110423.013938 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 88252.612732 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17835.761921 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17962.271539 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17876.422915 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17880.799257 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17771.656198 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17815.324244 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80402.981575 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69544.140830 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 75700.579190 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71846.153846 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68207.465922 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77572.664185 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90812.054018 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76892.857143 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70560.885515 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70775.623552 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122229.036396 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 86523.829726 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78696.917808 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67786.821886 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78257.137128 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91740.464995 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73037.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70300.124184 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71250.700931 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110423.013938 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 87000.263060 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71846.153846 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68207.465922 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77572.664185 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90812.054018 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76892.857143 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70560.885515 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70775.623552 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122229.036396 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 86523.829726 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67786.821886 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78257.137128 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91740.464995 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73037.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70300.124184 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71250.700931 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110423.013938 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 87000.263060 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 163641.771141 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60857.142857 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143630.996148 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151419.130592 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 136846.302312 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143297.904391 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 137883.111500 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151031.543401 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60857.142857 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 143475.354505 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 145373.407943 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 214962 # Transaction distribution -system.membus.trans_dist::ReadResp 214962 # Transaction distribution -system.membus.trans_dist::WriteReq 31066 # Transaction distribution -system.membus.trans_dist::WriteResp 31066 # Transaction distribution -system.membus.trans_dist::Writeback 138129 # Transaction distribution +system.membus.trans_dist::ReadReq 215059 # Transaction distribution +system.membus.trans_dist::ReadResp 215059 # Transaction distribution +system.membus.trans_dist::WriteReq 31175 # Transaction distribution +system.membus.trans_dist::WriteResp 31175 # Transaction distribution +system.membus.trans_dist::Writeback 138467 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 76255 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40796 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14193 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 40018 # Transaction distribution -system.membus.trans_dist::ReadExResp 19540 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 78265 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41611 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15010 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution +system.membus.trans_dist::ReadExReq 39963 # Transaction distribution +system.membus.trans_dist::ReadExResp 19392 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661851 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 783963 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 892875 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14788 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 665413 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 788151 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108866 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108866 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 897017 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19273388 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19465716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24102196 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123912 # Total snoops (count) -system.membus.snoop_fanout::samples 507941 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19282584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19476170 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4634432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4634432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24110602 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 126068 # Total snoops (count) +system.membus.snoop_fanout::samples 580884 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 507941 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 580884 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 507941 # Request fanout histogram -system.membus.reqLayer0.occupancy 88612000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 580884 # Request fanout histogram +system.membus.reqLayer0.occupancy 88642500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12528499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 13073499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1167691410 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1170162100 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1172073016 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1173257543 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37476242 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 37390482 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2836,44 +2899,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 516720 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 516705 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31066 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31066 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 232835 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 79932 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41134 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 121066 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51762 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51762 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1083099 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 338756 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1421855 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34093856 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5618324 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 39712180 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 288702 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 920160 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.039660 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.195160 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 519203 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 519188 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31175 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 233506 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 82002 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41949 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 123951 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51897 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51897 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1081118 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 347519 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1428637 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32891255 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6822675 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 39713930 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 293844 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 996034 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.036652 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.187907 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 883666 96.03% 96.03% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36494 3.97% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 959527 96.33% 96.33% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36507 3.67% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 920160 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 787000770 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 996034 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 791138952 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 342000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 321000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 681574777 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 673122022 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 259216519 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 273051412 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |