diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | 5064 |
1 files changed, 2532 insertions, 2532 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 14253ba3e..636a3faf7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,162 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.848172 # Number of seconds simulated -sim_ticks 2848172284000 # Number of ticks simulated -final_tick 2848172284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.848927 # Number of seconds simulated +sim_ticks 2848926718000 # Number of ticks simulated +final_tick 2848926718000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135409 # Simulator instruction rate (inst/s) -host_op_rate 163982 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3007675070 # Simulator tick rate (ticks/s) -host_mem_usage 625764 # Number of bytes of host memory used -host_seconds 946.97 # Real time elapsed on the host -sim_insts 128228197 # Number of instructions simulated -sim_ops 155285827 # Number of ops (including micro ops) simulated +host_inst_rate 113585 # Simulator instruction rate (inst/s) +host_op_rate 137549 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2529912934 # Simulator tick rate (ticks/s) +host_mem_usage 622248 # Number of bytes of host memory used +host_seconds 1126.10 # Real time elapsed on the host +sim_insts 127907365 # Number of instructions simulated +sim_ops 154893549 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 8960 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 9536 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1677760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1343340 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8401088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 221184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 660436 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 438272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1676224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1355764 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8486720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 229952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 664980 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 417216 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12753472 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1677760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 221184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1898944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9008896 # Number of bytes written to this memory +system.physmem.bytes_read::total 12842440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1676224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 229952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1906176 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9074368 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 9026460 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 140 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 9091932 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 149 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26215 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21511 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 131267 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10340 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26191 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21707 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 132605 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3593 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10411 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6519 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 199815 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 140764 # Number of write requests responded to by this memory +system.physmem.num_reads::total 201207 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 141787 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 145155 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3146 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 146178 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3347 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 589065 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 471650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2949642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 494 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 77658 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 231881 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 153878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 588370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 475886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2978918 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 80715 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 233414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 146447 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4477774 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 589065 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 77658 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 666724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3163045 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6153 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4507817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 588370 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 80715 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 669086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3185188 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3169211 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3163045 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3191353 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3185188 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3347 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 589065 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 477803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2949642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 77658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 231895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 153878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 588370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 482037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2978918 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 80715 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 233428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 146447 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7646985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 199815 # Number of read requests accepted -system.physmem.writeReqs 145155 # Number of write requests accepted -system.physmem.readBursts 199815 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 145155 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12777984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue -system.physmem.bytesWritten 9038976 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12753472 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9026460 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::total 7699170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 201207 # Number of read requests accepted +system.physmem.writeReqs 146178 # Number of write requests accepted +system.physmem.readBursts 201207 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 146178 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12868352 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue +system.physmem.bytesWritten 9104640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12842440 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9091932 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12196 # Per bank write bursts -system.physmem.perBankRdBursts::1 12508 # Per bank write bursts -system.physmem.perBankRdBursts::2 12943 # Per bank write bursts -system.physmem.perBankRdBursts::3 12617 # Per bank write bursts -system.physmem.perBankRdBursts::4 14662 # Per bank write bursts -system.physmem.perBankRdBursts::5 11885 # Per bank write bursts -system.physmem.perBankRdBursts::6 12499 # Per bank write bursts -system.physmem.perBankRdBursts::7 12704 # Per bank write bursts -system.physmem.perBankRdBursts::8 12537 # Per bank write bursts -system.physmem.perBankRdBursts::9 12319 # Per bank write bursts -system.physmem.perBankRdBursts::10 11826 # Per bank write bursts -system.physmem.perBankRdBursts::11 10998 # Per bank write bursts -system.physmem.perBankRdBursts::12 12485 # Per bank write bursts -system.physmem.perBankRdBursts::13 13119 # Per bank write bursts -system.physmem.perBankRdBursts::14 12369 # Per bank write bursts -system.physmem.perBankRdBursts::15 11989 # Per bank write bursts -system.physmem.perBankWrBursts::0 8816 # Per bank write bursts -system.physmem.perBankWrBursts::1 9166 # Per bank write bursts -system.physmem.perBankWrBursts::2 9495 # Per bank write bursts -system.physmem.perBankWrBursts::3 9136 # Per bank write bursts -system.physmem.perBankWrBursts::4 8038 # Per bank write bursts -system.physmem.perBankWrBursts::5 8411 # Per bank write bursts -system.physmem.perBankWrBursts::6 8988 # Per bank write bursts -system.physmem.perBankWrBursts::7 8984 # Per bank write bursts -system.physmem.perBankWrBursts::8 9026 # Per bank write bursts -system.physmem.perBankWrBursts::9 8762 # Per bank write bursts -system.physmem.perBankWrBursts::10 8598 # Per bank write bursts -system.physmem.perBankWrBursts::11 8287 # Per bank write bursts -system.physmem.perBankWrBursts::12 9114 # Per bank write bursts -system.physmem.perBankWrBursts::13 9118 # Per bank write bursts -system.physmem.perBankWrBursts::14 8888 # Per bank write bursts -system.physmem.perBankWrBursts::15 8407 # Per bank write bursts +system.physmem.perBankRdBursts::0 12387 # Per bank write bursts +system.physmem.perBankRdBursts::1 12818 # Per bank write bursts +system.physmem.perBankRdBursts::2 13574 # Per bank write bursts +system.physmem.perBankRdBursts::3 13051 # Per bank write bursts +system.physmem.perBankRdBursts::4 15332 # Per bank write bursts +system.physmem.perBankRdBursts::5 12655 # Per bank write bursts +system.physmem.perBankRdBursts::6 12896 # Per bank write bursts +system.physmem.perBankRdBursts::7 13054 # Per bank write bursts +system.physmem.perBankRdBursts::8 12485 # Per bank write bursts +system.physmem.perBankRdBursts::9 12494 # Per bank write bursts +system.physmem.perBankRdBursts::10 11451 # Per bank write bursts +system.physmem.perBankRdBursts::11 10701 # Per bank write bursts +system.physmem.perBankRdBursts::12 11947 # Per bank write bursts +system.physmem.perBankRdBursts::13 12784 # Per bank write bursts +system.physmem.perBankRdBursts::14 11815 # Per bank write bursts +system.physmem.perBankRdBursts::15 11624 # Per bank write bursts +system.physmem.perBankWrBursts::0 9013 # Per bank write bursts +system.physmem.perBankWrBursts::1 9459 # Per bank write bursts +system.physmem.perBankWrBursts::2 10048 # Per bank write bursts +system.physmem.perBankWrBursts::3 9447 # Per bank write bursts +system.physmem.perBankWrBursts::4 8653 # Per bank write bursts +system.physmem.perBankWrBursts::5 8898 # Per bank write bursts +system.physmem.perBankWrBursts::6 9273 # Per bank write bursts +system.physmem.perBankWrBursts::7 9228 # Per bank write bursts +system.physmem.perBankWrBursts::8 8869 # Per bank write bursts +system.physmem.perBankWrBursts::9 8977 # Per bank write bursts +system.physmem.perBankWrBursts::10 8270 # Per bank write bursts +system.physmem.perBankWrBursts::11 7926 # Per bank write bursts +system.physmem.perBankWrBursts::12 8743 # Per bank write bursts +system.physmem.perBankWrBursts::13 8906 # Per bank write bursts +system.physmem.perBankWrBursts::14 8530 # Per bank write bursts +system.physmem.perBankWrBursts::15 8020 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 34 # Number of times write queue was full causing retry -system.physmem.totGap 2848171745000 # Total gap between requests +system.physmem.numWrRetry 92 # Number of times write queue was full causing retry +system.physmem.totGap 2848926179000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 552 # Read request sizes (log2) +system.physmem.readPktSize::2 554 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 199235 # Read request sizes (log2) +system.physmem.readPktSize::6 200625 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 140764 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 87471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61591 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3767 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 141787 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 84607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6758 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5703 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3992 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -185,162 +185,178 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 88 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88570 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 246.323767 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 141.050118 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 301.878369 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 44937 50.74% 50.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18529 20.92% 71.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6585 7.43% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3856 4.35% 83.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3004 3.39% 86.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1517 1.71% 88.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 921 1.04% 89.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1037 1.17% 90.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8184 9.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88570 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7038 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.368144 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 555.266808 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7037 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8671 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 295 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 89804 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 244.676495 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.021398 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 301.276619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45910 51.12% 51.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18733 20.86% 71.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6663 7.42% 79.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3737 4.16% 83.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2991 3.33% 86.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1528 1.70% 88.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 943 1.05% 89.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1048 1.17% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8251 9.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 89804 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7084 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.382976 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 553.950604 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7082 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7038 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7038 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.067349 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.571017 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.392738 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5944 84.46% 84.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 388 5.51% 89.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 60 0.85% 90.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 46 0.65% 91.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 266 3.78% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.30% 95.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 22 0.31% 95.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 25 0.36% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 15 0.21% 96.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 13 0.18% 96.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 13 0.18% 96.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 149 2.12% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.07% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.10% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 11 0.16% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.09% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.06% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 7 0.10% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 9 0.13% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.11% 99.83% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7084 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7084 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.081875 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.511113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.183489 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5975 84.35% 84.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 419 5.91% 90.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 68 0.96% 91.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 50 0.71% 91.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 261 3.68% 95.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.30% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 13 0.18% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 17 0.24% 96.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 10 0.14% 96.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.08% 96.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.11% 96.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 9 0.13% 96.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 144 2.03% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 9 0.13% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.07% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.06% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 8 0.11% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 5 0.07% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 9 0.13% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.04% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.04% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.16% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.06% 99.83% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 3 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7038 # Writes before turning the bus around for reads -system.physmem.totQLat 5532611303 # Total ticks spent queuing -system.physmem.totMemAccLat 9276161303 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 998280000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27710.72 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 3 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7084 # Writes before turning the bus around for reads +system.physmem.totQLat 9521946881 # Total ticks spent queuing +system.physmem.totMemAccLat 13291971881 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1005340000 # Total ticks spent in databus transfers +system.physmem.avgQLat 47356.85 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46460.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.48 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.17 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 66106.85 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.20 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.19 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.18 # Average write queue length when enqueuing -system.physmem.readRowHits 165300 # Number of row buffer hits during reads -system.physmem.writeRowHits 87019 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.79 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.60 # Row buffer hit rate for writes -system.physmem.avgGap 8256288.21 # Average gap between requests -system.physmem.pageHitRate 74.01 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 339738840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 185373375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 795709200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 460300320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186028705200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83305465515 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1635827969250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1906943261700 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.532441 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2721218544299 # Time in different power states -system.physmem_0.memoryStateTime::REF 95106700000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31846334451 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 329850360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179977875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 761599800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 454896000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186028705200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82993384530 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1636101724500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1906850138265 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.499746 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2721674822130 # Time in different power states -system.physmem_1.memoryStateTime::REF 95106700000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31390664370 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 25.49 # Average write queue length when enqueuing +system.physmem.readRowHits 166479 # Number of row buffer hits during reads +system.physmem.writeRowHits 87044 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.80 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.18 # Row buffer hit rate for writes +system.physmem.avgGap 8201062.74 # Average gap between requests +system.physmem.pageHitRate 73.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 339864000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 180642000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 755176380 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 386379180 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5802201600.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5394350610 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 323555040 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 11564942040 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8568107520 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 670261966035 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 703579433835 # Total energy per rank (pJ) +system.physmem_0.averagePower 246.962980 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2836248193267 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 586826713 # Time in different power states +system.physmem_0.memoryStateTime::REF 2465512000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2788574898250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 22312648073 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9624892520 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 25361940444 # Time in different power states +system.physmem_1.actEnergy 301343700 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 160164180 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 680449140 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 356218020 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5736435120.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5416162800 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 310781280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10711678260 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8807078880 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 670588805775 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 703071916065 # Total energy per rank (pJ) +system.physmem_1.averagePower 246.784837 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2836233678907 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 556712196 # Time in different power states +system.physmem_1.memoryStateTime::REF 2438058000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2789808007000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 22935120354 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9698204397 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 23490616053 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory @@ -359,30 +375,30 @@ system.realview.nvmem.bw_inst_read::total 472 # I system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 20844041 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13655604 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1017556 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 13118749 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 8767800 # Number of BTB hits +system.cpu0.branchPred.lookups 20832099 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13651765 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1014112 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13085676 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 8745572 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.834117 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3422259 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 208349 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 764708 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 581484 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 183224 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 100888 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 66.833169 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3412344 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 213562 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 762387 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 580471 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 181916 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 99152 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -412,61 +428,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 67283 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 67283 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46446 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20837 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 67283 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 67283 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 67283 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6844 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12453.243717 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11569.675575 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5895.982503 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6363 92.97% 92.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 412 6.02% 98.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 59 0.86% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 3 0.04% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.07% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6844 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 338010000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 338010000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 338010000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5263 76.90% 76.90% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1581 23.10% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6844 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67283 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 65584 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 65584 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44931 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20653 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 65584 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 65584 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 65584 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6815 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12330.961115 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11272.043541 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 9573.930789 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 6808 99.90% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 5 0.07% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6815 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 338892000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 338892000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 338892000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5268 77.30% 77.30% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1547 22.70% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6815 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65584 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67283 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6844 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65584 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6815 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6844 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 74127 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6815 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 72399 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17352300 # DTB read hits -system.cpu0.dtb.read_misses 60872 # DTB read misses -system.cpu0.dtb.write_hits 14551648 # DTB write hits -system.cpu0.dtb.write_misses 6411 # DTB write misses +system.cpu0.dtb.read_hits 17333612 # DTB read hits +system.cpu0.dtb.read_misses 59171 # DTB read misses +system.cpu0.dtb.write_hits 14536785 # DTB write hits +system.cpu0.dtb.write_misses 6413 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3450 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1427 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1946 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3455 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1366 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1951 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 519 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17413172 # DTB read accesses -system.cpu0.dtb.write_accesses 14558059 # DTB write accesses +system.cpu0.dtb.perms_faults 521 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17392783 # DTB read accesses +system.cpu0.dtb.write_accesses 14543198 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31903948 # DTB hits -system.cpu0.dtb.misses 67283 # DTB misses -system.cpu0.dtb.accesses 31971231 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 31870397 # DTB hits +system.cpu0.dtb.misses 65584 # DTB misses +system.cpu0.dtb.accesses 31935981 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -496,42 +509,41 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 3992 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3992 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3686 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3992 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3992 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3992 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2438 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12900.533224 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 12073.120538 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5370.959057 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 392 16.08% 16.08% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1803 73.95% 90.03% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 168 6.89% 96.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 38 1.56% 98.48% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 34 1.39% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2438 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 337545500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 337545500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 337545500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2137 87.65% 87.65% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 301 12.35% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2438 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 3993 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3993 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 304 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3689 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3993 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3993 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3993 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2420 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12562.190083 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11733.706609 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5199.448662 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 453 18.72% 18.72% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1764 72.89% 91.61% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 139 5.74% 97.36% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 98.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 27 1.12% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2420 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 338263500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 338263500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 338263500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2121 87.64% 87.64% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 299 12.36% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2420 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3992 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3992 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3993 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3993 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2438 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2438 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6430 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 38811638 # ITB inst hits -system.cpu0.itb.inst_misses 3992 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2420 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2420 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6413 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 38722571 # ITB inst hits +system.cpu0.itb.inst_misses 3993 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -540,45 +552,44 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2175 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7061 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7056 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 38815630 # ITB inst accesses -system.cpu0.itb.hits 38811638 # DTB hits -system.cpu0.itb.misses 3992 # DTB misses -system.cpu0.itb.accesses 38815630 # DTB accesses -system.cpu0.numPwrStateTransitions 3698 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1849 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1494392801.532720 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23960009045.887756 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1074 58.09% 58.09% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 768 41.54% 99.62% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.68% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.05% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 38726564 # ITB inst accesses +system.cpu0.itb.hits 38722571 # DTB hits +system.cpu0.itb.misses 3993 # DTB misses +system.cpu0.itb.accesses 38726564 # DTB accesses +system.cpu0.numPwrStateTransitions 3692 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1846 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1496527734.232936 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23959432114.332718 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1066 57.75% 57.75% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 773 41.87% 99.62% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499963441540 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1849 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 85039993966 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2763132290034 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 170082548 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499963466540 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1846 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 86336520606 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2762590197394 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 172675597 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 79775908 # Number of instructions committed -system.cpu0.committedOps 96002231 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 5290576 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1849 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5526291371 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.132004 # CPI: cycles per instruction -system.cpu0.ipc 0.469042 # IPC: instructions per cycle +system.cpu0.committedInsts 79702454 # Number of instructions committed +system.cpu0.committedOps 95912008 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 5263315 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1846 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5525206368 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.166503 # CPI: cycles per instruction +system.cpu0.ipc 0.461573 # IPC: instructions per cycle system.cpu0.op_class_0::No_OpClass 2273 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 63778191 66.43% 66.44% # Class of committed instruction -system.cpu0.op_class_0::IntMult 92152 0.10% 66.53% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 63720470 66.44% 66.44% # Class of committed instruction +system.cpu0.op_class_0::IntMult 92091 0.10% 66.53% # Class of committed instruction system.cpu0.op_class_0::IntDiv 0 0.00% 66.53% # Class of committed instruction system.cpu0.op_class_0::FloatAdd 0 0.00% 66.53% # Class of committed instruction system.cpu0.op_class_0::FloatCmp 0 0.00% 66.53% # Class of committed instruction @@ -602,740 +613,739 @@ system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.53% # Cl system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.53% # Class of committed instruction system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.53% # Class of committed instruction system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 8115 0.01% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 8071 0.01% 66.54% # Class of committed instruction system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.54% # Class of committed instruction system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.54% # Class of committed instruction system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::MemRead 16825163 17.53% 84.07% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 15296337 15.93% 100.00% # Class of committed instruction +system.cpu0.op_class_0::MemRead 16807812 17.52% 84.07% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 15281291 15.93% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 96002231 # Class of committed instruction +system.cpu0.op_class_0::total 95912008 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1849 # number of quiesce instructions executed -system.cpu0.tickCycles 121004168 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 49078380 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 716277 # number of replacements -system.cpu0.dcache.tags.tagsinuse 496.364938 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 30460734 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 716789 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 42.496096 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 356009000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.364938 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.969463 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.969463 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1846 # number of quiesce instructions executed +system.cpu0.tickCycles 120803038 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 51872559 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 716043 # number of replacements +system.cpu0.dcache.tags.tagsinuse 497.070686 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 30430864 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 716555 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 42.468288 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 356904000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.070686 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970841 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.970841 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 74 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63863131 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63863131 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 15863909 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15863909 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 13436402 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 13436402 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320993 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 320993 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365530 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365530 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361278 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361278 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 29300311 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 29300311 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 29621304 # number of overall hits -system.cpu0.dcache.overall_hits::total 29621304 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 439369 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 439369 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 580672 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 580672 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 135956 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 135956 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21086 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21086 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20448 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20448 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1020041 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1020041 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1155997 # number of overall misses -system.cpu0.dcache.overall_misses::total 1155997 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6148409000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6148409000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10121621500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10121621500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 324178500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 324178500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 483049500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 483049500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 688000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 688000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 16270030500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 16270030500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 16270030500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 16270030500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16303278 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16303278 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 14017074 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 14017074 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456949 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 456949 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386616 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386616 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381726 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381726 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30320352 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30320352 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30777301 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30777301 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026950 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.026950 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041426 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.041426 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.297530 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.297530 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054540 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054540 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053567 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053567 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033642 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.033642 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037560 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.037560 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13993.725092 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13993.725092 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17430.875778 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17430.875778 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15374.110784 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15374.110784 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23623.312793 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23623.312793 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63800570 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63800570 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 15847676 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15847676 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 13422923 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 13422923 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320765 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 320765 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365692 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365692 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361178 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361178 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 29270599 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 29270599 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 29591364 # number of overall hits +system.cpu0.dcache.overall_hits::total 29591364 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 438302 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 438302 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 581071 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 581071 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 135874 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 135874 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20748 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20748 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20391 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20391 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1019373 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1019373 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1155247 # number of overall misses +system.cpu0.dcache.overall_misses::total 1155247 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6426011500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6426011500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11337499000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 11337499000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330321500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 330321500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 481265000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 481265000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 655500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 655500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 17763510500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 17763510500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 17763510500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 17763510500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16285978 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16285978 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 14003994 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 14003994 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456639 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 456639 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386440 # 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miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.297552 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.297552 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053690 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053690 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053440 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053440 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033654 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.033654 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037573 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.037573 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14661.150303 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14661.150303 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19511.383291 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19511.383291 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15920.642954 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15920.642954 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23601.834143 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23601.834143 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15950.369152 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15950.369152 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14074.457373 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14074.457373 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17425.918187 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 17425.918187 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15376.374490 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15376.374490 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 716277 # number of writebacks -system.cpu0.dcache.writebacks::total 716277 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44943 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 44943 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255413 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 255413 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14625 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14625 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 300356 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 300356 # 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number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5005155000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5005155000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5561809000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5561809000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1663563000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1663563000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98784500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98784500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 462621500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 462621500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 668000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 668000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10566964000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10566964000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12230527000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12230527000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4556252000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4556252000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4556252000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4556252000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024193 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024193 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023204 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023204 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224069 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224069 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016712 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016712 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053567 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053567 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023736 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023736 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026710 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026710 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12689.718731 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12689.718731 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17099.631371 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17099.631371 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16247.636442 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16247.636442 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15289.351494 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15289.351494 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22624.290884 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22624.290884 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 716044 # number of writebacks +system.cpu0.dcache.writebacks::total 716044 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44411 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 44411 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255478 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 255478 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14411 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14411 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 299889 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 299889 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 299889 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 299889 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 393891 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 393891 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325593 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 325593 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102318 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 102318 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6337 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6337 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20391 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20391 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 719484 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 719484 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 821802 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 821802 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20577 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20577 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19270 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19270 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39847 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39847 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5265212000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5265212000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6193589500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6193589500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1698431500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1698431500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 100630000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100630000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 460892000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 460892000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 637500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 637500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11458801500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11458801500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13157233000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13157233000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4606601500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4606601500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4606601500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4606601500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024186 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024186 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023250 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023250 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224068 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224068 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016398 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016398 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053440 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053440 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023753 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023753 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026728 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026728 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13367.180261 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13367.180261 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19022.489734 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19022.489734 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16599.537716 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16599.537716 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15879.753827 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15879.753827 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22602.716885 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22602.716885 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14682.762598 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14682.762598 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14877.665365 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14877.665365 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223520.996860 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223520.996860 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115438.749398 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115438.749398 # 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average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15926.416015 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16010.222657 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16010.222657 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223871.385528 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223871.385528 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115607.235175 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115607.235175 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1964076 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.773099 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36750687 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1964588 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.706562 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6697445000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.773099 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999557 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999557 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 104 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 79579816 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 79579816 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 36833218 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36833218 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36833218 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36833218 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36833218 # number of overall hits -system.cpu0.icache.overall_hits::total 36833218 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1971127 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1971127 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1971127 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1971127 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1971127 # number of overall misses -system.cpu0.icache.overall_misses::total 1971127 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 19380486500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 19380486500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 19380486500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 19380486500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 19380486500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 19380486500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 38804345 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 38804345 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 38804345 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 38804345 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 38804345 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 38804345 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050797 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050797 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050797 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050797 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050797 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050797 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9832.185597 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9832.185597 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9832.185597 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9832.185597 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9832.185597 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9832.185597 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 79395176 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 79395176 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 36750687 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36750687 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36750687 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36750687 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36750687 # number of overall hits +system.cpu0.icache.overall_hits::total 36750687 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1964601 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1964601 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1964601 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1964601 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1964601 # number of overall misses +system.cpu0.icache.overall_misses::total 1964601 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 19791309500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 19791309500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 19791309500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 19791309500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 19791309500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 19791309500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 38715288 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 38715288 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 38715288 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 38715288 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 38715288 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 38715288 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050745 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050745 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050745 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050745 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050745 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050745 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10073.958783 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10073.958783 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10073.958783 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10073.958783 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10073.958783 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10073.958783 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1970602 # number of writebacks -system.cpu0.icache.writebacks::total 1970602 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1971127 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1971127 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1971127 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1971127 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1971127 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1971127 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3448 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 3448 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3448 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 3448 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 18394923500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 18394923500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 18394923500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 18394923500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 18394923500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 18394923500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 319413000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 319413000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 319413000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 319413000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050797 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050797 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050797 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.050797 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050797 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.050797 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9332.185851 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9332.185851 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9332.185851 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9332.185851 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9332.185851 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9332.185851 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92637.180974 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92637.180974 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92637.180974 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92637.180974 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1842994 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1843099 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 91 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.writebacks::writebacks 1964076 # number of writebacks +system.cpu0.icache.writebacks::total 1964076 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1964601 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1964601 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1964601 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1964601 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1964601 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1964601 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 3277 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 3277 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 18809009500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 18809009500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 18809009500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 18809009500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 18809009500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 18809009500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 323882000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 323882000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 323882000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 323882000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050745 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050745 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050745 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.050745 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050745 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.050745 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9573.959038 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9573.959038 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9573.959038 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9573.959038 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9573.959038 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9573.959038 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98834.909979 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98834.909979 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1843459 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1843558 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 87 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # 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average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38321.366749 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24124.678165 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24124.678165 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29462.621885 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17290.055249 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38321.366749 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28328.993195 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31984.995219 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29462.621885 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17290.055249 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38321.366749 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28328.993195 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54426.267559 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43487.383325 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215516.311813 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196580.794730 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111304.682156 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109162.185148 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 5528539 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2785631 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 220679 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 216467 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4212 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 119671 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2643248 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19085 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19085 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 716138 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 2204203 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 105351 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 312801 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 88645 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43001 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114336 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 287716 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284337 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1971127 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 603215 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3113 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5919751 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2595390 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13207 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 168847 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 8697195 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 252491264 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99508828 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22116 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 322908 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 352345116 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 940127 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 19140516 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 3787201 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.076346 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.269706 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.181890 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41808.681672 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17453.333333 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38435.364728 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63655.903730 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63655.903730 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17349.847789 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17349.847789 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15060.200981 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15060.200981 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 499499 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 499499 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50864.680672 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50864.680672 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43407.069133 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43407.069133 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26866.440514 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26866.440514 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41808.681672 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17453.333333 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43407.069133 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33432.804868 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37131.537597 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41808.681672 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17453.333333 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43407.069133 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33432.804868 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63655.903730 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50784.937791 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215865.626671 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198689.234510 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111473.059452 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109904.763009 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 5514708 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2778846 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42068 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 220650 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 216436 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4214 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 117829 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2634124 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19270 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19270 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 714129 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 2198813 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 105915 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 313152 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 88836 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42982 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114292 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 287887 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284399 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1964601 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 602822 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3087 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5899831 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2594741 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13052 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 164810 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 8672434 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 251644992 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99451448 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 21480 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314292 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 351432212 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 940964 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 19090924 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3779220 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.076318 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.269673 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3502276 92.48% 92.48% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 280713 7.41% 99.89% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4212 0.11% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3495013 92.48% 92.48% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 279993 7.41% 99.89% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4214 0.11% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3787201 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 5519275492 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3779220 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 5504902494 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 116183079 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115882925 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2962129461 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2952081467 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1227256511 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1226789533 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7683988 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7686990 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 88134970 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 86252968 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 19426531 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6224342 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 651829 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 10038478 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3634441 # Number of BTB hits +system.cpu1.branchPred.lookups 19393527 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6185527 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 769783 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 9956759 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3606289 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 36.205100 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 8674574 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 447731 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3678807 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 3614078 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 64729 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 23620 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 36.219507 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8702764 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 566393 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3646067 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 3582470 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 63597 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 23601 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1365,66 +1375,58 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 27735 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 27735 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 21301 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6434 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 27735 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 27735 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 27735 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2744 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12429.118076 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11482.413236 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6276.586572 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 644 23.47% 23.47% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1820 66.33% 89.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 198 7.22% 97.01% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 63 2.30% 99.31% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 9 0.33% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 4 0.15% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.04% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.04% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.04% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2744 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1939283032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1939283032 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1939283032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 2036 74.20% 74.20% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 708 25.80% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2744 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 27735 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 26638 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 26638 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20208 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6430 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 26638 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 26638 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 26638 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2684 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12533.532042 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11490.379150 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 8690.810286 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 2656 98.96% 98.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 26 0.97% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2684 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1849661032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1849661032 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1849661032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1998 74.44% 74.44% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 686 25.56% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2684 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26638 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 27735 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2744 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26638 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2684 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2744 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 30479 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2684 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 29322 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 11374009 # DTB read hits -system.cpu1.dtb.read_misses 25676 # DTB read misses -system.cpu1.dtb.write_hits 7084428 # DTB write hits -system.cpu1.dtb.write_misses 2059 # DTB write misses +system.cpu1.dtb.read_hits 11320530 # DTB read hits +system.cpu1.dtb.read_misses 24586 # DTB read misses +system.cpu1.dtb.write_hits 7061626 # DTB write hits +system.cpu1.dtb.write_misses 2052 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1996 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 172 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 434 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1992 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 148 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 300 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 262 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 11399685 # DTB read accesses -system.cpu1.dtb.write_accesses 7086487 # DTB write accesses +system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 11345116 # DTB read accesses +system.cpu1.dtb.write_accesses 7063678 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 18458437 # DTB hits -system.cpu1.dtb.misses 27735 # DTB misses -system.cpu1.dtb.accesses 18486172 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 18382156 # DTB hits +system.cpu1.dtb.misses 26638 # DTB misses +system.cpu1.dtb.accesses 18408794 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1454,46 +1456,45 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 2480 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2480 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 2499 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2499 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 180 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2300 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2480 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2480 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2480 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1130 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12659.734513 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11853.270475 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5315.711785 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 183 16.19% 16.19% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 614 54.34% 70.53% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 213 18.85% 89.38% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 45 3.98% 93.36% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 23 2.04% 95.40% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.48% 97.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 15 1.33% 99.20% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.18% 99.38% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 4 0.35% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::53248-57343 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1130 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1939872532 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1939872532 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1939872532 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 965 85.40% 85.40% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 165 14.60% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1130 # Table walker page sizes translated +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2319 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2499 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2499 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2499 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1128 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12699.024823 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11989.496313 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4984.320484 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 166 14.72% 14.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 634 56.21% 70.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 206 18.26% 89.18% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.34% 93.53% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 22 1.95% 95.48% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.48% 97.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.42% 99.38% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 99.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 2 0.18% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1128 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1850303532 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1850303532 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1850303532 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 963 85.37% 85.37% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 165 14.63% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1128 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2480 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2480 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2499 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2499 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1130 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1130 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3610 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 39704875 # ITB inst hits -system.cpu1.itb.inst_misses 2480 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1128 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1128 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3627 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 39699373 # ITB inst hits +system.cpu1.itb.inst_misses 2499 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1502,777 +1503,777 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1100 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1101 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1840 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1838 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 39707355 # ITB inst accesses -system.cpu1.itb.hits 39704875 # DTB hits -system.cpu1.itb.misses 2480 # DTB misses -system.cpu1.itb.accesses 39707355 # DTB accesses -system.cpu1.numPwrStateTransitions 5533 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2767 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1008221990.514637 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25700822378.312321 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1966 71.05% 71.05% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 797 28.80% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 39701872 # ITB inst accesses +system.cpu1.itb.hits 39699373 # DTB hits +system.cpu1.itb.misses 2499 # DTB misses +system.cpu1.itb.accesses 39701872 # DTB accesses +system.cpu1.numPwrStateTransitions 5523 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2762 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1010212132.618392 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25718871891.755051 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1964 71.11% 71.11% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 794 28.75% 99.86% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 949980874116 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2767 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 58422036246 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2789750247754 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 116847616 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 949979704076 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2762 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 58720807708 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2790205910292 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 117445100 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48452289 # Number of instructions committed -system.cpu1.committedOps 59283596 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 5163197 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2767 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5578862239 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.411602 # CPI: cycles per instruction -system.cpu1.ipc 0.414662 # IPC: instructions per cycle +system.cpu1.committedInsts 48204911 # Number of instructions committed +system.cpu1.committedOps 58981541 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 5132548 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2762 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5579768700 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.436372 # CPI: cycles per instruction +system.cpu1.ipc 0.410446 # IPC: instructions per cycle system.cpu1.op_class_0::No_OpClass 66 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 40834570 68.88% 68.88% # Class of committed instruction -system.cpu1.op_class_0::IntMult 45625 0.08% 68.96% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 3333 0.01% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.96% # Class of committed instruction -system.cpu1.op_class_0::MemRead 11200779 18.89% 87.86% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 7199223 12.14% 100.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 40607989 68.85% 68.85% # Class of committed instruction +system.cpu1.op_class_0::IntMult 45709 0.08% 68.93% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 3353 0.01% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.93% # Class of committed instruction +system.cpu1.op_class_0::MemRead 11147247 18.90% 87.83% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 7177177 12.17% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 59283596 # Class of committed instruction +system.cpu1.op_class_0::total 58981541 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2767 # number of quiesce instructions executed -system.cpu1.tickCycles 94150450 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 22697166 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 195596 # number of replacements -system.cpu1.dcache.tags.tagsinuse 473.279573 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 18031187 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 195963 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 92.013222 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 91237126000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.279573 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.924374 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.924374 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 57 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.716797 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 36965565 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 36965565 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 10998874 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10998874 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6796614 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6796614 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50142 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50142 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80008 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 80008 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71567 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71567 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 17795488 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 17795488 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 17845630 # number of overall hits -system.cpu1.dcache.overall_hits::total 17845630 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 148727 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 148727 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 145387 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 145387 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30687 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30687 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16966 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16966 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23611 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23611 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 294114 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 294114 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 324801 # number of overall misses -system.cpu1.dcache.overall_misses::total 324801 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2356620500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2356620500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3915884500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3915884500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 322199000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 322199000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 556849500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 556849500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 389000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 389000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6272505000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6272505000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6272505000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6272505000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11147601 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11147601 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6942001 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6942001 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80829 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 80829 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96974 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96974 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95178 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95178 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 18089602 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 18089602 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 18170431 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 18170431 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013342 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.013342 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.020943 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.020943 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379653 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379653 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174954 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174954 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248072 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248072 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.016259 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.016259 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.017875 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.017875 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15845.276917 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15845.276917 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26934.213513 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 26934.213513 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18990.864081 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18990.864081 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23584.325103 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23584.325103 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2762 # number of quiesce instructions executed +system.cpu1.tickCycles 94223774 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 23221326 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 197231 # number of replacements +system.cpu1.dcache.tags.tagsinuse 476.160023 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 17961880 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 197583 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 90.908023 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 91326739500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 476.160023 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.930000 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.930000 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 69 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 36815018 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 36815018 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 10942799 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10942799 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6773317 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6773317 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50710 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50710 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80304 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 80304 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71747 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71747 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 17716116 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 17716116 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 17766826 # number of overall hits +system.cpu1.dcache.overall_hits::total 17766826 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 150509 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 150509 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 145770 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 145770 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30651 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30651 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16960 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16960 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23697 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23697 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 296279 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 296279 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 326930 # number of overall misses +system.cpu1.dcache.overall_misses::total 326930 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2503108000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2503108000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4131089000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4131089000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325863000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 325863000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557327500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 557327500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 612000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 612000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6634197000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6634197000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6634197000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6634197000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11093308 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11093308 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6919087 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6919087 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81361 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 81361 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97264 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97264 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95444 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95444 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 18012395 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 18012395 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 18093756 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 18093756 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013568 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.013568 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021068 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.021068 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.376728 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.376728 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174371 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174371 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248282 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248282 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.016449 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.016449 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018069 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.018069 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16630.952302 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16630.952302 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28339.774988 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 28339.774988 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19213.620283 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19213.620283 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23518.905347 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23518.905347 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21326.781452 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 21326.781452 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19311.840173 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 19311.840173 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22391.721992 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 22391.721992 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20292.408161 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20292.408161 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 195596 # number of writebacks -system.cpu1.dcache.writebacks::total 195596 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 5710 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 5710 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52879 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 52879 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12082 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12082 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 58589 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 58589 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 58589 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 58589 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 143017 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 143017 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92508 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 92508 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29859 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29859 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4884 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4884 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23611 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23611 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 235525 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 235525 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 265384 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 265384 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14595 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14595 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11928 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11928 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26523 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26523 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2115141000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2115141000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2362860000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2362860000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 507235000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 507235000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82984000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82984000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 533247500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 533247500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 380000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 380000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4478001000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4478001000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4985236000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4985236000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2537758000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2537758000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2537758000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2537758000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.012829 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.012829 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013326 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013326 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369409 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369409 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050364 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050364 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248072 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248072 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013020 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.013020 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014605 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.014605 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14789.437619 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14789.437619 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25542.223375 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25542.223375 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16987.675408 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16987.675408 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16990.990991 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16990.990991 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22584.706281 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22584.706281 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 197231 # number of writebacks +system.cpu1.dcache.writebacks::total 197231 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 5831 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 5831 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53065 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 53065 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12062 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12062 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 58896 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 58896 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 58896 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 58896 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 144678 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 144678 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92705 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 92705 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29814 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29814 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4898 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4898 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23697 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23697 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 237383 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 237383 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 267197 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 267197 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14423 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14423 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11756 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11756 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26179 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26179 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2254716500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2254716500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2475419500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2475419500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 516532000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 516532000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86654500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86654500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 533644500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 533644500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 598000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 598000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4730136000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4730136000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5246668000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5246668000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2493280000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2493280000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2493280000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2493280000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013042 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013042 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013398 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013398 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.366441 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.366441 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050358 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050358 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248282 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248282 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013179 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.013179 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014767 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.014767 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15584.377030 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15584.377030 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26702.114233 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26702.114233 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17325.149259 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17325.149259 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17691.812985 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17691.812985 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22519.496139 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22519.496139 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19012.847893 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19012.847893 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18784.990806 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18784.990806 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173878.588558 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173878.588558 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95681.408589 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95681.408589 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 948026 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.199607 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 38754409 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 948538 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.856991 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 72914784000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.199607 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974999 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974999 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19926.178370 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19926.178370 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19635.953996 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19635.953996 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172868.335298 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172868.335298 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95239.695939 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95239.695939 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 951926 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.186802 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 38745002 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 952438 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.679815 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 73025806000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.186802 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974974 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974974 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 461 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 80354432 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 80354432 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 38754409 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 38754409 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 38754409 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 38754409 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 38754409 # number of overall hits -system.cpu1.icache.overall_hits::total 38754409 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 948538 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 948538 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 948538 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 948538 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 948538 # number of overall misses -system.cpu1.icache.overall_misses::total 948538 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8680888000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8680888000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8680888000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8680888000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8680888000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8680888000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 39702947 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 39702947 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 39702947 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 39702947 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 39702947 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 39702947 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023891 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023891 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023891 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023891 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023891 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023891 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9151.861075 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9151.861075 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9151.861075 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9151.861075 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9151.861075 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9151.861075 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 80347318 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 80347318 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 38745002 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 38745002 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 38745002 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 38745002 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 38745002 # number of overall hits +system.cpu1.icache.overall_hits::total 38745002 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 952438 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 952438 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 952438 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 952438 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 952438 # number of overall misses +system.cpu1.icache.overall_misses::total 952438 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8816320000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8816320000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8816320000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8816320000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8816320000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8816320000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 39697440 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 39697440 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 39697440 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 39697440 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 39697440 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 39697440 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023992 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.023992 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023992 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.023992 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023992 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.023992 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9256.581531 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9256.581531 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9256.581531 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9256.581531 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9256.581531 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9256.581531 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 948026 # number of writebacks -system.cpu1.icache.writebacks::total 948026 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 948538 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 948538 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 948538 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 948538 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 948538 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 948538 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 951926 # number of writebacks +system.cpu1.icache.writebacks::total 951926 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 952438 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 952438 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 952438 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 952438 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 952438 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 952438 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8206619000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8206619000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8206619000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8206619000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8206619000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8206619000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10719000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10719000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10719000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10719000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023891 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023891 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023891 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.023891 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023891 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023891 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8651.861075 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8651.861075 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8651.861075 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8651.861075 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8651.861075 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8651.861075 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95705.357143 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95705.357143 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95705.357143 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95705.357143 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 199515 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 199547 # number of prefetch candidates identified +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8340101000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8340101000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8340101000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8340101000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8340101000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8340101000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11130500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 11130500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 11130500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 11130500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023992 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023992 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023992 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023992 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023992 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023992 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8756.581531 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8756.581531 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8756.581531 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8756.581531 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8756.581531 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8756.581531 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 99379.464286 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 99379.464286 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 99379.464286 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 99379.464286 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 201450 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 201482 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 59237 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 51581 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14798.019682 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1058904 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 65844 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 16.082012 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 57990 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 53299 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14769.496108 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1064390 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 67600 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 15.745414 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14409.418299 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 42.207150 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.101777 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 346.292455 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.879481 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002576 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.021136 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.903199 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 289 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13932 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14396.977583 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 38.648393 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.118214 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 333.751919 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.878722 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002359 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000007 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.020371 # 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number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1304028987 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 12503500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4198500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1042424000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2469455486 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 3528581486 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 12503500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4198500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1042424000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2469455486 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 979860887 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 4508442373 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9823000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2420981000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2430804000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9823000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2420981000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2430804000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023300 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.084289 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029517 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26179 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26291 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 14391500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3995000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 18386500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 996240965 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 996240965 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 460605000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 460605000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 354483500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 354483500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 493000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 493000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1271760500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1271760500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 1146491500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 1146491500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1443582493 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1443582493 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 14391500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3995000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1146491500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2715342993 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3880220993 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 14391500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3995000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1146491500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2715342993 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 996240965 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4876461958 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10234500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2377871000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2388105500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10234500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2377871000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2388105500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023488 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.078896 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029433 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.551439 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.551439 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.037418 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.037418 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.421225 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.421225 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023300 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.084289 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.037418 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.455149 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119294 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023300 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.084289 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.037418 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.455149 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.552707 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.552707 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.037198 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.037198 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.420854 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.420854 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023488 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.078896 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.037198 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454998 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119351 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023488 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.078896 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.037198 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454998 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.140483 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17462.988827 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14280.612245 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16536.633663 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37807.650847 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37807.650847 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15389.853763 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15389.853763 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15022.489518 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15022.489518 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.140779 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 20529.957204 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14116.607774 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18685.467480 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37862.608886 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37862.608886 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15343.782271 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15343.782271 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14959.003249 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14959.003249 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33746.242913 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33746.242913 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29370.675082 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29370.675082 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17415.614768 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17415.614768 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17462.988827 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14280.612245 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29370.675082 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22570.243538 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24182.610894 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17462.988827 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14280.612245 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29370.675082 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22570.243538 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37807.650847 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26237.654282 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87705.357143 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165877.423775 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165282.110560 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87705.357143 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91278.550692 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91263.525436 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 2396557 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1207646 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20286 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 118595 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 110586 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8009 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 53656 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1217922 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11928 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11928 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 153983 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 1025852 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 34704 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 31184 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 74094 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41981 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86038 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 20 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 69927 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 67092 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 948538 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295426 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 64 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2845326 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 911410 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8268 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 64898 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3829902 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121387264 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30723028 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13952 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 122916 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 152247160 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 369470 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 5053360 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1597738 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.098519 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.314386 # Request fanout histogram +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36706.222761 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36706.222761 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32360.255723 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32360.255723 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 19121.057698 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 19121.057698 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 20529.957204 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14116.607774 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32360.255723 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24652.663722 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26475.848939 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 20529.957204 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14116.607774 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32360.255723 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24652.663722 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37862.608886 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28209.001949 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91379.464286 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164866.601955 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164300.343997 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91379.464286 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90831.238779 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90833.574227 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 2407842 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1213344 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20026 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 118526 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 110630 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 7896 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 52421 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1221670 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11756 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11756 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 155519 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 1031415 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 35412 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 31701 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 73485 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42116 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86132 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 18 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 69767 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 67286 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 952438 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295145 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 55 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2857026 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 915642 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8405 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62913 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3843986 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121886464 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30908928 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14348 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 119380 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 152929120 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 368607 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 5126040 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1602092 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.097939 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.313375 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1448339 90.65% 90.65% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 141390 8.85% 99.50% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 8009 0.50% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1453081 90.70% 90.70% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 141115 8.81% 99.51% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 7896 0.49% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1597738 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2375408982 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1602092 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2385821492 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79990687 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79306117 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1423068313 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 409788212 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1428899351 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 412338887 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4783493 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4820495 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 34178481 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 33080974 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 31003 # Transaction distribution -system.iobus.trans_dist::ReadResp 31003 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 31015 # Transaction distribution +system.iobus.trans_dist::ReadResp 31015 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution system.iobus.trans_dist::WriteResp 59422 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) @@ -2295,9 +2296,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) @@ -2318,34 +2319,34 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48331500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48391001 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 111500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 333000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 334500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 88500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 620000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 622500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 47000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) @@ -2353,58 +2354,58 @@ system.iobus.reqLayer19.occupancy 2500 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6355500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6378000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 39060500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38950500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187669353 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187782564 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36449 # number of replacements -system.iocache.tags.tagsinuse 14.473969 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 36461 # number of replacements +system.iocache.tags.tagsinuse 14.472132 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 271637878000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.473969 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.904623 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.904623 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 272036828000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.472132 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904508 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904508 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328203 # Number of tag accesses -system.iocache.tags.data_accesses 328203 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses -system.iocache.ReadReq_misses::total 243 # number of ReadReq misses +system.iocache.tags.tag_accesses 328311 # Number of tag accesses +system.iocache.tags.data_accesses 328311 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses +system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses -system.iocache.demand_misses::total 36467 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36467 # number of overall misses -system.iocache.overall_misses::total 36467 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31680877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31680877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4302277476 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4302277476 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4333958353 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4333958353 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4333958353 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4333958353 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses +system.iocache.demand_misses::total 36479 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36479 # number of overall misses +system.iocache.overall_misses::total 36479 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 33219876 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 33219876 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4376166688 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4376166688 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4409386564 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4409386564 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4409386564 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4409386564 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36467 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36467 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36467 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36467 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2413,38 +2414,38 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 130373.979424 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 130373.979424 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118768.702407 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118768.702407 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118846.034853 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118846.034853 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118846.034853 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118846.034853 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 130274.023529 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 130274.023529 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120808.488516 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120808.488516 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120874.655665 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120874.655665 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120874.655665 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120874.655665 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 3 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 4.166667 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36467 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19530877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19530877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2488777487 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2488777487 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2508308364 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2508308364 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2508308364 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2508308364 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36479 # 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number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2453,592 +2454,591 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80373.979424 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 80373.979424 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68705.208895 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68705.208895 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68782.964434 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68782.964434 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68782.964434 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68782.964434 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 143192 # number of replacements -system.l2c.tags.tagsinuse 65154.235518 # Cycle average of tags in use -system.l2c.tags.total_refs 608270 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 208652 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.915237 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 94157771000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 6329.103935 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 78.467327 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.034862 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8953.646572 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6857.938638 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35058.708510 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 16.060603 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2144.069552 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3463.562714 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2252.642806 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.096574 # 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Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 145308 # number of replacements +system.l2c.tags.tagsinuse 65153.014694 # Cycle average of tags in use +system.l2c.tags.total_refs 608197 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 210799 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.885199 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 94570968000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 6725.818981 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 88.835717 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.039308 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8741.022578 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6775.934473 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34864.204134 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 12.618119 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2235.319135 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3466.513349 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2242.708901 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.102628 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001356 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.136622 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.104644 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.534953 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000245 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.032716 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.052850 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034373 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994175 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31682 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 69 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 33709 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 141 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4562 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 26979 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.133377 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.103393 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.531986 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000193 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.034108 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.052895 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034221 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994156 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 31590 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 60 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 33841 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 126 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4772 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 26692 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 67 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1943 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 31665 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.483429 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.001053 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.514359 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6826219 # Number of tag accesses -system.l2c.tags.data_accesses 6826219 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 268100 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 268100 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 43283 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5296 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 48579 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2814 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2244 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 5058 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4306 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1499 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5805 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 471 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 104 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 69073 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 63736 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47705 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 122 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 31 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 32133 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 13324 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5520 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 232219 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 471 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 104 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 69073 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 68042 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 47705 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 122 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 31 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 32133 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14823 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5520 # number of demand (read+write) hits -system.l2c.demand_hits::total 238024 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 471 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 104 # number of overall hits -system.l2c.overall_hits::cpu0.inst 69073 # number of overall hits -system.l2c.overall_hits::cpu0.data 68042 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 47705 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 122 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 31 # number of overall hits -system.l2c.overall_hits::cpu1.inst 32133 # number of overall hits -system.l2c.overall_hits::cpu1.data 14823 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5520 # number of overall hits -system.l2c.overall_hits::total 238024 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 486 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 293 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 779 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 96 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 129 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 225 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11283 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8662 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19945 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 140 # number of ReadSharedReq misses +system.l2c.tags.age_task_id_blocks_1023::4 58 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1899 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 31836 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.482025 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000916 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.516373 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6845829 # Number of tag accesses +system.l2c.tags.data_accesses 6845829 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 269041 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 269041 # 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mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.247986 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.237095 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733684 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.152778 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.094585 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.410546 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.553687 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.451635 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.229133 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.009524 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.247986 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.237095 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733684 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.152778 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.094585 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.410546 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.553687 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.451635 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21985.596708 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22336.177474 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22117.458280 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26411.458333 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23174.418605 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24555.555556 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89296.286449 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73405.045024 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 82394.810730 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80892.857143 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71387.918298 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79887.660955 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92756.068382 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 83477.272727 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73091.748585 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80309.869434 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116100.999562 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 89676.133235 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80892.857143 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71387.918298 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84907.878559 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92756.068382 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83477.272727 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73091.748585 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74516.612069 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116100.999562 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 88935.335554 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80892.857143 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71387.918298 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84907.878559 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92756.068382 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83477.272727 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73091.748585 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74516.612069 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116100.999562 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 88935.335554 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63637.035963 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197515.134419 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66705.357143 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147906.284265 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166371.405958 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63637.035963 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102007.866934 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66705.357143 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81381.919306 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 92183.762527 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 516977 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 290556 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 569 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.013009 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.040159 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.016199 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.025115 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.023701 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.024465 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.727448 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.853529 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.777221 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.229231 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.011236 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.249864 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.136982 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736797 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.108108 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098620 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.112265 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526575 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.434107 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.229231 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011236 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.249864 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.240730 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736797 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.108108 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.098620 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.406886 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526575 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.454412 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.229231 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011236 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.249864 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.240730 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736797 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.108108 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098620 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.406886 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526575 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.454412 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23063.492063 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21418.454936 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22584.375000 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26563.380282 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24096.491228 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25464.843750 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129705.383936 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 85368.527390 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 110484.100845 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 152187.919463 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 91370.054526 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 109547.806974 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110307.425762 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 237906.250000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100532.198054 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 151834.587045 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124331.046173 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108593.359665 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 152187.919463 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 91370.054526 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 120250.527204 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110307.425762 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 237906.250000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100532.198054 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96418.509808 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124331.046173 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 108784.734956 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 152187.919463 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 91370.054526 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 120250.527204 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110307.425762 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 237906.250000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100532.198054 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96418.509808 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124331.046173 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 108784.734956 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197862.516402 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70379.464286 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146895.873786 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167414.851769 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102176.249153 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70379.464286 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80922.925581 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92583.220481 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 519453 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 291586 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 583 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 38536 # Transaction distribution -system.membus.trans_dist::ReadResp 214874 # Transaction distribution -system.membus.trans_dist::WriteReq 31013 # Transaction distribution -system.membus.trans_dist::WriteResp 31013 # Transaction distribution -system.membus.trans_dist::WritebackDirty 140764 # Transaction distribution -system.membus.trans_dist::CleanEvict 19586 # Transaction distribution -system.membus.trans_dist::UpgradeReq 64644 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 38971 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 38386 # Transaction distribution +system.membus.trans_dist::ReadResp 216245 # Transaction distribution +system.membus.trans_dist::WriteReq 31026 # Transaction distribution +system.membus.trans_dist::WriteResp 31026 # Transaction distribution +system.membus.trans_dist::WritebackDirty 141787 # Transaction distribution +system.membus.trans_dist::CleanEvict 20009 # Transaction distribution +system.membus.trans_dist::UpgradeReq 64008 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38952 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 40377 # Transaction distribution -system.membus.trans_dist::ReadExResp 19925 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 176338 # Transaction distribution +system.membus.trans_dist::ReadExReq 40468 # Transaction distribution +system.membus.trans_dist::ReadExResp 19978 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 177859 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14120 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 656690 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 778768 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 851699 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14184 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 782434 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72955 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72955 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 855389 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19461788 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19654168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19616228 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19808736 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21972312 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123613 # Total snoops (count) -system.membus.snoopTraffic 36288 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 426105 # Request fanout histogram -system.membus.snoop_fanout::mean 0.011500 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.106618 # Request fanout histogram +system.membus.pkt_size::total 22126880 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123082 # Total snoops (count) +system.membus.snoopTraffic 37120 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 426925 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011573 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.106956 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 421205 98.85% 98.85% # Request fanout histogram -system.membus.snoop_fanout::1 4900 1.15% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 421984 98.84% 98.84% # Request fanout histogram +system.membus.snoop_fanout::1 4941 1.16% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 426105 # Request fanout histogram -system.membus.reqLayer0.occupancy 95080500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 426925 # Request fanout histogram +system.membus.reqLayer0.occupancy 95052999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12459499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12480499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1008366249 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1015492813 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1144784655 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1151697269 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1337127 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1408128 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3070,77 +3070,77 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1122676 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 592030 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 210689 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 28909 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 27742 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1167 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 38539 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 569123 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31013 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31013 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 372658 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 153621 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 113203 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 44029 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 157232 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 29 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51954 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51954 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 530586 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4329 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1344687 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 405982 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1750669 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 38363344 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7028808 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45392152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 398871 # Total snoops (count) -system.toL2Bus.snoopTraffic 16195724 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 956902 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.408687 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.494066 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1122951 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 592347 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 209143 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 29689 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 28433 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1256 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848926718000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 38389 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 568851 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31026 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31026 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 374622 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 155080 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 112572 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 44056 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 156628 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51647 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51647 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 530464 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4356 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1342563 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 408877 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1751440 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 38341228 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7151796 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45493024 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 399228 # Total snoops (count) +system.toL2Bus.snoopTraffic 16183244 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 957878 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.406657 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.493872 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 566996 59.25% 59.25% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 388739 40.62% 99.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1167 0.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 569606 59.47% 59.47% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 387016 40.40% 99.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1256 0.13% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 956902 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 952868265 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 957878 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 953761642 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 342123 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 360622 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 724877328 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 722683237 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 285789223 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 286574903 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |