diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | 5121 |
1 files changed, 2563 insertions, 2558 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 26497932e..43f49bfd8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,162 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.847227 # Number of seconds simulated -sim_ticks 2847227406000 # Number of ticks simulated -final_tick 2847227406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.647778 # Number of seconds simulated +sim_ticks 2647778082500 # Number of ticks simulated +final_tick 2647778082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166460 # Simulator instruction rate (inst/s) -host_op_rate 201569 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3722516357 # Simulator tick rate (ticks/s) -host_mem_usage 624360 # Number of bytes of host memory used -host_seconds 764.87 # Real time elapsed on the host -sim_insts 127319545 # Number of instructions simulated -sim_ops 154173476 # Number of ops (including micro ops) simulated +host_inst_rate 109262 # Simulator instruction rate (inst/s) +host_op_rate 132319 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2267003011 # Simulator tick rate (ticks/s) +host_mem_usage 618500 # Number of bytes of host memory used +host_seconds 1167.96 # Real time elapsed on the host +sim_insts 127613917 # Number of instructions simulated +sim_ops 154544077 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 7488 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 8192 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1647744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1317552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8353536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 217280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 643604 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 446720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1505216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1244784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8319232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 374976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 749140 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 607232 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12635780 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1647744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 217280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1865024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8874176 # Number of bytes written to this memory +system.physmem.bytes_read::total 12811716 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1505216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 374976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1880192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9040448 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8891740 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 117 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 9058012 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 128 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25746 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21109 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 130524 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10077 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 23519 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 19972 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 129988 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 30 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5859 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11726 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 9488 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 197977 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138659 # Number of write requests responded to by this memory +system.physmem.num_reads::total 200726 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 141257 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143050 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 578719 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 462749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2933919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 292 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 76313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 226046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 156896 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4437924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 578719 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 76313 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 655032 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3116778 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3122947 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3116778 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 578719 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 468904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2933919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 292 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 76313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 226060 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 156896 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7560871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 197977 # Number of read requests accepted -system.physmem.writeReqs 143050 # Number of write requests accepted -system.physmem.readBursts 197977 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 143050 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12661056 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue -system.physmem.bytesWritten 8904256 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12635780 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8891740 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_writes::total 145648 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 24 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 568483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 470124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3141967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 141619 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 282932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 229336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4838667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 568483 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 141619 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 710102 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3414353 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6618 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3420986 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3414353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 568483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 476742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3141967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 141619 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 282947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 229336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 8259653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 200726 # Number of read requests accepted +system.physmem.writeReqs 145648 # Number of write requests accepted +system.physmem.readBursts 200726 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 145648 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12837568 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue +system.physmem.bytesWritten 9070080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12811716 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9058012 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11990 # Per bank write bursts -system.physmem.perBankRdBursts::1 12090 # Per bank write bursts -system.physmem.perBankRdBursts::2 12710 # Per bank write bursts -system.physmem.perBankRdBursts::3 12556 # Per bank write bursts -system.physmem.perBankRdBursts::4 14859 # Per bank write bursts -system.physmem.perBankRdBursts::5 12263 # Per bank write bursts -system.physmem.perBankRdBursts::6 12121 # Per bank write bursts -system.physmem.perBankRdBursts::7 12401 # Per bank write bursts -system.physmem.perBankRdBursts::8 11839 # Per bank write bursts -system.physmem.perBankRdBursts::9 11973 # Per bank write bursts -system.physmem.perBankRdBursts::10 12288 # Per bank write bursts -system.physmem.perBankRdBursts::11 11633 # Per bank write bursts -system.physmem.perBankRdBursts::12 12418 # Per bank write bursts -system.physmem.perBankRdBursts::13 12730 # Per bank write bursts -system.physmem.perBankRdBursts::14 11938 # Per bank write bursts -system.physmem.perBankRdBursts::15 12020 # Per bank write bursts -system.physmem.perBankWrBursts::0 8637 # Per bank write bursts -system.physmem.perBankWrBursts::1 8726 # Per bank write bursts -system.physmem.perBankWrBursts::2 9304 # Per bank write bursts -system.physmem.perBankWrBursts::3 8986 # Per bank write bursts -system.physmem.perBankWrBursts::4 8078 # Per bank write bursts -system.physmem.perBankWrBursts::5 8592 # Per bank write bursts -system.physmem.perBankWrBursts::6 8645 # Per bank write bursts -system.physmem.perBankWrBursts::7 8770 # Per bank write bursts -system.physmem.perBankWrBursts::8 8363 # Per bank write bursts -system.physmem.perBankWrBursts::9 8478 # Per bank write bursts -system.physmem.perBankWrBursts::10 8927 # Per bank write bursts -system.physmem.perBankWrBursts::11 8795 # Per bank write bursts -system.physmem.perBankWrBursts::12 9084 # Per bank write bursts -system.physmem.perBankWrBursts::13 8813 # Per bank write bursts -system.physmem.perBankWrBursts::14 8578 # Per bank write bursts -system.physmem.perBankWrBursts::15 8353 # Per bank write bursts +system.physmem.perBankRdBursts::0 12684 # Per bank write bursts +system.physmem.perBankRdBursts::1 12558 # Per bank write bursts +system.physmem.perBankRdBursts::2 12677 # Per bank write bursts +system.physmem.perBankRdBursts::3 12470 # Per bank write bursts +system.physmem.perBankRdBursts::4 15173 # Per bank write bursts +system.physmem.perBankRdBursts::5 12439 # Per bank write bursts +system.physmem.perBankRdBursts::6 12705 # Per bank write bursts +system.physmem.perBankRdBursts::7 12895 # Per bank write bursts +system.physmem.perBankRdBursts::8 12483 # Per bank write bursts +system.physmem.perBankRdBursts::9 12862 # Per bank write bursts +system.physmem.perBankRdBursts::10 12103 # Per bank write bursts +system.physmem.perBankRdBursts::11 11319 # Per bank write bursts +system.physmem.perBankRdBursts::12 11938 # Per bank write bursts +system.physmem.perBankRdBursts::13 12281 # Per bank write bursts +system.physmem.perBankRdBursts::14 12069 # Per bank write bursts +system.physmem.perBankRdBursts::15 11931 # Per bank write bursts +system.physmem.perBankWrBursts::0 9144 # Per bank write bursts +system.physmem.perBankWrBursts::1 9177 # Per bank write bursts +system.physmem.perBankWrBursts::2 9224 # Per bank write bursts +system.physmem.perBankWrBursts::3 8920 # Per bank write bursts +system.physmem.perBankWrBursts::4 8442 # Per bank write bursts +system.physmem.perBankWrBursts::5 8744 # Per bank write bursts +system.physmem.perBankWrBursts::6 9263 # Per bank write bursts +system.physmem.perBankWrBursts::7 9163 # Per bank write bursts +system.physmem.perBankWrBursts::8 8908 # Per bank write bursts +system.physmem.perBankWrBursts::9 9183 # Per bank write bursts +system.physmem.perBankWrBursts::10 8711 # Per bank write bursts +system.physmem.perBankWrBursts::11 8187 # Per bank write bursts +system.physmem.perBankWrBursts::12 8717 # Per bank write bursts +system.physmem.perBankWrBursts::13 8673 # Per bank write bursts +system.physmem.perBankWrBursts::14 8851 # Per bank write bursts +system.physmem.perBankWrBursts::15 8413 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 38 # Number of times write queue was full causing retry -system.physmem.totGap 2847226871000 # Total gap between requests +system.physmem.numWrRetry 30 # Number of times write queue was full causing retry +system.physmem.totGap 2647777471000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 553 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 197396 # Read request sizes (log2) +system.physmem.readPktSize::6 200145 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 138659 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 85811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11580 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9476 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6090 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4527 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 718 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 141 # What read queue length does an incoming req see +system.physmem.writePktSize::6 141257 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 87468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7877 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4696 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 756 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 134 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -185,164 +185,165 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 145 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 92332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 233.562015 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.589518 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 297.350425 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50532 54.73% 54.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17809 19.29% 74.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6200 6.71% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3503 3.79% 84.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2794 3.03% 87.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1407 1.52% 89.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 909 0.98% 90.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 989 1.07% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8189 8.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 92332 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6903 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.657830 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 561.171003 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6902 99.99% 99.99% # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 90 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 94963 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 230.695997 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 131.239554 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 294.689609 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52509 55.29% 55.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18085 19.04% 74.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6234 6.56% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3686 3.88% 84.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2895 3.05% 87.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1483 1.56% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 908 0.96% 90.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1023 1.08% 91.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8140 8.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 94963 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7063 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.398839 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 555.406402 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7061 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6903 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6903 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.154860 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.644326 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.603874 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5813 84.21% 84.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 373 5.40% 89.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 70 1.01% 90.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 58 0.84% 91.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 265 3.84% 95.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 25 0.36% 95.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 18 0.26% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 26 0.38% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 14 0.20% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 9 0.13% 96.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.04% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.12% 96.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 153 2.22% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.09% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.07% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 5 0.07% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.04% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.04% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.04% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 8 0.12% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 9 0.13% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7063 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7063 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.065128 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.613340 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.212436 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5945 84.17% 84.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 392 5.55% 89.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 71 1.01% 90.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 48 0.68% 91.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 279 3.95% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 27 0.38% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 19 0.27% 96.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 25 0.35% 96.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 16 0.23% 96.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 12 0.17% 96.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.04% 96.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.10% 96.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 160 2.27% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.08% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 5 0.07% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 7 0.10% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 4 0.06% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 3 0.04% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.01% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.11% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.83% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 6 0.09% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6903 # Writes before turning the bus around for reads -system.physmem.totQLat 5250518808 # Total ticks spent queuing -system.physmem.totMemAccLat 8959812558 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 989145000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26540.69 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::144-147 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7063 # Writes before turning the bus around for reads +system.physmem.totQLat 5391615341 # Total ticks spent queuing +system.physmem.totMemAccLat 9152621591 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1002935000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26879.19 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45290.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.45 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.13 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.44 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 45629.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.85 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.43 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.42 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.07 # Average write queue length when enqueuing -system.physmem.readRowHits 164412 # Number of row buffer hits during reads -system.physmem.writeRowHits 80213 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.11 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.64 # Row buffer hit rate for writes -system.physmem.avgGap 8348977.86 # Average gap between requests -system.physmem.pageHitRate 72.59 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 354957120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 193677000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 787722000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 451902240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185966660880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83190012300 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1635359290500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1906304222040 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.531375 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2720439936839 # Time in different power states -system.physmem_0.memoryStateTime::REF 95074980000 # Time in different power states +system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.36 # Average write queue length when enqueuing +system.physmem.readRowHits 166580 # Number of row buffer hits during reads +system.physmem.writeRowHits 80763 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 56.97 # Row buffer hit rate for writes +system.physmem.avgGap 7644273.16 # Average gap between requests +system.physmem.pageHitRate 72.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 370341720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 202071375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 808080000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 467058960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 172939896480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 79567681680 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1518869897250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1773225027465 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.703351 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2526645938707 # Time in different power states +system.physmem_0.memoryStateTime::REF 88415080000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31706739411 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32716967293 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 343072800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 187192500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 755336400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 449653680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185966660880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82901008620 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635612802500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1906215727380 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.500294 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2720864046511 # Time in different power states -system.physmem_1.memoryStateTime::REF 95074980000 # Time in different power states +system.physmem_1.actEnergy 347578560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 189651000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 756490800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 451286640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 172939896480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 78874475895 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1519477980750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1773037360125 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.632470 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2527659145749 # Time in different power states +system.physmem_1.memoryStateTime::REF 88415080000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31288281989 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31702650501 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory @@ -352,39 +353,39 @@ system.realview.nvmem.bytes_inst_read::total 1344 system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.bw_read::cpu0.inst 193 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 314 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 508 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 193 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 314 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 508 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 193 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 314 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 508 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 20737076 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13605991 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1017313 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 13202297 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 8722072 # Number of BTB hits +system.cpu0.branchPred.lookups 34732065 # Number of BP lookups +system.cpu0.branchPred.condPredicted 16497595 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1496295 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 19609177 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 10269070 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.064807 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3399643 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 216094 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 760668 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 581758 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 178910 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 99353 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 52.368695 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 11117365 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 739154 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4170441 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 3984607 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 185834 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 94839 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -414,60 +415,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 68420 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 68420 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46092 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22328 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 68420 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 68420 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 68420 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6777 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12395.971669 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11546.443771 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5803.014677 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6374 94.05% 94.05% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 345 5.09% 99.14% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 47 0.69% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 6 0.09% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.06% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6777 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 65243 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 65243 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44492 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20751 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 65243 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 65243 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 65243 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6699 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12206.821914 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11332.778692 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5808.192470 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6323 94.39% 94.39% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 330 4.93% 99.31% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 32 0.48% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 7 0.10% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6699 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 338010000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 338010000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 338010000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5225 77.10% 77.10% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1552 22.90% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6777 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 68420 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5176 77.27% 77.27% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1523 22.73% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6699 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65243 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 68420 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6777 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65243 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6699 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6777 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 75197 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6699 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 71942 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17339981 # DTB read hits -system.cpu0.dtb.read_misses 61941 # DTB read misses -system.cpu0.dtb.write_hits 14540400 # DTB write hits -system.cpu0.dtb.write_misses 6479 # DTB write misses +system.cpu0.dtb.read_hits 23418517 # DTB read hits +system.cpu0.dtb.read_misses 59363 # DTB read misses +system.cpu0.dtb.write_hits 17357852 # DTB write hits +system.cpu0.dtb.write_misses 5880 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3449 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1354 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1959 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1178 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1722 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 521 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17401922 # DTB read accesses -system.cpu0.dtb.write_accesses 14546879 # DTB write accesses +system.cpu0.dtb.perms_faults 516 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 23477880 # DTB read accesses +system.cpu0.dtb.write_accesses 17363732 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31880381 # DTB hits -system.cpu0.dtb.misses 68420 # DTB misses -system.cpu0.dtb.accesses 31948801 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 40776369 # DTB hits +system.cpu0.dtb.misses 65243 # DTB misses +system.cpu0.dtb.accesses 40841612 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -497,41 +499,41 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 3977 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3977 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 304 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3673 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3977 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3977 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3977 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2411 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12713.811696 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 12041.525578 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 4752.572139 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 358 14.85% 14.85% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1847 76.61% 91.46% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 161 6.68% 98.13% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 17 0.71% 98.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 26 1.08% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 4001 # Table walker walks requested +system.cpu0.itb.walker.walksShort 4001 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3695 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 4001 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 4001 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 4001 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2427 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12648.125258 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11968.911523 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 4734.087286 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 373 15.37% 15.37% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1885 77.67% 93.04% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 118 4.86% 97.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 27 1.11% 99.01% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 22 0.91% 99.92% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2411 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2427 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 337545500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 337545500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 337545500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2112 87.60% 87.60% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 299 12.40% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2411 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2126 87.60% 87.60% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 301 12.40% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2427 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3977 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3977 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4001 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4001 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2411 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2411 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6388 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 38606266 # ITB inst hits -system.cpu0.itb.inst_misses 3977 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2427 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2427 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6428 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 68314752 # ITB inst hits +system.cpu0.itb.inst_misses 4001 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -540,797 +542,795 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2164 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 6955 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7135 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 38610243 # ITB inst accesses -system.cpu0.itb.hits 38606266 # DTB hits -system.cpu0.itb.misses 3977 # DTB misses -system.cpu0.itb.accesses 38610243 # DTB accesses -system.cpu0.numPwrStateTransitions 3704 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1852 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1492233091.644168 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23940880637.068275 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1073 57.94% 57.94% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 772 41.68% 99.62% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.68% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.05% 99.73% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499965331660 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1852 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 83611720275 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2763615685725 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 167224982 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 68318753 # ITB inst accesses +system.cpu0.itb.hits 68314752 # DTB hits +system.cpu0.itb.misses 4001 # DTB misses +system.cpu0.itb.accesses 68318753 # DTB accesses +system.cpu0.numPwrStateTransitions 4126 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 2063 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1227700157.144935 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 21500702795.368797 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1198 58.07% 58.07% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 860 41.69% 99.76% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.81% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.05% 99.85% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 3 0.15% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 499984309000 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 2063 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 115032658310 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2532745424190 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 230068064 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 79715648 # Number of instructions committed -system.cpu0.committedOps 95927461 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 5237247 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1849 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5527254348 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.097769 # CPI: cycles per instruction -system.cpu0.ipc 0.476697 # IPC: instructions per cycle -system.cpu0.op_class_0::No_OpClass 2273 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 63730677 66.44% 66.44% # Class of committed instruction -system.cpu0.op_class_0::IntMult 92076 0.10% 66.53% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.53% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 8115 0.01% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::MemRead 16811055 17.52% 84.07% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 15283265 15.93% 100.00% # Class of committed instruction +system.cpu0.committedInsts 106706103 # Number of instructions committed +system.cpu0.committedOps 129024022 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 8506641 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 2063 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5065528558 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.156091 # CPI: cycles per instruction +system.cpu0.ipc 0.463802 # IPC: instructions per cycle +system.cpu0.op_class_0::No_OpClass 2272 0.00% 0.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 87919988 68.14% 68.14% # Class of committed instruction +system.cpu0.op_class_0::IntMult 105727 0.08% 68.23% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 7151 0.01% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 68.23% # Class of committed instruction +system.cpu0.op_class_0::MemRead 22900542 17.75% 85.98% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 18088342 14.02% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 95927461 # Class of committed instruction +system.cpu0.op_class_0::total 129024022 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1852 # number of quiesce instructions executed -system.cpu0.tickCycles 128530134 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 38694848 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 715130 # number of replacements -system.cpu0.dcache.tags.tagsinuse 500.249385 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 30394670 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 715642 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 42.471892 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 2063 # number of quiesce instructions executed +system.cpu0.tickCycles 178511666 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 51556398 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 681177 # number of replacements +system.cpu0.dcache.tags.tagsinuse 487.337065 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 39381714 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 681689 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 57.770793 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 356009000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.249385 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977050 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.977050 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 487.337065 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.951830 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.951830 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63780153 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63780153 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 15810332 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15810332 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 13424812 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 13424812 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320440 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 320440 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365226 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365226 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361080 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361080 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 29235144 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 29235144 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 29555584 # number of overall hits -system.cpu0.dcache.overall_hits::total 29555584 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 463723 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 463723 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 580901 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 580901 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 136483 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 136483 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21307 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21307 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20567 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20567 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1044624 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1044624 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1181107 # number of overall misses -system.cpu0.dcache.overall_misses::total 1181107 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6183627500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6183627500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10315375000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10315375000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 321766500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 321766500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 497952500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 497952500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 229500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 229500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 16499002500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 16499002500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 16499002500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 16499002500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16274055 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16274055 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 14005713 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 14005713 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456923 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 456923 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386533 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386533 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381647 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381647 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30279768 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30279768 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30736691 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30736691 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028495 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.028495 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041476 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.041476 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.298700 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.298700 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055123 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055123 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053890 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053890 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034499 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.034499 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038427 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.038427 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13334.744017 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13334.744017 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17757.543884 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17757.543884 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15101.445534 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15101.445534 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24211.236447 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24211.236447 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 81578447 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 81578447 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 21978387 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 21978387 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 16273218 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 16273218 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 306177 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 306177 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 357355 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 357355 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352292 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 352292 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 38251605 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 38251605 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 38557782 # number of overall hits +system.cpu0.dcache.overall_hits::total 38557782 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 418335 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 418335 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 561531 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 561531 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131453 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 131453 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20802 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20802 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21460 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 21460 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 979866 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 979866 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1111319 # number of overall misses +system.cpu0.dcache.overall_misses::total 1111319 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5562272000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5562272000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10028849500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10028849500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 328076000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 328076000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 523772000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 523772000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 516000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 516000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 15591121500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 15591121500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 15591121500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 15591121500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 22396722 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 22396722 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 16834749 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 16834749 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 437630 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 437630 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378157 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 378157 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 373752 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 373752 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 39231471 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 39231471 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 39669101 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 39669101 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.018678 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.018678 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033355 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.033355 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300375 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300375 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055009 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055009 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.057418 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.057418 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024977 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.024977 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028015 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.028015 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13296.214756 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13296.214756 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17859.832316 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17859.832316 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15771.368138 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15771.368138 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24406.896552 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24406.896552 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15794.202029 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15794.202029 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13969.100598 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13969.100598 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15911.483305 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15911.483305 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14029.384452 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14029.384452 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 715130 # number of writebacks -system.cpu0.dcache.writebacks::total 715130 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 71798 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 71798 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255281 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 255281 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14780 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14780 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 327079 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 327079 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 327079 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 327079 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 391925 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 391925 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325620 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 325620 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103078 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 103078 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6527 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6527 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20567 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20567 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 717545 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 717545 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 820623 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 820623 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20575 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20575 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19271 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19271 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39846 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4674150000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4674150000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5703236000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5703236000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1673631500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1673631500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101407500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101407500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 477391500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 477391500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 223500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 223500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10377386000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10377386000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12051017500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12051017500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4615609000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4615609000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4615609000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4615609000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024083 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024083 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023249 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023249 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225592 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225592 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016886 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016886 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053890 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053890 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023697 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023697 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026698 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026698 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11926.133827 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11926.133827 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17515.005221 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17515.005221 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16236.553872 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16236.553872 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15536.617129 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15536.617129 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23211.528176 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23211.528176 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 681177 # number of writebacks +system.cpu0.dcache.writebacks::total 681177 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44450 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 44450 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 246335 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 246335 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14695 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14695 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 290785 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 290785 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 290785 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 290785 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 373885 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 373885 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 315196 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 315196 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98829 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 98829 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6107 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6107 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21460 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 21460 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 689081 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 689081 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 787910 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 787910 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29629 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29629 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26357 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26357 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 55986 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 55986 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4452451000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4452451000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5571993500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5571993500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1619437000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1619437000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94023500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94023500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 502325000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 502325000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 503000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 503000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10024444500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10024444500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11643881500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11643881500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6101487500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6101487500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6101487500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6101487500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016694 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016694 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018723 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018723 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225828 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225828 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016149 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016149 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.057418 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.057418 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017564 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.017564 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019862 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.019862 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11908.610937 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11908.610937 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17677.868691 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17677.868691 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16386.253023 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16386.253023 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15396.020960 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15396.020960 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23407.502330 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23407.502330 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # 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Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 79160710 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 79160710 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 36636559 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36636559 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36636559 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36636559 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36636559 # 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number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18757498000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 38599090 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 38599090 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 38599090 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 38599090 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 38599090 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 38599090 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050844 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050844 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050844 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050844 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050844 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050844 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9557.809787 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9557.809787 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9557.809787 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9557.809787 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9557.809787 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9557.809787 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 138502472 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 138502472 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 66419655 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 66419655 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 66419655 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 66419655 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 66419655 # number of overall hits +system.cpu0.icache.overall_hits::total 66419655 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1887721 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1887721 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1887721 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1887721 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1887721 # number of overall misses +system.cpu0.icache.overall_misses::total 1887721 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17836461000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 17836461000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 17836461000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 17836461000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 17836461000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 17836461000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 68307376 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 68307376 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 68307376 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 68307376 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 68307376 # 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average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9448.674354 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9448.674354 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1962004 # number of writebacks -system.cpu0.icache.writebacks::total 1962004 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1962531 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1962531 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1962531 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1962531 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1962531 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1962531 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3449 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 3449 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3449 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 3449 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17776233000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17776233000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17776233000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17776233000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17776233000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17776233000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 319470000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 319470000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 319470000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 319470000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050844 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050844 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050844 # 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average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92626.848362 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92626.848362 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1841200 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1841258 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 51 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.writebacks::writebacks 1887196 # number of writebacks +system.cpu0.icache.writebacks::total 1887196 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1887721 # 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mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027636 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027636 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.027636 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027636 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.027636 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8948.674619 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8948.674619 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8948.674619 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8948.674619 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8948.674619 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8948.674619 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92637.180974 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92637.180974 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92637.180974 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92637.180974 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1767222 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1767306 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 74 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # 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Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 281957 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16020.304669 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 4495555 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 298080 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 15.081706 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14756.008973 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.059574 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.057522 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1311.534778 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.900635 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003544 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.080050 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.984232 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 965 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15115 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 296 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 400 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 257 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 15153.098614 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.898882 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.073768 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 805.233405 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.924872 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003778 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.049148 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.977802 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1000 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15110 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 18 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 315 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 390 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 277 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4162 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7775 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2779 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.058899 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922546 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 89320549 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 89320549 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 82730 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5417 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 88147 # 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number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2997000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 31764000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 121525500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 121525500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 25214000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 25214000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 212499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 212499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2304231000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2304231000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3342274500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3342274500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3044310495 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3044310495 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 28767000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2997000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3342274500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 5348541495 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 8722579995 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 28767000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2997000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3342274500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 5348541495 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 8722579995 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 83586 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5545 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 89131 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 481961 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 481961 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 2152508 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 2152508 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56747 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 56747 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20566 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 20566 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 268881 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 268881 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1962531 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1962531 # 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mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.161648 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.031959 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.031959 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.209586 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.209586 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009669 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.021626 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.031959 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192817 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075029 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009669 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.021626 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.031959 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192817 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.167436 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26280.487805 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54135.843337 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 54135.843337 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19643.217143 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19643.217143 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15674.098026 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15674.098026 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 176499 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 176499 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39870.893725 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39870.893725 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42872.146620 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42872.146620 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24148.579986 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24148.579986 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42872.146620 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28945.690941 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33389.283701 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27606.308411 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17414.062500 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42872.146620 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28945.690941 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54135.843337 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44757.813723 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84626.703392 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 216325.103281 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197417.852980 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84626.703392 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111702.278773 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109545.363206 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 5508026 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2775137 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42660 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 346625 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 340732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5893 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 122459 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2635557 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19271 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19271 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 716131 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 2195168 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 240019 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 309687 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 88590 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43220 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114518 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 14 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 288089 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284462 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1962531 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 586533 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3131 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5893963 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2592135 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13195 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 174334 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 8673627 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 251390912 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99322292 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22180 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 334344 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 351069728 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1056913 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3897709 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.106693 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.313582 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.166430 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28639.046538 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56558.077101 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56558.077101 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19461.965107 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19461.965107 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15860.109060 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15860.109060 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 101124.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 101124.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40772.358309 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40772.358309 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43199.340284 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43199.340284 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23209.032047 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23209.032047 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43199.340284 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28359.545844 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32766.548688 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43199.340284 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28359.545844 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56558.077101 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45832.549870 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197926.474063 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 186117.014844 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 104746.963527 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103580.315981 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 5292246 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2668157 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 40914 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 334901 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 330475 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4426 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 126809 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2542571 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 26357 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26357 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 693110 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 2103191 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 223137 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 294264 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 92982 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43850 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 116200 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 275510 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 272175 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1887721 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 569608 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3113 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5669533 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2525108 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13291 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 164598 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 8372530 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 241815296 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 94996751 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22380 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314416 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 337148843 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1025467 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 18711896 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3771293 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.106316 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.312026 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3487742 89.48% 89.48% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 404074 10.37% 99.85% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 5893 0.15% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3374771 89.49% 89.49% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 392096 10.40% 99.88% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4426 0.12% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3897709 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 5501303494 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3771293 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 5293903990 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115667783 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114422325 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2949460514 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2837181638 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1225261932 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1188012916 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7656487 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7701489 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 90771952 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 86027432 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 19337823 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6215951 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 910078 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 9913117 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3669706 # Number of BTB hits +system.cpu1.branchPred.lookups 5469499 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3374978 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 316517 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 3346860 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 2136825 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 37.018689 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 8699112 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 707232 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3579063 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 3516137 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 62926 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 23615 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 63.845664 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 972408 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 68961 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 195238 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 132437 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 62801 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 28788 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1360,64 +1360,59 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 26974 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 26974 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20087 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6887 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 26974 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 26974 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 26974 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2714 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11914.148858 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11049.041659 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5760.245338 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 673 24.80% 24.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1844 67.94% 92.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 118 4.35% 97.09% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.06% 99.15% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 13 0.48% 99.63% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 4 0.15% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.04% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.07% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 2 0.07% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2714 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -2024068032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -2024068032 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -2024068032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1997 73.58% 73.58% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 717 26.42% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2714 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26974 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 30404 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 30404 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 23807 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6597 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 30404 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 30404 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 30404 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2736 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12207.419591 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11247.456123 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 8821.385005 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 2714 99.20% 99.20% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 14 0.51% 99.71% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 4 0.15% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 3 0.11% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2736 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1954228032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1954228032 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1954228032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 2033 74.31% 74.31% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 703 25.69% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2736 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30404 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26974 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2714 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30404 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2736 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2714 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 29688 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2736 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 33140 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 11185393 # DTB read hits -system.cpu1.dtb.read_misses 25019 # DTB read misses -system.cpu1.dtb.write_hits 6992115 # DTB write hits -system.cpu1.dtb.write_misses 1955 # DTB write misses +system.cpu1.dtb.read_hits 5173966 # DTB read hits +system.cpu1.dtb.read_misses 27871 # DTB read misses +system.cpu1.dtb.write_hits 4222414 # DTB write hits +system.cpu1.dtb.write_misses 2533 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1996 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 164 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 367 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2009 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 306 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 555 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 283 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 11210412 # DTB read accesses -system.cpu1.dtb.write_accesses 6994070 # DTB write accesses +system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 5201837 # DTB read accesses +system.cpu1.dtb.write_accesses 4224947 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 18177508 # DTB hits -system.cpu1.dtb.misses 26974 # DTB misses -system.cpu1.dtb.accesses 18204482 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 9396380 # DTB hits +system.cpu1.dtb.misses 30404 # DTB misses +system.cpu1.dtb.accesses 9426784 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1447,46 +1442,44 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 2420 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2420 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2239 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2420 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2420 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2420 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1133 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12165.931156 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11504.985007 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4742.932714 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 196 17.30% 17.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 640 56.49% 73.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 219 19.33% 93.12% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 41 3.62% 96.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 96.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 1.32% 98.23% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.71% 98.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.26% 99.21% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.44% 99.65% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1133 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -2024645532 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -2024645532 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -2024645532 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 964 85.08% 85.08% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 169 14.92% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1133 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 2488 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2488 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 182 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2306 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2488 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2488 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2488 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1135 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12427.312775 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11760.899210 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5007.072010 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 4 0.35% 0.35% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 156 13.74% 14.10% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 686 60.44% 74.54% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 210 18.50% 93.04% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 30 2.64% 95.68% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 95.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 1.85% 97.71% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.70% 98.41% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 15 1.32% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.26% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1135 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1954817532 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1954817532 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1954817532 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 965 85.02% 85.02% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 170 14.98% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1135 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2420 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2420 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2488 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2488 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1133 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1133 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3553 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 39602800 # ITB inst hits -system.cpu1.itb.inst_misses 2420 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1135 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1135 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3623 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 10174079 # ITB inst hits +system.cpu1.itb.inst_misses 2488 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1495,769 +1488,778 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1102 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1107 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1819 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1891 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 39605220 # ITB inst accesses -system.cpu1.itb.hits 39602800 # DTB hits -system.cpu1.itb.misses 2420 # DTB misses -system.cpu1.itb.accesses 39605220 # DTB accesses -system.cpu1.numPwrStateTransitions 5553 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2777 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1004505001.039251 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25654466824.490025 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1974 71.08% 71.08% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 799 28.77% 99.86% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 949981296504 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2777 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 57717018114 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2789510387886 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 115435582 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 10176567 # ITB inst accesses +system.cpu1.itb.hits 10174079 # DTB hits +system.cpu1.itb.misses 2488 # DTB misses +system.cpu1.itb.accesses 10176567 # DTB accesses +system.cpu1.numPwrStateTransitions 5445 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2723 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 962192053.212266 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 19383110303.670654 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1861 68.34% 68.34% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 855 31.40% 99.74% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 3 0.11% 99.85% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 4 0.15% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 499966911836 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2723 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 27729121603 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2620048960897 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 55461727 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 47603897 # Number of instructions committed -system.cpu1.committedOps 58246015 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 5049538 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2772 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5578401245 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.424919 # CPI: cycles per instruction -system.cpu1.ipc 0.412385 # IPC: instructions per cycle -system.cpu1.op_class_0::No_OpClass 66 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 40076529 68.81% 68.81% # Class of committed instruction -system.cpu1.op_class_0::IntMult 45752 0.08% 68.88% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.88% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 3347 0.01% 68.89% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.89% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.89% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.89% # Class of committed instruction -system.cpu1.op_class_0::MemRead 11012402 18.91% 87.80% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 7107919 12.20% 100.00% # Class of committed instruction +system.cpu1.committedInsts 20907814 # Number of instructions committed +system.cpu1.committedOps 25520055 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1855956 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2723 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5239453402 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.652679 # CPI: cycles per instruction +system.cpu1.ipc 0.376977 # IPC: instructions per cycle +system.cpu1.op_class_0::No_OpClass 67 0.00% 0.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 16137166 63.23% 63.23% # Class of committed instruction +system.cpu1.op_class_0::IntMult 34169 0.13% 63.37% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 63.37% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 4083 0.02% 63.38% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 63.38% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 63.38% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 63.38% # Class of committed instruction +system.cpu1.op_class_0::MemRead 4989153 19.55% 82.93% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 4355417 17.07% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 58246015 # Class of committed instruction +system.cpu1.op_class_0::total 25520055 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2777 # number of quiesce instructions executed -system.cpu1.tickCycles 97896037 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 17539545 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 196286 # number of replacements -system.cpu1.dcache.tags.tagsinuse 471.109798 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 17737294 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 196629 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 90.206907 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 91177108000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.109798 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920136 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.920136 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 36398755 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 36398755 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 10795076 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10795076 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6704752 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6704752 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50350 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50350 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80171 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 80171 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71533 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71533 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 17499828 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 17499828 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 17550178 # number of overall hits -system.cpu1.dcache.overall_hits::total 17550178 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 159722 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 159722 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 145538 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 145538 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 31004 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 31004 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16960 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16960 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23795 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23795 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 305260 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 305260 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 336264 # number of overall misses -system.cpu1.dcache.overall_misses::total 336264 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2429598500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2429598500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3913148500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3913148500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317482500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 317482500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 583924500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 583924500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 387500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 387500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6342747000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6342747000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6342747000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6342747000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 10954798 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 10954798 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6850290 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6850290 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81354 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 81354 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97131 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 97131 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95328 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95328 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 17805088 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 17805088 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 17886442 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 17886442 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.014580 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.014580 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021246 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.021246 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381100 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381100 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174610 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174610 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249612 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249612 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.017145 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.017145 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018800 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.018800 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15211.420468 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15211.420468 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26887.469252 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 26887.469252 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18719.487028 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18719.487028 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24539.798277 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24539.798277 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2723 # number of quiesce instructions executed +system.cpu1.tickCycles 37036327 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 18425400 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 231690 # number of replacements +system.cpu1.dcache.tags.tagsinuse 479.724430 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 8932333 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 232024 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 38.497453 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 109862994000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.724430 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.936962 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.936962 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 334 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 70 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.652344 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 18884551 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 18884551 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 4750067 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4750067 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3901959 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3901959 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65733 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 65733 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87399 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 87399 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79392 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 79392 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 8652026 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 8652026 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 8717759 # number of overall hits +system.cpu1.dcache.overall_hits::total 8717759 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 172325 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 172325 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 169730 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 169730 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34831 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 34831 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17668 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17668 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23402 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23402 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 342055 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 342055 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 376886 # number of overall misses +system.cpu1.dcache.overall_misses::total 376886 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2622225500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2622225500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4369952500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4369952500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 333352000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 333352000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 570866500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 570866500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 547000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 547000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6992178000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6992178000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6992178000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6992178000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4922392 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4922392 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4071689 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4071689 # 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average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25718.586585 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17785.469830 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17785.469830 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16931.915764 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16931.915764 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23540.134482 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23540.134482 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 231690 # number of writebacks +system.cpu1.dcache.writebacks::total 231690 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 6182 # 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number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5399 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5399 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4698 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4698 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10097 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10097 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2348457500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2348457500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2649909000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2649909000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 556338500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 556338500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95279500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95279500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 547474500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 547474500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 537000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 537000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4998366500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4998366500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5554705000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5554705000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 994956000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 994956000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 994956000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 994956000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033752 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033752 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026162 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026162 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.331858 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.331858 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051995 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051995 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.227659 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.227659 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030316 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030316 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033650 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033650 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14135.157665 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14135.157665 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24876.635812 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24876.635812 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16670.317322 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16670.317322 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17440.874977 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17440.874977 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23394.346637 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23394.346637 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18737.126355 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18737.126355 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18629.486399 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18629.486399 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171920.653078 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171920.653078 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94713.295394 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 94713.295394 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 946364 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.210861 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 38654025 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 946876 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.822690 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 72815756000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.210861 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975021 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975021 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18331.529533 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18331.529533 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18150.376751 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18150.376751 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184285.238007 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184285.238007 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 98539.764286 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 98539.764286 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 1038587 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.233977 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 9132995 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 1039099 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 8.789341 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 72888333000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.233977 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973113 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973113 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 50 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 80148678 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 80148678 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 38654025 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 38654025 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 38654025 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 38654025 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 38654025 # number of overall hits -system.cpu1.icache.overall_hits::total 38654025 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 946876 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 946876 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 946876 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 946876 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 946876 # number of overall misses -system.cpu1.icache.overall_misses::total 946876 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8324695000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8324695000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8324695000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8324695000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8324695000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8324695000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 39600901 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 39600901 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 39600901 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 39600901 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 39600901 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 39600901 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023910 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023910 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023910 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023910 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023910 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023910 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8791.747811 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8791.747811 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8791.747811 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8791.747811 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8791.747811 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8791.747811 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 21383287 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21383287 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 9132995 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 9132995 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 9132995 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 9132995 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 9132995 # number of overall hits +system.cpu1.icache.overall_hits::total 9132995 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 1039099 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 1039099 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 1039099 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 1039099 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 1039099 # number of overall misses +system.cpu1.icache.overall_misses::total 1039099 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9377315500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 9377315500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 9377315500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 9377315500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 9377315500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 9377315500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 10172094 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 10172094 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 10172094 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 10172094 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 10172094 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 10172094 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.102152 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.102152 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.102152 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.102152 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.102152 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.102152 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9024.467832 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9024.467832 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9024.467832 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9024.467832 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9024.467832 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9024.467832 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 946364 # number of writebacks -system.cpu1.icache.writebacks::total 946364 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 946876 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 946876 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 946876 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 946876 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 946876 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 946876 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 1038587 # number of writebacks +system.cpu1.icache.writebacks::total 1038587 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 1039099 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 1039099 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 1039099 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 1039099 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 1039099 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 1039099 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7851257000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7851257000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7851257000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7851257000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7851257000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7851257000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10474500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10474500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10474500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10474500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023910 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023910 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023910 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.023910 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023910 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023910 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8291.747811 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8291.747811 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8291.747811 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8291.747811 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 93522.321429 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 93522.321429 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 199879 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 199934 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 48 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8857766000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8857766000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8857766000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8857766000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8857766000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8857766000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10704000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10704000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10704000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10704000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.102152 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.102152 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.102152 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.102152 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.102152 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.102152 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8524.467832 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8524.467832 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8524.467832 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8524.467832 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8524.467832 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8524.467832 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95571.428571 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95571.428571 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95571.428571 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95571.428571 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 276399 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 276459 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 53 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 58626 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 53638 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15286.424872 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 2058198 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 68366 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 30.105579 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 69493 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 70219 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15563.656432 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 2283330 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 85023 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 26.855439 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14816.571197 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 39.116539 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.045474 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 428.691662 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.904332 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002387 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026165 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.933009 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 907 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 45 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13776 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 323 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 581 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5681 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7813 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.055359 # 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number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 178417 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 178417 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 30698 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 3365 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 946876 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 240944 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1221883 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 30698 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 3365 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 946876 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 240944 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1221883 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020262 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.068351 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.025012 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.occ_blocks::writebacks 14385.822816 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 54.124799 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.170471 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1123.538345 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.878041 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 19 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5206 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 8191 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.064453 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.836548 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 42757972 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 42757972 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 32984 # 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number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 13878500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1006636893 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1006636893 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 505691500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 505691500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 380458500 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 380458500 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 318000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 318000 # 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number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2381835496 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 3071557996 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 10605000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3273500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 675844000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2381835496 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1006636893 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 4078194889 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9578500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2364337500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2373916000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9578500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2364337500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2373916000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020262 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.068351 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025012 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10097 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10209 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 13702000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3438500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 17140500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1312457547 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1312457547 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 566974500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 566974500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 370291999 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 370291999 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 461000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 461000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1222094000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1222094000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 987020000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 987020000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1373517992 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1373517992 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 13702000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3438500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 987020000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2595611992 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3599772492 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 13702000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3438500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 987020000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2595611992 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1312457547 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4912230039 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9808000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 951737000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 961545000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9808000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 951737000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 961545000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020869 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.067908 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025284 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.548003 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.548003 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.021165 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.021165 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.402142 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402142 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020262 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.068351 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.021165 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.439994 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103862 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020262 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.068351 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.021165 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.439994 # mshr miss rate for overall accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.489121 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.489121 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.025623 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.025623 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.364724 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.364724 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020869 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.067908 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.025623 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.397900 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.102366 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020869 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.067908 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.025623 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.397900 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.125170 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16289.319249 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38663.269819 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38663.269819 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16840.104566 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16840.104566 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15989.010296 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15989.010296 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33124.908799 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33124.908799 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33723.067711 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33723.067711 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17377.391964 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17377.391964 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33723.067711 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22467.178825 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24203.219649 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17049.839228 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14232.608696 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33723.067711 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22467.178825 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38663.269819 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26664.802502 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85522.321429 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163916.909318 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163312.878371 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85522.321429 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90303.930181 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90283.562790 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 2394243 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1206431 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20164 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 192169 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 190372 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1797 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 53056 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1216172 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11758 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11758 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 154274 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 1024857 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 118852 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 31456 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 74303 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42261 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86315 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 14 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 69975 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 67112 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 946876 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 270105 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 65 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2840340 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 913098 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8024 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 64559 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3826021 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121174528 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30799564 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13460 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 122792 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 152110344 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 428107 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1655199 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.135380 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.345288 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.130971 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18234.574468 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33841.925300 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33841.925300 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17731.251564 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17731.251564 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15823.768172 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15823.768172 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 461000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 461000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33516.002523 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33516.002523 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 37071.173709 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 37071.173709 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18372.364794 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18372.364794 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 37071.173709 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23337.007561 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25937.202726 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 37071.173709 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23337.007561 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33841.925300 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27663.625832 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87571.428571 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176280.237081 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174477.408819 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87571.428571 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 94259.383975 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 94186.012342 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 2654318 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1335711 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 21986 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 212975 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 211032 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1943 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 47306 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1331970 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 4698 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 4698 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 177822 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 1135956 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 137781 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 47279 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 75014 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42924 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 89713 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 82844 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 80563 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1039099 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 293637 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3117009 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1002647 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8284 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70688 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 4198628 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 132979072 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 35729427 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13960 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 134748 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 168857207 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 473910 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 5785960 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1814338 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.136111 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.346015 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1432915 86.57% 86.57% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 220487 13.32% 99.89% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1797 0.11% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1569330 86.50% 86.50% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 243065 13.40% 99.89% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1943 0.11% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1655199 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2373087991 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1814338 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2620766990 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79906669 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 87124018 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1420645672 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 410383006 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1558968196 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 456771923 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4659998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4794998 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 33872477 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 37016968 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 31003 # Transaction distribution -system.iobus.trans_dist::ReadResp 31003 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 31014 # Transaction distribution +system.iobus.trans_dist::ReadResp 31014 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution system.iobus.trans_dist::WriteResp 59422 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) @@ -2266,7 +2268,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2279,17 +2281,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180872 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2302,94 +2304,94 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48463001 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48375000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 113500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 326500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 329000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 29000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 27500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 84000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 574000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 619500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 45500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6138000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6358000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33143500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38893000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187679851 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187720844 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36784000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36449 # number of replacements -system.iocache.tags.tagsinuse 14.476064 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 36462 # number of replacements +system.iocache.tags.tagsinuse 14.359878 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36478 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 271175186000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.476064 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.904754 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.904754 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 271405535000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.359878 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.897492 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.897492 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328203 # Number of tag accesses -system.iocache.tags.data_accesses 328203 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses -system.iocache.ReadReq_misses::total 243 # number of ReadReq misses +system.iocache.tags.tag_accesses 328320 # Number of tag accesses +system.iocache.tags.data_accesses 328320 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::realview.ide 256 # number of ReadReq misses +system.iocache.ReadReq_misses::total 256 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses -system.iocache.demand_misses::total 36467 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36467 # number of overall misses -system.iocache.overall_misses::total 36467 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31712877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31712877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4301380974 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4301380974 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4333093851 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4333093851 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4333093851 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4333093851 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 36480 # number of demand (read+write) misses +system.iocache.demand_misses::total 36480 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36480 # number of overall misses +system.iocache.overall_misses::total 36480 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 33042377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 33042377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4307289467 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4307289467 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4340331844 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4340331844 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4340331844 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4340331844 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 256 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 256 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36467 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36467 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36467 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36467 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36480 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36480 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36480 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36480 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2398,38 +2400,38 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 130505.666667 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 130505.666667 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118743.953567 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118743.953567 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118822.328434 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118822.328434 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118822.328434 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118822.328434 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 152 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129071.785156 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129071.785156 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118907.063466 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118907.063466 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118978.394846 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118978.394846 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118978.394846 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118978.394846 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 16.888889 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.666667 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 256 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 256 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36467 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19562877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19562877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2487893822 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2487893822 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2507456699 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2507456699 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2507456699 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2507456699 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 36480 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36480 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36480 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36480 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 20242377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 20242377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2493740476 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2493740476 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2513982853 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2513982853 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2513982853 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2513982853 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2438,588 +2440,590 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80505.666667 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 80505.666667 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68680.814432 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68680.814432 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68759.610031 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68759.610031 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 131721 # number of replacements -system.l2c.tags.tagsinuse 63119.316885 # Cycle average of tags in use -system.l2c.tags.total_refs 480965 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 195649 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.458305 # Average number of references to valid blocks. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79071.785156 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 79071.785156 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68842.217204 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68842.217204 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68914.003646 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68914.003646 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68914.003646 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68914.003646 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 135113 # number of replacements +system.l2c.tags.tagsinuse 63251.941629 # Cycle average of tags in use +system.l2c.tags.total_refs 475115 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 198978 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.387777 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13508.912510 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 74.990696 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.038635 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 9208.691215 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2842.970469 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33089.520800 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.769626 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2121.922145 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 593.095570 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1670.405219 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.206130 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001144 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 14216.048080 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 74.910809 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.033810 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7426.792759 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2102.106662 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29896.915616 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 20.238831 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3811.016358 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1509.520853 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4194.357849 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.216920 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001143 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.140513 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043380 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.504906 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000134 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.032378 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009050 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.025488 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.963124 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 27523 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 36326 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.113324 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.032076 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.456191 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000309 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.058151 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023033 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.064001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.965148 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 27324 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 89 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 36452 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 134 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4354 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 23032 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 79 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3689 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 32199 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.419968 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.001205 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.554291 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6440622 # Number of tag accesses -system.l2c.tags.data_accesses 6440622 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 269250 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 269250 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 33826 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2712 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 36538 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2202 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1074 # 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number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5491 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 177850 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 466 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 69 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 46028 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 54421 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 48669 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 136 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 26 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 16745 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 11684 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5491 # number of demand (read+write) hits -system.l2c.demand_hits::total 183735 # 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Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70918.459566 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84623.329098 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91570.072857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 92050 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73433.246875 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74043.911922 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109721.537416 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 88063.668908 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63637.035963 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179924.347835 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66571.428571 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158365.363232 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166188.791033 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63637.035963 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 95219.849641 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66571.428571 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 84658.163265 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92079.185841 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 535318 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 308111 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 583 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 38557 # Transaction distribution -system.membus.trans_dist::ReadResp 213679 # Transaction distribution -system.membus.trans_dist::WriteReq 31029 # Transaction distribution -system.membus.trans_dist::WriteResp 31029 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138659 # Transaction distribution -system.membus.trans_dist::CleanEvict 18543 # Transaction distribution -system.membus.trans_dist::UpgradeReq 76988 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41072 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 38585 # Transaction distribution +system.membus.trans_dist::ReadResp 215902 # Transaction distribution +system.membus.trans_dist::WriteReq 31055 # Transaction distribution +system.membus.trans_dist::WriteResp 31055 # Transaction distribution +system.membus.trans_dist::WritebackDirty 141257 # Transaction distribution +system.membus.trans_dist::CleanEvict 18818 # Transaction distribution +system.membus.trans_dist::UpgradeReq 79128 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41795 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 39665 # Transaction distribution -system.membus.trans_dist::ReadExResp 19299 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 175122 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 40708 # Transaction distribution +system.membus.trans_dist::ReadExResp 19870 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 177317 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664223 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 786371 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 859302 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 675920 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 798178 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72957 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72957 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 871135 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28380 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19209376 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19401896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19551584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19744330 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21720040 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123861 # Total snoops (count) -system.membus.snoop_fanout::samples 438659 # Request fanout histogram -system.membus.snoop_fanout::mean 0.011132 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.104918 # Request fanout histogram +system.membus.pkt_size::total 22062474 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 126237 # Total snoops (count) +system.membus.snoopTraffic 37184 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 444815 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011558 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.106883 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 433776 98.89% 98.89% # Request fanout histogram -system.membus.snoop_fanout::1 4883 1.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 439674 98.84% 98.84% # Request fanout histogram +system.membus.snoop_fanout::1 5141 1.16% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 438659 # Request fanout histogram -system.membus.reqLayer0.occupancy 89013499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 444815 # Request fanout histogram +system.membus.reqLayer0.occupancy 94951000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12314999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12539499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1002605728 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1031011447 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1133893717 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1149570495 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1318131 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1412877 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3051,76 +3055,77 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1068358 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 578478 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 169754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 19773 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 18732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1041 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 38560 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 513452 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31029 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31029 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 371703 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 144260 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 113415 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 44348 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 157763 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 14 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51662 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51662 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 474894 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4314 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1271960 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 368625 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1640585 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36024040 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5855360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 41879400 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 387762 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 889983 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.383411 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.488617 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1073312 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 580718 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 172518 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 20634 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 19568 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1066 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 38588 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 515387 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31055 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 375084 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 144219 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 115852 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 44839 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 160691 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51833 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51833 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 476801 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4556 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1253209 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 392983 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1646192 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34630659 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7267527 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 41898186 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 395888 # Total snoops (count) +system.toL2Bus.snoopTraffic 16395788 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 898686 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.386698 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.489423 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 549795 61.78% 61.78% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 339147 38.11% 99.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1041 0.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 552232 61.45% 61.45% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 345388 38.43% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1066 0.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 889983 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 926156147 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 898686 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 930017339 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 342619 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 361623 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 669727799 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 658710189 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 257138606 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 272587474 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |