diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | 4857 |
1 files changed, 2470 insertions, 2387 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index e45890e36..8f982bce7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,162 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.649116 # Number of seconds simulated -sim_ticks 2649116242500 # Number of ticks simulated -final_tick 2649116242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.848878 # Number of seconds simulated +sim_ticks 2848878048000 # Number of ticks simulated +final_tick 2848878048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120147 # Simulator instruction rate (inst/s) -host_op_rate 145490 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2497044812 # Simulator tick rate (ticks/s) -host_mem_usage 602856 # Number of bytes of host memory used -host_seconds 1060.90 # Real time elapsed on the host -sim_insts 127464482 # Number of instructions simulated -sim_ops 154350851 # Number of ops (including micro ops) simulated +host_inst_rate 194660 # Simulator instruction rate (inst/s) +host_op_rate 235713 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4372273286 # Simulator tick rate (ticks/s) +host_mem_usage 620428 # Number of bytes of host memory used +host_seconds 651.58 # Real time elapsed on the host +sim_insts 126836472 # Number of instructions simulated +sim_ops 153585571 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 7744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 8960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1526336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1246188 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8224576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 2560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 394816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 723292 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 617536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1701632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1345580 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8578560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 207872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 624532 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 336128 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12744072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1526336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 394816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1921152 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8953600 # Number of bytes written to this memory +system.physmem.bytes_read::total 12804992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1701632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 207872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1909504 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8865600 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8971164 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 121 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8883164 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 140 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 23849 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 19993 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 128509 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 40 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11324 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 9649 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26588 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21546 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134040 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3248 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9779 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5252 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 199670 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 139900 # Number of write requests responded to by this memory +system.physmem.num_reads::total 200620 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138525 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 144291 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2923 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 576168 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 470417 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3104649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 149037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 273031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 233110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 362 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4810688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 576168 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 149037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 725205 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3379844 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6615 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3386474 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3379844 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 576168 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 477032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3104649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 149037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 273047 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 233110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 8197162 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 199670 # Number of read requests accepted -system.physmem.writeReqs 144291 # Number of write requests accepted -system.physmem.readBursts 199670 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 144291 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12768704 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue -system.physmem.bytesWritten 8984192 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12744072 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8971164 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one +system.physmem.num_writes::total 142916 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3145 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 597299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 472319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3011206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 247 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 72966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 219220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 117986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4494749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 597299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 72966 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 670265 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3111962 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3118127 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3111962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 597299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 478470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3011206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 72966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 219234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 117986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7612876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 200620 # Number of read requests accepted +system.physmem.writeReqs 142916 # Number of write requests accepted +system.physmem.readBursts 200620 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 142916 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12829952 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9728 # Total number of bytes read from write queue +system.physmem.bytesWritten 8896256 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12804992 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8883164 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12456 # Per bank write bursts -system.physmem.perBankRdBursts::1 12907 # Per bank write bursts -system.physmem.perBankRdBursts::2 13452 # Per bank write bursts -system.physmem.perBankRdBursts::3 12663 # Per bank write bursts -system.physmem.perBankRdBursts::4 15992 # Per bank write bursts -system.physmem.perBankRdBursts::5 12602 # Per bank write bursts -system.physmem.perBankRdBursts::6 12853 # Per bank write bursts -system.physmem.perBankRdBursts::7 13005 # Per bank write bursts -system.physmem.perBankRdBursts::8 12164 # Per bank write bursts -system.physmem.perBankRdBursts::9 12306 # Per bank write bursts -system.physmem.perBankRdBursts::10 11290 # Per bank write bursts -system.physmem.perBankRdBursts::11 10778 # Per bank write bursts -system.physmem.perBankRdBursts::12 11668 # Per bank write bursts -system.physmem.perBankRdBursts::13 12164 # Per bank write bursts -system.physmem.perBankRdBursts::14 11811 # Per bank write bursts -system.physmem.perBankRdBursts::15 11400 # Per bank write bursts -system.physmem.perBankWrBursts::0 8970 # Per bank write bursts -system.physmem.perBankWrBursts::1 9418 # Per bank write bursts -system.physmem.perBankWrBursts::2 9818 # Per bank write bursts -system.physmem.perBankWrBursts::3 9016 # Per bank write bursts -system.physmem.perBankWrBursts::4 8619 # Per bank write bursts -system.physmem.perBankWrBursts::5 8911 # Per bank write bursts -system.physmem.perBankWrBursts::6 9199 # Per bank write bursts -system.physmem.perBankWrBursts::7 9114 # Per bank write bursts -system.physmem.perBankWrBursts::8 8718 # Per bank write bursts -system.physmem.perBankWrBursts::9 8852 # Per bank write bursts -system.physmem.perBankWrBursts::10 8120 # Per bank write bursts -system.physmem.perBankWrBursts::11 7867 # Per bank write bursts -system.physmem.perBankWrBursts::12 8570 # Per bank write bursts -system.physmem.perBankWrBursts::13 8570 # Per bank write bursts -system.physmem.perBankWrBursts::14 8685 # Per bank write bursts -system.physmem.perBankWrBursts::15 7931 # Per bank write bursts +system.physmem.perBankRdBursts::0 12282 # Per bank write bursts +system.physmem.perBankRdBursts::1 12615 # Per bank write bursts +system.physmem.perBankRdBursts::2 13546 # Per bank write bursts +system.physmem.perBankRdBursts::3 12896 # Per bank write bursts +system.physmem.perBankRdBursts::4 15667 # Per bank write bursts +system.physmem.perBankRdBursts::5 12734 # Per bank write bursts +system.physmem.perBankRdBursts::6 12682 # Per bank write bursts +system.physmem.perBankRdBursts::7 12950 # Per bank write bursts +system.physmem.perBankRdBursts::8 12070 # Per bank write bursts +system.physmem.perBankRdBursts::9 12307 # Per bank write bursts +system.physmem.perBankRdBursts::10 11595 # Per bank write bursts +system.physmem.perBankRdBursts::11 10656 # Per bank write bursts +system.physmem.perBankRdBursts::12 11845 # Per bank write bursts +system.physmem.perBankRdBursts::13 12839 # Per bank write bursts +system.physmem.perBankRdBursts::14 12069 # Per bank write bursts +system.physmem.perBankRdBursts::15 11715 # Per bank write bursts +system.physmem.perBankWrBursts::0 8801 # Per bank write bursts +system.physmem.perBankWrBursts::1 9221 # Per bank write bursts +system.physmem.perBankWrBursts::2 9816 # Per bank write bursts +system.physmem.perBankWrBursts::3 9124 # Per bank write bursts +system.physmem.perBankWrBursts::4 8304 # Per bank write bursts +system.physmem.perBankWrBursts::5 8866 # Per bank write bursts +system.physmem.perBankWrBursts::6 8953 # Per bank write bursts +system.physmem.perBankWrBursts::7 8983 # Per bank write bursts +system.physmem.perBankWrBursts::8 8497 # Per bank write bursts +system.physmem.perBankWrBursts::9 8715 # Per bank write bursts +system.physmem.perBankWrBursts::10 8212 # Per bank write bursts +system.physmem.perBankWrBursts::11 7775 # Per bank write bursts +system.physmem.perBankWrBursts::12 8513 # Per bank write bursts +system.physmem.perBankWrBursts::13 8820 # Per bank write bursts +system.physmem.perBankWrBursts::14 8499 # Per bank write bursts +system.physmem.perBankWrBursts::15 7905 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 32 # Number of times write queue was full causing retry -system.physmem.totGap 2649115714000 # Total gap between requests +system.physmem.numWrRetry 24 # Number of times write queue was full causing retry +system.physmem.totGap 2848877502000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 554 # Read request sizes (log2) +system.physmem.readPktSize::2 552 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 199088 # Read request sizes (log2) +system.physmem.readPktSize::6 200040 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 139900 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 88665 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60851 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3733 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 673 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 208 # What read queue length does an incoming req see +system.physmem.writePktSize::6 138525 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 88667 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11649 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7800 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 205 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 130 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -184,162 +184,160 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 103 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 93964 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 231.501767 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 131.710526 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 295.455834 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 51656 54.97% 54.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18156 19.32% 74.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6272 6.67% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3449 3.67% 84.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2927 3.12% 87.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1465 1.56% 89.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 883 0.94% 90.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 950 1.01% 91.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8206 8.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 93964 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6826 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.227952 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 564.671734 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6825 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 83 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 92501 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 234.874693 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.252552 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 298.003949 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50468 54.56% 54.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17746 19.18% 73.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6298 6.81% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3474 3.76% 84.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2881 3.11% 87.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1488 1.61% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 938 1.01% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 959 1.04% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8249 8.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 92501 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6731 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.782499 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 569.000641 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6729 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6826 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6826 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.565192 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.817384 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.562313 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5689 83.34% 83.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 486 7.12% 90.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 93 1.36% 91.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 54 0.79% 92.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 43 0.63% 93.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 24 0.35% 93.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 57 0.84% 94.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.12% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 116 1.70% 96.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 16 0.23% 96.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 10 0.15% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 12 0.18% 96.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 73 1.07% 97.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 7 0.10% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 20 0.29% 98.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 80 1.17% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.04% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.03% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.04% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 9 0.13% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.01% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 3 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6826 # Writes before turning the bus around for reads -system.physmem.totQLat 5414962245 # Total ticks spent queuing -system.physmem.totMemAccLat 9155793495 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 997555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27141.17 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6731 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6731 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.651315 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.819444 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.992190 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5609 83.33% 83.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 487 7.24% 90.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 91 1.35% 91.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 48 0.71% 92.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 35 0.52% 93.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 15 0.22% 93.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 45 0.67% 94.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 18 0.27% 94.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 127 1.89% 96.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 10 0.15% 96.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.12% 96.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 12 0.18% 96.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 75 1.11% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 97.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.04% 97.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 23 0.34% 98.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 82 1.22% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 5 0.07% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.12% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 9 0.13% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6731 # Writes before turning the bus around for reads +system.physmem.totQLat 5345988099 # Total ticks spent queuing +system.physmem.totMemAccLat 9104763099 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1002340000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26667.54 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45891.17 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.39 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.81 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.39 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 45417.54 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.50 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.49 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.22 # Average write queue length when enqueuing -system.physmem.readRowHits 165357 # Number of row buffer hits during reads -system.physmem.writeRowHits 80567 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.88 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.39 # Row buffer hit rate for writes -system.physmem.avgGap 7701790.94 # Average gap between requests -system.physmem.pageHitRate 72.35 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 377130600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 205775625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 826254000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 473461200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 173027368800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 81211791960 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1518231236250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1774353018435 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.790588 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2525572951341 # Time in different power states -system.physmem_0.memoryStateTime::REF 88459800000 # Time in different power states +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.22 # Average write queue length when enqueuing +system.physmem.readRowHits 166512 # Number of row buffer hits during reads +system.physmem.writeRowHits 80458 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.06 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.88 # Row buffer hit rate for writes +system.physmem.avgGap 8292806.29 # Average gap between requests +system.physmem.pageHitRate 72.75 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 369525240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 201625875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 821901600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 467000640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186074475600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 85037796405 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634728846500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1907701171860 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.633786 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2719381991131 # Time in different power states +system.physmem_0.memoryStateTime::REF 95130100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35083346159 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34360263869 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 333237240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 181825875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 729924000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 436188240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 173027368800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79517209320 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1519717712250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1773943465725 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.635988 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2528054644365 # Time in different power states -system.physmem_1.memoryStateTime::REF 88459800000 # Time in different power states +system.physmem_1.actEnergy 329782320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179940750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 741741000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 433745280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186074475600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 83868136740 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635754863750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1907382685440 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.521992 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2721101495830 # Time in different power states +system.physmem_1.memoryStateTime::REF 95130100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32601653135 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32646289170 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory @@ -350,30 +348,34 @@ system.realview.nvmem.bytes_inst_read::total 1344 system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 193 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 314 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 507 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 193 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 314 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 507 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 193 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 314 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 507 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 19632721 # Number of BP lookups -system.cpu0.branchPred.condPredicted 12741106 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 957809 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 12414007 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 8826841 # Number of BTB hits +system.cpu0.branchPred.lookups 36258885 # Number of BP lookups +system.cpu0.branchPred.condPredicted 17779541 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1788671 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 20741460 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 11048316 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.103883 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3283973 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 196273 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 53.266819 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 11219024 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 931479 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4153759 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 3951203 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 202556 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 105471 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -404,56 +406,59 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 67362 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 67362 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44747 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22615 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 67362 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 67362 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 67362 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6703 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 11941.220349 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 10822.969980 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 8452.619900 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 6653 99.25% 99.25% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 41 0.61% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 8 0.12% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 71829 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 71829 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46722 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 25107 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 71829 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 71829 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 71829 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 7556 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12351.641080 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11368.840758 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 8528.588507 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 7496 99.21% 99.21% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 51 0.67% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 5 0.07% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 1 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6703 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 7556 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 581987000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 581987000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 581987000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5190 77.43% 77.43% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1513 22.57% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6703 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67362 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5875 77.75% 77.75% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1681 22.25% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 7556 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71829 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67362 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6703 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71829 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7556 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6703 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 74065 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7556 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 79385 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 16471465 # DTB read hits -system.cpu0.dtb.read_misses 61259 # DTB read misses -system.cpu0.dtb.write_hits 13861421 # DTB write hits -system.cpu0.dtb.write_misses 6103 # DTB write misses +system.cpu0.dtb.read_hits 24842790 # DTB read hits +system.cpu0.dtb.read_misses 65179 # DTB read misses +system.cpu0.dtb.write_hits 18502994 # DTB write hits +system.cpu0.dtb.write_misses 6650 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1118 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1582 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3814 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1457 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2027 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 565 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 16532724 # DTB read accesses -system.cpu0.dtb.write_accesses 13867524 # DTB write accesses +system.cpu0.dtb.perms_faults 602 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 24907969 # DTB read accesses +system.cpu0.dtb.write_accesses 18509644 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 30332886 # DTB hits -system.cpu0.dtb.misses 67362 # DTB misses -system.cpu0.dtb.accesses 30400248 # DTB accesses +system.cpu0.dtb.hits 43345784 # DTB hits +system.cpu0.dtb.misses 71829 # DTB misses +system.cpu0.dtb.accesses 43417613 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -483,37 +488,38 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3870 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3870 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 303 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3567 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3870 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3870 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3870 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2416 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12175.289735 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11303.436072 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5287.236665 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 2213 91.60% 91.60% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 183 7.57% 99.17% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 19 0.79% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 4265 # Table walker walks requested +system.cpu0.itb.walker.walksShort 4265 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 325 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3940 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 4265 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 4265 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 4265 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2684 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12705.663189 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11959.550432 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5173.129128 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 2444 91.06% 91.06% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 221 8.23% 99.29% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 17 0.63% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2416 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2684 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 581277500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 581277500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 581277500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2118 87.67% 87.67% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 298 12.33% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2416 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2364 88.08% 88.08% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 320 11.92% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2684 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3870 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3870 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4265 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4265 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2416 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2416 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6286 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 36732226 # ITB inst hits -system.cpu0.itb.inst_misses 3870 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2684 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2684 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6949 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 71322502 # ITB inst hits +system.cpu0.itb.inst_misses 4265 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -522,131 +528,166 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2219 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2459 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7242 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7664 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 36736096 # ITB inst accesses -system.cpu0.itb.hits 36732226 # DTB hits -system.cpu0.itb.misses 3870 # DTB misses -system.cpu0.itb.accesses 36736096 # DTB accesses -system.cpu0.numCycles 162382442 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 71326767 # ITB inst accesses +system.cpu0.itb.hits 71322502 # DTB hits +system.cpu0.itb.misses 4265 # DTB misses +system.cpu0.itb.accesses 71326767 # DTB accesses +system.cpu0.numCycles 248723849 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 75583432 # Number of instructions committed -system.cpu0.committedOps 90974289 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 5013155 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 2059 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5135888904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.148387 # CPI: cycles per instruction -system.cpu0.ipc 0.465466 # IPC: instructions per cycle +system.cpu0.committedInsts 112829406 # Number of instructions committed +system.cpu0.committedOps 136421013 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 8883957 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1865 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5449058541 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.204424 # CPI: cycles per instruction +system.cpu0.ipc 0.453633 # IPC: instructions per cycle +system.cpu0.op_class_0::No_OpClass 2315 0.00% 0.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 92785256 68.01% 68.02% # Class of committed instruction +system.cpu0.op_class_0::IntMult 112251 0.08% 68.10% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 8279 0.01% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 68.10% # Class of committed instruction +system.cpu0.op_class_0::MemRead 24255979 17.78% 85.88% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 19256933 14.12% 100.00% # Class of committed instruction +system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu0.op_class_0::total 136421013 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 2063 # number of quiesce instructions executed -system.cpu0.tickCycles 121978989 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 40403453 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 680701 # number of replacements -system.cpu0.dcache.tags.tagsinuse 486.682235 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 28901777 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 681213 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 42.426931 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1871 # number of quiesce instructions executed +system.cpu0.tickCycles 199772172 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 48951677 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 757698 # number of replacements +system.cpu0.dcache.tags.tagsinuse 497.510170 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 41768211 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 758210 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.087919 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 600550000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 486.682235 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.950551 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.950551 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.510170 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971700 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.971700 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 60666006 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 60666006 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 14995152 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 14995152 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 12778726 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 12778726 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 305913 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 305913 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 356785 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 356785 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 351877 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 351877 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 27773878 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 27773878 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 28079791 # number of overall hits -system.cpu0.dcache.overall_hits::total 28079791 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 443645 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 443645 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 558771 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 558771 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131921 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 131921 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20933 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20933 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21449 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 21449 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1002416 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1002416 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1134337 # number of overall misses -system.cpu0.dcache.overall_misses::total 1134337 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6380347500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6380347500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11838491500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 11838491500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330148000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 330148000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 572278500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 572278500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 490000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 490000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 18218839000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 18218839000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 18218839000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 18218839000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15438797 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 15438797 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 13337497 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 13337497 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 437834 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 437834 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 377718 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 377718 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 373326 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 373326 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 28776294 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 28776294 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 29214128 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 29214128 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028736 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.028736 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041895 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.041895 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301304 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301304 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055420 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055420 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.057454 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.057454 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034835 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.034835 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038828 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.038828 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14381.650870 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14381.650870 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21186.660546 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 21186.660546 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15771.652415 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15771.652415 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26680.894214 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26680.894214 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 86683357 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 86683357 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 23240588 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23240588 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 17340312 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 17340312 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 329150 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 329150 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374937 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 374937 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370987 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 370987 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 40580900 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 40580900 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 40910050 # number of overall hits +system.cpu0.dcache.overall_hits::total 40910050 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 491866 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 491866 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 603751 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 603751 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141943 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 141943 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21447 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21447 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20439 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20439 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1095617 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1095617 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1237560 # number of overall misses +system.cpu0.dcache.overall_misses::total 1237560 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6971329500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6971329500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12451928500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 12451928500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330609500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 330609500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 530569000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 530569000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 651500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 651500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 19423258000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 19423258000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 19423258000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 19423258000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 23732454 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23732454 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 17944063 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 17944063 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 471093 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 471093 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396384 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 396384 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391426 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 391426 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 41676517 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 41676517 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 42147610 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 42147610 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.020725 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.020725 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033646 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.033646 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301306 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301306 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054107 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054107 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052217 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052217 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026289 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026289 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029363 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029363 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14173.229091 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14173.229091 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20624.278055 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20624.278055 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15415.186273 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15415.186273 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25958.657469 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25958.657469 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18174.928373 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18174.928373 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16061.222547 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 16061.222547 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17728.145876 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 17728.145876 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15694.801060 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15694.801060 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -655,149 +696,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 680701 # number of writebacks -system.cpu0.dcache.writebacks::total 680701 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 70219 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 70219 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 244921 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 244921 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14844 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14844 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 315140 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 315140 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 315140 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 315140 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 373426 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 373426 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 313850 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 313850 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99342 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 99342 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6089 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6089 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21449 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 21449 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 687276 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 687276 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 786618 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 786618 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17966 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17966 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16715 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16715 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34681 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34681 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4799499000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4799499000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6708842500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6708842500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1708183000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1708183000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97000000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97000000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 550839500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 550839500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 480000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 480000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11508341500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11508341500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13216524500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13216524500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3964655000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3964655000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3079216000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3079216000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7043871000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7043871000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024188 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024188 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023531 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023531 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226894 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226894 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016120 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016120 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.057454 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.057454 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023883 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023883 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026926 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026926 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12852.610691 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12852.610691 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21375.951888 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21375.951888 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17194.972922 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17194.972922 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15930.366234 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15930.366234 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25681.360436 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25681.360436 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 757698 # number of writebacks +system.cpu0.dcache.writebacks::total 757698 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 75572 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 75572 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266010 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 266010 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14891 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14891 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 341582 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 341582 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 341582 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 341582 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 416294 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 416294 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337741 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 337741 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 108342 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 108342 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6556 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6556 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20439 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20439 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 754035 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 754035 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 862377 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 862377 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32042 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32042 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28724 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28724 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60766 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60766 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5289052500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5289052500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7033138500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7033138500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1803466000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1803466000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104788000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104788000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 510140000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 510140000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 641500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 641500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12322191000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12322191000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14125657000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 14125657000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6702357000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6702357000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5444959500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5444959500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12147316500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12147316500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017541 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017541 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018822 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018822 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.229980 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.229980 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016540 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016540 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052217 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052217 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018093 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.018093 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020461 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.020461 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12705.089432 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12705.089432 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20824.058968 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20824.058968 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16646.046778 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16646.046778 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15983.526541 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15983.526541 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24959.146729 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24959.146729 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16744.861599 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16744.861599 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16801.706165 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16801.706165 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 220675.442503 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220675.442503 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 184218.725695 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184218.725695 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 203104.610594 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 203104.610594 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16341.669816 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16341.669816 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16379.909251 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16379.909251 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209174.115224 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209174.115224 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189561.325024 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189561.325024 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199903.177764 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199903.177764 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1875262 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.707229 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 34848846 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1875774 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 18.578382 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6975539000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.707229 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999428 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999428 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 2042425 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.725794 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 69271608 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 2042937 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 33.907853 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6975620000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.725794 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999464 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999464 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 75325070 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 75325070 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 34848846 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 34848846 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 34848846 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 34848846 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 34848846 # number of overall hits -system.cpu0.icache.overall_hits::total 34848846 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1875793 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1875793 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1875793 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1875793 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1875793 # number of overall misses -system.cpu0.icache.overall_misses::total 1875793 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18730135500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18730135500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18730135500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18730135500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18730135500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18730135500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 36724639 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 36724639 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 36724639 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 36724639 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 36724639 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 36724639 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051077 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.051077 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051077 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.051077 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051077 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.051077 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9985.182533 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9985.182533 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9985.182533 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9985.182533 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9985.182533 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9985.182533 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 144672089 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 144672089 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 69271608 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 69271608 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 69271608 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 69271608 # 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number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -806,464 +847,460 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 1875262 # number of writebacks -system.cpu0.icache.writebacks::total 1875262 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1875793 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1875793 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1875793 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1875793 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1875793 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 19557342500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19557342500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 19557342500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 557356500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 557356500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 557356500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 557356500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.051077 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.051077 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.051077 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.051077 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.051077 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.051077 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9485.182800 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9485.182800 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9485.182800 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9485.182800 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9485.182800 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9485.182800 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028647 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028647 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028647 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028647 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028647 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028647 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9573.051673 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9573.051673 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9573.051673 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9573.051673 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1759572 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1759695 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 108 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927381 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1927559 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 155 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 223393 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 281012 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16001.828165 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 4472083 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 297133 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 15.050779 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 244697 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 304900 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16120.127106 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 4899871 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 321020 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 15.263445 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15118.800161 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 44.428887 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.070691 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 838.528425 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.922778 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002712 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_blocks::writebacks 14747.855464 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 65.322901 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.062340 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1306.886401 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.900138 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003987 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.051180 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.976674 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 954 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 17 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15150 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 288 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 395 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 262 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 349 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4006 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8013 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2701 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.058228 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001038 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.924683 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 85407529 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 85407529 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 81193 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4894 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 86087 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 464150 # 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number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2916947999 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 31901000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1833000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 4100378000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5357247999 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 9491359999 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 31901000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1833000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 4100378000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5357247999 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21051299430 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 30542659429 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 526020000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3820755500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4346775500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2953338000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2953338000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6445890500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6971910500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5229022000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5229022000 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 526020000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6774093500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7300113500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009588 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.023154 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010369 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11674912500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12200932500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009054 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.162793 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.162793 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.032080 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.032080 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.209154 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.209154 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009588 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.023154 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.032080 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192971 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075242 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009588 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.023154 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.032080 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192971 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150478 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150478 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034232 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034232 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.188570 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.188570 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034232 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.175382 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.072306 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034232 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.175382 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.166547 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36727.099237 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17288.793103 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34227.272727 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 81971.291951 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 81971.291951 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25307.858808 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25307.858808 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18145.521518 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18145.521518 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 200999.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 200999.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56332.256907 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56332.256907 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 59786.314915 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 59786.314915 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27498.028017 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27498.028017 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36727.099237 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17288.793103 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 59786.314915 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35989.317324 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 43034.348579 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36727.099237 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17288.793103 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 59786.314915 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35989.317324 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 81971.291951 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 64380.460217 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.161933 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 39501.170960 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79624.255077 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 79624.255077 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26001.258151 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26001.258151 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17421.547042 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17421.547042 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57646.697534 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57646.697534 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 58632.110275 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29121.138899 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29121.138899 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37595.250453 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44500.623571 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37595.250453 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79624.255077 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63941.054222 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 212665.896694 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198637.092720 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 176687.885133 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176687.885133 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201170.042444 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193884.994021 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182043.656872 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182043.656872 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 195325.783570 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 189131.910980 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192129.027746 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188626.571124 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 5267322 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2655927 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 41328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 334158 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 329304 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4854 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 119336 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2522924 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 16715 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 16715 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 692222 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 2091812 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 222834 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 309300 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 91686 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43805 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 115698 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 274549 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 271267 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1875793 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 569005 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3104 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5634681 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2479031 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12447 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 171956 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 8298115 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 240318144 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 94807159 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 20040 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 327916 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 335473259 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1039321 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3754204 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.107024 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.313298 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 5755490 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2900081 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44333 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 350983 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 345970 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5013 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 141142 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2764242 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28724 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28724 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 743774 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 2294086 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 245615 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 332229 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 86791 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42912 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113818 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 300259 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 296935 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2042958 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 604813 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3110 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6136174 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2759564 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14116 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 185351 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 9095205 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 261715136 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104822354 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 23644 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 353660 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 366914794 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1076546 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4066304 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.104124 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.309432 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3357269 89.43% 89.43% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 392081 10.44% 99.87% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4854 0.13% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3647917 89.71% 89.71% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 413374 10.17% 99.88% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 5013 0.12% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3754204 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 5255285493 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 4066304 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 5765624998 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 113846370 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115477021 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2820178266 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 3070848423 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1169961199 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1304480252 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7446481 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 8215479 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 90008437 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 96957457 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 20449244 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7039055 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 963225 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 10410340 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 7679577 # Number of BTB hits +system.cpu1.branchPred.lookups 3600044 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2023819 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 196135 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2284720 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1344428 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.768743 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 8836366 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 692168 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 58.844322 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 748131 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 53981 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 144785 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 107908 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 36877 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 17103 # Number of mispredicted indirect branches. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1293,58 +1330,58 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 30868 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 30868 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 23108 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7760 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 30868 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 30868 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 30868 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2696 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11992.210682 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10915.827455 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 8355.113227 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 2479 91.95% 91.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 196 7.27% 99.22% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-49151 12 0.45% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.11% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-147455 3 0.11% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::147456-163839 3 0.11% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2696 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1558893032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1558893032 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1558893032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1974 73.22% 73.22% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 722 26.78% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2696 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30868 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 22955 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 22955 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18858 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4097 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 22955 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 22955 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 22955 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1846 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11730.498375 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11025.049339 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6418.983235 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 1704 92.31% 92.31% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 130 7.04% 99.35% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-49151 9 0.49% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-65535 1 0.05% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1846 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1572230032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1572230032 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1572230032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1316 71.29% 71.29% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 530 28.71% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1846 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 22955 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30868 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2696 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 22955 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1846 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2696 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 33564 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1846 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 24801 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12117944 # DTB read hits -system.cpu1.dtb.read_misses 28100 # DTB read misses -system.cpu1.dtb.write_hits 7719144 # DTB write hits -system.cpu1.dtb.write_misses 2768 # DTB write misses +system.cpu1.dtb.read_hits 3573471 # DTB read hits +system.cpu1.dtb.read_misses 21372 # DTB read misses +system.cpu1.dtb.write_hits 2968093 # DTB write hits +system.cpu1.dtb.write_misses 1583 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2067 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 330 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 545 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1717 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 261 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 280 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12146044 # DTB read accesses -system.cpu1.dtb.write_accesses 7721912 # DTB write accesses +system.cpu1.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3594843 # DTB read accesses +system.cpu1.dtb.write_accesses 2969676 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 19837088 # DTB hits -system.cpu1.dtb.misses 30868 # DTB misses -system.cpu1.dtb.accesses 19867956 # DTB accesses +system.cpu1.dtb.hits 6541564 # DTB hits +system.cpu1.dtb.misses 22955 # DTB misses +system.cpu1.dtb.accesses 6564519 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1374,44 +1411,44 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 2320 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2320 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 184 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2136 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2320 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2320 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2320 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1123 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12081.032947 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11456.275098 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4603.593303 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 188 16.74% 16.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 645 57.44% 74.18% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 209 18.61% 92.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.36% 97.15% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 97.24% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 1.34% 98.58% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 3 0.27% 98.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.09% 98.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 10 0.89% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1123 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1559948532 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1559948532 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1559948532 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 953 84.86% 84.86% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 170 15.14% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1123 # Table walker page sizes translated +system.cpu1.itb.walker.walks 2082 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2082 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 151 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1931 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2082 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2082 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2082 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 843 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11844.009490 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11365.721789 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4291.658656 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 129 15.30% 15.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 559 66.31% 81.61% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 106 12.57% 94.19% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 28 3.32% 97.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.24% 97.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 9 1.07% 98.81% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 1 0.12% 98.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.24% 99.17% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.59% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.12% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.12% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 843 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1573105532 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1573105532 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1573105532 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 703 83.39% 83.39% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 140 16.61% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 843 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2320 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2320 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2082 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2082 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1123 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1123 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3443 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 41835871 # ITB inst hits -system.cpu1.itb.inst_misses 2320 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 843 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 843 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2925 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 6880260 # ITB inst hits +system.cpu1.itb.inst_misses 2082 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1420,130 +1457,165 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1161 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 907 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1837 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1103 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 41838191 # ITB inst accesses -system.cpu1.itb.hits 41835871 # DTB hits -system.cpu1.itb.misses 2320 # DTB misses -system.cpu1.itb.accesses 41838191 # DTB accesses -system.cpu1.numCycles 128464441 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 6882342 # ITB inst accesses +system.cpu1.itb.hits 6880260 # DTB hits +system.cpu1.itb.misses 2082 # DTB misses +system.cpu1.itb.accesses 6882342 # DTB accesses +system.cpu1.numCycles 40344479 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 51881050 # Number of instructions committed -system.cpu1.committedOps 63376562 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 5336781 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2726 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5169132523 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.476134 # CPI: cycles per instruction -system.cpu1.ipc 0.403855 # IPC: instructions per cycle +system.cpu1.committedInsts 14007066 # Number of instructions committed +system.cpu1.committedOps 17164558 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1348197 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2750 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5656772716 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.880295 # CPI: cycles per instruction +system.cpu1.ipc 0.347187 # IPC: instructions per cycle +system.cpu1.op_class_0::No_OpClass 24 0.00% 0.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 10609725 61.81% 61.81% # Class of committed instruction +system.cpu1.op_class_0::IntMult 25154 0.15% 61.96% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 61.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 3180 0.02% 61.98% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 61.98% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 61.98% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 61.98% # Class of committed instruction +system.cpu1.op_class_0::MemRead 3461168 20.16% 82.14% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 3065307 17.86% 100.00% # Class of committed instruction +system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu1.op_class_0::total 17164558 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2733 # number of quiesce instructions executed -system.cpu1.tickCycles 105981069 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 22483372 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 234073 # number of replacements -system.cpu1.dcache.tags.tagsinuse 481.612157 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 19315800 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 234411 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 82.401423 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 91649523000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.612157 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940649 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.940649 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 43 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.660156 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 39692249 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 39692249 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 11657958 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 11657958 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7379701 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7379701 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 66326 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 66326 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88715 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 88715 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80616 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 80616 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19037659 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19037659 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19103985 # number of overall hits -system.cpu1.dcache.overall_hits::total 19103985 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 186675 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 186675 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 168872 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 168872 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35031 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 35031 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17765 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17765 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23562 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23562 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 355547 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 355547 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 390578 # number of overall misses -system.cpu1.dcache.overall_misses::total 390578 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2934466500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2934466500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5329870000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 5329870000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 334697000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 334697000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 633629500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 633629500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 219500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 219500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8264336500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8264336500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8264336500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8264336500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11844633 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11844633 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7548573 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7548573 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 101357 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 101357 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106480 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 106480 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 104178 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 104178 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 19393206 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 19393206 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 19494563 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 19494563 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.015760 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.015760 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.022371 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.022371 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.345620 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.345620 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.166839 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.166839 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.226171 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.226171 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.018334 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.018334 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.020035 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.020035 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15719.654480 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15719.654480 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31561.596949 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 31561.596949 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18840.247678 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18840.247678 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26892.008318 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26892.008318 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2755 # number of quiesce instructions executed +system.cpu1.tickCycles 27219778 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 13124701 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 155125 # number of replacements +system.cpu1.dcache.tags.tagsinuse 474.675908 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6200474 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 155475 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 39.880843 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 91637729500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.675908 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.927101 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.927101 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 281 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 69 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.683594 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 13156233 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 13156233 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3254524 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3254524 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2729726 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2729726 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42620 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 42620 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70434 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 70434 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61835 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 61835 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 5984250 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 5984250 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6026870 # number of overall hits +system.cpu1.dcache.overall_hits::total 6026870 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 133031 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 133031 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 121759 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 121759 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24466 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 24466 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16570 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16570 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23417 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23417 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 254790 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 254790 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 279256 # number of overall misses +system.cpu1.dcache.overall_misses::total 279256 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2166796500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2166796500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4455024500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4455024500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320532500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 320532500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 635944000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 635944000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1106500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1106500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6621821000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6621821000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6621821000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6621821000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3387555 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3387555 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2851485 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2851485 # 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number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1552,148 +1624,149 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 234075 # number of writebacks -system.cpu1.dcache.writebacks::total 234075 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18534 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 18534 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62653 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 62653 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12294 # 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average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14706.332780 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30477.513439 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30477.513439 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17432.201370 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17432.201370 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18112.136721 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18112.136721 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25892.093201 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25892.093201 # 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number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2713747500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2713747500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 448609500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 448609500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89247000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89247000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 612539000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 612539000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1094500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1094500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4556767000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4556767000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5005376500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5005376500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 389467000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 389467000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 251809500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 251809500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641276500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641276500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035506 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035506 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027923 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027923 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.356796 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.356796 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056135 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056135 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274680 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274680 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032040 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.032040 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035495 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035495 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15322.997556 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15322.997556 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34082.457330 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34082.457330 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18742.041277 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18742.041277 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18273.341523 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18273.341523 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26157.876756 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26157.876756 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20812.175609 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20812.175609 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20443.696619 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20443.696619 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182436.662784 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182436.662784 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182102.629758 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 182102.629758 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 182284.013283 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 182284.013283 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22795.118584 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22795.118584 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22361.702936 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22361.702936 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131001.345442 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 131001.345442 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 108961.272177 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 108961.272177 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121361.941711 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121361.941711 # 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Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6021932 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 857169 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 7.025373 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 73312939000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.135889 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974875 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974875 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 50 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 84713500 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 84713500 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 40788041 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 40788041 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 40788041 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 40788041 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 40788041 # number of overall hits -system.cpu1.icache.overall_hits::total 40788041 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 1045806 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 1045806 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 1045806 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 1045806 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 1045806 # number of overall misses -system.cpu1.icache.overall_misses::total 1045806 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9756409000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 9756409000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 9756409000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 9756409000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 9756409000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 9756409000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 41833847 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 41833847 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 41833847 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 41833847 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 41833847 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 41833847 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024999 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024999 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024999 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024999 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024999 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024999 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9329.081111 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9329.081111 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9329.081111 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9329.081111 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9329.081111 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9329.081111 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 14615371 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 14615371 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 6021932 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6021932 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6021932 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6021932 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6021932 # number of overall hits +system.cpu1.icache.overall_hits::total 6021932 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 857169 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 857169 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 857169 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 857169 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 857169 # number of overall misses +system.cpu1.icache.overall_misses::total 857169 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7590039500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7590039500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7590039500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7590039500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7590039500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7590039500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 6879101 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 6879101 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 6879101 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 6879101 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 6879101 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 6879101 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.124605 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.124605 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.124605 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.124605 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.124605 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.124605 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8854.776013 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8854.776013 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8854.776013 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8854.776013 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8854.776013 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8854.776013 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1702,453 +1775,464 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # 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number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 857169 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 857169 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 857169 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 857169 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 857169 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 857169 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9233506000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 9233506000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9233506000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 9233506000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9233506000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 9233506000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15350500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15350500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15350500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 15350500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024999 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024999 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024999 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024999 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024999 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024999 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8829.081111 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8829.081111 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8829.081111 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8829.081111 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8829.081111 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8829.081111 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137058.035714 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137058.035714 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7161455000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7161455000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7161455000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7161455000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7161455000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7161455000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15471500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15471500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15471500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 15471500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.124605 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.124605 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.124605 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.124605 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.124605 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.124605 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8354.776013 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8354.776013 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8354.776013 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8354.776013 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 138138.392857 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 138138.392857 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 138138.392857 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 274967 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 275055 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 76 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 119555 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 119603 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 42 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # 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Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14349.457044 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 61.253461 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.124525 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1150.572683 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.875821 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003739 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000008 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.070225 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.949793 # 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average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15839.048673 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48141.089849 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48141.089849 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20158.858671 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20158.858671 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18611.232116 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18611.232116 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 500499.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 500499.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46505.975598 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46505.975598 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 51500.038889 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18067.826079 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18067.826079 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27308.083789 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29983.303639 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27308.083789 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48141.089849 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32725.097946 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122984.695594 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123244.408428 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101403.937689 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101403.937689 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113546.177139 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113890.567087 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 2671947 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1344357 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 22211 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 212012 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 209828 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2184 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 60366 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1353600 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 14450 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 14450 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 179270 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 1143304 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 137947 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 47540 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 74191 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43096 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 89660 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 82906 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 80697 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1045806 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295809 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 50 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3137130 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1052074 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7597 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 73953 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 4270754 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 133837568 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 36094549 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12564 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 141300 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 170085981 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 473244 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1845377 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.133426 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.343498 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 2128285 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1071677 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18282 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 177050 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 175620 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1430 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 34150 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1077374 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2311 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2311 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 124900 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 917333 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 97527 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 24473 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71017 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41707 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 84949 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 57470 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 55019 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 857169 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 232907 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 41 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2571219 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 743876 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6996 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 52037 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3374128 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 109692032 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25376564 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11932 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 99940 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 135180468 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 380471 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1449236 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.140738 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.350577 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1601339 86.78% 86.78% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 241854 13.11% 99.88% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 2184 0.12% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1246703 86.02% 86.02% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 201103 13.88% 99.90% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1430 0.10% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1845377 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2655073991 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1449236 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2091716493 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 86773438 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 78610365 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1569094564 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 476141581 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1286047248 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 331216893 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4456000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4013000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 38655445 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 27068966 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31014 # Transaction distribution -system.iobus.trans_dist::ReadResp 31014 # Transaction distribution -system.iobus.trans_dist::WriteReq 59421 # Transaction distribution -system.iobus.trans_dist::WriteResp 59421 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31009 # Transaction distribution +system.iobus.trans_dist::ReadResp 31009 # Transaction distribution +system.iobus.trans_dist::WriteReq 59425 # Transaction distribution +system.iobus.trans_dist::WriteResp 59425 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2161,17 +2245,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107910 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2184,23 +2268,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 51031501 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48277500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 109500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 336000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 29000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 13000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 88000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 565500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 577000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 19000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2208,13 +2292,13 @@ system.iobus.reqLayer13.occupancy 8500 # La system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 46000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) @@ -2222,54 +2306,54 @@ system.iobus.reqLayer20.occupancy 9500 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6103500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6148000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 32838000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33110001 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187160706 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187086234 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84713000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36784000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36462 # number of replacements -system.iocache.tags.tagsinuse 14.353695 # Cycle average of tags in use +system.iocache.tags.replacements 36433 # number of replacements +system.iocache.tags.tagsinuse 14.469289 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36478 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 272566004000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.353695 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.897106 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.897106 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 272370801000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.469289 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904331 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904331 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328320 # Number of tag accesses -system.iocache.tags.data_accesses 328320 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 256 # number of ReadReq misses -system.iocache.ReadReq_misses::total 256 # number of ReadReq misses +system.iocache.tags.tag_accesses 328203 # Number of tag accesses +system.iocache.tags.data_accesses 328203 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses +system.iocache.ReadReq_misses::total 243 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 256 # number of demand (read+write) misses -system.iocache.demand_misses::total 256 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 256 # number of overall misses -system.iocache.overall_misses::total 256 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 33038877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 33038877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4577477829 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4577477829 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 33038877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 33038877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 33038877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 33038877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 256 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 256 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses +system.iocache.demand_misses::total 243 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 243 # number of overall misses +system.iocache.overall_misses::total 243 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31660877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31660877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4578259357 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4578259357 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31660877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31660877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31660877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31660877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 256 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 256 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 256 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 256 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2278,40 +2362,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129058.113281 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129058.113281 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126365.885297 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126365.885297 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 129058.113281 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 129058.113281 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 129058.113281 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 129058.113281 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 12 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 130291.674897 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 130291.674897 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126387.460165 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126387.460165 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 130291.674897 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 130291.674897 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 130291.674897 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 130291.674897 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36206 # number of writebacks -system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 256 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 256 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 256 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 256 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 256 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 256 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 20238877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 20238877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764566568 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2764566568 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 20238877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 20238877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 20238877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 20238877 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19510877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19510877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2765398414 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2765398414 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19510877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19510877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19510877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19510877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2320,576 +2404,575 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79058.113281 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 79058.113281 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76318.644214 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76318.644214 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 79058.113281 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 79058.113281 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 79058.113281 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 79058.113281 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80291.674897 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 80291.674897 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76341.608160 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76341.608160 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 80291.674897 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 80291.674897 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 80291.674897 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 80291.674897 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 134245 # number of replacements -system.l2c.tags.tagsinuse 63310.759075 # Cycle average of tags in use -system.l2c.tags.total_refs 474981 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 198059 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.398179 # Average number of references to valid blocks. +system.l2c.tags.replacements 132278 # number of replacements +system.l2c.tags.tagsinuse 63284.055151 # Cycle average of tags in use +system.l2c.tags.total_refs 475189 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 196356 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.420038 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 14231.075006 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 68.949164 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999781 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7026.716381 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2024.667607 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 30360.457538 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 27.102838 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4106.821272 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1547.963396 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3916.006093 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.217149 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001052 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.107219 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.030894 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.463264 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000414 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.062665 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.023620 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.059754 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.966046 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 27725 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 35997 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 133 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4285 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 23307 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 91 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 428 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3332 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 32208 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.423050 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.001404 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.549271 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6430843 # Number of tag accesses -system.l2c.tags.data_accesses 6430843 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 269664 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 269664 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 32870 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 3603 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 36473 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1969 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1232 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3201 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4063 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2251 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 6314 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 366 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 61 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 40218 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 47314 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45570 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 178 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 25 # 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number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 8121 # number of demand (read+write) hits -system.l2c.demand_hits::total 181454 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 366 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 61 # number of overall hits -system.l2c.overall_hits::cpu0.inst 40218 # number of overall hits -system.l2c.overall_hits::cpu0.data 51377 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 45570 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 178 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 25 # number of overall hits -system.l2c.overall_hits::cpu1.inst 20885 # number of overall hits -system.l2c.overall_hits::cpu1.data 14653 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 8121 # number of overall hits -system.l2c.overall_hits::total 181454 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9292 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129412.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122469.112521 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124118.079453 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156673.498705 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 137191.647062 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121108.391191 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133328.864550 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140333.580665 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125863.636364 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123255.799619 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123072.534527 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 136698.978074 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194664.561616 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 156457.826411 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169529.646596 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 159680.317200 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157593.287266 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 158712.642484 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183168.856719 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 105088.889899 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 170005.801849 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165038.278199 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84398.529641 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159033.494603 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 177803.408668 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 156976.769048 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 164736.154294 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174598.558569 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 96034.653475 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 165146.426951 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 39162 # Transaction distribution -system.membus.trans_dist::ReadResp 215417 # Transaction distribution -system.membus.trans_dist::WriteReq 31165 # Transaction distribution -system.membus.trans_dist::WriteResp 31165 # Transaction distribution -system.membus.trans_dist::WritebackDirty 139900 # Transaction distribution -system.membus.trans_dist::CleanEvict 18801 # Transaction distribution -system.membus.trans_dist::UpgradeReq 78213 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41798 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 40189 # Transaction distribution -system.membus.trans_dist::ReadExResp 19404 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 176255 # Transaction distribution +system.membus.trans_dist::ReadReq 39041 # Transaction distribution +system.membus.trans_dist::ReadResp 216336 # Transaction distribution +system.membus.trans_dist::WriteReq 31035 # Transaction distribution +system.membus.trans_dist::WriteResp 31035 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138525 # Transaction distribution +system.membus.trans_dist::CleanEvict 18214 # Transaction distribution +system.membus.trans_dist::UpgradeReq 73002 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40704 # Transaction distribution +system.membus.trans_dist::UpgradeResp 16 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 39822 # Transaction distribution +system.membus.trans_dist::ReadExResp 19318 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 177295 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14740 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 671466 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 794158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72957 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72957 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 867115 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14218 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664863 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 787057 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72915 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72915 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 859972 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19397092 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19590708 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21908852 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 125573 # Total snoops (count) -system.membus.snoop_fanout::samples 601741 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28436 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19371036 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19563630 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21880750 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 120342 # Total snoops (count) +system.membus.snoop_fanout::samples 593889 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 601741 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 593889 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 601741 # Request fanout histogram -system.membus.reqLayer0.occupancy 91242999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 593889 # Request fanout histogram +system.membus.reqLayer0.occupancy 88806999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12732000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12293000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1019564727 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1011120672 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1144074788 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1148583006 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1412877 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1341627 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2932,52 +3015,52 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 1069309 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 577929 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 171835 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 21548 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 20404 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1144 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 39165 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 514340 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31165 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31165 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 409596 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 144328 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 114559 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 44999 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 159558 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51602 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51602 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 475191 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 1040507 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 561217 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 153026 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 21153 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 20199 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 954 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 39044 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 500503 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31035 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 404834 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 139205 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 109172 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43834 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 153006 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 22 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50921 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50921 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 461474 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1207299 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 435215 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1642514 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34510571 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7361417 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 41871988 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 461244 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 963683 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.359503 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.482323 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1330590 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 273408 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1603998 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36819910 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4347048 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 41166958 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 447482 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 940492 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.338468 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.475327 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 618380 64.17% 64.17% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 344159 35.71% 99.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1144 0.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 623120 66.25% 66.25% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 316418 33.64% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 954 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 963683 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 919452336 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 940492 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 900307645 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 360123 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 342123 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 640437781 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 690598933 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 288270065 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 213088139 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |