diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini | 111 |
1 files changed, 68 insertions, 43 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini index 6291ea543..b511ae924 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm +boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain default_p_state=UNDEFINED -dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -49,7 +49,7 @@ panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh +readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh reset_addr_64=0 symbolfile= thermal_components= @@ -99,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img +image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -175,6 +175,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system threadPolicy=RoundRobin tracer=system.cpu.tracer @@ -212,10 +213,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -229,6 +230,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -241,15 +243,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -461,9 +464,9 @@ timings=system.cpu.executeFuncUnits.funcUnits4.timings [system.cpu.executeFuncUnits.funcUnits4.opClasses] type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] type=MinorOpClass @@ -483,116 +486,126 @@ opClass=FloatCvt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] type=MinorOpClass eventq_index=0 -opClass=FloatMult +opClass=FloatMisc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] type=MinorOpClass eventq_index=0 -opClass=FloatDiv +opClass=FloatMult [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] type=MinorOpClass eventq_index=0 -opClass=FloatSqrt +opClass=FloatMultAcc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] type=MinorOpClass eventq_index=0 -opClass=SimdAdd +opClass=FloatDiv [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] type=MinorOpClass eventq_index=0 -opClass=SimdAddAcc +opClass=FloatSqrt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] type=MinorOpClass eventq_index=0 -opClass=SimdAlu +opClass=SimdAdd [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] type=MinorOpClass eventq_index=0 -opClass=SimdCmp +opClass=SimdAddAcc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] type=MinorOpClass eventq_index=0 -opClass=SimdCvt +opClass=SimdAlu [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] type=MinorOpClass eventq_index=0 -opClass=SimdMisc +opClass=SimdCmp [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] type=MinorOpClass eventq_index=0 -opClass=SimdMult +opClass=SimdCvt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] type=MinorOpClass eventq_index=0 -opClass=SimdMultAcc +opClass=SimdMisc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] type=MinorOpClass eventq_index=0 -opClass=SimdShift +opClass=SimdMult [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] type=MinorOpClass eventq_index=0 -opClass=SimdShiftAcc +opClass=SimdMultAcc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] type=MinorOpClass eventq_index=0 -opClass=SimdSqrt +opClass=SimdShift [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] type=MinorOpClass eventq_index=0 -opClass=SimdFloatAdd +opClass=SimdShiftAcc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] type=MinorOpClass eventq_index=0 -opClass=SimdFloatAlu +opClass=SimdSqrt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] type=MinorOpClass eventq_index=0 -opClass=SimdFloatCmp +opClass=SimdFloatAdd [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] type=MinorOpClass eventq_index=0 -opClass=SimdFloatCvt +opClass=SimdFloatAlu [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] type=MinorOpClass eventq_index=0 -opClass=SimdFloatDiv +opClass=SimdFloatCmp [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] type=MinorOpClass eventq_index=0 -opClass=SimdFloatMisc +opClass=SimdFloatCvt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] type=MinorOpClass eventq_index=0 -opClass=SimdFloatMult +opClass=SimdFloatDiv [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] type=MinorOpClass eventq_index=0 -opClass=SimdFloatMultAcc +opClass=SimdFloatMisc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] type=MinorOpClass eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27] +type=MinorOpClass +eventq_index=0 opClass=SimdFloatSqrt [system.cpu.executeFuncUnits.funcUnits4.timings] @@ -626,9 +639,9 @@ timings=system.cpu.executeFuncUnits.funcUnits5.timings [system.cpu.executeFuncUnits.funcUnits5.opClasses] type=MinorOpClassSet -children=opClasses0 opClasses1 +children=opClasses0 opClasses1 opClasses2 opClasses3 eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] type=MinorOpClass @@ -640,6 +653,16 @@ type=MinorOpClass eventq_index=0 opClass=MemWrite +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemWrite + [system.cpu.executeFuncUnits.funcUnits5.timings] type=MinorFUTiming children=opClasses @@ -692,10 +715,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -709,6 +732,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -721,15 +745,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -748,8 +773,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -760,8 +783,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -824,10 +845,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -841,6 +862,7 @@ response_latency=20 sequential_access=false size=4194304 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -853,15 +875,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=4194304 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -941,10 +964,10 @@ addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +data_latency=50 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 @@ -958,6 +981,7 @@ response_latency=50 sequential_access=false size=1024 system=system +tag_latency=50 tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 @@ -970,15 +994,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +data_latency=50 default_p_state=UNDEFINED eventq_index=0 -hit_latency=50 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=1024 +tag_latency=50 [system.membus] type=CoherentXBar |