diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt | 1311 |
1 files changed, 656 insertions, 655 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 4491c3f13..4c74a9fb4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.567677 # Number of seconds simulated -sim_ticks 2567677478000 # Number of ticks simulated -final_tick 2567677478000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.566439 # Number of seconds simulated +sim_ticks 2566439177500 # Number of ticks simulated +final_tick 2566439177500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53140 # Simulator instruction rate (inst/s) -host_op_rate 68307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2251849348 # Simulator tick rate (ticks/s) -host_mem_usage 443244 # Number of bytes of host memory used -host_seconds 1140.25 # Real time elapsed on the host -sim_insts 60592948 # Number of instructions simulated -sim_ops 77887482 # Number of ops (including micro ops) simulated +host_inst_rate 73545 # Simulator instruction rate (inst/s) +host_op_rate 88536 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3115018228 # Simulator tick rate (ticks/s) +host_mem_usage 470576 # Number of bytes of host memory used +host_seconds 823.89 # Real time elapsed on the host +sim_insts 60593470 # Number of instructions simulated +sim_ops 72944147 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10106264 # Number of bytes read from this memory -system.physmem.bytes_read::total 131218072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1017856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1017856 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3829760 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 10079960 # Number of bytes read from this memory +system.physmem.bytes_read::total 131191960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1001344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1001344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3811328 # Number of bytes written to this memory system.physmem.bytes_written::cpu.inst 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6845832 # Number of bytes written to this memory +system.physmem.bytes_written::total 6827400 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 157946 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15296782 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59840 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 157525 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15296364 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59552 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.inst 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813858 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47167344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 449 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813570 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47190103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 524 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 3935955 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51103798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 396411 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 396411 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1491527 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.inst 1174630 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2666157 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1491527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47167344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3927605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51118281 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 390169 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 390169 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1485065 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.inst 1175197 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2660262 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1485065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47190103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 524 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5110586 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53769956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15296782 # Number of read requests accepted -system.physmem.writeReqs 813858 # Number of write requests accepted -system.physmem.readBursts 15296782 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813858 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 978883904 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 110144 # Total number of bytes read from write queue -system.physmem.bytesWritten 6853696 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131218072 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6845832 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1721 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706743 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4671 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955926 # Per bank write bursts -system.physmem.perBankRdBursts::1 955615 # Per bank write bursts -system.physmem.perBankRdBursts::2 955732 # Per bank write bursts -system.physmem.perBankRdBursts::3 955955 # Per bank write bursts -system.physmem.perBankRdBursts::4 957630 # Per bank write bursts -system.physmem.perBankRdBursts::5 955653 # Per bank write bursts -system.physmem.perBankRdBursts::6 955569 # Per bank write bursts -system.physmem.perBankRdBursts::7 955430 # Per bank write bursts -system.physmem.perBankRdBursts::8 956341 # Per bank write bursts -system.physmem.perBankRdBursts::9 955977 # Per bank write bursts -system.physmem.perBankRdBursts::10 955547 # Per bank write bursts -system.physmem.perBankRdBursts::11 955151 # Per bank write bursts -system.physmem.perBankRdBursts::12 956306 # Per bank write bursts -system.physmem.perBankRdBursts::13 956026 # Per bank write bursts -system.physmem.perBankRdBursts::14 956165 # Per bank write bursts -system.physmem.perBankRdBursts::15 956038 # Per bank write bursts -system.physmem.perBankWrBursts::0 6624 # Per bank write bursts -system.physmem.perBankWrBursts::1 6445 # Per bank write bursts -system.physmem.perBankWrBursts::2 6544 # Per bank write bursts -system.physmem.perBankWrBursts::3 6594 # Per bank write bursts -system.physmem.perBankWrBursts::4 6491 # Per bank write bursts -system.physmem.perBankWrBursts::5 6747 # Per bank write bursts -system.physmem.perBankWrBursts::6 6783 # Per bank write bursts -system.physmem.perBankWrBursts::7 6690 # Per bank write bursts -system.physmem.perBankWrBursts::8 7075 # Per bank write bursts -system.physmem.perBankWrBursts::9 6811 # Per bank write bursts -system.physmem.perBankWrBursts::10 6482 # Per bank write bursts -system.physmem.perBankWrBursts::11 6150 # Per bank write bursts -system.physmem.perBankWrBursts::12 7106 # Per bank write bursts -system.physmem.perBankWrBursts::13 6684 # Per bank write bursts -system.physmem.perBankWrBursts::14 7011 # Per bank write bursts -system.physmem.perBankWrBursts::15 6852 # Per bank write bursts +system.physmem.bw_total::cpu.inst 5102802 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15296364 # Number of read requests accepted +system.physmem.writeReqs 813570 # Number of write requests accepted +system.physmem.readBursts 15296364 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813570 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 978868736 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 98560 # Total number of bytes read from write queue +system.physmem.bytesWritten 6836224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131191960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6827400 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1540 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706728 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4670 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955903 # Per bank write bursts +system.physmem.perBankRdBursts::1 955584 # Per bank write bursts +system.physmem.perBankRdBursts::2 955711 # Per bank write bursts +system.physmem.perBankRdBursts::3 955912 # Per bank write bursts +system.physmem.perBankRdBursts::4 957606 # Per bank write bursts +system.physmem.perBankRdBursts::5 955733 # Per bank write bursts +system.physmem.perBankRdBursts::6 955604 # Per bank write bursts +system.physmem.perBankRdBursts::7 955438 # Per bank write bursts +system.physmem.perBankRdBursts::8 956293 # Per bank write bursts +system.physmem.perBankRdBursts::9 955954 # Per bank write bursts +system.physmem.perBankRdBursts::10 955536 # Per bank write bursts +system.physmem.perBankRdBursts::11 955097 # Per bank write bursts +system.physmem.perBankRdBursts::12 956286 # Per bank write bursts +system.physmem.perBankRdBursts::13 955995 # Per bank write bursts +system.physmem.perBankRdBursts::14 956150 # Per bank write bursts +system.physmem.perBankRdBursts::15 956022 # Per bank write bursts +system.physmem.perBankWrBursts::0 6610 # Per bank write bursts +system.physmem.perBankWrBursts::1 6419 # Per bank write bursts +system.physmem.perBankWrBursts::2 6537 # Per bank write bursts +system.physmem.perBankWrBursts::3 6577 # Per bank write bursts +system.physmem.perBankWrBursts::4 6482 # Per bank write bursts +system.physmem.perBankWrBursts::5 6744 # Per bank write bursts +system.physmem.perBankWrBursts::6 6779 # Per bank write bursts +system.physmem.perBankWrBursts::7 6682 # Per bank write bursts +system.physmem.perBankWrBursts::8 7031 # Per bank write bursts +system.physmem.perBankWrBursts::9 6794 # Per bank write bursts +system.physmem.perBankWrBursts::10 6476 # Per bank write bursts +system.physmem.perBankWrBursts::11 6093 # Per bank write bursts +system.physmem.perBankWrBursts::12 7096 # Per bank write bursts +system.physmem.perBankWrBursts::13 6664 # Per bank write bursts +system.physmem.perBankWrBursts::14 6987 # Per bank write bursts +system.physmem.perBankWrBursts::15 6845 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2567675574500 # Total gap between requests +system.physmem.totGap 2566437420000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 38 # Read request sizes (log2) -system.physmem.readPktSize::3 15138816 # Read request sizes (log2) +system.physmem.readPktSize::2 18 # Read request sizes (log2) +system.physmem.readPktSize::3 15138826 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157928 # Read request sizes (log2) +system.physmem.readPktSize::6 157520 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59840 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1112326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 958648 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 963944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1085542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 974308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1043218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2679684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2578598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3358182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 142716 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 121801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 111705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 108393 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59552 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1111382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 958419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 963594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1074014 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 973771 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1037292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2691805 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2600171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3390697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 128159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 109522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 101552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 98177 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -155,25 +155,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -204,63 +204,64 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1015088 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 971.085857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 904.509360 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 205.145024 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22501 2.22% 2.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22772 2.24% 4.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8563 0.84% 5.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2455 0.24% 5.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2778 0.27% 5.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1897 0.19% 6.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8457 0.83% 6.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 971 0.10% 6.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 944694 93.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1015088 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6216 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2460.593951 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 115853.550339 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6211 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1014534 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 971.583959 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 905.812030 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 204.103928 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21965 2.17% 2.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22634 2.23% 4.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8771 0.86% 5.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2477 0.24% 5.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2600 0.26% 5.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1707 0.17% 5.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8766 0.86% 6.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1031 0.10% 6.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 944583 93.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1014534 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6199 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2467.302629 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 115861.516346 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6194 99.92% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6216 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6216 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.227960 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.199911 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.974162 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2395 38.53% 38.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 16 0.26% 38.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3798 61.10% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 7 0.11% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6216 # Writes before turning the bus around for reads -system.physmem.totQLat 396370290250 # Total ticks spent queuing -system.physmem.totMemAccLat 683152684000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76475305000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25914.92 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6199 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6199 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.231166 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.203067 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.975146 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2381 38.41% 38.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 18 0.29% 38.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3787 61.09% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 12 0.19% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6199 # Writes before turning the bus around for reads +system.physmem.totQLat 394563559000 # Total ticks spent queuing +system.physmem.totMemAccLat 681341509000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76474120000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25797.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44664.92 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.23 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.10 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44547.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.66 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.12 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.00 # Data bus utilization in percentage system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.49 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.85 # Average write queue length when enqueuing -system.physmem.readRowHits 14297424 # Number of row buffer hits during reads -system.physmem.writeRowHits 89638 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.61 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.40 # Average write queue length when enqueuing +system.physmem.readRowHits 14297661 # Number of row buffer hits during reads +system.physmem.writeRowHits 89445 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.68 # Row buffer hit rate for writes -system.physmem.avgGap 159377.63 # Average gap between requests +system.physmem.writeRowHitRate 83.72 # Row buffer hit rate for writes +system.physmem.avgGap 159307.76 # Average gap between requests system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2210132306750 # Time in different power states -system.physmem.memoryStateTime::REF 85740200000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2209628504250 # Time in different power states +system.physmem.memoryStateTime::REF 85698860000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 271799415750 # Time in different power states +system.physmem.memoryStateTime::ACT 271106544500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 256 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 256 # Number of bytes read from this memory @@ -274,49 +275,49 @@ system.realview.nvmem.bw_inst_read::cpu.inst 100 system.realview.nvmem.bw_inst_read::total 100 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 100 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 100 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54704015 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16349240 # Transaction distribution -system.membus.trans_dist::ReadResp 16349240 # Transaction distribution +system.membus.throughput 54713053 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16348871 # Transaction distribution +system.membus.trans_dist::ReadResp 16348871 # Transaction distribution system.membus.trans_dist::WriteReq 763365 # Transaction distribution system.membus.trans_dist::WriteResp 763365 # Transaction distribution -system.membus.trans_dist::Writeback 59840 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4671 # Transaction distribution -system.membus.trans_dist::ReadExReq 131634 # Transaction distribution -system.membus.trans_dist::ReadExResp 131634 # Transaction distribution +system.membus.trans_dist::Writeback 59552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4670 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4670 # Transaction distribution +system.membus.trans_dist::ReadExReq 131585 # Transaction distribution +system.membus.trans_dist::ReadExResp 131585 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383068 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 8 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3800 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893150 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280028 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892024 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4278902 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34557660 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34556534 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390502 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7600 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16953376 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19351738 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16908832 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19307194 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140462266 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140462266 # Total data (bytes) +system.membus.tot_pkt_size::total 140417722 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140417722 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1731218500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1781248000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3525000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3519500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17560732500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17618628000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4805026968 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4827706725 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37408380500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37448813750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -324,7 +325,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48098342 # Throughput (bytes/s) +system.iobus.throughput 48121550 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16322172 # Transaction distribution system.iobus.trans_dist::ReadResp 16322172 # Transaction distribution system.iobus.trans_dist::WriteReq 8178 # Transaction distribution @@ -434,18 +435,18 @@ system.iobus.reqLayer25.occupancy 15138816000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374890000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38224979500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38181688250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 12907759 # Number of BP lookups -system.cpu.branchPred.condPredicted 9898849 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1085572 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8888360 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6291175 # Number of BTB hits +system.cpu.branchPred.lookups 12541574 # Number of BP lookups +system.cpu.branchPred.condPredicted 9090690 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1061681 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8536244 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6183587 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.779930 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1515479 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 141893 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.439202 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1558068 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 139509 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -469,25 +470,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 15416418 # DTB read hits -system.cpu.dtb.read_misses 42733 # DTB read misses -system.cpu.dtb.write_hits 11344011 # DTB write hits -system.cpu.dtb.write_misses 3796 # DTB write misses +system.cpu.dtb.read_hits 13629654 # DTB read hits +system.cpu.dtb.read_misses 33608 # DTB read misses +system.cpu.dtb.write_hits 11376786 # DTB write hits +system.cpu.dtb.write_misses 3775 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3452 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1264 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 262 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3449 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1586 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 251 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 531 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15459151 # DTB read accesses -system.cpu.dtb.write_accesses 11347807 # DTB write accesses +system.cpu.dtb.perms_faults 593 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 13663262 # DTB read accesses +system.cpu.dtb.write_accesses 11380561 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26760429 # DTB hits -system.cpu.dtb.misses 46529 # DTB misses -system.cpu.dtb.accesses 26806958 # DTB accesses +system.cpu.dtb.hits 25006440 # DTB hits +system.cpu.dtb.misses 37383 # DTB misses +system.cpu.dtb.accesses 25043823 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -509,8 +510,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 23352687 # ITB inst hits -system.cpu.itb.inst_misses 9286 # ITB inst misses +system.cpu.itb.inst_hits 22903214 # ITB inst hits +system.cpu.itb.inst_misses 9061 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -519,84 +520,84 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2392 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2388 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 4189 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 5760 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 23361973 # ITB inst accesses -system.cpu.itb.hits 23352687 # DTB hits -system.cpu.itb.misses 9286 # DTB misses -system.cpu.itb.accesses 23361973 # DTB accesses -system.cpu.numCycles 576983411 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 22912275 # ITB inst accesses +system.cpu.itb.hits 22903214 # DTB hits +system.cpu.itb.misses 9061 # DTB misses +system.cpu.itb.accesses 22912275 # DTB accesses +system.cpu.numCycles 572663270 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60592948 # Number of instructions committed -system.cpu.committedOps 77887482 # Number of ops (including micro ops) committed -system.cpu.discardedOps 3584241 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 77491 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 4560301069 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 9.522287 # CPI: cycles per instruction -system.cpu.ipc 0.105017 # IPC: instructions per cycle +system.cpu.committedInsts 60593470 # Number of instructions committed +system.cpu.committedOps 72944147 # Number of ops (including micro ops) committed +system.cpu.discardedOps 3225433 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 77492 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 4562060973 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 9.450907 # CPI: cycles per instruction +system.cpu.ipc 0.105810 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 82977 # number of quiesce instructions executed -system.cpu.tickCycles 470832364 # Number of cycles that the object actually ticked -system.cpu.idleCycles 106151047 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 1545254 # number of replacements -system.cpu.icache.tags.tagsinuse 511.467506 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 21802506 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1545766 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14.104661 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 10068892000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.467506 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998960 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998960 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 82978 # number of quiesce instructions executed +system.cpu.tickCycles 466702382 # Number of cycles that the object actually ticked +system.cpu.idleCycles 105960888 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 1529303 # number of replacements +system.cpu.icache.tags.tagsinuse 511.463660 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 21367406 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1529815 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13.967314 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 9992606000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.463660 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998952 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998952 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 190 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 24894039 # Number of tag accesses -system.cpu.icache.tags.data_accesses 24894039 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 21802506 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 21802506 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 21802506 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 21802506 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 21802506 # number of overall hits -system.cpu.icache.overall_hits::total 21802506 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1545767 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1545767 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1545767 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1545767 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1545767 # number of overall misses -system.cpu.icache.overall_misses::total 1545767 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20898816329 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20898816329 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20898816329 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20898816329 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20898816329 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20898816329 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 23348273 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 23348273 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 23348273 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 23348273 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 23348273 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 23348273 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.066205 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.066205 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.066205 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.066205 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.066205 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.066205 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13520.030075 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13520.030075 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13520.030075 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13520.030075 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13520.030075 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13520.030075 # average overall miss latency +system.cpu.icache.tags.tag_accesses 24427037 # Number of tag accesses +system.cpu.icache.tags.data_accesses 24427037 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 21367406 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 21367406 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 21367406 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 21367406 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 21367406 # number of overall hits +system.cpu.icache.overall_hits::total 21367406 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1529816 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1529816 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1529816 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1529816 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1529816 # number of overall misses +system.cpu.icache.overall_misses::total 1529816 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20677210137 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20677210137 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20677210137 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20677210137 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20677210137 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20677210137 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22897222 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22897222 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22897222 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22897222 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22897222 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22897222 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.066812 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.066812 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.066812 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.066812 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.066812 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.066812 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13516.141900 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13516.141900 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13516.141900 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13516.141900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13516.141900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13516.141900 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -605,198 +606,198 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1545767 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1545767 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1545767 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1545767 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1545767 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1545767 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17801487671 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17801487671 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17801487671 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17801487671 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17801487671 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17801487671 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 172412750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 172412750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 172412750 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 172412750 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066205 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066205 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066205 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.066205 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066205 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.066205 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11516.281348 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11516.281348 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11516.281348 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11516.281348 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11516.281348 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11516.281348 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1529816 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1529816 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1529816 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1529816 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1529816 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1529816 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17611902863 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17611902863 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17611902863 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17611902863 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17611902863 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17611902863 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 172141250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 172141250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 172141250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 172141250 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066812 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.066812 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.066812 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11512.432125 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11512.432125 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11512.432125 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11512.432125 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11512.432125 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11512.432125 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 71776562 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3214470 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3214469 # Transaction distribution +system.cpu.toL2Bus.throughput 71285625 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3182019 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3182018 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 602969 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2961 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2961 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247546 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3094256 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5780457 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 29847 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126652 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 9031212 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 98954304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84855034 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 45620 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214364 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 184069322 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 184069322 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 229740 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3400466435 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 600964 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2972 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2972 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247467 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247467 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3062398 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5774016 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 28971 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 100817 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8966202 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 97936512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84584698 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43908 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 166616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 182731734 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 182731734 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 218488 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3381194945 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2325579079 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2301585887 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2551211790 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2547997212 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 18447489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 18000487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 73062749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 59164999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 65493 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51631.050557 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2439202 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 130882 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 18.636650 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2525290748000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36364.368368 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.573566 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 65085 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51558.734735 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2407104 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 130473 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 18.449058 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2524856942500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36497.819876 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.059887 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000576 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 15253.108047 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.554876 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000207 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 15046.854396 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.556913 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000215 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.232744 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.787827 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65379 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 10 # 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number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184020278361 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000336 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000175 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012380 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011988 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.991557 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991557 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.538765 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.538765 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000336 # 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number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 167362107750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167362107750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 16707879855 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16707879855 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 184069987605 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184069987605 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000504 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000182 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012310 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011992 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.991588 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991588 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.538690 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.538690 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000504 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000182 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.072504 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.070793 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000504 # 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average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56962.235871 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56963.195616 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64736.111111 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57718.643869 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57719.711088 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65238.095238 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56962.235871 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56963.195616 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57718.643869 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57719.711088 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -890,86 +891,86 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 637780 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.959208 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 23638258 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 638292 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.033612 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 227414250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959208 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 635561 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.959259 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21828853 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 636073 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.318157 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 227074250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959259 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999920 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999920 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 98967232 # 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number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 462868 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 462868 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 473290 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 473290 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.inst 10831 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 10831 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.inst 936158 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 936158 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 936158 # number of overall misses -system.cpu.dcache.overall_misses::total 936158 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7014286436 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7014286436 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21912161323 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21912161323 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 150765000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 150765000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 28926447759 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28926447759 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 28926447759 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28926447759 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 13864478 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13864478 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 10222552 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222552 # 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