diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt | 1811 |
1 files changed, 906 insertions, 905 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index d6c8679c7..60c7bcf62 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.852840 # Number of seconds simulated -sim_ticks 2852839554500 # Number of ticks simulated -final_tick 2852839554500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.852796 # Number of seconds simulated +sim_ticks 2852795541500 # Number of ticks simulated +final_tick 2852795541500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169032 # Simulator instruction rate (inst/s) -host_op_rate 204382 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4294589830 # Simulator tick rate (ticks/s) -host_mem_usage 620820 # Number of bytes of host memory used -host_seconds 664.29 # Real time elapsed on the host -sim_insts 112285680 # Number of instructions simulated -sim_ops 135768245 # Number of ops (including micro ops) simulated +host_inst_rate 152327 # Simulator instruction rate (inst/s) +host_op_rate 184181 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3876544573 # Simulator tick rate (ticks/s) +host_mem_usage 573860 # Number of bytes of host memory used +host_seconds 735.91 # Real time elapsed on the host +sim_insts 112099513 # Number of instructions simulated +sim_ops 135541235 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 7680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1672128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9190636 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 7488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1672384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9151084 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10871532 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1672128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1672128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7983360 # Number of bytes written to this memory +system.physmem.bytes_read::total 10831980 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1672384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1672384 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7949952 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8000884 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 120 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26127 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144125 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7967476 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 117 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26131 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143507 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170389 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124740 # Number of write requests responded to by this memory +system.physmem.num_reads::total 169771 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124218 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 129121 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2692 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 586128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3221575 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128599 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 586226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3207760 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3810776 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 586128 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 586128 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2798391 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3796970 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 586226 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 586226 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2786723 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2804533 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2798391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 586128 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3227717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2792866 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2786723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 586226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3213903 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6615309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170389 # Number of read requests accepted -system.physmem.writeReqs 165345 # Number of write requests accepted -system.physmem.readBursts 170389 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 165345 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10897024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7872 # Total number of bytes read from write queue -system.physmem.bytesWritten 9054784 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10871532 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10319220 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 123 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23835 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4587 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10917 # Per bank write bursts -system.physmem.perBankRdBursts::1 10861 # Per bank write bursts -system.physmem.perBankRdBursts::2 10721 # Per bank write bursts -system.physmem.perBankRdBursts::3 10725 # Per bank write bursts -system.physmem.perBankRdBursts::4 13339 # Per bank write bursts -system.physmem.perBankRdBursts::5 10813 # Per bank write bursts -system.physmem.perBankRdBursts::6 11142 # Per bank write bursts -system.physmem.perBankRdBursts::7 10985 # Per bank write bursts -system.physmem.perBankRdBursts::8 10153 # Per bank write bursts -system.physmem.perBankRdBursts::9 10280 # Per bank write bursts -system.physmem.perBankRdBursts::10 10274 # Per bank write bursts -system.physmem.perBankRdBursts::11 9203 # Per bank write bursts -system.physmem.perBankRdBursts::12 10314 # Per bank write bursts -system.physmem.perBankRdBursts::13 10760 # Per bank write bursts -system.physmem.perBankRdBursts::14 10035 # Per bank write bursts -system.physmem.perBankRdBursts::15 9744 # Per bank write bursts -system.physmem.perBankWrBursts::0 9017 # Per bank write bursts -system.physmem.perBankWrBursts::1 9225 # Per bank write bursts -system.physmem.perBankWrBursts::2 9344 # Per bank write bursts -system.physmem.perBankWrBursts::3 9210 # Per bank write bursts -system.physmem.perBankWrBursts::4 8591 # Per bank write bursts -system.physmem.perBankWrBursts::5 8923 # Per bank write bursts -system.physmem.perBankWrBursts::6 9235 # Per bank write bursts -system.physmem.perBankWrBursts::7 9154 # Per bank write bursts -system.physmem.perBankWrBursts::8 8919 # Per bank write bursts -system.physmem.perBankWrBursts::9 8830 # Per bank write bursts -system.physmem.perBankWrBursts::10 8770 # Per bank write bursts -system.physmem.perBankWrBursts::11 8263 # Per bank write bursts -system.physmem.perBankWrBursts::12 8824 # Per bank write bursts -system.physmem.perBankWrBursts::13 8884 # Per bank write bursts -system.physmem.perBankWrBursts::14 8238 # Per bank write bursts -system.physmem.perBankWrBursts::15 8054 # Per bank write bursts +system.physmem.bw_total::total 6589836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 169771 # Number of read requests accepted +system.physmem.writeReqs 164823 # Number of write requests accepted +system.physmem.readBursts 169771 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 164823 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10857344 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue +system.physmem.bytesWritten 9026432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10831980 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10285812 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23760 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4596 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10712 # Per bank write bursts +system.physmem.perBankRdBursts::1 10437 # Per bank write bursts +system.physmem.perBankRdBursts::2 10571 # Per bank write bursts +system.physmem.perBankRdBursts::3 10533 # Per bank write bursts +system.physmem.perBankRdBursts::4 13317 # Per bank write bursts +system.physmem.perBankRdBursts::5 10551 # Per bank write bursts +system.physmem.perBankRdBursts::6 11242 # Per bank write bursts +system.physmem.perBankRdBursts::7 11054 # Per bank write bursts +system.physmem.perBankRdBursts::8 10299 # Per bank write bursts +system.physmem.perBankRdBursts::9 10415 # Per bank write bursts +system.physmem.perBankRdBursts::10 10045 # Per bank write bursts +system.physmem.perBankRdBursts::11 9308 # Per bank write bursts +system.physmem.perBankRdBursts::12 10198 # Per bank write bursts +system.physmem.perBankRdBursts::13 10751 # Per bank write bursts +system.physmem.perBankRdBursts::14 10066 # Per bank write bursts +system.physmem.perBankRdBursts::15 10147 # Per bank write bursts +system.physmem.perBankWrBursts::0 8889 # Per bank write bursts +system.physmem.perBankWrBursts::1 8834 # Per bank write bursts +system.physmem.perBankWrBursts::2 9167 # Per bank write bursts +system.physmem.perBankWrBursts::3 9119 # Per bank write bursts +system.physmem.perBankWrBursts::4 8534 # Per bank write bursts +system.physmem.perBankWrBursts::5 8844 # Per bank write bursts +system.physmem.perBankWrBursts::6 9286 # Per bank write bursts +system.physmem.perBankWrBursts::7 9148 # Per bank write bursts +system.physmem.perBankWrBursts::8 9054 # Per bank write bursts +system.physmem.perBankWrBursts::9 9024 # Per bank write bursts +system.physmem.perBankWrBursts::10 8594 # Per bank write bursts +system.physmem.perBankWrBursts::11 8355 # Per bank write bursts +system.physmem.perBankWrBursts::12 8781 # Per bank write bursts +system.physmem.perBankWrBursts::13 8812 # Per bank write bursts +system.physmem.perBankWrBursts::14 8169 # Per bank write bursts +system.physmem.perBankWrBursts::15 8428 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 37 # Number of times write queue was full causing retry -system.physmem.totGap 2852839149500 # Total gap between requests +system.physmem.numWrRetry 51 # Number of times write queue was full causing retry +system.physmem.totGap 2852795136500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169832 # Read request sizes (log2) +system.physmem.readPktSize::6 169214 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 160964 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6336 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 160442 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 162758 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -159,160 +159,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 43 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61975 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 321.932134 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.780856 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 337.844354 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22404 36.15% 36.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14558 23.49% 59.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6628 10.69% 70.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3590 5.79% 76.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2633 4.25% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1568 2.53% 82.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1136 1.83% 84.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1187 1.92% 86.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8271 13.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61975 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5903 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.841945 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 583.033382 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5902 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 149 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61582 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 322.881881 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.150015 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.764187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22212 36.07% 36.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14518 23.58% 59.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6522 10.59% 70.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3539 5.75% 75.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2583 4.19% 80.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1569 2.55% 82.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1183 1.92% 84.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1177 1.91% 86.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8279 13.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61582 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5853 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.981890 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 585.529205 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5852 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5903 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5903 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.967644 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.368451 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 42.492651 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 5572 94.39% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 86 1.46% 95.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 22 0.37% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 13 0.22% 96.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 26 0.44% 96.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 23 0.39% 97.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 23 0.39% 97.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 20 0.34% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 7 0.12% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 2 0.03% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 23 0.39% 98.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 13 0.22% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 11 0.19% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 2 0.03% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.03% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 3 0.05% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 2 0.03% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 6 0.10% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 7 0.12% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 5 0.08% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 2 0.03% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 15 0.25% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 4 0.07% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.02% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 3 0.05% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5903 # Writes before turning the bus around for reads -system.physmem.totQLat 1723482630 # Total ticks spent queuing -system.physmem.totMemAccLat 4915970130 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 851330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10122.29 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5853 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5853 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.096703 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.379226 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 43.965113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5522 94.34% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 97 1.66% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 18 0.31% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 12 0.21% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 21 0.36% 96.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 25 0.43% 97.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 23 0.39% 97.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 16 0.27% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 12 0.21% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 2 0.03% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 16 0.27% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 11 0.19% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 11 0.19% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 5 0.09% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.02% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 1 0.02% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 9 0.15% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 6 0.10% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 2 0.03% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 7 0.12% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 16 0.27% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 1 0.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 4 0.07% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 3 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 2 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5853 # Writes before turning the bus around for reads +system.physmem.totQLat 1681739444 # Total ticks spent queuing +system.physmem.totMemAccLat 4862601944 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 848230000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9913.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28872.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.62 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28663.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.62 # Average write queue length when enqueuing -system.physmem.readRowHits 140451 # Number of row buffer hits during reads -system.physmem.writeRowHits 109320 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.25 # Row buffer hit rate for writes -system.physmem.avgGap 8497319.75 # Average gap between requests -system.physmem.pageHitRate 80.11 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 245019600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 133691250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 698123400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 471089520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186333332640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83679210810 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1638298500750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1909858967970 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.459893 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2725317218918 # Time in different power states -system.physmem_0.memoryStateTime::REF 95262440000 # Time in different power states +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.33 # Average write queue length when enqueuing +system.physmem.readRowHits 140075 # Number of row buffer hits during reads +system.physmem.writeRowHits 109026 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.29 # Row buffer hit rate for writes +system.physmem.avgGap 8526139.55 # Average gap between requests +system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 241398360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 131715375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 689652600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 465400080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186330281280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83595060855 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1638344286000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1909797794550 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.449413 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2725393996990 # Time in different power states +system.physmem_0.memoryStateTime::REF 95260880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32255883582 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32133948010 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 223511400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 121955625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 629943600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 445707360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186333332640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82264054140 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1639539866250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1909558371015 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.354525 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2727396126418 # Time in different power states -system.physmem_1.memoryStateTime::REF 95262440000 # Time in different power states +system.physmem_1.actEnergy 224161560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122310375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 633578400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 448526160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186330281280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82127793645 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1639631362500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1909518013920 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.351340 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2727553667240 # Time in different power states +system.physmem_1.memoryStateTime::REF 95260880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30180892082 # Time in different power states +system.physmem_1.memoryStateTime::ACT 29980898760 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -332,15 +334,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31043514 # Number of BP lookups -system.cpu.branchPred.condPredicted 16869099 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2536489 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18574786 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13386311 # Number of BTB hits +system.cpu.branchPred.lookups 31028841 # Number of BP lookups +system.cpu.branchPred.condPredicted 16848703 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2523288 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18558243 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13348746 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.067108 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7804422 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1529182 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.928932 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7829101 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1515846 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -371,59 +373,58 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 65823 # Table walker walks requested -system.cpu.dtb.walker.walksShort 65823 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43117 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22706 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 65823 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 65823 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 65823 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7829 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 10980.553072 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 8717.816397 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7451.711579 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 6121 78.18% 78.18% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 1701 21.73% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 66007 # Table walker walks requested +system.cpu.dtb.walker.walksShort 66007 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43361 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22646 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 66007 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 66007 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 66007 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7799 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11136.363636 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8861.352080 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7418.451261 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 6073 77.87% 77.87% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 1719 22.04% 99.91% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.97% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7829 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7799 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 262515000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 262515000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 262515000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6444 82.31% 82.31% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1385 17.69% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7829 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65823 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 6423 82.36% 82.36% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1376 17.64% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7799 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66007 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65823 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7829 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66007 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7799 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7829 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 73652 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7799 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 73806 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24809902 # DTB read hits -system.cpu.dtb.read_misses 58990 # DTB read misses -system.cpu.dtb.write_hits 19469042 # DTB write hits -system.cpu.dtb.write_misses 6833 # DTB write misses +system.cpu.dtb.read_hits 24765986 # DTB read hits +system.cpu.dtb.read_misses 59321 # DTB read misses +system.cpu.dtb.write_hits 19441821 # DTB write hits +system.cpu.dtb.write_misses 6686 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1238 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1767 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4350 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1269 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1784 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 748 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24868892 # DTB read accesses -system.cpu.dtb.write_accesses 19475875 # DTB write accesses +system.cpu.dtb.perms_faults 729 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24825307 # DTB read accesses +system.cpu.dtb.write_accesses 19448507 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44278944 # DTB hits -system.cpu.dtb.misses 65823 # DTB misses -system.cpu.dtb.accesses 44344767 # DTB accesses +system.cpu.dtb.hits 44207807 # DTB hits +system.cpu.dtb.misses 66007 # DTB misses +system.cpu.dtb.accesses 44273814 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -453,37 +454,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 5435 # Table walker walks requested -system.cpu.itb.walker.walksShort 5435 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 321 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5114 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5435 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5435 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5435 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3183 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 11172.007540 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 8898.591631 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7073.724538 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1308 41.09% 41.09% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1159 36.41% 77.51% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 715 22.46% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 5444 # Table walker walks requested +system.cpu.itb.walker.walksShort 5444 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 317 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5127 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5444 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5444 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5444 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3189 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 11300.094073 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 9048.158428 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7023.995661 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1265 39.67% 39.67% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1207 37.85% 77.52% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 716 22.45% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3183 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3189 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 262109500 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 262109500 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 262109500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2873 90.26% 90.26% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 310 9.74% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3183 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 2879 90.28% 90.28% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.72% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3189 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5435 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5435 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5444 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5444 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3183 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3183 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 8618 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57700454 # ITB inst hits -system.cpu.itb.inst_misses 5435 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3189 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3189 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 8633 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57608448 # ITB inst hits +system.cpu.itb.inst_misses 5444 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -492,274 +493,274 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2972 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2978 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8445 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8408 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57705889 # ITB inst accesses -system.cpu.itb.hits 57700454 # DTB hits -system.cpu.itb.misses 5435 # DTB misses -system.cpu.itb.accesses 57705889 # DTB accesses -system.cpu.numCycles 315730000 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57613892 # ITB inst accesses +system.cpu.itb.hits 57608448 # DTB hits +system.cpu.itb.misses 5444 # DTB misses +system.cpu.itb.accesses 57613892 # DTB accesses +system.cpu.numCycles 315454477 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112285680 # Number of instructions committed -system.cpu.committedOps 135768245 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7761547 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 112099513 # Number of instructions committed +system.cpu.committedOps 135541235 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7725935 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5390009685 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.811846 # CPI: cycles per instruction -system.cpu.ipc 0.355638 # IPC: instructions per cycle +system.cpu.quiesceCycles 5390197145 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.814058 # CPI: cycles per instruction +system.cpu.ipc 0.355359 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed -system.cpu.tickCycles 227805023 # Number of cycles that the object actually ticked -system.cpu.idleCycles 87924977 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 842413 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.947858 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42688411 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 842925 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.643190 # Average number of references to valid blocks. +system.cpu.tickCycles 227606231 # Number of cycles that the object actually ticked +system.cpu.idleCycles 87848246 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 842088 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.947851 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42623753 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 842600 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.585987 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 313221250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.947858 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.947851 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999898 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999898 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 176513094 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 176513094 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23118388 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23118388 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18306742 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18306742 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 356409 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 356409 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443709 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443709 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460231 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460231 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41425130 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41425130 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41781539 # number of overall hits -system.cpu.dcache.overall_hits::total 41781539 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 491811 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 491811 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 547829 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 547829 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 170067 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 170067 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22347 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22347 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 176253823 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 176253823 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23074723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23074723 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18285747 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18285747 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 356646 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 356646 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443503 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443503 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460198 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460198 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41360470 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41360470 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41717116 # number of overall hits +system.cpu.dcache.overall_hits::total 41717116 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 491782 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 491782 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 547820 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 547820 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 169860 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 169860 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22518 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22518 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 1039640 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1039640 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1209707 # number of overall misses -system.cpu.dcache.overall_misses::total 1209707 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7276171447 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7276171447 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23463335520 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23463335520 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 282730000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 282730000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30739506967 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30739506967 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30739506967 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30739506967 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23610199 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23610199 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18854571 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18854571 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 526476 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 526476 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466056 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466056 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460233 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460233 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42464770 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42464770 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42991246 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42991246 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020830 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020830 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029056 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029056 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.323029 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.323029 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047949 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047949 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 1039602 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1039602 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1209462 # number of overall misses +system.cpu.dcache.overall_misses::total 1209462 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7264308005 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7264308005 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23337097788 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23337097788 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 285724000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 285724000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30601405793 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30601405793 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5703692140 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12347213418 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12347213418 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562689830 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562689830 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105383000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105383000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18050905558 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18050905558 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19613595388 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19613595388 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5837245750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5837245750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4509635000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4509635000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346880750 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346880750 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017664 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017664 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015849 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015849 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231099 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231099 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017665 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017665 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5688327646 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5688327646 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12278776156 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12278776156 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1560607790 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1560607790 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 106146500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 106146500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17967103802 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17967103802 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19527711592 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19527711592 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5837082750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5837082750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510053000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510053000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10347135750 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10347135750 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017687 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017687 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015864 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015864 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231042 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231042 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017647 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017647 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016858 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016858 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019482 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019482 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13676.016621 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13676.016621 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41319.349912 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41319.349912 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12843.885245 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12843.885245 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12800.072877 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12800.072877 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25214.917484 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25214.917484 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23417.820295 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23417.820295 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187523.957530 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187523.957530 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163493.274843 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163493.274843 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176234.108600 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176234.108600 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016877 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016877 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019504 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019504 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13647.193456 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13647.193456 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41096.516676 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41096.516676 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12829.197994 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12829.197994 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12906.918774 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12906.918774 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81250 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81250 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25108.027762 # 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Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.879908 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 15532248250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.399912 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998828 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998828 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 196 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 194 # 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average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13559.570342 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13559.570342 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13559.570342 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13559.570342 # average overall miss latency +system.cpu.icache.tags.tag_accesses 60497051 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60497051 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 54702268 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 54702268 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 54702268 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 54702268 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 54702268 # number of overall hits +system.cpu.icache.overall_hits::total 54702268 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34933961847 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 34933961847 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34935956838 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 34935956838 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34935956838 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 34935956838 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34935956838 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 34935956838 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 247386750 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 247386750 # 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average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12056.266959 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12056.266959 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12056.266959 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12056.266959 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050302 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050302 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050302 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050302 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050302 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.050302 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12057.725305 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12057.725305 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12057.725305 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12057.725305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12057.725305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12057.725305 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77990.778689 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77990.778689 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77990.778689 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77990.778689 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 12239.354143 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5328.608352 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.723767 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000974 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186540 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.080792 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.992704 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65201 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 58 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186758 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.081308 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.992807 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 39 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65212 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 39 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2302 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6944 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55834 # 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average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442409 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442409 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001660 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000222 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044072 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001660 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000222 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044072 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76959.401709 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67689.004746 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71214.411931 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69055.756834 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17774.445922 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17774.445922 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65003.775370 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65003.775370 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76959.401709 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67689.004746 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65608.118329 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65900.319529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76959.401709 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67689.004746 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65608.118329 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65900.319529 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60444.435687 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173507.677975 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163051.800292 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150488.851829 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150488.851829 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173502.602159 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163047.193878 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150503.734184 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150503.734184 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60444.435687 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162693.209109 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157452.139521 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162697.509836 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157456.219802 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3578143 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3578049 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3577827 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3577732 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 697807 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2829 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 697883 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2834 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2831 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296000 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296000 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5801472 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506940 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14959 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158425 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8481796 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185646272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98800797 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 279584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 284744293 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 61425 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4638617 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.029225 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.168438 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2836 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295950 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295950 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5801098 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506371 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15072 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159127 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8481668 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185634176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98784669 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18004 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 281896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 284718745 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 60910 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4638337 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.029260 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.168533 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4503052 97.08% 97.08% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 135565 2.92% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4502621 97.07% 97.07% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 135716 2.93% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4638617 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3012663750 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4638337 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3012597000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 211500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 210000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4356641403 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4356351412 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1341917112 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1341303908 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10549250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10571000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 88533000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 88656750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution @@ -1230,23 +1231,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198836241 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198957934 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36810509 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36810010 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.031382 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.031201 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270536492000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.031382 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064461 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064461 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270527174000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.031201 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064450 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064450 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1260,14 +1261,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29235877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29235877 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6642330855 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6642330855 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29235877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29235877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29235877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29235877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29240377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29240377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6662157547 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6662157547 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29240377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29240377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29240377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29240377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1284,19 +1285,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124939.645299 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124939.645299 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183368.232525 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183368.232525 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124939.645299 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124939.645299 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124939.645299 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124939.645299 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22431 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124958.876068 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124958.876068 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183915.568325 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183915.568325 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124958.876068 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124958.876068 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124958.876068 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124958.876068 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 23447 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3441 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3545 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.518745 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.614104 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1310,14 +1311,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16926877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16926877 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4758664873 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4758664873 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16926877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16926877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16926877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16926877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16932377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16932377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4778489567 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4778489567 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16932377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16932377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16932377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16932377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1326,66 +1327,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72337.081197 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72337.081197 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131367.736114 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131367.736114 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72337.081197 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72337.081197 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72337.081197 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72337.081197 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72360.585470 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72360.585470 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131915.016757 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131915.016757 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72360.585470 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72360.585470 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72360.585470 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72360.585470 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 71805 # Transaction distribution -system.membus.trans_dist::ReadResp 71805 # Transaction distribution +system.membus.trans_dist::ReadReq 71735 # Transaction distribution +system.membus.trans_dist::ReadResp 71735 # Transaction distribution system.membus.trans_dist::WriteReq 27583 # Transaction distribution system.membus.trans_dist::WriteResp 27583 # Transaction distribution -system.membus.trans_dist::Writeback 124740 # Transaction distribution +system.membus.trans_dist::Writeback 124218 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4587 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4589 # Transaction distribution -system.membus.trans_dist::ReadExReq 129666 # Transaction distribution -system.membus.trans_dist::ReadExResp 129666 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4598 # Transaction distribution +system.membus.trans_dist::ReadExReq 129118 # Transaction distribution +system.membus.trans_dist::ReadExResp 129118 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447521 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 555081 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445781 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553341 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 663968 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 662228 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16555296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16719005 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16482336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16646045 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21354461 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21281501 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 506 # Total snoops (count) -system.membus.snoop_fanout::samples 394644 # Request fanout histogram +system.membus.snoop_fanout::samples 393527 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 394644 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 393527 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 394644 # Request fanout histogram -system.membus.reqLayer0.occupancy 90290000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 393527 # Request fanout histogram +system.membus.reqLayer0.occupancy 90546500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1707500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1706500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1026254667 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1023221651 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 999643493 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 996325444 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37473491 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 37473990 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |