diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt | 1750 |
1 files changed, 874 insertions, 876 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 456fdbc09..11bd5dafc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.858559 # Number of seconds simulated -sim_ticks 2858558607500 # Number of ticks simulated -final_tick 2858558607500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.858536 # Number of seconds simulated +sim_ticks 2858536032500 # Number of ticks simulated +final_tick 2858536032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164210 # Simulator instruction rate (inst/s) -host_op_rate 198546 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4188709682 # Simulator tick rate (ticks/s) -host_mem_usage 583452 # Number of bytes of host memory used -host_seconds 682.44 # Real time elapsed on the host -sim_insts 112064376 # Number of instructions simulated -sim_ops 135496266 # Number of ops (including micro ops) simulated +host_inst_rate 177299 # Simulator instruction rate (inst/s) +host_op_rate 214372 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4522420422 # Simulator tick rate (ticks/s) +host_mem_usage 585260 # Number of bytes of host memory used +host_seconds 632.08 # Real time elapsed on the host +sim_insts 112067614 # Number of instructions simulated +sim_ops 135500271 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 8064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1707776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9151404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 8000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1708096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9152172 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10868268 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1707776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1707776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7938560 # Number of bytes written to this memory +system.physmem.bytes_read::total 10869356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1708096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1708096 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7939328 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7956084 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 126 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26684 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143512 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7956852 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 125 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26689 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143524 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170338 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124040 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170355 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124052 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128421 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 597426 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3201405 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128433 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 597542 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3201699 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3802010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 597426 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 597426 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2777120 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3802420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 597542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 597542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2777411 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6130 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2783250 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2777120 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2821 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 597426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3207535 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2783541 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2777411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 597542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3207829 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6585260 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170338 # Number of read requests accepted -system.physmem.writeReqs 128421 # Number of write requests accepted -system.physmem.readBursts 170338 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 128421 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10893184 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8448 # Total number of bytes read from write queue -system.physmem.bytesWritten 7968384 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10868268 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7956084 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 132 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6585961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170355 # Number of read requests accepted +system.physmem.writeReqs 128433 # Number of write requests accepted +system.physmem.readBursts 170355 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 128433 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10894592 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8128 # Total number of bytes read from write queue +system.physmem.bytesWritten 7969344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10869356 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7956852 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 127 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 49420 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10768 # Per bank write bursts -system.physmem.perBankRdBursts::1 10789 # Per bank write bursts -system.physmem.perBankRdBursts::2 10902 # Per bank write bursts -system.physmem.perBankRdBursts::3 10725 # Per bank write bursts -system.physmem.perBankRdBursts::4 14061 # Per bank write bursts -system.physmem.perBankRdBursts::5 10215 # Per bank write bursts -system.physmem.perBankRdBursts::6 11008 # Per bank write bursts -system.physmem.perBankRdBursts::7 10953 # Per bank write bursts -system.physmem.perBankRdBursts::8 9930 # Per bank write bursts -system.physmem.perBankRdBursts::9 10231 # Per bank write bursts -system.physmem.perBankRdBursts::10 9936 # Per bank write bursts -system.physmem.perBankRdBursts::11 9160 # Per bank write bursts -system.physmem.perBankRdBursts::12 10275 # Per bank write bursts -system.physmem.perBankRdBursts::13 11196 # Per bank write bursts -system.physmem.perBankRdBursts::14 10249 # Per bank write bursts -system.physmem.perBankRdBursts::15 9808 # Per bank write bursts -system.physmem.perBankWrBursts::0 8070 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10771 # Per bank write bursts +system.physmem.perBankRdBursts::1 10790 # Per bank write bursts +system.physmem.perBankRdBursts::2 10898 # Per bank write bursts +system.physmem.perBankRdBursts::3 10736 # Per bank write bursts +system.physmem.perBankRdBursts::4 14068 # Per bank write bursts +system.physmem.perBankRdBursts::5 10207 # Per bank write bursts +system.physmem.perBankRdBursts::6 11005 # Per bank write bursts +system.physmem.perBankRdBursts::7 10952 # Per bank write bursts +system.physmem.perBankRdBursts::8 9928 # Per bank write bursts +system.physmem.perBankRdBursts::9 10232 # Per bank write bursts +system.physmem.perBankRdBursts::10 9939 # Per bank write bursts +system.physmem.perBankRdBursts::11 9163 # Per bank write bursts +system.physmem.perBankRdBursts::12 10281 # Per bank write bursts +system.physmem.perBankRdBursts::13 11195 # Per bank write bursts +system.physmem.perBankRdBursts::14 10251 # Per bank write bursts +system.physmem.perBankRdBursts::15 9812 # Per bank write bursts +system.physmem.perBankWrBursts::0 8074 # Per bank write bursts system.physmem.perBankWrBursts::1 8145 # Per bank write bursts -system.physmem.perBankWrBursts::2 8537 # Per bank write bursts -system.physmem.perBankWrBursts::3 8263 # Per bank write bursts -system.physmem.perBankWrBursts::4 7645 # Per bank write bursts -system.physmem.perBankWrBursts::5 7425 # Per bank write bursts -system.physmem.perBankWrBursts::6 7936 # Per bank write bursts -system.physmem.perBankWrBursts::7 8025 # Per bank write bursts -system.physmem.perBankWrBursts::8 7562 # Per bank write bursts -system.physmem.perBankWrBursts::9 7724 # Per bank write bursts -system.physmem.perBankWrBursts::10 7502 # Per bank write bursts -system.physmem.perBankWrBursts::11 7049 # Per bank write bursts -system.physmem.perBankWrBursts::12 7677 # Per bank write bursts -system.physmem.perBankWrBursts::13 8301 # Per bank write bursts -system.physmem.perBankWrBursts::14 7534 # Per bank write bursts -system.physmem.perBankWrBursts::15 7111 # Per bank write bursts +system.physmem.perBankWrBursts::2 8532 # Per bank write bursts +system.physmem.perBankWrBursts::3 8274 # Per bank write bursts +system.physmem.perBankWrBursts::4 7651 # Per bank write bursts +system.physmem.perBankWrBursts::5 7419 # Per bank write bursts +system.physmem.perBankWrBursts::6 7942 # Per bank write bursts +system.physmem.perBankWrBursts::7 8023 # Per bank write bursts +system.physmem.perBankWrBursts::8 7561 # Per bank write bursts +system.physmem.perBankWrBursts::9 7722 # Per bank write bursts +system.physmem.perBankWrBursts::10 7504 # Per bank write bursts +system.physmem.perBankWrBursts::11 7050 # Per bank write bursts +system.physmem.perBankWrBursts::12 7678 # Per bank write bursts +system.physmem.perBankWrBursts::13 8296 # Per bank write bursts +system.physmem.perBankWrBursts::14 7536 # Per bank write bursts +system.physmem.perBankWrBursts::15 7114 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 7 # Number of times write queue was full causing retry -system.physmem.totGap 2858558162000 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 2858535588000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169781 # Read request sizes (log2) +system.physmem.readPktSize::6 169798 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 124040 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6437 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 292 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124052 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163475 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 291 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,113 +159,112 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61425 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 307.065592 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 182.884404 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.926844 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22406 36.48% 36.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14897 24.25% 60.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6725 10.95% 71.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3636 5.92% 77.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2599 4.23% 81.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1993 3.24% 85.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1038 1.69% 86.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1103 1.80% 88.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7028 11.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61425 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6226 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.335689 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 568.600385 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6225 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61427 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 307.093102 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.837118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.066728 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22431 36.52% 36.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14913 24.28% 60.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6673 10.86% 71.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3644 5.93% 77.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2598 4.23% 81.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2007 3.27% 85.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1018 1.66% 86.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1090 1.77% 88.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7053 11.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61427 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6076 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.016458 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 575.560734 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6075 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6226 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6226 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.997751 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.449468 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.121367 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5404 86.80% 86.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 111 1.78% 88.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 39 0.63% 89.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 181 2.91% 92.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 25 0.40% 92.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 156 2.51% 95.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 42 0.67% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.13% 95.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 19 0.31% 96.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 12 0.19% 96.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.10% 96.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 165 2.65% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.05% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 22 0.35% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 9 0.14% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6226 # Writes before turning the bus around for reads -system.physmem.totQLat 1816793750 # Total ticks spent queuing -system.physmem.totMemAccLat 5008156250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 851030000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10674.09 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6076 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6075 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.495967 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.543257 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.157568 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5370 88.40% 88.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 94 1.55% 89.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 44 0.72% 90.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 49 0.81% 91.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 46 0.76% 92.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 25 0.41% 92.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 47 0.77% 93.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.16% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 146 2.40% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.05% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.13% 96.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 10 0.16% 96.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 76 1.25% 97.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.07% 97.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.08% 97.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 24 0.40% 98.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 88 1.45% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.13% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 8 0.13% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6075 # Writes before turning the bus around for reads +system.physmem.totQLat 1806632250 # Total ticks spent queuing +system.physmem.totMemAccLat 4998407250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 851140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10613.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29424.09 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29363.01 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.79 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s @@ -275,40 +274,40 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.34 # Average write queue length when enqueuing -system.physmem.readRowHits 139582 # Number of row buffer hits during reads -system.physmem.writeRowHits 93704 # Number of row buffer hits during writes +system.physmem.avgWrQLen 21.23 # Average write queue length when enqueuing +system.physmem.readRowHits 139599 # Number of row buffer hits during reads +system.physmem.writeRowHits 93721 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.01 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.24 # Row buffer hit rate for writes -system.physmem.avgGap 9568107.28 # Average gap between requests +system.physmem.writeRowHitRate 75.25 # Row buffer hit rate for writes +system.physmem.avgGap 9567103.06 # Average gap between requests system.physmem.pageHitRate 79.15 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 242131680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132115500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 697483800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 415018080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186707124240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 87047496990 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1638777600000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1914018970290 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.574900 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2726091168500 # Time in different power states -system.physmem_0.memoryStateTime::REF 95453540000 # Time in different power states +system.physmem_0.actEnergy 242282880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132198000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 697530600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 415063440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186705598560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 87013655235 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1638793270500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1913999599215 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.573595 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2726118833250 # Time in different power states +system.physmem_0.memoryStateTime::REF 95452760000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 37013727750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 36964415750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 222241320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 121262625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 630115200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 222075000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121171875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 630240000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 391780800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186707124240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85156608060 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1640436274500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1913665406745 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.451214 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2728865158250 # Time in different power states -system.physmem_1.memoryStateTime::REF 95453540000 # Time in different power states +system.physmem_1.refreshEnergy 186705598560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85155956550 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1640422830750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1913649653535 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.451174 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2728842952750 # Time in different power states +system.physmem_1.memoryStateTime::REF 95452760000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 34239762750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 34240173750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory @@ -328,15 +327,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31021791 # Number of BP lookups -system.cpu.branchPred.condPredicted 16837881 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2510623 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18481524 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13330573 # Number of BTB hits +system.cpu.branchPred.lookups 31018850 # Number of BP lookups +system.cpu.branchPred.condPredicted 16837096 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2510697 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18467994 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13332341 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.129187 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7835102 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1517797 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.191603 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7836957 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1518082 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -367,55 +366,55 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 66394 # Table walker walks requested -system.cpu.dtb.walker.walksShort 66394 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43409 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22985 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 66394 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 66394 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 66394 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7806 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12863.502434 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10677.385301 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8586.171053 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 7798 99.90% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 66340 # Table walker walks requested +system.cpu.dtb.walker.walksShort 66340 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43350 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22990 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 66340 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 66340 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 66340 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7812 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 12842.037890 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10664.293591 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8573.106392 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7804 99.90% 99.90% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::131072-163839 7 0.09% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7806 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7812 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 517922000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 517922000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 517922000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6430 82.37% 82.37% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1376 17.63% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7806 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66394 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 6422 82.21% 82.21% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1390 17.79% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7812 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66340 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66394 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7806 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66340 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7812 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7806 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 74200 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7812 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 74152 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24767538 # DTB read hits -system.cpu.dtb.read_misses 59423 # DTB read misses -system.cpu.dtb.write_hits 19447940 # DTB write hits -system.cpu.dtb.write_misses 6971 # DTB write misses +system.cpu.dtb.read_hits 24767530 # DTB read hits +system.cpu.dtb.read_misses 59359 # DTB read misses +system.cpu.dtb.write_hits 19448397 # DTB write hits +system.cpu.dtb.write_misses 6981 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4352 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1291 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1803 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4358 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1306 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1806 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 767 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24826961 # DTB read accesses -system.cpu.dtb.write_accesses 19454911 # DTB write accesses +system.cpu.dtb.perms_faults 756 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24826889 # DTB read accesses +system.cpu.dtb.write_accesses 19455378 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44215478 # DTB hits -system.cpu.dtb.misses 66394 # DTB misses -system.cpu.dtb.accesses 44281872 # DTB accesses +system.cpu.dtb.hits 44215927 # DTB hits +system.cpu.dtb.misses 66340 # DTB misses +system.cpu.dtb.accesses 44282267 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -445,19 +444,19 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 5448 # Table walker walks requested -system.cpu.itb.walker.walksShort 5448 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walks 5454 # Table walker walks requested +system.cpu.itb.walker.walksShort 5454 # Table walker walks initiated with short descriptors system.cpu.itb.walker.walksShortTerminationLevel::Level1 321 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5127 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5448 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5448 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5448 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5133 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5454 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5454 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5454 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkCompletionTime::samples 3187 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 13028.710386 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10952.783272 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7366.378700 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 2453 76.97% 76.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 733 23.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 13010.982115 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10938.412651 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7360.815983 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2457 77.09% 77.09% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 729 22.87% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::total 3187 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 517267500 # Table walker pending requests distribution @@ -467,14 +466,14 @@ system.cpu.itb.walker.walkPageSizes::4K 2877 90.27% 90.27% # Ta system.cpu.itb.walker.walkPageSizes::1M 310 9.73% 100.00% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::total 3187 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5448 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5448 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5454 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5454 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3187 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3187 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 8635 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57565583 # ITB inst hits -system.cpu.itb.inst_misses 5448 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin::total 8641 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57568551 # ITB inst hits +system.cpu.itb.inst_misses 5454 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -487,123 +486,123 @@ system.cpu.itb.flush_entries 2975 # Nu system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8500 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8464 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57571031 # ITB inst accesses -system.cpu.itb.hits 57565583 # DTB hits -system.cpu.itb.misses 5448 # DTB misses -system.cpu.itb.accesses 57571031 # DTB accesses -system.cpu.numCycles 333209630 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57574005 # ITB inst accesses +system.cpu.itb.hits 57568551 # DTB hits +system.cpu.itb.misses 5454 # DTB misses +system.cpu.itb.accesses 57574005 # DTB accesses +system.cpu.numCycles 333181944 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112064376 # Number of instructions committed -system.cpu.committedOps 135496266 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7785576 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 112067614 # Number of instructions committed +system.cpu.committedOps 135500271 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7782146 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5383968359 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.973377 # CPI: cycles per instruction -system.cpu.ipc 0.336318 # IPC: instructions per cycle +system.cpu.quiesceCycles 5383950822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.973044 # CPI: cycles per instruction +system.cpu.ipc 0.336356 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed -system.cpu.tickCycles 228553577 # Number of cycles that the object actually ticked -system.cpu.idleCycles 104656053 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 842821 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.899795 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42614913 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 843333 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.531537 # Average number of references to valid blocks. +system.cpu.tickCycles 228532556 # Number of cycles that the object actually ticked +system.cpu.idleCycles 104649388 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 842951 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.899807 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42615127 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 843463 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.524003 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 594757500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.899795 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.899807 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 176231729 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 176231729 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23070027 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23070027 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18281270 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18281270 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 356578 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 356578 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443846 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443846 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460293 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460293 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41351297 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41351297 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41707875 # number of overall hits -system.cpu.dcache.overall_hits::total 41707875 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 494345 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 494345 # number of ReadReq misses +system.cpu.dcache.tags.tag_accesses 176233418 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 176233418 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23069734 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23069734 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18281775 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18281775 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 356571 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 356571 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443857 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443857 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460299 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460299 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41351509 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41351509 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41708080 # number of overall hits +system.cpu.dcache.overall_hits::total 41708080 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 494516 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 494516 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 548690 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 548690 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 169778 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 169778 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22262 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22262 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22259 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22259 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 1043035 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1043035 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1212813 # number of overall misses -system.cpu.dcache.overall_misses::total 1212813 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8029817000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8029817000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 35659469481 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 35659469481 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 293513500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 293513500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1043206 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1043206 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1212984 # number of overall misses +system.cpu.dcache.overall_misses::total 1212984 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8031253000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8031253000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 35635370481 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 35635370481 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 293366000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 293366000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 43689286481 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 43689286481 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 43689286481 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 43689286481 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23564372 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23564372 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18829960 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18829960 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 526356 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 526356 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466108 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466108 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460295 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460295 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42394332 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42394332 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42920688 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42920688 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020978 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020978 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029139 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029139 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322554 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.322554 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047761 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047761 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 43666623481 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 43666623481 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 43666623481 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 43666623481 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23564250 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23564250 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18830465 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18830465 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 526349 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 526349 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466116 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466116 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460301 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460301 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42394715 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42394715 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42921064 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42921064 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020986 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020986 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029138 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029138 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322558 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.322558 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047754 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047754 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024603 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024603 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.028257 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.028257 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16243.346246 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16243.346246 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64990.193882 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64990.193882 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13184.507232 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13184.507232 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.024607 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024607 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.028261 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.028261 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16240.633266 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16240.633266 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64946.272906 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64946.272906 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13179.657667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13179.657667 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83500 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41886.692662 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41886.692662 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36023.102062 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36023.102062 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41858.102312 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41858.102312 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35999.340042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35999.340042 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 280 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked @@ -612,145 +611,145 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.333333 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 699997 # number of writebacks -system.cpu.dcache.writebacks::total 699997 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76799 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 76799 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249722 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 249722 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 13994 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 13994 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 326521 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 326521 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 326521 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 326521 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417546 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 417546 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298968 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298968 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121374 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 121374 # number of SoftPFReq MSHR misses +system.cpu.dcache.writebacks::writebacks 700113 # number of writebacks +system.cpu.dcache.writebacks::total 700113 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76813 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 76813 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249717 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 249717 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 13991 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 13991 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 326530 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 326530 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 326530 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 326530 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417703 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 417703 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298973 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298973 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121335 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 121335 # number of SoftPFReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8268 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 8268 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 716514 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 716514 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 837888 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 837888 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 716676 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 716676 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 838011 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 838011 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31130 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6518403500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6518403500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19210408500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19210408500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1713722500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1713722500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 116087000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 116087000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6520814500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6520814500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19192223000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19192223000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1711136500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1711136500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115838000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115838000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25728812000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25728812000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27442534500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27442534500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6277728500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6277728500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5083599000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5083599000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11361327500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11361327500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017719 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017719 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25713037500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25713037500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27424174000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27424174000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6277780500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6277780500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5083615500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5083615500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11361396000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11361396000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017726 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017726 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015877 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015877 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230593 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230593 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230522 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230522 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017738 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017738 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016901 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016901 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019522 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019522 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15611.222476 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15611.222476 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64255.734727 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64255.734727 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14119.354227 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14119.354227 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14040.517658 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14040.517658 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016905 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016905 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019524 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019524 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15611.126805 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15611.126805 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64193.833557 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64193.833557 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14102.579635 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14102.579635 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14010.401548 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14010.401548 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82500 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35908.317214 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35908.317214 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32752.031894 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32752.031894 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201661.692901 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201661.692901 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184295.207367 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184295.207367 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193502.869844 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193502.869844 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35878.189726 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35878.189726 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32725.315061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32725.315061 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201663.363315 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201663.363315 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184295.805539 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184295.805539 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193504.036516 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193504.036516 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2896771 # number of replacements -system.cpu.icache.tags.tagsinuse 511.208867 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54659323 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2897283 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.865718 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2897049 # number of replacements +system.cpu.icache.tags.tagsinuse 511.208859 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54662046 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2897561 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.864847 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 18409362500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.208867 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.208859 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998455 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998455 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 198 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60453912 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60453912 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 54659323 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54659323 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54659323 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54659323 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54659323 # number of overall hits -system.cpu.icache.overall_hits::total 54659323 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2897295 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 2897295 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2897295 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 2897295 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 2897295 # number of overall misses -system.cpu.icache.overall_misses::total 2897295 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 40482979500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 40482979500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 40482979500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 40482979500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 40482979500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 40482979500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 57556618 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 57556618 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 57556618 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 57556618 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 57556618 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 57556618 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050338 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.050338 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.050338 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.050338 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.050338 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120436.573347 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118607.271587 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118866.533260 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118120.405780 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118120.405780 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120379.278022 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120379.278022 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122132.052736 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122132.052736 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131892 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120379.278022 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118510.415877 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118775.376236 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131892 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120379.278022 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118510.415877 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118775.376236 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189159.877931 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181003.782994 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172793.956642 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172793.956642 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189161.612592 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181005.330582 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172794.663573 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172794.663573 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181471.122731 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177379.091506 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181472.374561 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177380.267939 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 7512196 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3771568 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58931 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 7513127 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3772095 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58799 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 590 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 590 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 134847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3579536 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 134810 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3579896 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 824044 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2845126 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 144354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2791 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 824175 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2897049 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 151656 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2785 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2793 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 2897295 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 547417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2787 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296193 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296193 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 2897573 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 547535 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8647216 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2645494 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15284 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 161772 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11469766 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 367754112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98971817 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18836 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 289572 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 467034337 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 192407 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4075202 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021767 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.145921 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8699695 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2653154 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15282 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 161550 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11529681 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 371094976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98987561 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18780 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 288880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 470390197 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 192578 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4075586 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.021763 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.145909 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3986498 97.82% 97.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 88704 2.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3986889 97.82% 97.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 88697 2.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4075202 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7433298000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4075586 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7434078000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 379376 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4352139390 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4352565871 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1311523184 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1311717177 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10577994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10589994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 89414413 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 89368907 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution @@ -1213,7 +1212,7 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46508500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46502500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1225,7 +1224,7 @@ system.iobus.reqLayer4.occupancy 14500 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 89500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 576500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 612500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1247,25 +1246,25 @@ system.iobus.reqLayer20.occupancy 9500 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6069000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6064500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 33518500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 186322027 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187144507 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.036865 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.036750 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 274891173000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.036865 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064804 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064804 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 274891170000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.036750 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064797 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064797 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1279,14 +1278,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29064376 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29064376 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4718637651 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4718637651 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29064376 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29064376 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29064376 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29064376 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29054877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29054877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4549676630 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4549676630 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29054877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29054877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29054877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29054877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1303,19 +1302,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124206.735043 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124206.735043 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130262.744341 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130262.744341 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124206.735043 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124206.735043 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124206.735043 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124206.735043 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 864 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124166.141026 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124166.141026 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125598.405201 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125598.405201 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124166.141026 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124166.141026 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124166.141026 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124166.141026 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 82 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.536585 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1329,14 +1328,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17364376 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17364376 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2907437651 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2907437651 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17364376 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17364376 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17364376 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17364376 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17354877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17354877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2737053618 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2737053618 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17354877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17354877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17354877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17354877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1345,68 +1344,67 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74206.735043 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74206.735043 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80262.744341 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80262.744341 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74206.735043 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74206.735043 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74206.735043 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74206.735043 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74166.141026 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74166.141026 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75559.121522 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75559.121522 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74166.141026 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74166.141026 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74166.141026 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74166.141026 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 34893 # Transaction distribution -system.membus.trans_dist::ReadResp 72281 # Transaction distribution +system.membus.trans_dist::ReadResp 72299 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::WritebackDirty 124040 # Transaction distribution -system.membus.trans_dist::CleanEvict 8592 # Transaction distribution +system.membus.trans_dist::WritebackDirty 124052 # Transaction distribution +system.membus.trans_dist::CleanEvict 8818 # Transaction distribution system.membus.trans_dist::UpgradeReq 4604 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4606 # Transaction distribution -system.membus.trans_dist::ReadExReq 129141 # Transaction distribution -system.membus.trans_dist::ReadExResp 129141 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 37388 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 129140 # Transaction distribution +system.membus.trans_dist::ReadExResp 129140 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 37406 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455331 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562899 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 671799 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450778 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558346 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 631243 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16507232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16671017 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16509088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16672873 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18988137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 18989993 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 505 # Total snoops (count) -system.membus.snoop_fanout::samples 402696 # Request fanout histogram +system.membus.snoop_fanout::samples 402733 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 402696 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 402733 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 402696 # Request fanout histogram -system.membus.reqLayer0.occupancy 87390000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 402733 # Request fanout histogram +system.membus.reqLayer0.occupancy 87415500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 8500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1706000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1703000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 878074394 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 878266116 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 999225638 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 990100000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64122797 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1264123 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks |