diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt | 1679 |
1 files changed, 847 insertions, 832 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 6dd28da03..46452a5a5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.853442 # Number of seconds simulated -sim_ticks 2853442108500 # Number of ticks simulated -final_tick 2853442108500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.852832 # Number of seconds simulated +sim_ticks 2852831758500 # Number of ticks simulated +final_tick 2852831758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171765 # Simulator instruction rate (inst/s) -host_op_rate 207684 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4374009836 # Simulator tick rate (ticks/s) -host_mem_usage 619996 # Number of bytes of host memory used -host_seconds 652.36 # Real time elapsed on the host -sim_insts 112053421 # Number of instructions simulated -sim_ops 135485276 # Number of ops (including micro ops) simulated +host_inst_rate 111123 # Simulator instruction rate (inst/s) +host_op_rate 134357 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2834419538 # Simulator tick rate (ticks/s) +host_mem_usage 554504 # Number of bytes of host memory used +host_seconds 1006.50 # Real time elapsed on the host +sim_insts 111845135 # Number of instructions simulated +sim_ops 135229426 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 7296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 7744 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1671680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9169380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1669888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9170532 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10849380 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1671680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1671680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7972992 # Number of bytes written to this memory +system.physmem.bytes_read::total 10849188 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1669888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1669888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7971008 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7990516 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 114 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7988532 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 121 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26120 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143791 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26092 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143809 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170041 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124578 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170038 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124547 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128959 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2557 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128928 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2714 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 585847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3213445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3802208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 585847 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 585847 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2794166 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6141 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2800308 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2794166 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 585344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3214537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3802954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 585344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 585344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2794069 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2800211 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2794069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2714 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 585847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3219587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6602516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170041 # Number of read requests accepted -system.physmem.writeReqs 165183 # Number of write requests accepted -system.physmem.readBursts 170041 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 165183 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10875008 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue -system.physmem.bytesWritten 9072064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10849380 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10308852 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23407 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4604 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10431 # Per bank write bursts -system.physmem.perBankRdBursts::1 10779 # Per bank write bursts -system.physmem.perBankRdBursts::2 11040 # Per bank write bursts -system.physmem.perBankRdBursts::3 10735 # Per bank write bursts -system.physmem.perBankRdBursts::4 13061 # Per bank write bursts -system.physmem.perBankRdBursts::5 10390 # Per bank write bursts -system.physmem.perBankRdBursts::6 11080 # Per bank write bursts -system.physmem.perBankRdBursts::7 11267 # Per bank write bursts -system.physmem.perBankRdBursts::8 10153 # Per bank write bursts -system.physmem.perBankRdBursts::9 10232 # Per bank write bursts -system.physmem.perBankRdBursts::10 10264 # Per bank write bursts -system.physmem.perBankRdBursts::11 9394 # Per bank write bursts -system.physmem.perBankRdBursts::12 10277 # Per bank write bursts -system.physmem.perBankRdBursts::13 10799 # Per bank write bursts -system.physmem.perBankRdBursts::14 10090 # Per bank write bursts -system.physmem.perBankRdBursts::15 9930 # Per bank write bursts -system.physmem.perBankWrBursts::0 8676 # Per bank write bursts -system.physmem.perBankWrBursts::1 9067 # Per bank write bursts -system.physmem.perBankWrBursts::2 9547 # Per bank write bursts -system.physmem.perBankWrBursts::3 9319 # Per bank write bursts -system.physmem.perBankWrBursts::4 8434 # Per bank write bursts -system.physmem.perBankWrBursts::5 8678 # Per bank write bursts -system.physmem.perBankWrBursts::6 9214 # Per bank write bursts -system.physmem.perBankWrBursts::7 9423 # Per bank write bursts -system.physmem.perBankWrBursts::8 8918 # Per bank write bursts -system.physmem.perBankWrBursts::9 8886 # Per bank write bursts -system.physmem.perBankWrBursts::10 8752 # Per bank write bursts -system.physmem.perBankWrBursts::11 8449 # Per bank write bursts -system.physmem.perBankWrBursts::12 8824 # Per bank write bursts -system.physmem.perBankWrBursts::13 8894 # Per bank write bursts -system.physmem.perBankWrBursts::14 8297 # Per bank write bursts -system.physmem.perBankWrBursts::15 8373 # Per bank write bursts +system.physmem.bw_total::cpu.inst 585344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3220679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6603165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170038 # Number of read requests accepted +system.physmem.writeReqs 165152 # Number of write requests accepted +system.physmem.readBursts 170038 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 165152 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10876672 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5760 # Total number of bytes read from write queue +system.physmem.bytesWritten 9051328 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10849188 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10306868 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 90 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23701 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4591 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10711 # Per bank write bursts +system.physmem.perBankRdBursts::1 10418 # Per bank write bursts +system.physmem.perBankRdBursts::2 10743 # Per bank write bursts +system.physmem.perBankRdBursts::3 10617 # Per bank write bursts +system.physmem.perBankRdBursts::4 13557 # Per bank write bursts +system.physmem.perBankRdBursts::5 10851 # Per bank write bursts +system.physmem.perBankRdBursts::6 10986 # Per bank write bursts +system.physmem.perBankRdBursts::7 10951 # Per bank write bursts +system.physmem.perBankRdBursts::8 10335 # Per bank write bursts +system.physmem.perBankRdBursts::9 10516 # Per bank write bursts +system.physmem.perBankRdBursts::10 10068 # Per bank write bursts +system.physmem.perBankRdBursts::11 9192 # Per bank write bursts +system.physmem.perBankRdBursts::12 10325 # Per bank write bursts +system.physmem.perBankRdBursts::13 10893 # Per bank write bursts +system.physmem.perBankRdBursts::14 9864 # Per bank write bursts +system.physmem.perBankRdBursts::15 9921 # Per bank write bursts +system.physmem.perBankWrBursts::0 8907 # Per bank write bursts +system.physmem.perBankWrBursts::1 8809 # Per bank write bursts +system.physmem.perBankWrBursts::2 9307 # Per bank write bursts +system.physmem.perBankWrBursts::3 9147 # Per bank write bursts +system.physmem.perBankWrBursts::4 8787 # Per bank write bursts +system.physmem.perBankWrBursts::5 9076 # Per bank write bursts +system.physmem.perBankWrBursts::6 9209 # Per bank write bursts +system.physmem.perBankWrBursts::7 9123 # Per bank write bursts +system.physmem.perBankWrBursts::8 9054 # Per bank write bursts +system.physmem.perBankWrBursts::9 9064 # Per bank write bursts +system.physmem.perBankWrBursts::10 8553 # Per bank write bursts +system.physmem.perBankWrBursts::11 8266 # Per bank write bursts +system.physmem.perBankWrBursts::12 8846 # Per bank write bursts +system.physmem.perBankWrBursts::13 9045 # Per bank write bursts +system.physmem.perBankWrBursts::14 8063 # Per bank write bursts +system.physmem.perBankWrBursts::15 8171 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 40 # Number of times write queue was full causing retry -system.physmem.totGap 2853441702500 # Total gap between requests +system.physmem.numWrRetry 51 # Number of times write queue was full causing retry +system.physmem.totGap 2852831352500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169486 # Read request sizes (log2) +system.physmem.readPktSize::6 169483 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 160802 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see +system.physmem.writePktSize::6 160771 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 280 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,121 +159,118 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6904 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 100 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61793 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 322.802648 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.147121 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 338.470119 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22296 36.08% 36.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14465 23.41% 59.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6637 10.74% 70.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3539 5.73% 75.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2616 4.23% 80.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1600 2.59% 82.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1149 1.86% 84.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1212 1.96% 86.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8279 13.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61793 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5874 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.927818 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 584.509202 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5873 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 157 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61712 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 322.918330 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.336942 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.461853 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22238 36.04% 36.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14509 23.51% 59.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6552 10.62% 70.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3615 5.86% 76.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2651 4.30% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1538 2.49% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1136 1.84% 84.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1152 1.87% 86.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8321 13.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61712 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5883 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.886962 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 584.019916 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5882 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5874 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5873 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.134684 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.418054 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 43.798135 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 5542 94.36% 94.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 90 1.53% 95.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 17 0.29% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 15 0.26% 96.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 16 0.27% 96.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 28 0.48% 97.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 28 0.48% 97.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 13 0.22% 97.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 10 0.17% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 8 0.14% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 17 0.29% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 16 0.27% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 10 0.17% 98.93% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5883 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5883 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.039946 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.374321 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 43.145306 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5549 94.32% 94.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 83 1.41% 95.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 21 0.36% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 19 0.32% 96.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 30 0.51% 96.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 24 0.41% 97.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 22 0.37% 97.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 15 0.25% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 11 0.19% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 3 0.05% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 21 0.36% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 13 0.22% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 9 0.15% 98.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-239 6 0.10% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 3 0.05% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 5 0.09% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 7 0.12% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 1 0.02% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 5 0.09% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 11 0.19% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 8 0.14% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 2 0.03% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 3 0.05% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.05% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::592-607 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5873 # Writes before turning the bus around for reads -system.physmem.totQLat 1685079736 # Total ticks spent queuing -system.physmem.totMemAccLat 4871117236 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 849610000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9916.78 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::240-255 2 0.03% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 2 0.03% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 4 0.07% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 7 0.12% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 3 0.05% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 2 0.03% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 6 0.10% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 9 0.15% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 2 0.03% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 3 0.05% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 2 0.03% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.03% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 5 0.08% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 2 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 5 0.08% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5883 # Writes before turning the bus around for reads +system.physmem.totQLat 1723441444 # Total ticks spent queuing +system.physmem.totMemAccLat 4909966444 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 849740000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10140.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28666.78 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28890.99 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 3.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s @@ -281,40 +278,40 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing -system.physmem.readRowHits 140217 # Number of row buffer hits during reads -system.physmem.writeRowHits 109661 # Number of row buffer hits during writes +system.physmem.avgWrQLen 27.38 # Average write queue length when enqueuing +system.physmem.readRowHits 140236 # Number of row buffer hits during reads +system.physmem.writeRowHits 109426 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.35 # Row buffer hit rate for writes -system.physmem.avgGap 8512044.79 # Average gap between requests +system.physmem.writeRowHitRate 77.36 # Row buffer hit rate for writes +system.physmem.avgGap 8511087.30 # Average gap between requests system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 242267760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132189750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 692507400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 468860400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186372491760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83617160895 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1638712655250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1910238133215 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.452112 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2726011845150 # Time in different power states -system.physmem_0.memoryStateTime::REF 95282460000 # Time in different power states +system.physmem_0.actEnergy 243129600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132660000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 692905200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 468925200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186332824080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83554754445 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1638403001250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1909828199775 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.450935 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2725489926444 # Time in different power states +system.physmem_0.memoryStateTime::REF 95262180000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32147776350 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32075649806 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 224857080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122689875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 632876400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 449634240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186372491760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82395435150 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1639784344500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1909982329005 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.362464 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2727805815350 # Time in different power states -system.physmem_1.memoryStateTime::REF 95282460000 # Time in different power states +system.physmem_1.actEnergy 223413120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121902000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 632681400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 447521760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186332824080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82328316795 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1639478823750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1909565482905 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.358845 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2727297379194 # Time in different power states +system.physmem_1.memoryStateTime::REF 95262180000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30353736650 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30272102306 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -334,15 +331,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31053109 # Number of BP lookups -system.cpu.branchPred.condPredicted 16852863 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2525514 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18620216 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13364906 # Number of BTB hits +system.cpu.branchPred.lookups 31016169 # Number of BP lookups +system.cpu.branchPred.condPredicted 16821620 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2509164 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18454178 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13299317 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.776321 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7853668 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1516989 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.066699 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7885459 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1501288 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -373,58 +370,58 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 65844 # Table walker walks requested -system.cpu.dtb.walker.walksShort 65844 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43330 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22514 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 65844 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 65844 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 65844 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7786 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 11086.116106 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 8821.657087 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7338.018596 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 6073 78.00% 78.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 1707 21.92% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 66365 # Table walker walks requested +system.cpu.dtb.walker.walksShort 66365 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43579 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22786 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 66365 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 66365 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 66365 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7796 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11013.949461 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8730.002722 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7624.437396 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 6093 78.16% 78.16% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 1696 21.75% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.97% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::163840-180223 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7786 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::229376-245759 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7796 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 262515000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 262515000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 262515000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6400 82.20% 82.20% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1386 17.80% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7786 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65844 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 6406 82.17% 82.17% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1390 17.83% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7796 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66365 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65844 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7786 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66365 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7796 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7786 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 73630 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7796 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 74161 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24757406 # DTB read hits -system.cpu.dtb.read_misses 59085 # DTB read misses -system.cpu.dtb.write_hits 19449348 # DTB write hits -system.cpu.dtb.write_misses 6759 # DTB write misses +system.cpu.dtb.read_hits 24709745 # DTB read hits +system.cpu.dtb.read_misses 59626 # DTB read misses +system.cpu.dtb.write_hits 19412201 # DTB write hits +system.cpu.dtb.write_misses 6739 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4357 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1268 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1766 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4351 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1292 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1782 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 739 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24816491 # DTB read accesses -system.cpu.dtb.write_accesses 19456107 # DTB write accesses +system.cpu.dtb.perms_faults 733 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24769371 # DTB read accesses +system.cpu.dtb.write_accesses 19418940 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44206754 # DTB hits -system.cpu.dtb.misses 65844 # DTB misses -system.cpu.dtb.accesses 44272598 # DTB accesses +system.cpu.dtb.hits 44121946 # DTB hits +system.cpu.dtb.misses 66365 # DTB misses +system.cpu.dtb.accesses 44188311 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -454,37 +451,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 5446 # Table walker walks requested -system.cpu.itb.walker.walksShort 5446 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 324 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5122 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5446 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5446 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5446 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3184 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 11253.454774 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 8989.562910 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7050.042435 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1281 40.23% 40.23% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1185 37.22% 77.45% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 717 22.52% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 5448 # Table walker walks requested +system.cpu.itb.walker.walksShort 5448 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 319 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5129 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5448 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5448 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5448 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3189 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 11214.016933 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 8947.518192 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7056.251032 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1295 40.61% 40.61% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1177 36.91% 77.52% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 716 22.45% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3184 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3189 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 262109500 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 262109500 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 262109500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2875 90.30% 90.30% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 309 9.70% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3184 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 2879 90.28% 90.28% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.72% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3189 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5446 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5446 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5448 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5448 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3184 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3184 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 8630 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57726188 # ITB inst hits -system.cpu.itb.inst_misses 5446 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3189 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3189 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 8637 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57588649 # ITB inst hits +system.cpu.itb.inst_misses 5448 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -493,191 +490,209 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2973 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2978 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8450 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8467 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57731634 # ITB inst accesses -system.cpu.itb.hits 57726188 # DTB hits -system.cpu.itb.misses 5446 # DTB misses -system.cpu.itb.accesses 57731634 # DTB accesses -system.cpu.numCycles 317415724 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57594097 # ITB inst accesses +system.cpu.itb.hits 57588649 # DTB hits +system.cpu.itb.misses 5448 # DTB misses +system.cpu.itb.accesses 57594097 # DTB accesses +system.cpu.numCycles 315565701 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112053421 # Number of instructions committed -system.cpu.committedOps 135485276 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7764036 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 111845135 # Number of instructions committed +system.cpu.committedOps 135229426 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7692999 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5389516808 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.832718 # CPI: cycles per instruction -system.cpu.ipc 0.353018 # IPC: instructions per cycle +system.cpu.quiesceCycles 5390158471 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.821452 # CPI: cycles per instruction +system.cpu.ipc 0.354427 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed -system.cpu.tickCycles 228406815 # Number of cycles that the object actually ticked -system.cpu.idleCycles 89008909 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 842109 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.947879 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42706608 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 842621 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.683057 # Average number of references to valid blocks. +system.cpu.tickCycles 227544928 # Number of cycles that the object actually ticked +system.cpu.idleCycles 88020773 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 842581 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.947861 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42538360 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 843093 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.455122 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 313221250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.947879 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.947861 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999898 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999898 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 176191359 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 176191359 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23499832 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23499832 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18286134 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18286134 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 457571 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457571 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460116 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460116 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41785966 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41785966 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41785966 # number of overall hits -system.cpu.dcache.overall_hits::total 41785966 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 583874 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 583874 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 541283 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 541283 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8366 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8366 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 175914832 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 175914832 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23018220 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23018220 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18257083 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18257083 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 356514 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 356514 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443429 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443429 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460179 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460179 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41275303 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41275303 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41631817 # number of overall hits +system.cpu.dcache.overall_hits::total 41631817 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 492255 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 492255 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 547766 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 547766 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 169911 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 169911 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22569 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22569 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 1125157 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1125157 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1125157 # number of overall misses -system.cpu.dcache.overall_misses::total 1125157 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8774452459 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8774452459 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23299729316 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23299729316 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 120081750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 120081750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1040021 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1040021 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1209932 # number of overall misses +system.cpu.dcache.overall_misses::total 1209932 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7281770758 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7281770758 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23432647284 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23432647284 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 285921000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 285921000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32074181775 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32074181775 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32074181775 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32074181775 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24083706 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24083706 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18827417 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18827417 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465937 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465937 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460118 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460118 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42911123 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42911123 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42911123 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42911123 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024244 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.024244 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028750 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.028750 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017955 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017955 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 30714418042 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30714418042 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30714418042 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30714418042 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23510475 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23510475 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18804849 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18804849 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 526425 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 526425 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465998 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465998 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460181 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460181 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42315324 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42315324 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42841749 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42841749 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020938 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020938 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029129 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029129 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322764 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.322764 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048432 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048432 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026221 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026221 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026221 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026221 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15027.989702 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15027.989702 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43045.374261 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43045.374261 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14353.544107 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14353.544107 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.024578 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024578 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.028242 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.028242 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14792.680131 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14792.680131 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42778.572025 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42778.572025 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12668.749169 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12668.749169 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28506.405573 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28506.405573 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28506.405573 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28506.405573 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29532.497942 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29532.497942 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25385.243172 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25385.243172 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 240 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 697919 # number of writebacks -system.cpu.dcache.writebacks::total 697919 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45195 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 45195 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 242825 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 242825 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 288020 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 288020 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 288020 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 288020 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 538679 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 538679 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298458 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298458 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8366 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8366 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 698329 # number of writebacks +system.cpu.dcache.writebacks::total 698329 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75041 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 75041 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249041 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 249041 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14319 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14319 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 324082 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 324082 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 324082 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 324082 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417214 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 417214 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298725 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298725 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121762 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 121762 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8250 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8250 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 837137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 837137 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 837137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 837137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7251218502 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7251218502 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12288582898 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12288582898 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 107501250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 107501250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 715939 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 715939 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 837701 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 837701 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5703446143 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5703446143 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12331014162 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12331014162 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562604290 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562604290 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 106206750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 106206750 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19539801400 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19539801400 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19539801400 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19539801400 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5836783750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5836783750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510033500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510033500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346817250 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346817250 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.022367 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022367 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015852 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015852 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017955 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017955 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18034460305 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18034460305 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19597064595 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19597064595 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5836567000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5836567000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510270500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510270500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346837500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346837500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017746 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017746 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015886 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015886 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.231300 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.231300 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017704 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017704 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.019509 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.019509 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019509 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019509 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13461.112280 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13461.112280 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41173.575170 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41173.575170 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12849.778867 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12849.778867 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016919 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016919 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019553 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019553 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13670.313419 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13670.313419 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41278.815506 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41278.815506 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12833.267276 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12833.267276 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12873.545455 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12873.545455 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81250 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81250 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23341.223002 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23341.223002 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23341.223002 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23341.223002 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25189.939792 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25189.939792 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23393.865586 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23393.865586 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -685,58 +700,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2898605 # number of replacements -system.cpu.icache.tags.tagsinuse 511.397830 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54818221 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2899117 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.908592 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 15715014250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.397830 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998824 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998824 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 2897467 # number of replacements +system.cpu.icache.tags.tagsinuse 511.399907 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54681814 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2897979 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.868948 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 15532087250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.399907 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998828 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998828 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60616478 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60616478 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 54818221 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54818221 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54818221 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54818221 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54818221 # number of overall hits -system.cpu.icache.overall_hits::total 54818221 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2899129 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 2899129 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2899129 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 2899129 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 2899129 # number of overall misses -system.cpu.icache.overall_misses::total 2899129 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39309012875 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000225 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025862 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010568 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.981279 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443805 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443805 # 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mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72850.877193 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443381 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443381 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001711 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000225 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172393 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044127 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001711 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000225 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172393 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044127 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73330.578512 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67515.739524 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71175.050492 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68921.445287 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17762.489134 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17762.489134 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67589.260794 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71774.622668 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69200.064778 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17764.678906 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17764.678906 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65033.561856 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65033.561856 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72850.877193 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65272.857503 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65272.857503 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73330.578512 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67515.739524 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65630.369857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65892.338336 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72850.877193 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67589.260794 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65905.910456 # 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average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1055,52 +1070,52 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3579627 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3579531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3579472 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3579378 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 697919 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2856 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 698329 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2831 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2858 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295607 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5804583 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506486 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15045 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158423 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8484537 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185746048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98788181 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17908 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 280260 # 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Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8484970 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185672448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98844821 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17796 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 282816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 284817881 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 61238 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4578493 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3.007970 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.088920 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4541479 99.20% 99.20% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 36488 0.80% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4542001 99.20% 99.20% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 36492 0.80% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4577967 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3013390750 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4578493 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3014061750 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 208500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 211500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4358889625 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4357263112 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1341438850 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1342100655 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10568000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10577000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 88362250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 89155750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution @@ -1197,23 +1212,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198914708 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198870981 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36809505 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36810507 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.032937 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.031296 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270823051000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.032937 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064559 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064559 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270543128000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.031296 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064456 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064456 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1227,14 +1242,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29244877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29244877 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6652334326 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6652334326 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29244877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29244877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29244877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29244877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29239875 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29239875 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6646548599 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6646548599 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29239875 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29239875 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29239875 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29239875 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1251,19 +1266,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124978.106838 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124978.106838 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183644.388417 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183644.388417 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124978.106838 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124978.106838 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124978.106838 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124978.106838 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22952 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124956.730769 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124956.730769 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183484.667596 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183484.667596 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124956.730769 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124956.730769 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124956.730769 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124956.730769 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22676 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3496 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3466 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.565217 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.542412 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1277,14 +1292,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16937877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16937877 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4768676336 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4768676336 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16937877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16937877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16937877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16937877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16928877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16928877 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4762888611 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4762888611 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16928877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16928877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16928877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16928877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1293,66 +1308,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72384.089744 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72384.089744 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131644.112633 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131644.112633 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72384.089744 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72384.089744 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72384.089744 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72384.089744 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72345.628205 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72345.628205 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131484.336655 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131484.336655 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72345.628205 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72345.628205 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72345.628205 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72345.628205 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 71726 # Transaction distribution -system.membus.trans_dist::ReadResp 71726 # Transaction distribution +system.membus.trans_dist::ReadReq 71736 # Transaction distribution +system.membus.trans_dist::ReadResp 71736 # Transaction distribution system.membus.trans_dist::WriteReq 27583 # Transaction distribution system.membus.trans_dist::WriteResp 27583 # Transaction distribution -system.membus.trans_dist::Writeback 124578 # Transaction distribution +system.membus.trans_dist::Writeback 124547 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4604 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4591 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4606 # Transaction distribution -system.membus.trans_dist::ReadExReq 129395 # Transaction distribution -system.membus.trans_dist::ReadExResp 129395 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4593 # Transaction distribution +system.membus.trans_dist::ReadExReq 129383 # Transaction distribution +system.membus.trans_dist::ReadExResp 129383 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446695 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554255 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446633 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554193 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 663142 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 663080 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16522776 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16686485 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16520600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16684309 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21321941 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 504 # Total snoops (count) -system.membus.snoop_fanout::samples 332271 # Request fanout histogram +system.membus.pkt_size::total 21319765 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 505 # Total snoops (count) +system.membus.snoop_fanout::samples 332236 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 332271 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 332236 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 332271 # Request fanout histogram -system.membus.reqLayer0.occupancy 90362500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 332236 # Request fanout histogram +system.membus.reqLayer0.occupancy 90365500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1704000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1715000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1022735199 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1025055153 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 997821410 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 997764949 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37468495 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 37471493 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |