diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt | 73 |
1 files changed, 68 insertions, 5 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 9c380c00f..ddbc8e898 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -4,15 +4,16 @@ sim_seconds 2.858505 # Nu sim_ticks 2858505242500 # Number of ticks simulated final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125507 # Simulator instruction rate (inst/s) -host_op_rate 151748 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3206183180 # Simulator tick rate (ticks/s) -host_mem_usage 578080 # Number of bytes of host memory used -host_seconds 891.56 # Real time elapsed on the host +host_inst_rate 258042 # Simulator instruction rate (inst/s) +host_op_rate 311992 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6591883972 # Simulator tick rate (ticks/s) +host_mem_usage 625700 # Number of bytes of host memory used +host_seconds 433.64 # Real time elapsed on the host sim_insts 111897168 # Number of instructions simulated sim_ops 135292215 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1705984 # Number of bytes read from this memory @@ -312,6 +313,7 @@ system.physmem_1.memoryStateTime::REF 95451720000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 34173617000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory @@ -324,6 +326,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 179 system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -344,6 +349,7 @@ system.cpu.branchPred.indirectHits 2857246 # Nu system.cpu.branchPred.indirectMisses 187135 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 108257 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -373,6 +379,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 66151 # Table walker walks requested system.cpu.dtb.walker.walksShort 66151 # Table walker walks initiated with short descriptors system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43510 # Level at which table walker walks with short descriptors terminate @@ -422,6 +429,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 44135237 # DTB hits system.cpu.dtb.misses 66151 # DTB misses system.cpu.dtb.accesses 44201388 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -451,6 +459,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 5761 # Table walker walks requested system.cpu.itb.walker.walksShort 5761 # Table walker walks initiated with short descriptors system.cpu.itb.walker.walksShortTerminationLevel::Level1 327 # Level at which table walker walks with short descriptors terminate @@ -500,6 +509,21 @@ system.cpu.itb.inst_accesses 57339683 # IT system.cpu.itb.hits 57333922 # DTB hits system.cpu.itb.misses 5761 # DTB misses system.cpu.itb.accesses 57339683 # DTB accesses +system.cpu.numPwrStateTransitions 6066 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 887601126.287174 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17445279478.153702 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 2969 97.89% 97.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 499966497156 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 166411026471 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2692094216029 # Cumulative time (in ticks) in various power states system.cpu.numCycles 332822103 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -549,6 +573,7 @@ system.cpu.kern.inst.arm 0 # nu system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed system.cpu.tickCycles 228131430 # Number of cycles that the object actually ticked system.cpu.idleCycles 104690673 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 842468 # number of replacements system.cpu.dcache.tags.tagsinuse 511.899803 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 42541759 # Total number of references to valid blocks. @@ -565,6 +590,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 175934555 # Number of tag accesses system.cpu.dcache.tags.data_accesses 175934555 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 23016255 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 23016255 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18262413 # number of WriteReq hits @@ -733,6 +759,7 @@ system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201679.548959 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201679.548959 # average ReadReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106928.531280 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106928.531280 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2894371 # number of replacements system.cpu.icache.tags.tagsinuse 511.208818 # Cycle average of tags in use system.cpu.icache.tags.total_refs 54430342 # Total number of references to valid blocks. @@ -749,6 +776,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 199 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 60220131 # Number of tag accesses system.cpu.icache.tags.data_accesses 60220131 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 54430342 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 54430342 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 54430342 # number of demand (read+write) hits @@ -829,6 +857,7 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129131.411108 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129131.411108 # average overall mshr uncacheable latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 96490 # number of replacements system.cpu.l2cache.tags.tagsinuse 65016.669962 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7024998 # Total number of references to valid blocks. @@ -858,6 +887,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000824 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994766 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 60430282 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 60430282 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 71969 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4812 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 76781 # number of ReadReq hits @@ -1138,6 +1168,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58373 system.cpu.toL2Bus.snoop_filter.tot_snoops 592 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 592 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 134878 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 3577264 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution @@ -1187,6 +1218,7 @@ system.cpu.toL2Bus.respLayer2.occupancy 11196996 # La system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer3.occupancy 88824919 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1281,6 +1313,7 @@ system.iobus.respLayer0.occupancy 82688000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36424 # number of replacements system.iocache.tags.tagsinuse 1.037066 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1295,6 +1328,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328122 # Number of tag accesses system.iocache.tags.data_accesses 328122 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1375,6 +1409,7 @@ system.iocache.demand_avg_mshr_miss_latency::realview.ide 75531.049344 system.iocache.demand_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 34891 # Transaction distribution system.membus.trans_dist::ReadResp 72400 # Transaction distribution system.membus.trans_dist::WriteReq 27583 # Transaction distribution @@ -1428,12 +1463,21 @@ system.membus.respLayer2.occupancy 990225250 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 1263123 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1465,9 +1509,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- |