diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt | 2110 |
1 files changed, 1056 insertions, 1054 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 12eb20a39..60905542e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.858505 # Number of seconds simulated -sim_ticks 2858505242500 # Number of ticks simulated -final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.858997 # Number of seconds simulated +sim_ticks 2858997339500 # Number of ticks simulated +final_tick 2858997339500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152549 # Simulator instruction rate (inst/s) -host_op_rate 184443 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3896990443 # Simulator tick rate (ticks/s) -host_mem_usage 585436 # Number of bytes of host memory used -host_seconds 733.52 # Real time elapsed on the host -sim_insts 111897168 # Number of instructions simulated -sim_ops 135292215 # Number of ops (including micro ops) simulated +host_inst_rate 120078 # Simulator instruction rate (inst/s) +host_op_rate 145187 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3059253370 # Simulator tick rate (ticks/s) +host_mem_usage 579060 # Number of bytes of host memory used +host_seconds 934.54 # Real time elapsed on the host +sim_insts 112217626 # Number of instructions simulated +sim_ops 135683579 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1705984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9156972 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 8000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1706880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9150764 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10871852 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1705984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1705984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7955328 # Number of bytes written to this memory +system.physmem.bytes_read::total 10866732 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1706880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1706880 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7954240 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7972852 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 123 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26656 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143599 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7971764 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 125 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26670 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143502 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170394 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124302 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170314 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124285 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2754 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 596810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3203413 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128666 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 597020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3200690 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3803335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 596810 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 596810 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2783038 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6130 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2789168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2783038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2754 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 596810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3209543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3800889 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 597020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 597020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2782178 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6129 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2788308 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2782178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 597020 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3206819 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6592503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170394 # Number of read requests accepted -system.physmem.writeReqs 128683 # Number of write requests accepted -system.physmem.readBursts 170394 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 128683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10896320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue -system.physmem.bytesWritten 7985280 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10871852 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7972852 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6589197 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170314 # Number of read requests accepted +system.physmem.writeReqs 128666 # Number of write requests accepted +system.physmem.readBursts 170314 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 128666 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10892160 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7936 # Total number of bytes read from write queue +system.physmem.bytesWritten 7984576 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10866732 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7971764 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 124 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10648 # Per bank write bursts -system.physmem.perBankRdBursts::1 11113 # Per bank write bursts -system.physmem.perBankRdBursts::2 10810 # Per bank write bursts -system.physmem.perBankRdBursts::3 10613 # Per bank write bursts -system.physmem.perBankRdBursts::4 13551 # Per bank write bursts -system.physmem.perBankRdBursts::5 10292 # Per bank write bursts -system.physmem.perBankRdBursts::6 10857 # Per bank write bursts -system.physmem.perBankRdBursts::7 10932 # Per bank write bursts -system.physmem.perBankRdBursts::8 10292 # Per bank write bursts -system.physmem.perBankRdBursts::9 10622 # Per bank write bursts -system.physmem.perBankRdBursts::10 10100 # Per bank write bursts -system.physmem.perBankRdBursts::11 9078 # Per bank write bursts -system.physmem.perBankRdBursts::12 10356 # Per bank write bursts -system.physmem.perBankRdBursts::13 10810 # Per bank write bursts -system.physmem.perBankRdBursts::14 10110 # Per bank write bursts -system.physmem.perBankRdBursts::15 10071 # Per bank write bursts -system.physmem.perBankWrBursts::0 7962 # Per bank write bursts -system.physmem.perBankWrBursts::1 8429 # Per bank write bursts -system.physmem.perBankWrBursts::2 8465 # Per bank write bursts -system.physmem.perBankWrBursts::3 8172 # Per bank write bursts -system.physmem.perBankWrBursts::4 7181 # Per bank write bursts -system.physmem.perBankWrBursts::5 7509 # Per bank write bursts -system.physmem.perBankWrBursts::6 7876 # Per bank write bursts -system.physmem.perBankWrBursts::7 8019 # Per bank write bursts -system.physmem.perBankWrBursts::8 7862 # Per bank write bursts -system.physmem.perBankWrBursts::9 8101 # Per bank write bursts -system.physmem.perBankWrBursts::10 7665 # Per bank write bursts -system.physmem.perBankWrBursts::11 6948 # Per bank write bursts -system.physmem.perBankWrBursts::12 7780 # Per bank write bursts -system.physmem.perBankWrBursts::13 8006 # Per bank write bursts -system.physmem.perBankWrBursts::14 7432 # Per bank write bursts -system.physmem.perBankWrBursts::15 7363 # Per bank write bursts +system.physmem.perBankRdBursts::0 10846 # Per bank write bursts +system.physmem.perBankRdBursts::1 10861 # Per bank write bursts +system.physmem.perBankRdBursts::2 10970 # Per bank write bursts +system.physmem.perBankRdBursts::3 10944 # Per bank write bursts +system.physmem.perBankRdBursts::4 13948 # Per bank write bursts +system.physmem.perBankRdBursts::5 10354 # Per bank write bursts +system.physmem.perBankRdBursts::6 10606 # Per bank write bursts +system.physmem.perBankRdBursts::7 10917 # Per bank write bursts +system.physmem.perBankRdBursts::8 10091 # Per bank write bursts +system.physmem.perBankRdBursts::9 10226 # Per bank write bursts +system.physmem.perBankRdBursts::10 9938 # Per bank write bursts +system.physmem.perBankRdBursts::11 9330 # Per bank write bursts +system.physmem.perBankRdBursts::12 10171 # Per bank write bursts +system.physmem.perBankRdBursts::13 10932 # Per bank write bursts +system.physmem.perBankRdBursts::14 10237 # Per bank write bursts +system.physmem.perBankRdBursts::15 9819 # Per bank write bursts +system.physmem.perBankWrBursts::0 8179 # Per bank write bursts +system.physmem.perBankWrBursts::1 8215 # Per bank write bursts +system.physmem.perBankWrBursts::2 8623 # Per bank write bursts +system.physmem.perBankWrBursts::3 8456 # Per bank write bursts +system.physmem.perBankWrBursts::4 7543 # Per bank write bursts +system.physmem.perBankWrBursts::5 7549 # Per bank write bursts +system.physmem.perBankWrBursts::6 7648 # Per bank write bursts +system.physmem.perBankWrBursts::7 8016 # Per bank write bursts +system.physmem.perBankWrBursts::8 7706 # Per bank write bursts +system.physmem.perBankWrBursts::9 7733 # Per bank write bursts +system.physmem.perBankWrBursts::10 7506 # Per bank write bursts +system.physmem.perBankWrBursts::11 7211 # Per bank write bursts +system.physmem.perBankWrBursts::12 7604 # Per bank write bursts +system.physmem.perBankWrBursts::13 8124 # Per bank write bursts +system.physmem.perBankWrBursts::14 7522 # Per bank write bursts +system.physmem.perBankWrBursts::15 7124 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 2858504798000 # Total gap between requests +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 2858996896000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169837 # Read request sizes (log2) +system.physmem.readPktSize::6 169757 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 124302 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 162916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7039 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 288 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124285 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 162889 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7005 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 284 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -160,115 +160,115 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61459 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 307.217495 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 182.591879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.526171 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22578 36.74% 36.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14767 24.03% 60.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6693 10.89% 71.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3646 5.93% 77.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2555 4.16% 81.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2031 3.30% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1005 1.64% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1119 1.82% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7065 11.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61459 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6091 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.951896 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 574.936120 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6090 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61663 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 306.126397 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.384465 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.388642 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22560 36.59% 36.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14992 24.31% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6700 10.87% 71.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3651 5.92% 77.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2898 4.70% 82.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1667 2.70% 85.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1045 1.69% 86.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1093 1.77% 88.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7057 11.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61663 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6083 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.977314 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 575.322656 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6082 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6091 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6090 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.486535 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.508732 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.308920 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5400 88.67% 88.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 109 1.79% 90.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 32 0.53% 90.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 43 0.71% 91.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 35 0.57% 92.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 14 0.23% 92.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 47 0.77% 93.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 15 0.25% 93.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 145 2.38% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.08% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.08% 96.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 14 0.23% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 63 1.03% 97.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 9 0.15% 97.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.08% 97.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 27 0.44% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 95 1.56% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.13% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.11% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6090 # Writes before turning the bus around for reads -system.physmem.totQLat 1821948750 # Total ticks spent queuing -system.physmem.totMemAccLat 5014230000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 851275000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10701.29 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6083 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6083 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.509453 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.487861 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.653648 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5420 89.10% 89.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 90 1.48% 90.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 39 0.64% 91.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 27 0.44% 91.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 35 0.58% 92.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 16 0.26% 92.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 41 0.67% 93.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.12% 93.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 151 2.48% 95.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.10% 95.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.13% 96.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 13 0.21% 96.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 69 1.13% 97.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.07% 97.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 97.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 36 0.59% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 90 1.48% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.16% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.05% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6083 # Writes before turning the bus around for reads +system.physmem.totQLat 1877618250 # Total ticks spent queuing +system.physmem.totMemAccLat 5068680750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 850950000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11032.48 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29451.29 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29782.48 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.79 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s @@ -277,43 +277,43 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.82 # Average write queue length when enqueuing -system.physmem.readRowHits 139699 # Number of row buffer hits during reads -system.physmem.writeRowHits 93863 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.05 # Row buffer hit rate for reads +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.79 # Average write queue length when enqueuing +system.physmem.readRowHits 139443 # Number of row buffer hits during reads +system.physmem.writeRowHits 93842 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.93 # Row buffer hit rate for reads system.physmem.writeRowHitRate 75.21 # Row buffer hit rate for writes -system.physmem.avgGap 9557755.35 # Average gap between requests -system.physmem.pageHitRate 79.16 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 240408000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 131175000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 692764800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 412173360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186703564320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 86549850225 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1639181430000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1913911365705 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.550023 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2726766742000 # Time in different power states -system.physmem_0.memoryStateTime::REF 95451720000 # Time in different power states +system.physmem.avgGap 9562502.16 # Average gap between requests +system.physmem.pageHitRate 79.09 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 244104840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 133192125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 697678800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 416203920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186735603600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86851227465 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1639211384250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1914289395000 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.567370 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2726812979000 # Time in different power states +system.physmem_0.memoryStateTime::REF 95468100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 36286757000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 36713387250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 224214480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122339250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 635216400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 396290880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186703564320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85109194890 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1640445162750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1913635982970 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.453685 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2728879759500 # Time in different power states -system.physmem_1.memoryStateTime::REF 95451720000 # Time in different power states +system.physmem_1.actEnergy 222067440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121167750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 629795400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 392234400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186735603600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85246386480 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1640619139500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1913966394570 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.454393 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2729170897750 # Time in different power states +system.physmem_1.memoryStateTime::REF 95468100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 34173617000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 34358196250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory @@ -326,30 +326,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst 179 system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 30988279 # Number of BP lookups -system.cpu.branchPred.condPredicted 16810499 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2467893 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18543680 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10372624 # Number of BTB hits +system.cpu.branchPred.lookups 31086887 # Number of BP lookups +system.cpu.branchPred.condPredicted 16880230 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2489626 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18671153 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10424859 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 55.936168 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7863209 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1506080 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3044381 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2857246 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 187135 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 108257 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 55.834040 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7822517 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1524102 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3081262 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2891722 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 189540 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 109414 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -379,57 +379,57 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 66151 # Table walker walks requested -system.cpu.dtb.walker.walksShort 66151 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43510 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22641 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 66151 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 66151 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 66151 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7866 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12681.604373 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10478.068683 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8425.510925 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 7859 99.91% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 67741 # Table walker walks requested +system.cpu.dtb.walker.walksShort 67741 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 45017 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22724 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 67741 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 67741 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 67741 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7842 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 12675.784239 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10493.995103 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8407.754568 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7835 99.91% 99.91% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::131072-163839 6 0.08% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7866 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 517922000 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 517922000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 517922000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6508 82.74% 82.74% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1358 17.26% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7866 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66151 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::total 7842 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 517795000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 517795000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 517795000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6453 82.29% 82.29% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1389 17.71% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7842 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 67741 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66151 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7866 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 67741 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7842 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7866 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 74017 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7842 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 75583 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24710833 # DTB read hits -system.cpu.dtb.read_misses 59358 # DTB read misses -system.cpu.dtb.write_hits 19424404 # DTB write hits -system.cpu.dtb.write_misses 6793 # DTB write misses +system.cpu.dtb.read_hits 24787454 # DTB read hits +system.cpu.dtb.read_misses 60877 # DTB read misses +system.cpu.dtb.write_hits 19460962 # DTB write hits +system.cpu.dtb.write_misses 6864 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4286 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1526 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1789 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4270 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1452 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1793 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 754 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24770191 # DTB read accesses -system.cpu.dtb.write_accesses 19431197 # DTB write accesses +system.cpu.dtb.perms_faults 741 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24848331 # DTB read accesses +system.cpu.dtb.write_accesses 19467826 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44135237 # DTB hits -system.cpu.dtb.misses 66151 # DTB misses -system.cpu.dtb.accesses 44201388 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 44248416 # DTB hits +system.cpu.dtb.misses 67741 # DTB misses +system.cpu.dtb.accesses 44316157 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -459,37 +459,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 5761 # Table walker walks requested -system.cpu.itb.walker.walksShort 5761 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 327 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5434 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5761 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5761 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5761 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3206 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12829.694323 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10737.941546 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7417.860411 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 2464 76.86% 76.86% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 741 23.11% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 5895 # Table walker walks requested +system.cpu.itb.walker.walksShort 5895 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 321 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5574 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5895 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5895 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5895 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3205 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12907.644306 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10876.938214 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7322.763550 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2473 77.16% 77.16% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 731 22.81% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3206 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 517267500 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 517267500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 517267500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2896 90.33% 90.33% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 310 9.67% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3206 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 3205 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 517140500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 517140500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 517140500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2896 90.36% 90.36% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 309 9.64% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3205 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5761 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5761 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5895 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5895 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3206 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3206 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 8967 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57333922 # ITB inst hits -system.cpu.itb.inst_misses 5761 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3205 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3205 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 9100 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57517109 # ITB inst hits +system.cpu.itb.inst_misses 5895 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -498,727 +498,728 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2928 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2926 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8365 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8405 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57339683 # ITB inst accesses -system.cpu.itb.hits 57333922 # DTB hits -system.cpu.itb.misses 5761 # DTB misses -system.cpu.itb.accesses 57339683 # DTB accesses -system.cpu.numPwrStateTransitions 6066 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 887601126.287174 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17445279478.153702 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 2969 97.89% 97.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 57523004 # ITB inst accesses +system.cpu.itb.hits 57517109 # DTB hits +system.cpu.itb.misses 5895 # DTB misses +system.cpu.itb.accesses 57523004 # DTB accesses +system.cpu.numPwrStateTransitions 6068 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 3034 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 887205873.057680 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17434832353.062756 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 2969 97.86% 97.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 59 1.94% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499966497156 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 166411026471 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2692094216029 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 332822103 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 499967463084 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 3034 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 167214720643 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2691782618857 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 334432391 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 111897168 # Number of instructions committed -system.cpu.committedOps 135292215 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7734017 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5384249089 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.974357 # CPI: cycles per instruction -system.cpu.ipc 0.336207 # IPC: instructions per cycle +system.cpu.committedInsts 112217626 # Number of instructions committed +system.cpu.committedOps 135683579 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7838903 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 3034 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 5383627132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.980213 # CPI: cycles per instruction +system.cpu.ipc 0.335547 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 90691008 67.03% 67.04% # Class of committed instruction -system.cpu.op_class_0::IntMult 113025 0.08% 67.12% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 8533 0.01% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::MemRead 24225299 17.91% 85.03% # Class of committed instruction -system.cpu.op_class_0::MemWrite 20252013 14.97% 100.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 90974393 67.05% 67.05% # Class of committed instruction +system.cpu.op_class_0::IntMult 113069 0.08% 67.13% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 8525 0.01% 67.14% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.14% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.14% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.14% # Class of committed instruction +system.cpu.op_class_0::MemRead 24296976 17.91% 85.05% # Class of committed instruction +system.cpu.op_class_0::MemWrite 20288279 14.95% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 135292215 # Class of committed instruction +system.cpu.op_class_0::total 135683579 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.tickCycles 228131430 # Number of cycles that the object actually ticked -system.cpu.idleCycles 104690673 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 842468 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.899803 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42541759 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 842980 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.465917 # Average number of references to valid blocks. +system.cpu.kern.inst.quiesce 3034 # number of quiesce instructions executed +system.cpu.tickCycles 218593350 # Number of cycles that the object actually ticked +system.cpu.idleCycles 115839041 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 844257 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.899744 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42705909 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 844769 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.553357 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 594757500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.899803 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.899744 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 175934555 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 175934555 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23016255 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23016255 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18262413 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18262413 # 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number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 35725670480 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 298069500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 298069500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 43652936479 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 43652936479 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 43652936479 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 43652936479 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23510097 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23510097 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18810394 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18810394 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 526172 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 526172 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466016 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466016 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460207 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460207 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42320491 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42320491 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42846663 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42846663 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021006 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.021006 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029132 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029132 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322841 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.322841 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047876 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047876 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 43200352480 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 43200352480 # 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number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460249 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42455342 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42455342 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42981702 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42981702 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019692 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.019692 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029102 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029102 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.321825 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.321825 # 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average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64975.544734 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13116.198288 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13116.198288 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023869 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023869 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.027518 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.027518 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16078.042590 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16078.042590 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65135.894866 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65135.894866 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13416.280326 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13416.280326 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83500 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41900.530588 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41900.530588 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36026.399822 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36026.399822 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 306 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 42630.005635 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 42630.005635 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36524.573549 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36524.573549 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 235 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.304348 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.681818 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 699681 # 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average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15678.536537 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64252.477354 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64252.477354 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14091.447796 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14091.447796 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13885.436893 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13885.436893 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016915 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016915 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019528 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 200 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60220131 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60220131 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 54430342 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54430342 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54430342 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54430342 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54430342 # 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number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 40456280000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 40456280000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 40456280000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 40456280000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 57508369 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 57508369 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 57508369 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 57508369 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 57508369 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 57508369 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050336 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.050336 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.050336 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.050336 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.050336 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.050336 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13975.665045 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13975.665045 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13975.665045 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13975.665045 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13975.665045 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13975.665045 # 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mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982399 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442730 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442730 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007912 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026032 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026032 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001706 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 129786.290323 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68029.497985 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68029.497985 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.441586 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.441586 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007919 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026052 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026052 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001691 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000411 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.171748 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044036 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001691 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000411 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.171748 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044036 # 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average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120589.285714 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122700.989682 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122700.989682 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120589.285714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118587.469692 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118868.308720 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120589.285714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118587.469692 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118868.308720 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189177.171678 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181018.744089 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100299.892695 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 101096.856292 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 7506242 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3768367 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58373 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 592 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 592 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118834.485210 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118834.485210 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120722.462156 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120722.462156 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122110.166527 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122110.166527 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 130548 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120722.462156 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119157.147485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119379.058302 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 130548 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120722.462156 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119157.147485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119379.058302 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113622.405535 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189838.580148 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181628.869525 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113622.405535 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100651.888817 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 101432.129594 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 7509695 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3770160 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58111 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 594 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 594 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 134878 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3577264 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 823992 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2894371 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 151399 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2778 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 136822 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3580395 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 825389 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2894242 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 151717 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2784 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2780 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295731 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295731 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 2894895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 547514 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296207 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296207 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 2894766 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 548829 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8691656 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2651684 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16008 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160884 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11520232 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370751872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98928925 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19252 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 288368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 469988417 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 192705 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4072528 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021538 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.145168 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8691264 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2657074 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16340 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 164402 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11529080 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370735360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99133929 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19484 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 295748 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 470184521 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 192671 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 8062744 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 4076067 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.021486 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.144999 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3984815 97.85% 97.85% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 87713 2.15% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3988487 97.85% 97.85% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 87580 2.15% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4072528 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7427836500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4076067 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7431755500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 378877 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4348460548 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4348377811 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1310984681 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1313662211 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 11196996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 11470497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 88824919 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 90488952 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1269,66 +1270,66 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46452000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46348000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 104000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 107000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 331500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 330500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 30500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 85500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 582500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 623500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 21500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 49000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 51000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6139500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6076000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 34107000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38906500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187147502 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187130005 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.037066 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.038429 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 274806935000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.037066 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064817 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064817 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 275018797000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.038429 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064902 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064902 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328122 # Number of tag accesses system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1337,14 +1338,14 @@ system.iocache.demand_misses::realview.ide 36458 # system.iocache.demand_misses::total 36458 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36458 # number of overall misses system.iocache.overall_misses::total 36458 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29059377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29059377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4548977125 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4548977125 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4578036502 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4578036502 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4578036502 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4578036502 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29054877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29054877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4548884128 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4548884128 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4577939005 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4577939005 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4577939005 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4577939005 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1361,14 +1362,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124185.371795 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124185.371795 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125579.094661 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125579.094661 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125570.149268 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125570.149268 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125570.149268 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125570.149268 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 124166.141026 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124166.141026 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125576.527385 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125576.527385 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125567.475040 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125567.475040 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125567.475040 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125567.475040 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1385,14 +1386,14 @@ system.iocache.demand_mshr_misses::realview.ide 36458 system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17359377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17359377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736351620 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2736351620 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2753710997 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2753710997 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2753710997 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2753710997 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17354877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17354877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736261614 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2736261614 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2753616491 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2753616491 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2753616491 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2753616491 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1401,83 +1402,84 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74185.371795 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74185.371795 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75539.742160 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75539.742160 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 34891 # Transaction distribution -system.membus.trans_dist::ReadResp 72400 # Transaction distribution -system.membus.trans_dist::WriteReq 27583 # Transaction distribution -system.membus.trans_dist::WriteResp 27583 # Transaction distribution -system.membus.trans_dist::WritebackDirty 124302 # Transaction distribution -system.membus.trans_dist::CleanEvict 8612 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4581 # Transaction distribution +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74166.141026 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74166.141026 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75537.257454 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75537.257454 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75528.457156 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75528.457156 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75528.457156 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75528.457156 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 34888 # Transaction distribution +system.membus.trans_dist::ReadResp 72464 # Transaction distribution +system.membus.trans_dist::WriteReq 27584 # Transaction distribution +system.membus.trans_dist::WriteResp 27584 # Transaction distribution +system.membus.trans_dist::WritebackDirty 124285 # Transaction distribution +system.membus.trans_dist::CleanEvict 8552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4603 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 129077 # Transaction distribution -system.membus.trans_dist::ReadExResp 129077 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 37509 # Transaction distribution +system.membus.trans_dist::ReadExReq 128933 # Transaction distribution +system.membus.trans_dist::ReadExResp 128933 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 37576 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450878 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558440 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450661 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558229 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 631337 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 631126 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16527584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16691357 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16521376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16685161 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19008477 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 506 # Total snoops (count) -system.membus.snoop_fanout::samples 402790 # Request fanout histogram +system.membus.pkt_size::total 19002281 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 504 # Total snoops (count) +system.membus.snoopTraffic 32128 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 402659 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 402790 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 402659 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 402790 # Request fanout histogram -system.membus.reqLayer0.occupancy 87987000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 402659 # Request fanout histogram +system.membus.reqLayer0.occupancy 92669500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 8500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 8000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1702000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1708000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 879699870 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 910164615 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 990225250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 990045000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1263123 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1264123 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1509,28 +1511,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- |