diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt | 1913 |
1 files changed, 959 insertions, 954 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 481a34a0c..e97d068c7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.858301 # Number of seconds simulated -sim_ticks 2858301146500 # Number of ticks simulated -final_tick 2858301146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.858555 # Number of seconds simulated +sim_ticks 2858554679500 # Number of ticks simulated +final_tick 2858554679500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158663 # Simulator instruction rate (inst/s) -host_op_rate 191838 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4049033168 # Simulator tick rate (ticks/s) -host_mem_usage 629392 # Number of bytes of host memory used -host_seconds 705.92 # Real time elapsed on the host -sim_insts 112003872 # Number of instructions simulated -sim_ops 135422492 # Number of ops (including micro ops) simulated +host_inst_rate 162796 # Simulator instruction rate (inst/s) +host_op_rate 196833 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4157408079 # Simulator tick rate (ticks/s) +host_mem_usage 628580 # Number of bytes of host memory used +host_seconds 687.58 # Real time elapsed on the host +sim_insts 111935485 # Number of instructions simulated +sim_ops 135338943 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 7936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 7616 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1692928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9156716 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1708096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9149804 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10858604 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1692928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1692928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7945984 # Number of bytes written to this memory +system.physmem.bytes_read::total 10866540 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1708096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1708096 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7937280 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7963508 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 124 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7954804 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 119 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26452 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143595 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26689 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143487 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170187 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124156 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170311 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124020 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128537 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2776 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128401 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2664 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 592285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3203552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 597538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3200850 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3798971 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 592285 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 592285 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2779967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6131 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2786098 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2779967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3801411 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 597538 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 597538 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2776676 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6130 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2782806 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2776676 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2664 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 592285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3209683 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 597538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3206980 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6585070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170187 # Number of read requests accepted -system.physmem.writeReqs 128537 # Number of write requests accepted -system.physmem.readBursts 170187 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 128537 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10884288 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue -system.physmem.bytesWritten 7975936 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10858604 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7963508 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6584217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170311 # Number of read requests accepted +system.physmem.writeReqs 128401 # Number of write requests accepted +system.physmem.readBursts 170311 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 128401 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10891264 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue +system.physmem.bytesWritten 7967296 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10866540 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7954804 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40806 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10600 # Per bank write bursts -system.physmem.perBankRdBursts::1 10887 # Per bank write bursts -system.physmem.perBankRdBursts::2 11108 # Per bank write bursts -system.physmem.perBankRdBursts::3 10980 # Per bank write bursts -system.physmem.perBankRdBursts::4 13553 # Per bank write bursts -system.physmem.perBankRdBursts::5 10410 # Per bank write bursts -system.physmem.perBankRdBursts::6 10585 # Per bank write bursts -system.physmem.perBankRdBursts::7 10816 # Per bank write bursts -system.physmem.perBankRdBursts::8 10327 # Per bank write bursts -system.physmem.perBankRdBursts::9 10604 # Per bank write bursts -system.physmem.perBankRdBursts::10 9912 # Per bank write bursts -system.physmem.perBankRdBursts::11 9123 # Per bank write bursts -system.physmem.perBankRdBursts::12 10363 # Per bank write bursts -system.physmem.perBankRdBursts::13 10770 # Per bank write bursts -system.physmem.perBankRdBursts::14 10067 # Per bank write bursts -system.physmem.perBankRdBursts::15 9962 # Per bank write bursts -system.physmem.perBankWrBursts::0 7842 # Per bank write bursts -system.physmem.perBankWrBursts::1 8249 # Per bank write bursts -system.physmem.perBankWrBursts::2 8721 # Per bank write bursts -system.physmem.perBankWrBursts::3 8464 # Per bank write bursts -system.physmem.perBankWrBursts::4 7420 # Per bank write bursts -system.physmem.perBankWrBursts::5 7583 # Per bank write bursts -system.physmem.perBankWrBursts::6 7625 # Per bank write bursts -system.physmem.perBankWrBursts::7 7909 # Per bank write bursts -system.physmem.perBankWrBursts::8 7872 # Per bank write bursts -system.physmem.perBankWrBursts::9 8104 # Per bank write bursts -system.physmem.perBankWrBursts::10 7451 # Per bank write bursts -system.physmem.perBankWrBursts::11 6976 # Per bank write bursts -system.physmem.perBankWrBursts::12 7788 # Per bank write bursts -system.physmem.perBankWrBursts::13 7975 # Per bank write bursts -system.physmem.perBankWrBursts::14 7387 # Per bank write bursts -system.physmem.perBankWrBursts::15 7258 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 49408 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10771 # Per bank write bursts +system.physmem.perBankRdBursts::1 10784 # Per bank write bursts +system.physmem.perBankRdBursts::2 10887 # Per bank write bursts +system.physmem.perBankRdBursts::3 10717 # Per bank write bursts +system.physmem.perBankRdBursts::4 14062 # Per bank write bursts +system.physmem.perBankRdBursts::5 10208 # Per bank write bursts +system.physmem.perBankRdBursts::6 10996 # Per bank write bursts +system.physmem.perBankRdBursts::7 10949 # Per bank write bursts +system.physmem.perBankRdBursts::8 9936 # Per bank write bursts +system.physmem.perBankRdBursts::9 10239 # Per bank write bursts +system.physmem.perBankRdBursts::10 9937 # Per bank write bursts +system.physmem.perBankRdBursts::11 9167 # Per bank write bursts +system.physmem.perBankRdBursts::12 10278 # Per bank write bursts +system.physmem.perBankRdBursts::13 11186 # Per bank write bursts +system.physmem.perBankRdBursts::14 10249 # Per bank write bursts +system.physmem.perBankRdBursts::15 9810 # Per bank write bursts +system.physmem.perBankWrBursts::0 8068 # Per bank write bursts +system.physmem.perBankWrBursts::1 8140 # Per bank write bursts +system.physmem.perBankWrBursts::2 8529 # Per bank write bursts +system.physmem.perBankWrBursts::3 8260 # Per bank write bursts +system.physmem.perBankWrBursts::4 7653 # Per bank write bursts +system.physmem.perBankWrBursts::5 7417 # Per bank write bursts +system.physmem.perBankWrBursts::6 7934 # Per bank write bursts +system.physmem.perBankWrBursts::7 8022 # Per bank write bursts +system.physmem.perBankWrBursts::8 7566 # Per bank write bursts +system.physmem.perBankWrBursts::9 7724 # Per bank write bursts +system.physmem.perBankWrBursts::10 7504 # Per bank write bursts +system.physmem.perBankWrBursts::11 7051 # Per bank write bursts +system.physmem.perBankWrBursts::12 7682 # Per bank write bursts +system.physmem.perBankWrBursts::13 8291 # Per bank write bursts +system.physmem.perBankWrBursts::14 7536 # Per bank write bursts +system.physmem.perBankWrBursts::15 7112 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 16 # Number of times write queue was full causing retry -system.physmem.totGap 2858300743000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 2858554234000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169630 # Read request sizes (log2) +system.physmem.readPktSize::6 169754 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 124156 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6497 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 287 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124020 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6708 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 291 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,159 +159,157 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2399 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 6060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6447 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 42 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61607 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 306.136640 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 182.409953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.199512 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22530 36.57% 36.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14842 24.09% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6878 11.16% 71.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3579 5.81% 77.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2575 4.18% 81.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2036 3.30% 85.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1091 1.77% 86.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1049 1.70% 88.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7027 11.41% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61607 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6204 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.410058 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 569.248357 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6203 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::34 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61347 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 307.404893 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.124702 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.856556 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22378 36.48% 36.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14856 24.22% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6657 10.85% 71.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3691 6.02% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2584 4.21% 81.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1979 3.23% 85.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1099 1.79% 86.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1109 1.81% 88.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6994 11.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61347 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6216 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.377091 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 569.055211 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6215 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6204 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6204 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.087685 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.454852 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.723718 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5415 87.28% 87.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 82 1.32% 88.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 29 0.47% 89.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 170 2.74% 91.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 36 0.58% 92.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 140 2.26% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 51 0.82% 95.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 9 0.15% 95.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 26 0.42% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 17 0.27% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.13% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 160 2.58% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.03% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 20 0.32% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.03% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.13% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6204 # Writes before turning the bus around for reads -system.physmem.totQLat 1827154250 # Total ticks spent queuing -system.physmem.totMemAccLat 5015910500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 850335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10743.73 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6216 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6215 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.029123 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.467033 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.100027 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5396 86.82% 86.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 102 1.64% 88.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 39 0.63% 89.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 172 2.77% 91.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 31 0.50% 92.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 152 2.45% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 39 0.63% 95.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.19% 95.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.27% 95.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 24 0.39% 96.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.11% 96.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 159 2.56% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.10% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.11% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 26 0.42% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 5 0.08% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.05% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6215 # Writes before turning the bus around for reads +system.physmem.totQLat 1812035750 # Total ticks spent queuing +system.physmem.totMemAccLat 5002835750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 850880000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10648.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29493.73 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29398.01 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.79 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.50 # Average write queue length when enqueuing -system.physmem.readRowHits 139389 # Number of row buffer hits during reads -system.physmem.writeRowHits 93694 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.17 # Row buffer hit rate for writes -system.physmem.avgGap 9568366.60 # Average gap between requests -system.physmem.pageHitRate 79.09 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 240959880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 131476125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 693724200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 413508240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186689833200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 86986692810 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1638672097500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1913828291955 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.570205 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2725916009250 # Time in different power states -system.physmem_0.memoryStateTime::REF 95444700000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.83 # Average write queue length when enqueuing +system.physmem.readRowHits 139556 # Number of row buffer hits during reads +system.physmem.writeRowHits 93759 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.01 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.30 # Row buffer hit rate for writes +system.physmem.avgGap 9569599.59 # Average gap between requests +system.physmem.pageHitRate 79.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 241731000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 131896875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 697117200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 414817200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186706615680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86828058675 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1638965418000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1913985654630 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.565069 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2726406946000 # Time in different power states +system.physmem_0.memoryStateTime::REF 95453280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 36932994500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 36694429000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 224789040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122652750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 632790600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 394055280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186689833200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85302372735 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1640149571250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1913516064855 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.460970 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2728391286000 # Time in different power states -system.physmem_1.memoryStateTime::REF 95444700000 # Time in different power states +system.physmem_1.actEnergy 222037200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121151250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 630247800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 391819680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186706615680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85116075930 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1640467157250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1913655104790 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.449434 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2728919167500 # Time in different power states +system.physmem_1.memoryStateTime::REF 95453280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 34465013500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 34182085000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory @@ -331,15 +329,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31040865 # Number of BP lookups -system.cpu.branchPred.condPredicted 16831531 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2506988 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18486474 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13317466 # Number of BTB hits +system.cpu.branchPred.lookups 31017399 # Number of BP lookups +system.cpu.branchPred.condPredicted 16820647 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2503170 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18419836 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13303162 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.038973 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7868005 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1514854 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.221935 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7872052 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1510670 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -370,55 +368,55 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 66489 # Table walker walks requested -system.cpu.dtb.walker.walksShort 66489 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43580 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22909 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 66489 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 66489 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 66489 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7766 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12735.320628 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10552.887084 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8498.851872 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 7759 99.91% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 6 0.08% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7766 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 513949000 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 513949000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 513949000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6383 82.19% 82.19% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1383 17.81% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7766 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66489 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 65808 # Table walker walks requested +system.cpu.dtb.walker.walksShort 65808 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 42987 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22821 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 65808 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 65808 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 65808 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7823 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 12723.315863 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10567.827696 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8328.598591 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7817 99.92% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.06% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7823 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 517922000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 517922000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 517922000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6431 82.21% 82.21% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1392 17.79% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7823 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65808 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66489 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7766 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65808 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7823 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7766 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 74255 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7823 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 73631 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24754555 # DTB read hits -system.cpu.dtb.read_misses 59253 # DTB read misses -system.cpu.dtb.write_hits 19441053 # DTB write hits -system.cpu.dtb.write_misses 7236 # DTB write misses +system.cpu.dtb.read_hits 24739501 # DTB read hits +system.cpu.dtb.read_misses 58797 # DTB read misses +system.cpu.dtb.write_hits 19434146 # DTB write hits +system.cpu.dtb.write_misses 7011 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4351 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1268 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1795 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1307 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1800 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 764 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24813808 # DTB read accesses -system.cpu.dtb.write_accesses 19448289 # DTB write accesses +system.cpu.dtb.perms_faults 763 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24798298 # DTB read accesses +system.cpu.dtb.write_accesses 19441157 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44195608 # DTB hits -system.cpu.dtb.misses 66489 # DTB misses -system.cpu.dtb.accesses 44262097 # DTB accesses +system.cpu.dtb.hits 44173647 # DTB hits +system.cpu.dtb.misses 65808 # DTB misses +system.cpu.dtb.accesses 44239455 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -448,36 +446,36 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 5448 # Table walker walks requested -system.cpu.itb.walker.walksShort 5448 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 320 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5128 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5448 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5448 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5448 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3191 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12717.173300 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10597.999219 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7372.723577 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 2455 76.94% 76.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 735 23.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 5439 # Table walker walks requested +system.cpu.itb.walker.walksShort 5439 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 319 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5120 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5439 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5439 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5439 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3184 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12910.175879 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10824.296487 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7389.330309 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2456 77.14% 77.14% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 727 22.83% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3191 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 513294500 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 513294500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 513294500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2881 90.29% 90.29% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 310 9.71% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3191 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 3184 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 517267500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 517267500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 517267500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2874 90.26% 90.26% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.74% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3184 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5448 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5448 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5439 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5439 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3191 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3191 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 8639 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57598121 # ITB inst hits -system.cpu.itb.inst_misses 5448 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3184 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3184 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 8623 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57560838 # ITB inst hits +system.cpu.itb.inst_misses 5439 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -486,127 +484,127 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2979 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2972 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8499 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8472 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57603569 # ITB inst accesses -system.cpu.itb.hits 57598121 # DTB hits -system.cpu.itb.misses 5448 # DTB misses -system.cpu.itb.accesses 57603569 # DTB accesses -system.cpu.numCycles 332010047 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57566277 # ITB inst accesses +system.cpu.itb.hits 57560838 # DTB hits +system.cpu.itb.misses 5439 # DTB misses +system.cpu.itb.accesses 57566277 # DTB accesses +system.cpu.numCycles 333233745 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112003872 # Number of instructions committed -system.cpu.committedOps 135422492 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7777324 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 3034 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5384653012 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.964273 # CPI: cycles per instruction -system.cpu.ipc 0.337351 # IPC: instructions per cycle +system.cpu.committedInsts 111935485 # Number of instructions committed +system.cpu.committedOps 135338943 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7768370 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 5383936377 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.977016 # CPI: cycles per instruction +system.cpu.ipc 0.335907 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3034 # number of quiesce instructions executed -system.cpu.tickCycles 227998615 # Number of cycles that the object actually ticked -system.cpu.idleCycles 104011432 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 840949 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.900791 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42597434 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 841461 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.623183 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 590729500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.900791 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999806 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999806 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed +system.cpu.tickCycles 228546607 # Number of cycles that the object actually ticked +system.cpu.idleCycles 104687138 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 843126 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.899809 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42573204 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 843638 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.463829 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 594757500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.899809 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 358 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 176149332 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 176149332 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23058407 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23058407 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18275243 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18275243 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 356879 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 356879 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443776 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443776 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460246 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460246 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41333650 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41333650 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41690529 # number of overall hits -system.cpu.dcache.overall_hits::total 41690529 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 492651 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 492651 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 547770 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 547770 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 169693 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 169693 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22295 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22295 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 176066237 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 176066237 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23041742 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23041742 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18267850 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18267850 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 356487 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 356487 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443903 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443903 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460330 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460330 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41309592 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41309592 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41666079 # number of overall hits +system.cpu.dcache.overall_hits::total 41666079 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 494543 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 494543 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 548727 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 548727 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 169803 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 169803 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22255 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22255 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 1040421 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1040421 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1210114 # number of overall misses -system.cpu.dcache.overall_misses::total 1210114 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8002189000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8002189000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 35630203980 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 35630203980 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 292207000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 292207000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1043270 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1043270 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1213073 # number of overall misses +system.cpu.dcache.overall_misses::total 1213073 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8036420500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8036420500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 35621632480 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 35621632480 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 292921000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 292921000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 43632392980 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 43632392980 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 43632392980 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 43632392980 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23551058 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23551058 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18823013 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18823013 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 526572 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 526572 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466071 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466071 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460248 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460248 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42374071 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42374071 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42900643 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42900643 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020918 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020918 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029101 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029101 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322260 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.322260 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047836 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047836 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 43658052980 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 43658052980 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 43658052980 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 43658052980 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23536285 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23536285 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18816577 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18816577 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 526290 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 526290 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466158 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466158 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460332 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460332 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42352862 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42352862 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42879152 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42879152 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021012 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.021012 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029162 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029162 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.322642 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.322642 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047741 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047741 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024553 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024553 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.028207 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.028207 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16243.119368 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16243.119368 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65045.920697 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65045.920697 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13106.391568 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13106.391568 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.024633 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024633 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.028291 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.028291 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16250.195635 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16250.195635 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64916.857527 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64916.857527 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13162.031004 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13162.031004 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83500 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41937.247499 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41937.247499 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36056.431857 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36056.431857 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41847.319467 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41847.319467 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35989.633748 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35989.633748 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 277 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked @@ -615,145 +613,145 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.043478 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 698521 # number of writebacks -system.cpu.dcache.writebacks::total 698521 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76580 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 76580 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249277 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 249277 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14066 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14066 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 325857 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 325857 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 325857 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 325857 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 416071 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 416071 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298493 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298493 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121470 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 121470 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8229 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8229 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 700279 # number of writebacks +system.cpu.dcache.writebacks::total 700279 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76721 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 76721 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249708 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 249708 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14008 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14008 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 326429 # 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number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 714564 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 714564 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 836034 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 836034 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 31128 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6493922500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6493922500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19218375500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19218375500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1715298500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1715298500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 114624000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 114624000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 716841 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 716841 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 838207 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 838207 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 31130 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6533285000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6533285000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19191527000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19191527000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1710229000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1710229000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 114982000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 114982000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25712298000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25712298000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27427596500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27427596500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5937313500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5937313500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4787315000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4787315000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10724628500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10724628500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017667 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017667 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015858 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015858 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230681 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230681 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017656 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017656 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25724812000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25724812000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27435041000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27435041000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6277494000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6277494000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5085199500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5085199500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11362693500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11362693500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017752 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017752 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015891 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015891 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230607 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230607 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017691 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017691 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016863 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016863 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019488 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15607.726806 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15607.726806 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64384.677363 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64384.677363 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14121.169836 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14121.169836 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13929.274517 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13929.274517 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016925 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016925 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019548 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019548 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15636.527038 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15636.527038 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64181.630599 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64181.630599 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14091.500091 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14091.500091 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13942.282042 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13942.282042 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82500 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35983.198146 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35983.198146 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32806.795537 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32806.795537 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190738.675790 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190738.675790 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173560.345140 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173560.345140 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182668.128630 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182668.128630 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35886.356947 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35886.356947 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32730.627399 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32730.627399 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201654.159974 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201654.159974 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184353.230133 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184353.230133 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193526.135164 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193526.135164 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2897329 # number of replacements -system.cpu.icache.tags.tagsinuse 511.212489 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54691304 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2897841 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.873121 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18295812500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.212489 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998462 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998462 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 2897280 # number of replacements +system.cpu.icache.tags.tagsinuse 511.208865 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54654096 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2897792 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.860600 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 18409362500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.208865 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998455 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998455 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60487009 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60487009 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 54691304 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54691304 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54691304 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54691304 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54691304 # 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number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 40491792500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 57589157 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 57589157 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 57589157 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 57589157 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 57589157 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 57589157 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050319 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.050319 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.050319 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.050319 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.050319 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.050319 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13973.031931 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13973.031931 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13973.031931 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13973.031931 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13973.031931 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13973.031931 # average overall miss latency +system.cpu.icache.tags.tag_accesses 60449703 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60449703 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 54654096 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 54654096 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 54654096 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 54654096 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 54654096 # number of overall hits +system.cpu.icache.overall_hits::total 54654096 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 2897804 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2897804 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 2897804 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2897804 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 2897804 # number of overall misses +system.cpu.icache.overall_misses::total 2897804 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 40494431000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 40494431000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 40494431000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 40494431000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 40494431000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 40494431000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 57551900 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 57551900 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 57551900 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 57551900 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 57551900 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 57551900 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050351 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.050351 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.050351 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.050351 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.050351 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.050351 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13974.178723 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13974.178723 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13974.178723 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13974.178723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13974.178723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13974.178723 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -762,212 +760,218 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897853 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 2897853 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 2897853 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 2897853 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 2897853 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 2897853 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3490 # number of ReadReq MSHR uncacheable -system.cpu.icache.ReadReq_mshr_uncacheable::total 3490 # number of ReadReq MSHR uncacheable -system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3490 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 3490 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37593940500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 37593940500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37593940500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 37593940500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37593940500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 37593940500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 450883500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 450883500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 450883500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 450883500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050319 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050319 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050319 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.050319 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050319 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.050319 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12973.032276 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12973.032276 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12973.032276 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12973.032276 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12973.032276 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12973.032276 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129192.979943 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129192.979943 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129192.979943 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129192.979943 # average overall mshr uncacheable latency +system.cpu.icache.writebacks::writebacks 2897280 # number of writebacks +system.cpu.icache.writebacks::total 2897280 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897804 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 2897804 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 2897804 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2897804 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 2897804 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2897804 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3763 # number of ReadReq MSHR uncacheable +system.cpu.icache.ReadReq_mshr_uncacheable::total 3763 # number of ReadReq MSHR uncacheable +system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3763 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 3763 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37596628000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 37596628000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37596628000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 37596628000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37596628000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 37596628000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 485921500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 485921500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 485921500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 485921500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050351 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050351 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050351 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050351 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050351 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.050351 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12974.179068 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12974.179068 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12974.179068 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12974.179068 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12974.179068 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12974.179068 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129131.411108 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129131.411108 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 96606 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65026.172791 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 7027132 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 161852 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 43.417023 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 96402 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65018.831836 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 7030117 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 161646 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 43.490819 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 47537.333831 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 67.598904 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000505 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 12131.683782 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5289.555770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.725362 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001031 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 47317.372704 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 63.574942 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000511 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 12247.402145 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5390.481534 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.722006 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000970 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.185115 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.080712 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.992221 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65196 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 50 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186881 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.082252 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.992109 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 45 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65199 # 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mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172517 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.044093 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000215 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172517 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.044093 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125903.225806 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.441961 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.441961 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007915 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007915 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025846 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025846 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001663 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000216 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007915 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.171957 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044041 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001663 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000216 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007915 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.171957 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044041 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 131340.336134 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125876 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70744.875549 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70744.875549 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131266.666667 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70755.482456 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70755.482456 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118205.063870 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118205.063870 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120864.906630 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120864.906630 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122468.814525 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122468.814525 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125903.225806 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118126.602050 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118126.602050 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120631.926582 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120631.926582 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122428.263482 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122428.263482 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131340.336134 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120864.906630 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118617.575945 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118929.787601 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125903.225806 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120631.926582 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118546.138204 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118839.765779 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131340.336134 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120864.906630 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118617.575945 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118929.787601 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113624.068768 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178237.262272 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 171723.308683 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162059.928217 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162059.928217 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113624.068768 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170636.993068 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 167438.087812 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120631.926582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118546.138204 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118839.765779 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189152.184388 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 180996.919153 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172852.051914 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172852.051914 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181494.336955 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177400.907534 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 7509435 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3770131 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58870 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 575 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 575 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 7513660 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3772219 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58915 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 590 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 590 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 134592 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3578420 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 822692 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2989768 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2779 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 134081 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3579527 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 824300 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2845639 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 144382 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2785 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2781 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295719 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295719 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 2897853 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 545999 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2787 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 2897804 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 547664 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8648477 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2639755 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15227 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 161605 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11465064 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185683904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98756893 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18604 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 288828 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 284748229 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 192861 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 7812074 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018867 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.136054 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8648746 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2646408 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15180 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160178 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11470512 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 367819456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99009385 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18484 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 286196 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 467133521 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 192542 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4075210 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.021724 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.145782 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 7664687 98.11% 98.11% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 147387 1.89% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3986679 97.83% 97.83% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 88531 2.17% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 7812074 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4533598000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 377377 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4075210 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7434516500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4352382759 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4352877441 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1308632806 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1312009118 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10576000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10561994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 89410974 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 88663416 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution @@ -1213,63 +1218,63 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46504000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 89000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 569500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6052000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 168000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 33698500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 124500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186368011 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186339520 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 37500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.036757 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.036928 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 274667845000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.036757 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064797 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064797 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 274875272000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.036928 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064808 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064808 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1283,14 +1288,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29104877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29104877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4697807134 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4697807134 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29104877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29104877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29104877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29104877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29051377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29051377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4719366143 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4719366143 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29051377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29051377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29051377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29051377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1307,19 +1312,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124379.816239 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124379.816239 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129687.696941 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129687.696941 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124379.816239 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124379.816239 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124379.816239 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124379.816239 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124151.183761 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124151.183761 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130282.855096 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130282.855096 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124151.183761 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124151.183761 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124151.183761 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124151.183761 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 731 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 70 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.442857 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1333,14 +1338,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17404877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17404877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886607134 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2886607134 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17404877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17404877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17404877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17404877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17351377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17351377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2908166143 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2908166143 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17351377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17351377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17351377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17351377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1349,68 +1354,68 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74379.816239 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74379.816239 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79687.696941 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79687.696941 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74379.816239 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74379.816239 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74379.816239 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74379.816239 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74151.183761 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74151.183761 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80282.855096 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80282.855096 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74151.183761 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74151.183761 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74151.183761 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74151.183761 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 34618 # Transaction distribution -system.membus.trans_dist::ReadResp 71995 # Transaction distribution -system.membus.trans_dist::WriteReq 27583 # Transaction distribution -system.membus.trans_dist::WriteResp 27583 # Transaction distribution -system.membus.trans_dist::Writeback 124156 # Transaction distribution -system.membus.trans_dist::CleanEvict 8653 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4582 # Transaction distribution +system.membus.trans_dist::ReadReq 34893 # Transaction distribution +system.membus.trans_dist::ReadResp 72333 # Transaction distribution +system.membus.trans_dist::WriteReq 27584 # Transaction distribution +system.membus.trans_dist::WriteResp 27584 # Transaction distribution +system.membus.trans_dist::WritebackDirty 124020 # Transaction distribution +system.membus.trans_dist::CleanEvict 8585 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4599 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4584 # Transaction distribution -system.membus.trans_dist::ReadExReq 129275 # Transaction distribution -system.membus.trans_dist::ReadExResp 129275 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 37377 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4601 # Transaction distribution +system.membus.trans_dist::ReadExReq 129063 # Transaction distribution +system.membus.trans_dist::ReadExResp 129063 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 37440 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455163 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562725 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455241 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562809 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 671625 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 671709 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16504992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16668765 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16504224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16668009 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18985885 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 18985129 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 506 # Total snoops (count) -system.membus.snoop_fanout::samples 402707 # Request fanout histogram +system.membus.snoop_fanout::samples 402632 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 402707 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 402632 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 402707 # Request fanout histogram -system.membus.reqLayer0.occupancy 87547000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 402632 # Request fanout histogram +system.membus.reqLayer0.occupancy 87539000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 8500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1701500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1722000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 878616291 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 878086902 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 998538415 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 999035643 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64594078 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64196432 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |