diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini | 92 |
1 files changed, 44 insertions, 48 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index 4dbc37659..6227da137 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -12,25 +12,23 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 flags_addr=469827632 gic_cpu_addr=738205696 -have_generic_timer=false have_large_asid_64=false have_lpae=false have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -44,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -87,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -363,7 +361,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -374,7 +372,6 @@ size=32768 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -446,9 +443,9 @@ opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntAlu opLat=1 +pipelined=true [system.cpu.fuPool.FUList1] type=FUDesc @@ -460,23 +457,23 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste [system.cpu.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntMult opLat=3 +pipelined=true [system.cpu.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=12 opClass=IntDiv opLat=12 +pipelined=false [system.cpu.fuPool.FUList1.opList2] type=OpDesc eventq_index=0 -issueLat=1 opClass=IprAccess opLat=3 +pipelined=true [system.cpu.fuPool.FUList2] type=FUDesc @@ -488,9 +485,9 @@ opList=system.cpu.fuPool.FUList2.opList [system.cpu.fuPool.FUList2.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=2 +pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc @@ -502,9 +499,9 @@ opList=system.cpu.fuPool.FUList3.opList [system.cpu.fuPool.FUList3.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=2 +pipelined=true [system.cpu.fuPool.FUList4] type=FUDesc @@ -516,184 +513,184 @@ opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 sys [system.cpu.fuPool.FUList4.opList00] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAdd opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList01] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAddAcc opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList02] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAlu opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList03] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCmp opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList04] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCvt opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList05] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMisc opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList06] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMult opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList07] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMultAcc opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList08] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShift opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList09] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShiftAcc opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList10] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdSqrt opLat=9 +pipelined=true [system.cpu.fuPool.FUList4.opList11] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAdd opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList12] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAlu opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList13] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCmp opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList14] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCvt opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList15] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatDiv opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList16] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMisc opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList17] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMult opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList18] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMultAcc opLat=1 +pipelined=true [system.cpu.fuPool.FUList4.opList19] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatSqrt opLat=9 +pipelined=true [system.cpu.fuPool.FUList4.opList20] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatAdd opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList21] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCmp opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList22] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCvt opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList23] type=OpDesc eventq_index=0 -issueLat=9 opClass=FloatDiv opLat=9 +pipelined=false [system.cpu.fuPool.FUList4.opList24] type=OpDesc eventq_index=0 -issueLat=33 opClass=FloatSqrt opLat=33 +pipelined=false [system.cpu.fuPool.FUList4.opList25] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatMult opLat=4 +pipelined=true [system.cpu.icache] type=BaseCache @@ -705,7 +702,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -716,7 +713,6 @@ size=32768 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -816,7 +812,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -827,7 +823,6 @@ size=4194304 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -905,7 +900,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -916,7 +911,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -1284,7 +1278,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -1314,6 +1309,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] |