diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt | 1384 |
1 files changed, 692 insertions, 692 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 07942a1c8..e2d527772 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.538055 # Number of seconds simulated -sim_ticks 2538055224500 # Number of ticks simulated -final_tick 2538055224500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.538087 # Number of seconds simulated +sim_ticks 2538087368500 # Number of ticks simulated +final_tick 2538087368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74782 # Simulator instruction rate (inst/s) -host_op_rate 96192 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3131579061 # Simulator tick rate (ticks/s) -host_mem_usage 390232 # Number of bytes of host memory used -host_seconds 810.47 # Real time elapsed on the host -sim_insts 60608338 # Number of instructions simulated -sim_ops 77960937 # Number of ops (including micro ops) simulated +host_inst_rate 75387 # Simulator instruction rate (inst/s) +host_op_rate 96971 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3156986836 # Simulator tick rate (ticks/s) +host_mem_usage 390016 # Number of bytes of host memory used +host_seconds 803.96 # Real time elapsed on the host +sim_insts 60608307 # Number of instructions simulated +sim_ops 77960925 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9090192 # Number of bytes read from this memory -system.physmem.bytes_read::total 131004176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3781888 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 799104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9092048 # Number of bytes read from this memory +system.physmem.bytes_read::total 131005648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 799104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784192 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6797960 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800264 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12492 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142068 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293438 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59092 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12486 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142097 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293461 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59128 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813110 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47717846 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813146 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47717242 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 1538 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3581558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51615968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1490073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188340 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2678413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1490073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47717846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3582244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51615894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1490962 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1188325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2679287 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1490962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47717242 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 1538 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4769898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54294380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4770569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54295181 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -61,149 +61,149 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64349 # number of replacements -system.l2c.tagsinuse 51370.291201 # Cycle average of tags in use -system.l2c.total_refs 1966684 # Total number of references to valid blocks. -system.l2c.sampled_refs 129742 # Sample count of references to valid blocks. -system.l2c.avg_refs 15.158422 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2527049892000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36909.964338 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 48.537302 # Average occupied blocks per requestor +system.l2c.replacements 64372 # number of replacements +system.l2c.tagsinuse 51362.522219 # Cycle average of tags in use +system.l2c.total_refs 1967256 # Total number of references to valid blocks. +system.l2c.sampled_refs 129768 # Sample count of references to valid blocks. +system.l2c.avg_refs 15.159793 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2527077414000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36916.413821 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 48.977748 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.itb.walker 0.000243 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 8186.541319 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6225.247998 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563201 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000741 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu.inst 8176.092256 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6221.038150 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563300 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000747 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.124917 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.094990 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.783848 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 122661 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11547 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 978702 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 387818 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1500728 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608398 # number of Writeback hits -system.l2c.Writeback_hits::total 608398 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 38 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 112928 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112928 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 122661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11547 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 978702 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 500746 # number of demand (read+write) hits -system.l2c.demand_hits::total 1613656 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 122661 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11547 # number of overall hits -system.l2c.overall_hits::cpu.inst 978702 # number of overall hits -system.l2c.overall_hits::cpu.data 500746 # number of overall hits -system.l2c.overall_hits::total 1613656 # number of overall hits +system.l2c.occ_percent::cpu.inst 0.124757 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.094926 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.783730 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 123430 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 11706 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 978266 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 387692 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1501094 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608347 # number of Writeback hits +system.l2c.Writeback_hits::total 608347 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 112891 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112891 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 123430 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 11706 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 978266 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 500583 # number of demand (read+write) hits +system.l2c.demand_hits::total 1613985 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 123430 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 11706 # number of overall hits +system.l2c.overall_hits::cpu.inst 978266 # number of overall hits +system.l2c.overall_hits::cpu.data 500583 # number of overall hits +system.l2c.overall_hits::total 1613985 # number of overall hits system.l2c.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12372 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 10691 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23125 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2903 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2903 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 10685 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23113 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2905 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133164 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133164 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 133199 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133199 # number of ReadExReq misses system.l2c.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 1 # 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mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985748 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.985748 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541261 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541261 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.223078 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.088264 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000087 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.088259 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000494 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.012476 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.223078 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.088264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.223167 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.088259 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41051.758835 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40465.011287 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40779.001605 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40066.999656 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40066.999656 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41042.964560 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40466.541176 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40775.015144 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.247849 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.247849 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40816.061360 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40816.061360 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40840.036322 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40840.036322 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41051.758835 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40790.105392 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40810.591225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -332,9 +332,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15052335 # DTB read hits +system.cpu.checker.dtb.read_hits 15052368 # DTB read hits system.cpu.checker.dtb.read_misses 7317 # DTB read misses -system.cpu.checker.dtb.write_hits 11295995 # DTB write hits +system.cpu.checker.dtb.write_hits 11296020 # DTB write hits system.cpu.checker.dtb.write_misses 2195 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -345,13 +345,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 181 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15059652 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11298190 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15059685 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11298215 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26348330 # DTB hits +system.cpu.checker.dtb.hits 26348388 # DTB hits system.cpu.checker.dtb.misses 9512 # DTB misses -system.cpu.checker.dtb.accesses 26357842 # DTB accesses -system.cpu.checker.itb.inst_hits 61787107 # ITB inst hits +system.cpu.checker.dtb.accesses 26357900 # DTB accesses +system.cpu.checker.itb.inst_hits 61787075 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -368,36 +368,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61791578 # ITB inst accesses -system.cpu.checker.itb.hits 61787107 # DTB hits +system.cpu.checker.itb.inst_accesses 61791546 # ITB inst accesses +system.cpu.checker.itb.hits 61787075 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61791578 # DTB accesses -system.cpu.checker.numCycles 78251513 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61791546 # DTB accesses +system.cpu.checker.numCycles 78251500 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51779226 # DTB read hits -system.cpu.dtb.read_misses 81574 # DTB read misses -system.cpu.dtb.write_hits 11882622 # DTB write hits -system.cpu.dtb.write_misses 18093 # DTB write misses +system.cpu.dtb.read_hits 51778790 # DTB read hits +system.cpu.dtb.read_misses 81353 # DTB read misses +system.cpu.dtb.write_hits 11881898 # DTB write hits +system.cpu.dtb.write_misses 18166 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 8066 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3293 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 606 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 8033 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3264 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 614 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1237 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51860800 # DTB read accesses -system.cpu.dtb.write_accesses 11900715 # DTB write accesses +system.cpu.dtb.perms_faults 1261 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51860143 # DTB read accesses +system.cpu.dtb.write_accesses 11900064 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63661848 # DTB hits -system.cpu.dtb.misses 99667 # DTB misses -system.cpu.dtb.accesses 63761515 # DTB accesses -system.cpu.itb.inst_hits 13144692 # ITB inst hits -system.cpu.itb.inst_misses 11967 # ITB inst misses +system.cpu.dtb.hits 63660688 # DTB hits +system.cpu.dtb.misses 99519 # DTB misses +system.cpu.dtb.accesses 63760207 # DTB accesses +system.cpu.itb.inst_hits 13142674 # ITB inst hits +system.cpu.itb.inst_misses 12012 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -406,122 +406,122 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5259 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5318 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3477 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13156659 # ITB inst accesses -system.cpu.itb.hits 13144692 # DTB hits -system.cpu.itb.misses 11967 # DTB misses -system.cpu.itb.accesses 13156659 # DTB accesses -system.cpu.numCycles 487285069 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13154686 # ITB inst accesses +system.cpu.itb.hits 13142674 # DTB hits +system.cpu.itb.misses 12012 # DTB misses +system.cpu.itb.accesses 13154686 # DTB accesses +system.cpu.numCycles 487300785 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15533008 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12472748 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 753945 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10621013 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8369898 # Number of BTB hits +system.cpu.BPredUnit.lookups 15530766 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12471723 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 754243 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10651914 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8369263 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1450891 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 81082 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33390116 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101781554 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15533008 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9820789 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22319812 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6080499 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 158808 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 102222011 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133571 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 207903 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 361 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13140422 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1021772 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6316 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 162617823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.771724 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.134680 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1449848 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 80901 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33379389 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 101786531 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15530766 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9819111 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22320239 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6081203 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 158853 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 102204493 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2684 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 133854 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208007 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 300 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13138430 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1021608 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6374 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 162590502 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.771886 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.134900 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140314971 86.29% 86.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1367844 0.84% 87.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1761669 1.08% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2653320 1.63% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2361626 1.45% 91.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1142802 0.70% 92.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2916048 1.79% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 808288 0.50% 94.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9291255 5.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140287148 86.28% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1367954 0.84% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1761574 1.08% 88.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2654240 1.63% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2359914 1.45% 91.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1143060 0.70% 91.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2915951 1.79% 93.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 808451 0.50% 94.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9292210 5.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 162617823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031877 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.208875 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35567426 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101892214 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20037549 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1109983 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4010651 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2100654 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174914 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118316762 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572114 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4010651 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37681511 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40491658 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 54797467 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18895098 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6741438 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110776004 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22866 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1160313 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4487001 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 30716 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115615239 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 507028919 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 506935731 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 93188 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78747197 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36868041 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898954 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797959 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13563069 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21067127 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13877132 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1956196 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2590406 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101357427 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2059773 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126494913 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 198538 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24680718 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65543860 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514575 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 162617823 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.777866 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.488052 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 162590502 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031871 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.208878 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35559403 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 101873570 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20035841 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1111053 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4010635 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2099297 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 175058 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118316110 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 572190 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4010635 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37673170 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40477243 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 54791602 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18894911 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6742941 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110777712 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22948 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1162010 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4487085 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 30869 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115617141 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 507045226 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 506952458 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 92768 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78747095 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36870045 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 898908 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797965 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13562847 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21065168 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13875966 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1948101 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2609238 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101350555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2059934 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126492219 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 199079 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24669987 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65519424 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 514717 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 162590502 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.777980 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.488111 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 116473756 71.62% 71.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14895850 9.16% 80.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7383355 4.54% 85.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6325930 3.89% 89.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12628751 7.77% 96.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2810327 1.73% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1536412 0.94% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 438084 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125358 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 116448984 71.62% 71.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14892562 9.16% 80.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7379275 4.54% 85.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6334493 3.90% 89.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12627372 7.77% 96.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2807487 1.73% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1536769 0.95% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 438389 0.27% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125171 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 162617823 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 162590502 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53829 0.61% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53974 0.61% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available @@ -549,13 +549,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8366722 94.73% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 411335 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8371302 94.73% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 411522 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60100692 47.51% 47.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95407 0.08% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60100206 47.51% 47.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95387 0.08% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.88% # Type of FU issued @@ -568,10 +568,10 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.88% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 12 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.88% # Type of FU issued @@ -583,361 +583,361 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.88% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 47.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53419362 42.23% 90.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12513627 9.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53417810 42.23% 90.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12512990 9.89% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126494913 # Type of FU issued -system.cpu.iq.rate 0.259591 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8831890 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.069820 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 424714403 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128119104 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87467949 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22973 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12866 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10326 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134951003 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12134 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 645792 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126492219 # Type of FU issued +system.cpu.iq.rate 0.259577 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8836801 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.069860 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 424687081 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128101552 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87467188 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22890 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12894 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10336 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134953294 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12060 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 646395 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5347388 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11096 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35111 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2076739 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5345399 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11042 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35020 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2075549 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107215 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1052024 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107217 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1052457 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4010651 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30083339 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540488 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103672693 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 219471 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21067127 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13877132 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1468075 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 126042 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 41068 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35111 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 376458 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332668 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 709126 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123289616 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52469824 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3205297 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4010635 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30068216 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 540743 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103665600 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 220216 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21065168 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13875966 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1468298 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 126232 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 40886 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35020 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 376820 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 332740 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 709560 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123288257 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52469499 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3203962 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 255493 # number of nop insts executed -system.cpu.iew.exec_refs 64863659 # number of memory reference insts executed -system.cpu.iew.exec_branches 11931891 # Number of branches executed -system.cpu.iew.exec_stores 12393835 # Number of stores executed -system.cpu.iew.exec_rate 0.253013 # Inst execution rate -system.cpu.iew.wb_sent 121912605 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87478275 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47524907 # num instructions producing a value -system.cpu.iew.wb_consumers 86445005 # num instructions consuming a value +system.cpu.iew.exec_nop 255111 # number of nop insts executed +system.cpu.iew.exec_refs 64862578 # number of memory reference insts executed +system.cpu.iew.exec_branches 11930392 # Number of branches executed +system.cpu.iew.exec_stores 12393079 # Number of stores executed +system.cpu.iew.exec_rate 0.253002 # Inst execution rate +system.cpu.iew.wb_sent 121911839 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87477524 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47523827 # num instructions producing a value +system.cpu.iew.wb_consumers 86459839 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179522 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549770 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179514 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549664 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24740610 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1545198 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 625619 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158689613 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.492227 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459221 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24732278 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1545217 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 625816 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158662310 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.492312 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.459485 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 130476861 82.22% 82.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14004142 8.82% 91.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3942589 2.48% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2238161 1.41% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2017118 1.27% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1061710 0.67% 96.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1402075 0.88% 97.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 657613 0.41% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2889344 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 130458831 82.22% 82.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13994447 8.82% 91.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3942201 2.48% 93.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2235545 1.41% 94.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2018631 1.27% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1062301 0.67% 96.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1402549 0.88% 97.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 657941 0.41% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2889864 1.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158689613 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60758719 # Number of instructions committed -system.cpu.commit.committedOps 78111318 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 158662310 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60758688 # Number of instructions committed +system.cpu.commit.committedOps 78111306 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27520132 # Number of memory references committed -system.cpu.commit.loads 15719739 # Number of loads committed -system.cpu.commit.membars 413350 # Number of memory barriers committed -system.cpu.commit.branches 10163894 # Number of branches committed +system.cpu.commit.refs 27520186 # Number of memory references committed +system.cpu.commit.loads 15719769 # Number of loads committed +system.cpu.commit.membars 413359 # Number of memory barriers committed +system.cpu.commit.branches 10163898 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69148099 # Number of committed integer instructions. -system.cpu.commit.function_calls 996264 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2889344 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69148075 # Number of committed integer instructions. +system.cpu.commit.function_calls 996262 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2889864 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 256736769 # The number of ROB reads -system.cpu.rob.rob_writes 209812510 # The number of ROB writes -system.cpu.timesIdled 1906775 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 324667246 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4588737338 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60608338 # Number of Instructions Simulated -system.cpu.committedOps 77960937 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60608338 # Number of Instructions Simulated -system.cpu.cpi 8.039902 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.039902 # CPI: Total CPI of All Threads -system.cpu.ipc 0.124380 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.124380 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 558055788 # number of integer regfile reads -system.cpu.int_regfile_writes 90157821 # number of integer regfile writes -system.cpu.fp_regfile_reads 8288 # number of floating regfile reads -system.cpu.fp_regfile_writes 2908 # number of floating regfile writes -system.cpu.misc_regfile_reads 134082325 # number of misc regfile reads -system.cpu.misc_regfile_writes 913357 # number of misc regfile writes -system.cpu.icache.replacements 991945 # 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Number of Instructions Simulated +system.cpu.committedOps 77960925 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60608307 # Number of Instructions Simulated +system.cpu.cpi 8.040165 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.040165 # CPI: Total CPI of All Threads +system.cpu.ipc 0.124376 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.124376 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 558050325 # number of integer regfile reads +system.cpu.int_regfile_writes 90161621 # number of integer regfile writes +system.cpu.fp_regfile_reads 8290 # number of floating regfile reads +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 134103665 # number of misc regfile reads +system.cpu.misc_regfile_writes 913390 # number of misc regfile writes +system.cpu.icache.replacements 991554 # number of replacements +system.cpu.icache.tagsinuse 511.576119 # Cycle average of tags in use +system.cpu.icache.total_refs 12061582 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 992066 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.158044 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 7225354000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.576119 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999172 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999172 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12062971 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12062971 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12062971 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12062971 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12062971 # number of overall hits -system.cpu.icache.overall_hits::total 12062971 # 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number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13140290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13140290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13140290 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13140290 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13140290 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13140290 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081986 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081986 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081986 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081986 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081986 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081986 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15476.262360 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15476.262360 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15476.262360 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15476.262360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15476.262360 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15476.262360 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2904990 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 12061582 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12061582 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12061582 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12061582 # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16664677991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16664677991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13138297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13138297 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13138297 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13138297 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13138297 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13138297 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081952 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081952 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.081952 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081952 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.081952 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081952 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15477.334291 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15477.334291 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15477.334291 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15477.334291 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2769993 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12649346990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12649346990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12649346990 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075531 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075531 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075531 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075531 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12744.998202 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12744.998202 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12744.998202 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12744.998202 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12744.998202 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12744.998202 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84611 # 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mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075512 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075512 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075512 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.714152 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.714152 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 644089 # number of replacements -system.cpu.dcache.tagsinuse 511.991456 # Cycle average of tags in use -system.cpu.dcache.total_refs 21738846 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644601 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.724499 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 50933000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991456 # Average occupied blocks per requestor +system.cpu.dcache.replacements 643955 # number of replacements +system.cpu.dcache.tagsinuse 511.991455 # Cycle average of tags in use +system.cpu.dcache.total_refs 21739303 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644467 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.732221 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 50940000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991455 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13908205 # 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number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 635043 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 635043 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 635043 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6270140101 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6270140101 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9248914453 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9248914453 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164305000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164305000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 305000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 305000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15519054554 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15519054554 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15519054554 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15519054554 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182411169000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182411169000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41923418941 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41923418941 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224334587941 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224334587941 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025477 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025477 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16238.165053 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16238.165053 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37158.113082 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37158.113082 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13281.464716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13281.464716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19062.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19062.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -959,16 +959,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323890643510 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323890643510 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323890643510 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1323585371203 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1323585371203 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88043 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |