diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt | 126 |
1 files changed, 63 insertions, 63 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 8cc8c8d31..11b022e8f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.832863 # Nu sim_ticks 2832862976500 # Number of ticks simulated final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92547 # Simulator instruction rate (inst/s) -host_op_rate 112251 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2318051416 # Simulator tick rate (ticks/s) +host_inst_rate 63021 # Simulator instruction rate (inst/s) +host_op_rate 76439 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1578508192 # Simulator tick rate (ticks/s) host_mem_usage 579360 # Number of bytes of host memory used -host_seconds 1222.09 # Real time elapsed on the host +host_seconds 1794.65 # Real time elapsed on the host sim_insts 113100501 # Number of instructions simulated sim_ops 137180951 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -395,9 +395,9 @@ system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7544 system.cpu.checker.dtb.walker.walkRequestOrigin::total 17252 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 24576303 # DTB read hits +system.cpu.checker.dtb.read_hits 24576304 # DTB read hits system.cpu.checker.dtb.read_misses 8296 # DTB read misses -system.cpu.checker.dtb.write_hits 19632669 # DTB write hits +system.cpu.checker.dtb.write_hits 19632670 # DTB write hits system.cpu.checker.dtb.write_misses 1412 # DTB write misses system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA @@ -408,12 +408,12 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 1622 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 24584599 # DTB read accesses -system.cpu.checker.dtb.write_accesses 19634081 # DTB write accesses +system.cpu.checker.dtb.read_accesses 24584600 # DTB read accesses +system.cpu.checker.dtb.write_accesses 19634082 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 44208972 # DTB hits +system.cpu.checker.dtb.hits 44208974 # DTB hits system.cpu.checker.dtb.misses 9708 # DTB misses -system.cpu.checker.dtb.accesses 44218680 # DTB accesses +system.cpu.checker.dtb.accesses 44218682 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -568,9 +568,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7718 system.cpu.dtb.walker.walkRequestOrigin::total 80086 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25410889 # DTB read hits +system.cpu.dtb.read_hits 25410890 # DTB read hits system.cpu.dtb.read_misses 62740 # DTB read misses -system.cpu.dtb.write_hits 19865162 # DTB write hits +system.cpu.dtb.write_hits 19865163 # DTB write hits system.cpu.dtb.write_misses 9628 # DTB write misses system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA @@ -581,12 +581,12 @@ system.cpu.dtb.align_faults 362 # Nu system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 1318 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25473629 # DTB read accesses -system.cpu.dtb.write_accesses 19874790 # DTB write accesses +system.cpu.dtb.read_accesses 25473630 # DTB read accesses +system.cpu.dtb.write_accesses 19874791 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45276051 # DTB hits +system.cpu.dtb.hits 45276053 # DTB hits system.cpu.dtb.misses 72368 # DTB misses -system.cpu.dtb.accesses 45348419 # DTB accesses +system.cpu.dtb.accesses 45348421 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -690,7 +690,7 @@ system.cpu.itb.accesses 66008446 # DT system.cpu.numCycles 278423951 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104963925 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 104963927 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 184057531 # Number of instructions fetch has processed system.cpu.fetch.Branches 46806016 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 33017160 # Number of branches that fetch has predicted taken @@ -704,21 +704,21 @@ system.cpu.fetch.IcacheWaitRetryStallCycles 188 # system.cpu.fetch.CacheLines 65994399 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 1047621 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 6260 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 270560619 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 270560621 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 0.829508 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 1.217052 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 171637462 63.44% 63.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 171637464 63.44% 63.44% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 29152121 10.77% 74.21% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 14032929 5.19% 79.40% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 55738107 20.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 270560619 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 270560621 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.168111 # Number of branch fetches per cycle system.cpu.fetch.rate 0.661069 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 77946486 # Number of cycles decode is idle +system.cpu.decode.IdleCycles 77946488 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 121877263 # Number of cycles decode is blocked system.cpu.decode.RunCycles 64301274 # Number of cycles decode is running system.cpu.decode.UnblockCycles 3866559 # Number of cycles decode is unblocking @@ -728,7 +728,7 @@ system.cpu.decode.BranchMispred 467954 # Nu system.cpu.decode.DecodedInsts 156976144 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 3511593 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 2569037 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83703987 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 83703989 # Number of cycles rename is idle system.cpu.rename.BlockCycles 11810773 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 76556801 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 62410429 # Number of cycles rename is running @@ -759,14 +759,14 @@ system.cpu.iq.iqSquashedInstsIssued 260968 # Nu system.cpu.iq.iqSquashedInstsExamined 8155598 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14296072 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 121861 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 270560619 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 270560621 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.528675 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 0.865256 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 182379690 67.41% 67.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45219626 16.71% 84.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31881926 11.78% 95.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10262341 3.79% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 182379693 67.41% 67.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45219625 16.71% 84.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31881925 11.78% 95.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10262342 3.79% 99.70% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 817003 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle @@ -775,7 +775,7 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 270560619 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 270560621 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 7341670 32.77% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available @@ -848,7 +848,7 @@ system.cpu.iq.FU_type_0::total 143038678 # Ty system.cpu.iq.rate 0.513744 # Inst issue rate system.cpu.iq.fu_busy_cnt 22406871 # FU busy when requested system.cpu.iq.fu_busy_rate 0.156649 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 579270173 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 579270175 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 153497654 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 139987851 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 35641 # Number of floating instruction queue reads @@ -892,30 +892,30 @@ system.cpu.iew.exec_stores 20827406 # Nu system.cpu.iew.exec_rate 0.510511 # Inst execution rate system.cpu.iew.wb_sent 141769563 # cumulative count of insts sent to commit system.cpu.iew.wb_count 139999221 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63237138 # num instructions producing a value -system.cpu.iew.wb_consumers 95708451 # num instructions consuming a value +system.cpu.iew.wb_producers 63237137 # num instructions producing a value +system.cpu.iew.wb_consumers 95708450 # num instructions consuming a value system.cpu.iew.wb_rate 0.502828 # insts written-back per cycle system.cpu.iew.wb_fanout 0.660727 # average fanout of values written-back system.cpu.commit.commitSquashedInsts 7372199 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1995871 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 715636 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 267668720 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 267668722 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.513081 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.118378 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 194241015 72.57% 72.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43280699 16.17% 88.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 194241019 72.57% 72.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43280697 16.17% 88.74% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 15455980 5.77% 94.51% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 4372366 1.63% 96.14% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 6407128 2.39% 98.54% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 1628567 0.61% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 798347 0.30% 99.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 798346 0.30% 99.45% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 412274 0.15% 99.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1072344 0.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1072345 0.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 267668720 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 267668722 # Number of insts commited each cycle system.cpu.commit.committedInsts 113255406 # Number of instructions committed system.cpu.commit.committedOps 137335856 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -961,11 +961,11 @@ system.cpu.commit.op_class_0::MemWrite 20590535 14.99% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 137335856 # Class of committed instruction -system.cpu.commit.bw_lim_events 1072344 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 389119867 # The number of ROB reads +system.cpu.commit.bw_lim_events 1072345 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 389119868 # The number of ROB reads system.cpu.rob.rob_writes 292294903 # The number of ROB writes system.cpu.timesIdled 890799 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7863332 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 7863330 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.quiesceCycles 5387302003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.committedInsts 113100501 # Number of Instructions Simulated system.cpu.committedOps 137180951 # Number of Ops (including micro ops) Simulated @@ -973,19 +973,19 @@ system.cpu.cpi 2.461739 # CP system.cpu.cpi_total 2.461739 # CPI: Total CPI of All Threads system.cpu.ipc 0.406217 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.406217 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155524958 # number of integer regfile reads +system.cpu.int_regfile_reads 155524954 # number of integer regfile reads system.cpu.int_regfile_writes 88488763 # number of integer regfile writes system.cpu.fp_regfile_reads 9529 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502156064 # number of cc regfile reads +system.cpu.cc_regfile_reads 502156067 # number of cc regfile reads system.cpu.cc_regfile_writes 53129749 # number of cc regfile writes -system.cpu.misc_regfile_reads 347863698 # number of misc regfile reads +system.cpu.misc_regfile_reads 347863701 # number of misc regfile reads system.cpu.misc_regfile_writes 1521708 # number of misc regfile writes system.cpu.dcache.tags.replacements 838747 # number of replacements system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40056709 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 40056711 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 839259 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.728662 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.728664 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.925928 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy @@ -995,22 +995,22 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 131 system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179125101 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179125101 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23264147 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23264147 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15542285 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15542285 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 179125109 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179125109 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23264148 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23264148 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15542286 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15542286 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 345698 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 345698 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 441334 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 441334 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460350 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460350 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38806432 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38806432 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39152130 # number of overall hits -system.cpu.dcache.overall_hits::total 39152130 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 38806434 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38806434 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39152132 # number of overall hits +system.cpu.dcache.overall_hits::total 39152132 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 705134 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 705134 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 3607427 # number of WriteReq misses @@ -1037,20 +1037,20 @@ system.cpu.dcache.demand_miss_latency::cpu.data 244199157697 system.cpu.dcache.demand_miss_latency::total 244199157697 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 244199157697 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 244199157697 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23969281 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23969281 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19149712 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19149712 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 23969282 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23969282 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19149713 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19149713 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 523410 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 523410 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468697 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 468697 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460355 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460355 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43118993 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43118993 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43642403 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43642403 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 43118995 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43118995 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43642405 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43642405 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029418 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.029418 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188380 # miss rate for WriteReq accesses |