diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt | 2614 |
1 files changed, 1315 insertions, 1299 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 51e8b32a5..ce335443d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.832619 # Number of seconds simulated -sim_ticks 2832618668500 # Number of ticks simulated -final_tick 2832618668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.832918 # Number of seconds simulated +sim_ticks 2832917624000 # Number of ticks simulated +final_tick 2832917624000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65632 # Simulator instruction rate (inst/s) -host_op_rate 79607 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1643300725 # Simulator tick rate (ticks/s) -host_mem_usage 630388 # Number of bytes of host memory used -host_seconds 1723.74 # Real time elapsed on the host -sim_insts 113133035 # Number of instructions simulated -sim_ops 137220830 # Number of ops (including micro ops) simulated +host_inst_rate 67788 # Simulator instruction rate (inst/s) +host_op_rate 82221 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1698232616 # Simulator tick rate (ticks/s) +host_mem_usage 630604 # Number of bytes of host memory used +host_seconds 1668.16 # Real time elapsed on the host +sim_insts 113081477 # Number of instructions simulated +sim_ops 137157144 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 1600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1321728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9386216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1316032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9392488 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10710952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1321728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1321728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8026688 # Number of bytes written to this memory +system.physmem.bytes_read::total 10711336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1316032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1316032 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8002368 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8044212 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 25 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22899 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 147180 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8019892 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22810 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 147278 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170126 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 125417 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170132 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 125037 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 129798 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 466610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3313618 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 129418 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 464550 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3315482 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3781290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 466610 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466610 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2833663 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6187 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2839850 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2833663 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 466610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3319804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3781026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 464550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 464550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2824780 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2830965 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2824780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 464550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3321668 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6621140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170127 # Number of read requests accepted -system.physmem.writeReqs 129798 # Number of write requests accepted -system.physmem.readBursts 170127 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 129798 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10879424 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue -system.physmem.bytesWritten 8056320 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10711016 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8044212 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6611992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170133 # Number of read requests accepted +system.physmem.writeReqs 129418 # Number of write requests accepted +system.physmem.readBursts 170133 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 129418 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10877696 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10816 # Total number of bytes read from write queue +system.physmem.bytesWritten 8031936 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10711400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8019892 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 169 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40796 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11277 # Per bank write bursts -system.physmem.perBankRdBursts::1 10595 # Per bank write bursts -system.physmem.perBankRdBursts::2 11086 # Per bank write bursts -system.physmem.perBankRdBursts::3 11282 # Per bank write bursts -system.physmem.perBankRdBursts::4 12957 # Per bank write bursts -system.physmem.perBankRdBursts::5 9975 # Per bank write bursts -system.physmem.perBankRdBursts::6 10510 # Per bank write bursts -system.physmem.perBankRdBursts::7 10855 # Per bank write bursts -system.physmem.perBankRdBursts::8 10363 # Per bank write bursts -system.physmem.perBankRdBursts::9 10082 # Per bank write bursts -system.physmem.perBankRdBursts::10 10269 # Per bank write bursts -system.physmem.perBankRdBursts::11 9303 # Per bank write bursts -system.physmem.perBankRdBursts::12 9940 # Per bank write bursts -system.physmem.perBankRdBursts::13 11053 # Per bank write bursts -system.physmem.perBankRdBursts::14 10302 # Per bank write bursts -system.physmem.perBankRdBursts::15 10142 # Per bank write bursts -system.physmem.perBankWrBursts::0 8501 # Per bank write bursts -system.physmem.perBankWrBursts::1 7938 # Per bank write bursts -system.physmem.perBankWrBursts::2 8637 # Per bank write bursts -system.physmem.perBankWrBursts::3 8770 # Per bank write bursts -system.physmem.perBankWrBursts::4 7610 # Per bank write bursts -system.physmem.perBankWrBursts::5 7376 # Per bank write bursts -system.physmem.perBankWrBursts::6 7709 # Per bank write bursts -system.physmem.perBankWrBursts::7 8071 # Per bank write bursts -system.physmem.perBankWrBursts::8 7782 # Per bank write bursts -system.physmem.perBankWrBursts::9 7594 # Per bank write bursts -system.physmem.perBankWrBursts::10 7680 # Per bank write bursts -system.physmem.perBankWrBursts::11 6982 # Per bank write bursts -system.physmem.perBankWrBursts::12 7590 # Per bank write bursts -system.physmem.perBankWrBursts::13 8396 # Per bank write bursts -system.physmem.perBankWrBursts::14 7757 # Per bank write bursts -system.physmem.perBankWrBursts::15 7487 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 48557 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11298 # Per bank write bursts +system.physmem.perBankRdBursts::1 10506 # Per bank write bursts +system.physmem.perBankRdBursts::2 10925 # Per bank write bursts +system.physmem.perBankRdBursts::3 11199 # Per bank write bursts +system.physmem.perBankRdBursts::4 12883 # Per bank write bursts +system.physmem.perBankRdBursts::5 10202 # Per bank write bursts +system.physmem.perBankRdBursts::6 10845 # Per bank write bursts +system.physmem.perBankRdBursts::7 11219 # Per bank write bursts +system.physmem.perBankRdBursts::8 10577 # Per bank write bursts +system.physmem.perBankRdBursts::9 10527 # Per bank write bursts +system.physmem.perBankRdBursts::10 10037 # Per bank write bursts +system.physmem.perBankRdBursts::11 8948 # Per bank write bursts +system.physmem.perBankRdBursts::12 9970 # Per bank write bursts +system.physmem.perBankRdBursts::13 10631 # Per bank write bursts +system.physmem.perBankRdBursts::14 9988 # Per bank write bursts +system.physmem.perBankRdBursts::15 10209 # Per bank write bursts +system.physmem.perBankWrBursts::0 8496 # Per bank write bursts +system.physmem.perBankWrBursts::1 7860 # Per bank write bursts +system.physmem.perBankWrBursts::2 8364 # Per bank write bursts +system.physmem.perBankWrBursts::3 8532 # Per bank write bursts +system.physmem.perBankWrBursts::4 7663 # Per bank write bursts +system.physmem.perBankWrBursts::5 7568 # Per bank write bursts +system.physmem.perBankWrBursts::6 8029 # Per bank write bursts +system.physmem.perBankWrBursts::7 8274 # Per bank write bursts +system.physmem.perBankWrBursts::8 8070 # Per bank write bursts +system.physmem.perBankWrBursts::9 7909 # Per bank write bursts +system.physmem.perBankWrBursts::10 7508 # Per bank write bursts +system.physmem.perBankWrBursts::11 6646 # Per bank write bursts +system.physmem.perBankWrBursts::12 7551 # Per bank write bursts +system.physmem.perBankWrBursts::13 8006 # Per bank write bursts +system.physmem.perBankWrBursts::14 7465 # Per bank write bursts +system.physmem.perBankWrBursts::15 7558 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 2832618457500 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 2832917392000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 2996 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166575 # Read request sizes (log2) +system.physmem.readPktSize::6 166581 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 125417 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 150718 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 125037 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150592 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 726 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -159,155 +159,156 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62118 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 304.834026 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.217682 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.637512 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23314 37.53% 37.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14709 23.68% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6728 10.83% 72.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3491 5.62% 77.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2622 4.22% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1595 2.57% 84.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1577 2.54% 86.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1006 1.62% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7076 11.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62118 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6287 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.034993 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 563.024200 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6286 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::59 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 36 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62145 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 304.281406 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.810971 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.663684 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23300 37.49% 37.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14989 24.12% 61.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6559 10.55% 72.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3523 5.67% 77.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2511 4.04% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1609 2.59% 84.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1592 2.56% 87.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1065 1.71% 88.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6997 11.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62145 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6266 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.121768 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 563.971651 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6265 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6287 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6287 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.022268 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.451800 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.249481 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5461 86.86% 86.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 111 1.77% 88.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 41 0.65% 89.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 176 2.80% 92.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 30 0.48% 92.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 149 2.37% 94.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 46 0.73% 95.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 9 0.14% 95.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.21% 96.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 18 0.29% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.08% 96.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.05% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 163 2.59% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.06% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.13% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 20 0.32% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.03% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.05% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.67% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6266 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6266 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.028567 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.454463 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.210745 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5460 87.14% 87.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 110 1.76% 88.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 30 0.48% 89.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 168 2.68% 92.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 26 0.41% 92.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 137 2.19% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 53 0.85% 95.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 15 0.24% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 11 0.18% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 21 0.34% 96.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.10% 96.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.11% 96.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 165 2.63% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.08% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 23 0.37% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.66% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.21% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6287 # Writes before turning the bus around for reads -system.physmem.totQLat 2109686750 # Total ticks spent queuing -system.physmem.totMemAccLat 5297018000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 849955000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12410.58 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 12 0.19% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6266 # Writes before turning the bus around for reads +system.physmem.totQLat 2116809750 # Total ticks spent queuing +system.physmem.totMemAccLat 5303634750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 849820000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12454.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31160.58 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31204.46 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.84 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.90 # Average write queue length when enqueuing -system.physmem.readRowHits 139766 # Number of row buffer hits during reads -system.physmem.writeRowHits 93986 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.64 # Row buffer hit rate for writes -system.physmem.avgGap 9444422.63 # Average gap between requests -system.physmem.pageHitRate 79.00 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 244301400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 133299375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 690588600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 418685760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185012602320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83544770610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1626283896000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1896328144065 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.462100 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2705327267750 # Time in different power states -system.physmem_0.memoryStateTime::REF 94587220000 # Time in different power states +system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing +system.physmem.readRowHits 139542 # Number of row buffer hits during reads +system.physmem.writeRowHits 93775 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.10 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes +system.physmem.avgGap 9457212.27 # Average gap between requests +system.physmem.pageHitRate 78.96 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 246546720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 134524500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 694792800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 419813280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185031927600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83588992920 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1626422631000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1896539228820 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.466691 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2705562728250 # Time in different power states +system.physmem_0.memoryStateTime::REF 94597100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32700163500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32757782250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 225310680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122937375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 635333400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 397016640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185012602320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82147816890 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1627509294000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1896050311305 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.364017 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2707380849000 # Time in different power states -system.physmem_1.memoryStateTime::REF 94587220000 # Time in different power states +system.physmem_1.actEnergy 223269480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121823625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 630918600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 393420240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185031927600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 81878542335 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1627923026250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1896202928130 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.347979 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2708066096500 # Time in different power states +system.physmem_1.memoryStateTime::REF 94597100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30650586000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30247332250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory @@ -327,15 +328,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46909632 # Number of BP lookups -system.cpu.branchPred.condPredicted 24036779 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1233520 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29533462 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21344460 # Number of BTB hits +system.cpu.branchPred.lookups 46858822 # Number of BP lookups +system.cpu.branchPred.condPredicted 24018425 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1233385 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29501817 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21322160 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.272123 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11742450 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33774 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.274057 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11724285 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33905 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -366,45 +367,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.walks 9696 # Table walker walks requested -system.cpu.checker.dtb.walker.walksShort 9696 # Table walker walks initiated with short descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 9696 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 9696 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 9696 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walks 9701 # Table walker walks requested +system.cpu.checker.dtb.walker.walksShort 9701 # Table walker walks initiated with short descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 9701 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 9701 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 9701 # Table walker wait (enqueue to first request) latency system.cpu.checker.dtb.walker.walksPending::samples 375751000 # Table walker pending requests distribution system.cpu.checker.dtb.walker.walksPending::0 375751000 100.00% 100.00% # Table walker pending requests distribution system.cpu.checker.dtb.walker.walksPending::total 375751000 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 6227 82.67% 82.67% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::1M 1305 17.33% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 7532 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9696 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkPageSizes::4K 6238 82.77% 82.77% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::1M 1299 17.23% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 7537 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9701 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9696 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7532 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9701 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7537 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7532 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 17228 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7537 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 17238 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 24584215 # DTB read hits -system.cpu.checker.dtb.read_misses 8281 # DTB read misses -system.cpu.checker.dtb.write_hits 19636610 # DTB write hits -system.cpu.checker.dtb.write_misses 1415 # DTB write misses +system.cpu.checker.dtb.read_hits 24572028 # DTB read hits +system.cpu.checker.dtb.read_misses 8280 # DTB read misses +system.cpu.checker.dtb.write_hits 19630755 # DTB write hits +system.cpu.checker.dtb.write_misses 1421 # DTB write misses system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.checker.dtb.flush_entries 4283 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 1642 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 24592496 # DTB read accesses -system.cpu.checker.dtb.write_accesses 19638025 # DTB write accesses +system.cpu.checker.dtb.read_accesses 24580308 # DTB read accesses +system.cpu.checker.dtb.write_accesses 19632176 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 44220825 # DTB hits -system.cpu.checker.dtb.misses 9696 # DTB misses -system.cpu.checker.dtb.accesses 44230521 # DTB accesses +system.cpu.checker.dtb.hits 44202783 # DTB hits +system.cpu.checker.dtb.misses 9701 # DTB misses +system.cpu.checker.dtb.accesses 44212484 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -452,7 +453,7 @@ system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3170 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3170 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin::total 7995 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 115833137 # ITB inst hits +system.cpu.checker.itb.inst_hits 115778479 # ITB inst hits system.cpu.checker.itb.inst_misses 4825 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -469,11 +470,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 115837962 # ITB inst accesses -system.cpu.checker.itb.hits 115833137 # DTB hits +system.cpu.checker.itb.inst_accesses 115783304 # ITB inst accesses +system.cpu.checker.itb.hits 115778479 # DTB hits system.cpu.checker.itb.misses 4825 # DTB misses -system.cpu.checker.itb.accesses 115837962 # DTB accesses -system.cpu.checker.numCycles 139072975 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 115783304 # DTB accesses +system.cpu.checker.numCycles 139006189 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -505,79 +506,84 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 71741 # Table walker walks requested -system.cpu.dtb.walker.walksShort 71741 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29467 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22287 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 19987 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 51754 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 426.227924 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 2584.933278 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-8191 50562 97.70% 97.70% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-16383 857 1.66% 99.35% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-24575 291 0.56% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-32767 20 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-40959 10 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::40960-49151 9 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 51754 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 17702 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12439.950288 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 9865.120013 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8642.768996 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 17474 98.71% 98.71% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 221 1.25% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 71435 # Table walker walks requested +system.cpu.dtb.walker.walksShort 71435 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29241 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22400 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 19794 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 51641 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 426.153638 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2576.445985 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 49864 96.56% 96.56% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::4096-8191 585 1.13% 97.69% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 525 1.02% 98.71% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::12288-16383 340 0.66% 99.37% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-20479 52 0.10% 99.47% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::20480-24575 220 0.43% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::28672-32767 10 0.02% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-36863 8 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::36864-40959 5 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::45056-49151 11 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 51641 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 17522 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11533.700491 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 9159.086359 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8173.463802 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 17339 98.96% 98.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 177 1.01% 99.97% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-360447 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 17702 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 131083168816 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.618031 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.493607 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 131025996816 99.96% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 38371000 0.03% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 7847500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 6991500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 1099000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 491500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 1479000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 882500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 17522 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 131382086816 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.616564 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.493575 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 131327318816 99.96% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 37570000 0.03% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 7000000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 6185500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 1198500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 643000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1366500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 794500 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 131083168816 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6361 82.57% 82.57% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1343 17.43% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7704 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71741 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walksPending::total 131382086816 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6381 82.69% 82.69% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1336 17.31% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7717 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71435 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71741 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7704 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71435 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7717 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7704 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 79445 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7717 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 79152 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25458814 # DTB read hits -system.cpu.dtb.read_misses 61805 # DTB read misses -system.cpu.dtb.write_hits 19912938 # DTB write hits -system.cpu.dtb.write_misses 9936 # DTB write misses +system.cpu.dtb.read_hits 25445516 # DTB read hits +system.cpu.dtb.read_misses 61525 # DTB read misses +system.cpu.dtb.write_hits 19906341 # DTB write hits +system.cpu.dtb.write_misses 9910 # DTB write misses system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4319 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2196 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 358 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2185 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1314 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25520619 # DTB read accesses -system.cpu.dtb.write_accesses 19922874 # DTB write accesses +system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25507041 # DTB read accesses +system.cpu.dtb.write_accesses 19916251 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45371752 # DTB hits -system.cpu.dtb.misses 71741 # DTB misses -system.cpu.dtb.accesses 45443493 # DTB accesses +system.cpu.dtb.hits 45351857 # DTB hits +system.cpu.dtb.misses 71435 # DTB misses +system.cpu.dtb.accesses 45423292 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -607,54 +613,55 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 11944 # Table walker walks requested -system.cpu.itb.walker.walksShort 11944 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 3964 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7740 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 240 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11704 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 651.102187 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 2927.030280 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-4095 11135 95.14% 95.14% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::4096-8191 148 1.26% 96.40% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-12287 183 1.56% 97.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::12288-16383 77 0.66% 98.62% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-20479 110 0.94% 99.56% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::20480-24575 40 0.34% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::28672-32767 6 0.05% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11704 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3569 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 13485.850378 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10973.901987 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 8473.200886 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 2612 73.19% 73.19% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 916 25.67% 98.85% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-49151 38 1.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-147455 3 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3569 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 23708925416 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.962784 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.189405 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 882867000 3.72% 3.72% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 22825544916 96.27% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 513500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 23708925416 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 3010 90.42% 90.42% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 319 9.58% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3329 # Table walker page sizes translated +system.cpu.itb.walker.walks 11899 # Table walker walks requested +system.cpu.itb.walker.walksShort 11899 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3941 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7737 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 221 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11678 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 616.629560 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2880.318774 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-4095 11122 95.24% 95.24% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::4096-8191 159 1.36% 96.60% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-12287 193 1.65% 98.25% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::12288-16383 62 0.53% 98.78% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-20479 98 0.84% 99.62% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::20480-24575 32 0.27% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 11678 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3549 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12870.386024 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10191.624224 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 8688.844550 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2600 73.26% 73.26% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 892 25.13% 98.39% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-49151 55 1.55% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3549 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 24007842416 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.962955 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.189019 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 889977000 3.71% 3.71% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 23117314916 96.29% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 493000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 57500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 24007842416 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 3008 90.38% 90.38% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 320 9.62% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3328 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11944 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 11944 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11899 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 11899 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3329 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3329 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 15273 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 66274552 # ITB inst hits -system.cpu.itb.inst_misses 11944 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3328 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3328 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 15227 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66219818 # ITB inst hits +system.cpu.itb.inst_misses 11899 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -663,143 +670,143 @@ system.cpu.itb.flush_tlb 128 # Nu system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3096 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2199 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2205 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66286496 # ITB inst accesses -system.cpu.itb.hits 66274552 # DTB hits -system.cpu.itb.misses 11944 # DTB misses -system.cpu.itb.accesses 66286496 # DTB accesses -system.cpu.numCycles 277645869 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66231717 # ITB inst accesses +system.cpu.itb.hits 66219818 # DTB hits +system.cpu.itb.misses 11899 # DTB misses +system.cpu.itb.accesses 66231717 # DTB accesses +system.cpu.numCycles 278809396 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104816225 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184723631 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46909632 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33086910 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 160672113 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6155878 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 195967 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 9078 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 333869 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 563276 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 182 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66274743 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1128462 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5280 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 269668649 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.835474 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.219488 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104752228 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184594753 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46858822 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33046445 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 161837102 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6149420 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 189977 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 9772 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 357687 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 560902 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 181 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66220013 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1133469 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5179 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 270782559 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.831431 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.217897 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 170383279 63.18% 63.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29238814 10.84% 74.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14077384 5.22% 79.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55969172 20.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 171565839 63.36% 63.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29222654 10.79% 74.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14067780 5.20% 79.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55926286 20.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269668649 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.168955 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.665321 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 77872075 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 120737431 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64613956 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3845227 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2599960 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3423402 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 486431 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157413712 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3694235 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2599960 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83719189 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11483136 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 75823110 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62612793 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 33430461 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146780851 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 948885 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 459435 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 64832 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 17222 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 30677805 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150464365 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678641295 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164414257 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10882 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141779508 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8684854 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2843849 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2647501 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13873635 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26407527 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21301019 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1697624 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2214062 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143514940 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2121406 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143299756 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 270446 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8415512 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14711754 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125531 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269668649 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.531392 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.866832 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 270782559 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.168068 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.662082 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 77849645 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 121907615 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64584092 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3844418 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2596789 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3423202 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 486322 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157325754 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3698413 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2596789 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83693975 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11775859 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 76672657 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62585691 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 33457588 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146699029 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 957260 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 452831 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 63761 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 16550 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 30707740 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150373398 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678238170 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164317610 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10889 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141712294 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8661101 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2840653 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2644485 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13863116 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26394295 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21292545 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1689185 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2215742 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143439670 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2121732 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143229007 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 270292 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8404254 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14686510 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125844 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 270782559 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.528945 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.865530 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 181393020 67.27% 67.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45154562 16.74% 84.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32029362 11.88% 95.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10280384 3.81% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 811287 0.30% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 34 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 182544969 67.41% 67.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45137079 16.67% 84.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32020155 11.83% 95.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10269839 3.79% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 810484 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269668649 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 270782559 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7353326 32.78% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 31 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5633689 25.11% 57.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9445566 42.11% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7336568 32.74% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 32 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5631848 25.13% 57.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9441706 42.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 95980665 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113853 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 95930740 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113813 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -823,101 +830,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8580 0.01% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26189090 18.28% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21005231 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8576 0.01% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26175663 18.28% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 20997878 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143299756 # Type of FU issued -system.cpu.iq.rate 0.516124 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22432612 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.156543 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 578935614 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 154057233 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140187198 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35605 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13116 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 11364 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165706663 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23368 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 323603 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 143229007 # Type of FU issued +system.cpu.iq.rate 0.513717 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22410154 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.156464 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 579885434 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 153971015 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140120635 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35585 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13122 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11367 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165613479 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23345 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 322744 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1496259 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 507 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18537 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 706534 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1495175 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 502 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18526 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 703988 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 88309 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6292 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 87827 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6407 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2599960 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1252151 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 541403 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145836919 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2596789 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1243570 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 532137 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145762333 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26407527 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21301019 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1096274 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 18146 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 505783 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18537 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317326 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471404 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 788730 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142356745 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25786743 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 871381 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26394295 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21292545 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1096246 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17995 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 497968 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18526 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317449 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471196 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 788645 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142286885 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25773498 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 870795 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 200573 # number of nop insts executed -system.cpu.iew.exec_refs 46662722 # number of memory reference insts executed -system.cpu.iew.exec_branches 26519669 # Number of branches executed -system.cpu.iew.exec_stores 20875979 # Number of stores executed -system.cpu.iew.exec_rate 0.512728 # Inst execution rate -system.cpu.iew.wb_sent 141970613 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140198562 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63271886 # num instructions producing a value -system.cpu.iew.wb_consumers 95802115 # num instructions consuming a value +system.cpu.iew.exec_nop 200931 # number of nop insts executed +system.cpu.iew.exec_refs 46642508 # number of memory reference insts executed +system.cpu.iew.exec_branches 26501737 # Number of branches executed +system.cpu.iew.exec_stores 20869010 # Number of stores executed +system.cpu.iew.exec_rate 0.510337 # Inst execution rate +system.cpu.iew.wb_sent 141900432 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140132002 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63223126 # num instructions producing a value +system.cpu.iew.wb_consumers 95712973 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.504955 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660444 # average fanout of values written-back +system.cpu.iew.wb_rate 0.502609 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660549 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7621436 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995875 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755541 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 266730475 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.515036 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.120154 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7603118 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995888 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755464 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 267848804 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.512648 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.117834 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 193314140 72.48% 72.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43245727 16.21% 88.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15468136 5.80% 94.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4389606 1.65% 96.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6355153 2.38% 98.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1682348 0.63% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 799161 0.30% 99.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 412032 0.15% 99.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1064172 0.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 194453826 72.60% 72.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43232556 16.14% 88.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15468323 5.78% 94.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4394328 1.64% 96.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6341907 2.37% 98.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1685586 0.63% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 800919 0.30% 99.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 412081 0.15% 99.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1059278 0.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 266730475 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113287940 # Number of instructions committed -system.cpu.commit.committedOps 137375735 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 267848804 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113236382 # Number of instructions committed +system.cpu.commit.committedOps 137312049 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45505753 # Number of memory references committed -system.cpu.commit.loads 24911268 # Number of loads committed -system.cpu.commit.membars 814898 # Number of memory barriers committed -system.cpu.commit.branches 26034583 # Number of branches committed +system.cpu.commit.refs 45487677 # Number of memory references committed +system.cpu.commit.loads 24899120 # Number of loads committed +system.cpu.commit.membars 814929 # Number of memory barriers committed +system.cpu.commit.branches 26016406 # Number of branches committed system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120199859 # Number of committed integer instructions. -system.cpu.commit.function_calls 4887749 # Number of function calls committed. +system.cpu.commit.int_insts 120142081 # Number of committed integer instructions. +system.cpu.commit.function_calls 4881652 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91748615 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 112788 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91703052 66.78% 66.78% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 112745 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -941,501 +948,507 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8579 0.01% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8575 0.01% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24911268 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20594485 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24899120 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20588557 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137375735 # Class of committed instruction -system.cpu.commit.bw_lim_events 1064172 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 388465780 # The number of ROB reads -system.cpu.rob.rob_writes 292930075 # The number of ROB writes -system.cpu.timesIdled 888709 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7977220 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5387591469 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113133035 # Number of Instructions Simulated -system.cpu.committedOps 137220830 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.454154 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.454154 # CPI: Total CPI of All Threads -system.cpu.ipc 0.407472 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.407472 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155797969 # number of integer regfile reads -system.cpu.int_regfile_writes 88612712 # number of integer regfile writes -system.cpu.fp_regfile_reads 9524 # number of floating regfile reads +system.cpu.commit.op_class_0::total 137312049 # Class of committed instruction +system.cpu.commit.bw_lim_events 1059278 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 389547304 # The number of ROB reads +system.cpu.rob.rob_writes 292761659 # The number of ROB writes +system.cpu.timesIdled 892855 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8026837 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5387025853 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113081477 # Number of Instructions Simulated +system.cpu.committedOps 137157144 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.465562 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.465562 # CPI: Total CPI of All Threads +system.cpu.ipc 0.405587 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.405587 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155726558 # number of integer regfile reads +system.cpu.int_regfile_writes 88564581 # number of integer regfile writes +system.cpu.fp_regfile_reads 9527 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502896978 # number of cc regfile reads -system.cpu.cc_regfile_writes 53174784 # number of cc regfile writes -system.cpu.misc_regfile_reads 347572280 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521694 # number of misc regfile writes -system.cpu.dcache.tags.replacements 840044 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.925899 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40105851 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 840556 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.713479 # Average number of references to valid blocks. +system.cpu.cc_regfile_reads 502647576 # number of cc regfile reads +system.cpu.cc_regfile_writes 53157224 # number of cc regfile writes +system.cpu.misc_regfile_reads 348272878 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521665 # number of misc regfile writes +system.cpu.dcache.tags.replacements 837515 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.925653 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40092431 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 838027 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.841455 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.925899 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.925653 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179336842 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179336842 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23308523 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23308523 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15546666 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15546666 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 346021 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 346021 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441431 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441431 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460353 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460353 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38855189 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38855189 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39201210 # number of overall hits -system.cpu.dcache.overall_hits::total 39201210 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 708825 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 708825 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3606988 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3606988 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177865 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177865 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 27388 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 27388 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4315813 # 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number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 244102956174 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 244102956174 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 244102956174 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 244102956174 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24017348 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24017348 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19153654 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19153654 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523886 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523886 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468819 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 468819 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460358 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460358 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43171002 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43171002 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43694888 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43694888 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029513 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029513 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188319 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.188319 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339511 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.339511 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.058419 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.058419 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.099970 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.099970 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.102842 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.102842 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16587.652806 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16587.652806 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64415.299739 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64415.299739 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13714.436980 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13714.436980 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 55600 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 55600 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56560.132743 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56560.132743 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54321.416927 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54321.416927 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 869823 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 179262738 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179262738 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23296604 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23296604 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15545032 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15545032 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 345927 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 345927 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441660 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441660 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460331 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460331 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38841636 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38841636 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39187563 # number of overall hits +system.cpu.dcache.overall_hits::total 39187563 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 708765 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 708765 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3602792 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3602792 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 177926 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 177926 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 27128 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 27128 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 4311557 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4311557 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4489483 # number of overall misses +system.cpu.dcache.overall_misses::total 4489483 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11704891500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11704891500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 232547539185 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 232547539185 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 374670000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 374670000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 305000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 305000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 244252430685 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 244252430685 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 244252430685 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 244252430685 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24005369 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24005369 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19147824 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19147824 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523853 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523853 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468788 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 468788 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460338 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460338 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43153193 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43153193 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43677046 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43677046 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029525 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029525 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188157 # 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miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16514.488582 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16514.488582 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64546.479282 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64546.479282 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13811.191389 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13811.191389 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43571.428571 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43571.428571 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56650.632401 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56650.632401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54405.469557 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54405.469557 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 871729 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6812 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6864 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.689812 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.000146 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # 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number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 415252 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 415252 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299955 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299955 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119671 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 119671 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8455 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8455 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 715207 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 715207 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6403711500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19964415469 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19964415469 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1698297000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1698297000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126773500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126773500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 273000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 273000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26368126969 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26368126969 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28066423969 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28066423969 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5935894500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5935894500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4789947462 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4789947462 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10725841962 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10725841962 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017290 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017290 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015660 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015660 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228429 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228429 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # 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average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14993.908930 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14993.908930 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54600 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54600 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36867.825635 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36867.825635 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33617.395558 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33617.395558 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190686.963924 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190686.963924 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173643.192387 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173643.192387 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182679.462513 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182679.462513 # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6386936500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6386936500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19975151483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19975151483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1701142500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1701142500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126808000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126808000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 298000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 298000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26362087983 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26362087983 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28063230483 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28063230483 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6277199000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6277199000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5075698951 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5075698951 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11352897951 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11352897951 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017210 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017210 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015648 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015648 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228392 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228392 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017904 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017904 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000015 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000015 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016517 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016517 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019058 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019058 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15459.459361 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15459.459361 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66666.504743 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66666.504743 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14218.368660 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14218.368660 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15108.781127 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15108.781127 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42571.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42571.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36985.458098 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36985.458098 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33713.109338 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33713.109338 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201651.161297 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201651.161297 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184002.137067 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184002.137067 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193359.300184 # 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number of replacements +system.cpu.icache.tags.tagsinuse 511.154154 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64237730 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1887345 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 34.036029 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 16318088500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.154154 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68161321 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68161321 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64290369 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64290369 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64290369 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64290369 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64290369 # number of overall hits -system.cpu.icache.overall_hits::total 64290369 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1981370 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1981370 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1981370 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1981370 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1981370 # number of overall misses -system.cpu.icache.overall_misses::total 1981370 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28130756994 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28130756994 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28130756994 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28130756994 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28130756994 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28130756994 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66271739 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66271739 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66271739 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66271739 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66271739 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66271739 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029898 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.029898 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.029898 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.029898 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.029898 # 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number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28148050491 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28148050491 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28148050491 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66217009 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66217009 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66217009 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66217009 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66217009 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66217009 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029891 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.029891 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.029891 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.029891 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.029891 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.029891 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14221.365705 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14221.365705 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14221.365705 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14221.365705 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14221.365705 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14221.365705 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4340 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 167 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 160 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.946108 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 27.125000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91786 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 91786 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 91786 # 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number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3004 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25162612496 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25162612496 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25162612496 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25162612496 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25162612496 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25162612496 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 377653500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 377653500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 377653500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 377653500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028513 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028513 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028513 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.028513 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028513 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.028513 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13316.482621 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13316.482621 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13316.482621 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13316.482621 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13316.482621 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13316.482621 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125716.877497 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125716.877497 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125716.877497 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125716.877497 # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25183213993 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25183213993 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25183213993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25183213993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25183213993 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25183213993 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 377667500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 377667500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 377667500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 377667500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028503 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028503 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028503 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.028503 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028503 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.028503 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13343.019118 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13343.019118 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13343.019118 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13343.019118 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13343.019118 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13343.019118 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125721.537949 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125721.537949 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125721.537949 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125721.537949 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 96843 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65028.531062 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5011588 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5055.325361 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.756503 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000180 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000056 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158380 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.077138 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.992257 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65300 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2907 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6671 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55556 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996399 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 44337663 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 44337663 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 56125 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12636 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 68761 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 698262 # 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65226 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2892 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6640 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55528 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995270 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 44234795 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 44234795 # 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number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1867481 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1867481 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 527598 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 527598 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 54117 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 11847 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1867481 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 689069 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2622514 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 54117 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 11847 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1867481 # 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average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119877.497915 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119877.497915 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122545.237617 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122545.237617 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124784.327741 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124784.327741 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129420 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122642.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122545.237617 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120315.917555 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120580.427643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129420 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122642.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122545.237617 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120315.917555 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120580.427643 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113216.711052 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178186.915738 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 192695000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 192695000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 212500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 212500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16252241500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16252241500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2425990000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2425990000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1667259500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1667259500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2710500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 1060500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2425990000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17919501000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20349262000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2710500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 1060500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2425990000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17919501000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20349262000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340117000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888077000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6228194000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4756881000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4756881000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340117000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10644958000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10985075000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000388 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000439 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988026 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988026 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.456330 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.456330 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010500 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024652 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024652 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000388 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177637 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060442 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000388 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177637 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060442 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 132562.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 130034.482759 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70765.699596 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70765.699596 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70833.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70833.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119915.307199 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119915.307199 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122419.639703 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122419.639703 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125000.712251 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125000.712251 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 132562.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122419.639703 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120370.936864 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120613.235338 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 132562.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122419.639703 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120370.936864 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120613.235338 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189150.856115 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182468.403012 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172444.480696 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172444.480696 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181301.870082 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177988.188211 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5492109 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2761974 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 46577 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 382 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 382 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5484076 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758688 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 47112 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 381 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 381 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 127618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2560581 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 127589 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2556141 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 823684 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1992109 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2751 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2756 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 297333 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 297333 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1889584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 543472 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5634635 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2637259 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32087 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130191 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8434172 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 120978240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98677545 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50572 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 219930957 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 194580 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5786927 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021369 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.144611 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 820637 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1846839 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 142823 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2757 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2763 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 297002 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 297002 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887370 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 541297 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 36194 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5627539 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2629603 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31270 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128179 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8416591 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 239034368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98344937 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47420 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 216552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 337643277 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 197136 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3052848 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025905 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.158851 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5663267 97.86% 97.86% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 123660 2.14% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2973765 97.41% 97.41% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 79083 2.59% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5786927 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3520664000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 259127 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3052848 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5400072997 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 264877 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2838013223 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2834880345 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1307328687 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1303595064 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19448990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19421986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74088903 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74092896 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30172 # Transaction distribution -system.iobus.trans_dist::ReadResp 30172 # Transaction distribution +system.iobus.trans_dist::ReadReq 30198 # Transaction distribution +system.iobus.trans_dist::ReadResp 30198 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1653,9 +1667,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178424 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -1678,207 +1692,209 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 43091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 99500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 29000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 91000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 647500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6192000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 167000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 33054500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 126000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186319025 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186395016 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 31500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36413 # number of replacements -system.iocache.tags.tagsinuse 1.005013 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 256397447000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.005013 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062813 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062813 # Average percentage of cache occupancy +system.iocache.tags.replacements 36409 # number of replacements +system.iocache.tags.tagsinuse 1.005392 # Cycle average of tags in use +system.iocache.tags.total_refs 30 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 256608771000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.005392 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062837 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062837 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328023 # Number of tag accesses -system.iocache.tags.data_accesses 328023 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses -system.iocache.ReadReq_misses::total 223 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 223 # number of demand (read+write) misses -system.iocache.demand_misses::total 223 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 223 # number of overall misses -system.iocache.overall_misses::total 223 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28159877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28159877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4697532148 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4697532148 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28159877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28159877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28159877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28159877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses) +system.iocache.tags.tag_accesses 328227 # Number of tag accesses +system.iocache.tags.data_accesses 328227 # Number of data accesses +system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits +system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits +system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses +system.iocache.ReadReq_misses::total 249 # number of ReadReq misses +system.iocache.WriteLineReq_misses::realview.ide 36195 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36195 # number of WriteLineReq misses +system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses +system.iocache.demand_misses::total 249 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 249 # number of overall misses +system.iocache.overall_misses::total 249 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31311876 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31311876 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4715518140 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4715518140 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31311876 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31311876 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31311876 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31311876 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 223 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 223 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 223 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 223 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 0.999199 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 0.999199 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 126277.475336 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126277.475336 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129680.105676 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129680.105676 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 126277.475336 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126277.475336 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 126277.475336 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126277.475336 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 125750.506024 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125750.506024 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130280.926647 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130280.926647 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125750.506024 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125750.506024 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125750.506024 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125750.506024 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 725 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 77 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.415584 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 223 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 223 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 223 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 223 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17009877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17009877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886332148 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2886332148 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17009877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17009877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17009877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17009877 # number of overall MSHR miss cycles +system.iocache.writebacks::writebacks 36160 # number of writebacks +system.iocache.writebacks::total 36160 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 36195 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 36195 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18861876 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18861876 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2905768140 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2905768140 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18861876 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18861876 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18861876 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18861876 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999199 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.999199 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76277.475336 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76277.475336 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79680.105676 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79680.105676 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76277.475336 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76277.475336 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76277.475336 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76277.475336 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75750.506024 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75750.506024 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80280.926647 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80280.926647 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75750.506024 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75750.506024 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75750.506024 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75750.506024 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 34133 # Transaction distribution -system.membus.trans_dist::ReadResp 67584 # Transaction distribution +system.membus.trans_dist::ReadResp 67565 # Transaction distribution system.membus.trans_dist::WriteReq 27585 # Transaction distribution system.membus.trans_dist::WriteResp 27585 # Transaction distribution -system.membus.trans_dist::Writeback 125417 # Transaction distribution -system.membus.trans_dist::CleanEvict 7628 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4571 # Transaction distribution +system.membus.trans_dist::WritebackDirty 125037 # Transaction distribution +system.membus.trans_dist::CleanEvict 7766 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4574 # Transaction distribution -system.membus.trans_dist::ReadExReq 133608 # Transaction distribution -system.membus.trans_dist::ReadExResp 133608 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 33452 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4599 # Transaction distribution +system.membus.trans_dist::ReadExReq 133659 # Transaction distribution +system.membus.trans_dist::ReadExResp 133659 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 33433 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36194 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455251 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562821 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108888 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108888 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 671709 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455099 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562669 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108826 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108826 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 671495 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16438044 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16601449 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18918569 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 487 # Total snoops (count) -system.membus.snoop_fanout::samples 402837 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16416028 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16579433 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 18894633 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 513 # Total snoops (count) +system.membus.snoop_fanout::samples 402650 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 402837 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 402650 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 402837 # Request fanout histogram -system.membus.reqLayer0.occupancy 83606500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 402650 # Request fanout histogram +system.membus.reqLayer0.occupancy 83677500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1745500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1748500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 875905157 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 874312374 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 988369672 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 988164899 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64470242 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64093300 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |