diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker')
4 files changed, 923 insertions, 854 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index 35fda0d55..f66d752af 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -10,13 +10,15 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +clock=1 +dtb_filename= early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -37,12 +39,11 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge +clock=1 delay=50000 -nack_delay=4000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[0] @@ -63,7 +64,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img read_only=true [system.cpu] @@ -134,7 +135,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -184,7 +184,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -201,8 +200,8 @@ walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[5] @@ -214,8 +213,8 @@ walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[4] @@ -227,16 +226,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=32768 subblock_size=0 system=system @@ -255,8 +256,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -528,16 +529,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=32768 subblock_size=0 system=system @@ -559,8 +562,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -586,16 +589,18 @@ type=BaseCache addr_ranges=0:268435455 assoc=8 block_size=64 +clock=1 forward_snoops=false hash_delay=1 +hit_latency=50000 is_top_level=false -latency=50000 max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=50000 size=1024 subblock_size=0 system=system @@ -611,16 +616,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=10000 is_top_level=false -latency=10000 max_miss_count=0 mshrs=92 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=10000 size=4194304 subblock_size=0 system=system @@ -645,9 +652,10 @@ slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake +clock=1 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -661,8 +669,9 @@ pio=system.membus.default [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=true -file= in_addr_map=true latency=30000 latency_var=0 @@ -682,17 +691,19 @@ system=system [system.realview.a9scu] type=A9SCU +clock=1 pio_addr=520093696 -pio_latency=1000 +pio_latency=100000 system=system pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268451840 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[21] @@ -736,16 +747,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1 config_latency=20000 ctrl_offset=2 disks=system.cf0 io_shift=1 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=2 pci_dev=7 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.realview system=system config=system.iobus.master[8] @@ -758,8 +768,6 @@ amba_id=1315089 clock=41667 gic=system.realview.gic int_num=55 -max_backoff_delay=10000000 -min_backoff_delay=4000 pio_addr=268566528 pio_latency=10000 system=system @@ -770,17 +778,19 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268632064 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake +clock=1 fake_mem=true pio_addr=1073741824 -pio_latency=1000 +pio_latency=100000 pio_size=536870912 ret_bad_addr=false ret_data16=65535 @@ -794,6 +804,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic +clock=1 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -807,39 +818,43 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268513280 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268517376 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268521472 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 +clock=1 gic=system.realview.gic int_delay=1000000 int_num=52 is_mouse=false pio_addr=268460032 -pio_latency=1000 +pio_latency=100000 system=system vnc=system.vncserver pio=system.iobus.master[5] @@ -847,21 +862,23 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 +clock=1 gic=system.realview.gic int_delay=1000000 int_num=53 is_mouse=true pio_addr=268464128 -pio_latency=1000 +pio_latency=100000 system=system vnc=system.vncserver pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake +clock=1 fake_mem=false pio_addr=520101888 -pio_latency=1000 +pio_latency=100000 pio_size=4095 ret_bad_addr=false ret_data16=65535 @@ -880,23 +897,25 @@ gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 -pio_latency=1000 +pio_latency=100000 system=system pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268455936 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 @@ -907,9 +926,10 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl +clock=1 idreg=0 pio_addr=268435456 -pio_latency=1000 +pio_latency=100000 proc_id0=201326592 proc_id1=201327138 system=system @@ -918,11 +938,12 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 +clock=1 gic=system.realview.gic int_delay=100000 int_num=42 pio_addr=268529664 -pio_latency=1000 +pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[23] @@ -930,73 +951,80 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268492800 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=269357056 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=true pio_addr=268439552 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268488704 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 +clock=1 clock0=1000000 clock1=1000000 gic=system.realview.gic int_num0=36 int_num1=36 pio_addr=268505088 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 +clock=1 clock0=1000000 clock1=1000000 gic=system.realview.gic int_num0=37 int_num1=37 pio_addr=268509184 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[3] [system.realview.uart] type=Pl011 +clock=1 end_on_eot=false gic=system.realview.gic int_delay=100000 int_num=44 pio_addr=268472320 -pio_latency=1000 +pio_latency=100000 platform=system.realview system=system terminal=system.terminal @@ -1005,36 +1033,40 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268476416 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268480512 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268484608 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268500992 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[15] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index 8990e0cd7..3e85e4166 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -4,8 +4,40 @@ warn: Sockets disabled, not accepting gdb connections warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. -panic: Not supported on checker! - @ cycle 197694500 -[getInstPort:build/ARM/cpu/checker/cpu.hh, line 130] -Memory Usage: 355632 KBytes -Program aborted at cycle 197694500 +warn: The ccsidr register isn't implemented and always reads as 0. +warn: instruction 'mcr bpiallis' unimplemented +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr dccimvac' unimplemented +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented +warn: 6471379000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 +warn: 6479236500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 6488789500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 6527432500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 6543641500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 +warn: 7089434000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 +warn: 12809896500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 12854316500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 13169361500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 14424922500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 14474529500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 15519752500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 15669382500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: LCD dual screen mode not supported +warn: 54391557500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: 816692532000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr bpiallis' unimplemented +warn: 2486377425500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 +warn: 2500398254500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2501706856500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 +warn: 2523057678500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2523647855500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2529994034500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2530576345500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 +warn: 2531219324500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2531220454500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 8772dfecb..5011d2336 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:40:00 -gem5 started Jul 27 2012 02:25:32 -gem5 executing on zizzer +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:35:22 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 2537929870500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index e2d527772..30432f4d1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.538087 # Number of seconds simulated -sim_ticks 2538087368500 # Number of ticks simulated -final_tick 2538087368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.537930 # Number of seconds simulated +sim_ticks 2537929870500 # Number of ticks simulated +final_tick 2537929870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75387 # Simulator instruction rate (inst/s) -host_op_rate 96971 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3156986836 # Simulator tick rate (ticks/s) -host_mem_usage 390016 # Number of bytes of host memory used -host_seconds 803.96 # Real time elapsed on the host -sim_insts 60608307 # Number of instructions simulated -sim_ops 77960925 # Number of ops (including micro ops) simulated +host_inst_rate 52642 # Simulator instruction rate (inst/s) +host_op_rate 67714 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2204296601 # Simulator tick rate (ticks/s) +host_mem_usage 387316 # Number of bytes of host memory used +host_seconds 1151.36 # Real time elapsed on the host +sim_insts 60609996 # Number of instructions simulated +sim_ops 77962726 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9092048 # Number of bytes read from this memory -system.physmem.bytes_read::total 131005648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784192 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 4160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9090320 # Number of bytes read from this memory +system.physmem.bytes_read::total 131004112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3779648 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800264 # Number of bytes written to this memory +system.physmem.bytes_written::total 6795720 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12486 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142097 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293461 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59128 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 65 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12484 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142070 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293437 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59057 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813146 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47717242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3582244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51615894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1490962 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2679287 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1490962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47717242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4770569 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54295181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 813075 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47720203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3581785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51618492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314814 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314814 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1188398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2677663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47720203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4770184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54296154 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -61,149 +61,153 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64372 # number of replacements -system.l2c.tagsinuse 51362.522219 # Cycle average of tags in use -system.l2c.total_refs 1967256 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 5868522496 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6378616995 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5274000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166745935000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166751209000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32089389588 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32089389588 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5274000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 198835324588 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40840.036322 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40840.036322 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -332,9 +336,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15052368 # DTB read hits -system.cpu.checker.dtb.read_misses 7317 # DTB read misses -system.cpu.checker.dtb.write_hits 11296020 # DTB write hits +system.cpu.checker.dtb.read_hits 15052897 # DTB read hits +system.cpu.checker.dtb.read_misses 7321 # DTB read misses +system.cpu.checker.dtb.write_hits 11296410 # DTB write hits system.cpu.checker.dtb.write_misses 2195 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -345,13 +349,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 181 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15059685 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11298215 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15060218 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11298605 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26348388 # DTB hits -system.cpu.checker.dtb.misses 9512 # DTB misses -system.cpu.checker.dtb.accesses 26357900 # DTB accesses -system.cpu.checker.itb.inst_hits 61787075 # ITB inst hits +system.cpu.checker.dtb.hits 26349307 # DTB hits +system.cpu.checker.dtb.misses 9516 # DTB misses +system.cpu.checker.dtb.accesses 26358823 # DTB accesses +system.cpu.checker.itb.inst_hits 61788771 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -368,36 +372,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61791546 # ITB inst accesses -system.cpu.checker.itb.hits 61787075 # DTB hits +system.cpu.checker.itb.inst_accesses 61793242 # ITB inst accesses +system.cpu.checker.itb.hits 61788771 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61791546 # DTB accesses -system.cpu.checker.numCycles 78251500 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61793242 # DTB accesses +system.cpu.checker.numCycles 78253308 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51778790 # DTB read hits -system.cpu.dtb.read_misses 81353 # DTB read misses -system.cpu.dtb.write_hits 11881898 # DTB write hits -system.cpu.dtb.write_misses 18166 # DTB write misses +system.cpu.dtb.read_hits 51757171 # DTB read hits +system.cpu.dtb.read_misses 78755 # DTB read misses +system.cpu.dtb.write_hits 11824944 # DTB write hits +system.cpu.dtb.write_misses 17612 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 8033 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3264 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 614 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 7813 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3128 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1261 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51860143 # DTB read accesses -system.cpu.dtb.write_accesses 11900064 # DTB write accesses +system.cpu.dtb.perms_faults 1187 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51835926 # DTB read accesses +system.cpu.dtb.write_accesses 11842556 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63660688 # DTB hits -system.cpu.dtb.misses 99519 # DTB misses -system.cpu.dtb.accesses 63760207 # DTB accesses -system.cpu.itb.inst_hits 13142674 # ITB inst hits -system.cpu.itb.inst_misses 12012 # ITB inst misses +system.cpu.dtb.hits 63582115 # DTB hits +system.cpu.dtb.misses 96367 # DTB misses +system.cpu.dtb.accesses 63678482 # DTB accesses +system.cpu.itb.inst_hits 13115769 # ITB inst hits +system.cpu.itb.inst_misses 12252 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -406,538 +410,538 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5318 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5204 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3477 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3277 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13154686 # ITB inst accesses -system.cpu.itb.hits 13142674 # DTB hits -system.cpu.itb.misses 12012 # DTB misses -system.cpu.itb.accesses 13154686 # DTB accesses -system.cpu.numCycles 487300785 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13128021 # ITB inst accesses +system.cpu.itb.hits 13115769 # DTB hits +system.cpu.itb.misses 12252 # DTB misses +system.cpu.itb.accesses 13128021 # DTB accesses +system.cpu.numCycles 487049956 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15530766 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12471723 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 754243 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10651914 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8369263 # Number of BTB hits +system.cpu.BPredUnit.lookups 15265836 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12253522 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 790029 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10231069 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8383104 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1449848 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 80901 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33379389 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101786531 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15530766 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9819111 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22320239 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6081203 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 158853 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 102204493 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2684 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133854 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208007 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 300 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13138430 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1021608 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6374 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 162590502 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.771886 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.134900 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1454061 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 83540 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33339940 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 101517104 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15265836 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9837165 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22278409 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6025504 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 157129 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 102031349 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2877 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 112878 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 209522 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13111736 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1022555 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6694 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 162271988 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.770946 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.133351 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140287148 86.28% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1367954 0.84% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1761574 1.08% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2654240 1.63% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2359914 1.45% 91.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1143060 0.70% 91.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2915951 1.79% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 808451 0.50% 94.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9292210 5.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140010343 86.28% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1387058 0.85% 87.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1759256 1.08% 88.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2673832 1.65% 89.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2324399 1.43% 91.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1142133 0.70% 92.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2914571 1.80% 93.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 802946 0.49% 94.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9257450 5.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 162590502 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031871 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.208878 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35559403 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101873570 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20035841 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1111053 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4010635 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2099297 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 175058 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118316110 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572190 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4010635 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37673170 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40477243 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 54791602 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18894911 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6742941 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110777712 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22948 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1162010 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4487085 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 30869 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115617141 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 507045226 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 506952458 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 92768 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78747095 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36870045 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898908 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797965 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13562847 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21065168 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13875966 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1948101 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2609238 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101350555 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2059934 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126492219 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 199079 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24669987 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65519424 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514717 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 162590502 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.777980 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.488111 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 162271988 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031343 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.208433 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35519413 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 101672639 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20003488 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1109197 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3967251 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2027366 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 175080 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118004769 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 577706 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3967251 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37625250 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40424922 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 54666118 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18858904 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6729543 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110552041 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22802 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1145502 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4490712 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 31851 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115544038 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 506134218 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 506042308 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91910 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78748778 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36795259 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 893517 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 798182 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13541663 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21062832 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13840935 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1956455 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2555240 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101213239 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2059558 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126297159 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 200424 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24661368 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65776088 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 514288 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 162271988 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.778305 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.488656 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 116448984 71.62% 71.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14892562 9.16% 80.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7379275 4.54% 85.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6334493 3.90% 89.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12627372 7.77% 96.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2807487 1.73% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1536769 0.95% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 438389 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125171 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 116217920 71.62% 71.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14878353 9.17% 80.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7338383 4.52% 85.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6288492 3.88% 89.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12644772 7.79% 96.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2813043 1.73% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1525517 0.94% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 444905 0.27% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 120603 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 162590502 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 162271988 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53974 0.61% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8371302 94.73% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 411522 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53198 0.60% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8363826 94.73% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412000 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60100206 47.51% 47.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95387 0.08% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 12 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53417810 42.23% 90.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12512990 9.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59965938 47.48% 47.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95633 0.08% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53400637 42.28% 90.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12469145 9.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126492219 # Type of FU issued -system.cpu.iq.rate 0.259577 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8836801 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.069860 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 424687081 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128101552 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87467188 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22890 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12894 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10336 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134953294 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12060 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 646395 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126297159 # Type of FU issued +system.cpu.iq.rate 0.259310 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8829028 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.069907 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 423968404 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 127951101 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87290001 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23313 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12742 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10305 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134750106 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12415 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 633498 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5345399 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11042 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35020 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2075549 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5342526 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8187 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30812 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2040125 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107217 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1052457 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107208 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1052465 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4010635 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30068216 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540743 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103665600 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 220216 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21065168 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13875966 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1468298 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 126232 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 40886 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35020 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 376820 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332740 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 709560 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123288257 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52469499 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3203962 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3967251 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30033054 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 539777 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103499292 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 223830 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21062832 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13840935 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1467584 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 130279 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 41269 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30812 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 412836 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 293063 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 705899 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123087993 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52445768 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3209166 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 255111 # number of nop insts executed -system.cpu.iew.exec_refs 64862578 # number of memory reference insts executed -system.cpu.iew.exec_branches 11930392 # Number of branches executed -system.cpu.iew.exec_stores 12393079 # Number of stores executed -system.cpu.iew.exec_rate 0.253002 # Inst execution rate -system.cpu.iew.wb_sent 121911839 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87477524 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47523827 # num instructions producing a value -system.cpu.iew.wb_consumers 86459839 # num instructions consuming a value +system.cpu.iew.exec_nop 226495 # number of nop insts executed +system.cpu.iew.exec_refs 64783153 # number of memory reference insts executed +system.cpu.iew.exec_branches 11753944 # Number of branches executed +system.cpu.iew.exec_stores 12337385 # Number of stores executed +system.cpu.iew.exec_rate 0.252721 # Inst execution rate +system.cpu.iew.wb_sent 121723565 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87300306 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47490892 # num instructions producing a value +system.cpu.iew.wb_consumers 86410198 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179514 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549664 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179243 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549598 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24732278 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1545217 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 625816 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158662310 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.492312 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459485 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24569978 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1545270 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 617808 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158387180 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.493178 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.461668 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 130458831 82.22% 82.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13994447 8.82% 91.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3942201 2.48% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2235545 1.41% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2018631 1.27% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1062301 0.67% 96.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1402549 0.88% 97.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 657941 0.41% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2889864 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 130224510 82.22% 82.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13962931 8.82% 91.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3932666 2.48% 93.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2224869 1.40% 94.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2020992 1.28% 96.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1058227 0.67% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1402359 0.89% 97.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 664028 0.42% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2896598 1.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158662310 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60758688 # Number of instructions committed -system.cpu.commit.committedOps 78111306 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 158387180 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60760377 # Number of instructions committed +system.cpu.commit.committedOps 78113107 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27520186 # Number of memory references committed -system.cpu.commit.loads 15719769 # Number of loads committed -system.cpu.commit.membars 413359 # Number of memory barriers committed -system.cpu.commit.branches 10163898 # Number of branches committed +system.cpu.commit.refs 27521116 # Number of memory references committed +system.cpu.commit.loads 15720306 # Number of loads committed +system.cpu.commit.membars 413361 # Number of memory barriers committed +system.cpu.commit.branches 10025135 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69148075 # Number of committed integer instructions. -system.cpu.commit.function_calls 996262 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2889864 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69149691 # Number of committed integer instructions. +system.cpu.commit.function_calls 996276 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2896598 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 256700614 # The number of ROB reads -system.cpu.rob.rob_writes 209796185 # The number of ROB writes -system.cpu.timesIdled 1906230 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 324710283 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4588785915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60608307 # Number of Instructions Simulated -system.cpu.committedOps 77960925 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60608307 # Number of Instructions Simulated -system.cpu.cpi 8.040165 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.040165 # CPI: Total CPI of All Threads -system.cpu.ipc 0.124376 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.124376 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 558050325 # number of integer regfile reads -system.cpu.int_regfile_writes 90161621 # number of integer regfile writes -system.cpu.fp_regfile_reads 8290 # number of floating regfile reads -system.cpu.fp_regfile_writes 2914 # number of floating regfile writes -system.cpu.misc_regfile_reads 134103665 # number of misc regfile reads -system.cpu.misc_regfile_writes 913390 # number of misc regfile writes -system.cpu.icache.replacements 991554 # number of replacements -system.cpu.icache.tagsinuse 511.576119 # Cycle average of tags in use -system.cpu.icache.total_refs 12061582 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 992066 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.158044 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 7225354000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.576119 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999172 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999172 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12061582 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12061582 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12061582 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12061582 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12061582 # number of overall hits -system.cpu.icache.overall_hits::total 12061582 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1076715 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1076715 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1076715 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1076715 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1076715 # number of overall misses -system.cpu.icache.overall_misses::total 1076715 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16664677991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16664677991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16664677991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16664677991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16664677991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16664677991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13138297 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13138297 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13138297 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13138297 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13138297 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13138297 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081952 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081952 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081952 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081952 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081952 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081952 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15477.334291 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15477.334291 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15477.334291 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15477.334291 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2769993 # number of cycles access was blocked +system.cpu.rob.rob_reads 256258159 # The number of ROB reads +system.cpu.rob.rob_writes 209428063 # The number of ROB writes +system.cpu.timesIdled 1906854 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 324777968 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4588721746 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60609996 # Number of Instructions Simulated +system.cpu.committedOps 77962726 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60609996 # Number of Instructions Simulated +system.cpu.cpi 8.035802 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.035802 # CPI: Total CPI of All Threads +system.cpu.ipc 0.124443 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.124443 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 557221655 # number of integer regfile reads +system.cpu.int_regfile_writes 90065137 # number of integer regfile writes +system.cpu.fp_regfile_reads 8220 # number of floating regfile reads +system.cpu.fp_regfile_writes 2852 # number of floating regfile writes +system.cpu.misc_regfile_reads 133714329 # number of misc regfile reads +system.cpu.misc_regfile_writes 913466 # number of misc regfile writes +system.cpu.icache.replacements 990831 # number of replacements +system.cpu.icache.tagsinuse 511.552497 # Cycle average of tags in use +system.cpu.icache.total_refs 12036161 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 991343 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.141268 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 7225774000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.552497 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999126 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999126 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12036161 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12036161 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12036161 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12036161 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12036161 # number of overall hits +system.cpu.icache.overall_hits::total 12036161 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1075440 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1075440 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1075440 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1075440 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1075440 # number of overall misses +system.cpu.icache.overall_misses::total 1075440 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16637783989 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16637783989 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16637783989 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16637783989 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16637783989 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16637783989 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13111601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13111601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13111601 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13111601 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13111601 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13111601 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082022 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082022 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082022 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082022 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082022 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082022 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15470.676178 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15470.676178 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15470.676178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15470.676178 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2693492 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 446 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 350 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6210.746637 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7695.691429 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84611 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84611 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84611 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84611 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84611 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84611 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 992104 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 992104 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 992104 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 992104 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 992104 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 992104 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12645073993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12645073993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12645073993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12645073993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12645073993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12645073993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8007500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8007500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8007500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 8007500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075512 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075512 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075512 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.714152 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.714152 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7938500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7938500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7938500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 7938500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075612 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075612 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075612 # 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Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 50910000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991460 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13908098 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13908098 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258651 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258651 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 283641 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 283641 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285792 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285792 # 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number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4513.093414 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 26063.604240 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13899785 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13899785 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7254429 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7254429 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 285860 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 285860 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285827 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285827 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21154214 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21154214 # 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miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.151102 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.151102 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.151102 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.151102 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19441.350363 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19441.350363 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43224.019859 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43224.019859 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16222.587479 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16222.587479 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 24192.307692 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 24192.307692 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38379.328311 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38379.328311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38379.328311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38379.328311 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 34382405 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7145000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7505 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4581.266489 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 25070.175439 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 608347 # number of writebacks -system.cpu.dcache.writebacks::total 608347 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379574 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 379574 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2744878 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2744878 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1442 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1442 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3124452 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3124452 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3124452 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3124452 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386136 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 386136 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248907 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248907 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12371 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12371 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 635043 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 635043 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 635043 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 635043 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6270140101 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6270140101 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9248914453 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9248914453 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164305000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164305000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 305000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 305000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15519054554 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15519054554 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15519054554 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15519054554 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182411169000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182411169000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41923418941 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41923418941 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224334587941 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 224334587941 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026315 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026315 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041590 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041590 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025477 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025477 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16238.165053 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16238.165053 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37158.113082 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37158.113082 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13281.464716 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13281.464716 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19062.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19062.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 609524 # number of writebacks +system.cpu.dcache.writebacks::total 609524 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379381 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 379381 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2749244 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2749244 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1475 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1475 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3128625 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3128625 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3128625 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3128625 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387657 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 387657 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249120 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249120 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12214 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12214 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 636777 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636777 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636777 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636777 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6303506404 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6303506404 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9254265450 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9254265450 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 162323500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 162323500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15557771854 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15557771854 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15557771854 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15557771854 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182409475000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182409475000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41932970674 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41932970674 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224342445674 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224342445674 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024298 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024298 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040775 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040775 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000045 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025553 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025553 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16260.525165 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16260.525165 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37147.822134 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37147.822134 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13289.954151 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13289.954151 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20884.615385 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 20884.615385 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -959,16 +963,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323585371203 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323585371203 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1323990187654 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1323990187654 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88038 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88040 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |