diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | 1326 |
1 files changed, 736 insertions, 590 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index d8f37781a..6605c6d1b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.582494 # Nu sim_ticks 2582494330500 # Number of ticks simulated final_tick 2582494330500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58235 # Simulator instruction rate (inst/s) -host_tick_rate 1883208568 # Simulator tick rate (ticks/s) -host_mem_usage 413296 # Number of bytes of host memory used -host_seconds 1371.33 # Real time elapsed on the host -sim_insts 79859495 # Number of instructions simulated +host_inst_rate 80373 # Simulator instruction rate (inst/s) +host_op_rate 103823 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3357432165 # Simulator tick rate (ticks/s) +host_mem_usage 383300 # Number of bytes of host memory used +host_seconds 769.19 # Real time elapsed on the host +sim_insts 61822124 # Number of instructions simulated +sim_ops 79859495 # Number of ops (including micro ops) simulated system.nvmem.bytes_read 384 # Number of bytes read from this memory system.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -34,127 +36,233 @@ system.l2c.total_refs 1820044 # To system.l2c.sampled_refs 162190 # Sample count of references to valid blocks. system.l2c.avg_refs 11.221678 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 4997.961622 # Average occupied blocks per context -system.l2c.occ_blocks::1 7175.690427 # Average occupied blocks per context -system.l2c.occ_blocks::2 15403.191755 # Average occupied blocks per context -system.l2c.occ_percent::0 0.076263 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.109492 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.235034 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 739066 # number of ReadReq hits -system.l2c.ReadReq_hits::1 627724 # number of ReadReq hits -system.l2c.ReadReq_hits::2 184257 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 15356.692298 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 22.670587 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 1.636552 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3410.170856 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 1587.790766 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 18.616033 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 3.576285 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2636.430831 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4539.259596 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.234325 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000346 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000025 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.052035 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.024228 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000284 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000055 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.040229 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.069264 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.420789 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 89183 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 17213 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 526448 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 212618 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 73946 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3915 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 477126 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 150598 # number of ReadReq hits system.l2c.ReadReq_hits::total 1551047 # number of ReadReq hits -system.l2c.Writeback_hits::0 599046 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 599046 # number of Writeback hits system.l2c.Writeback_hits::total 599046 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 992 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 1000 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu0.data 992 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1000 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 1992 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 175 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 443 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 175 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 443 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 618 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 58603 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 38925 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 58603 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 38925 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 97528 # number of ReadExReq hits -system.l2c.demand_hits::0 797669 # number of demand (read+write) hits -system.l2c.demand_hits::1 666649 # number of demand (read+write) hits -system.l2c.demand_hits::2 184257 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.dtb.walker 89183 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 17213 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 526448 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 271221 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 73946 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3915 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 477126 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 189523 # number of demand (read+write) hits system.l2c.demand_hits::total 1648575 # number of demand (read+write) hits -system.l2c.overall_hits::0 797669 # number of overall hits -system.l2c.overall_hits::1 666649 # number of overall hits -system.l2c.overall_hits::2 184257 # number of overall hits +system.l2c.overall_hits::cpu0.dtb.walker 89183 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 17213 # number of overall hits +system.l2c.overall_hits::cpu0.inst 526448 # number of overall hits +system.l2c.overall_hits::cpu0.data 271221 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 73946 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3915 # number of overall hits +system.l2c.overall_hits::cpu1.inst 477126 # number of overall hits +system.l2c.overall_hits::cpu1.data 189523 # number of overall hits system.l2c.overall_hits::total 1648575 # number of overall hits -system.l2c.ReadReq_misses::0 19787 # number of ReadReq misses -system.l2c.ReadReq_misses::1 20563 # number of ReadReq misses -system.l2c.ReadReq_misses::2 170 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.dtb.walker 70 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 10 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 10849 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 8938 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 78 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 12 # 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number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5139681999 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 2639420000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7779101999 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 3650500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 521000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 567333500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 5606089999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 4067500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 625000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 392575500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3321348000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9896210999 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 3650500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 521000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 567333500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 5606089999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 4067500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 625000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 392575500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3321348000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9896210999 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 89253 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 17223 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 537297 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 221556 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 74024 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 3927 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 484630 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 163657 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1591567 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 599046 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 599046 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 599046 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 8343 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 4816 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 8343 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4816 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 13159 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 1024 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 891 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1024 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 891 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1915 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 156488 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 89319 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 156488 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 89319 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 245807 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 915341 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 737606 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 184427 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.dtb.walker 89253 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 17223 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 537297 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 378044 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 74024 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 3927 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 484630 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 252976 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1837374 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 915341 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 737606 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 184427 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 89253 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 17223 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 537297 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 378044 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 74024 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 3927 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 484630 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 252976 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1837374 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.026075 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.031719 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.000922 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.058716 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.881098 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.792359 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.829102 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.502806 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.625511 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.564202 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.128555 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.096199 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.000922 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.225676 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.128555 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.096199 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.000922 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.225676 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 106994.946177 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 102957.204688 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 12453582.352941 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 12663534.503806 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 8207.046660 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 15809.748428 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 9038.280330 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 17128.348214 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 79471.849609 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 154365.638747 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 84099.964299 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 139467.719873 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 58213005.876471 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 58436573.560642 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 84099.964299 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 139467.719873 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 58213005.876471 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 58436573.560642 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000784 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000581 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.020192 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.040342 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001054 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.003056 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.015484 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.079795 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.881098 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.792359 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.829102 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.502806 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.625511 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.564202 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000784 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000581 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.020192 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.282568 # 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miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52150 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52100 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52293.621532 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52182.591184 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52147.435897 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52083.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52315.498401 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52219.006049 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3746.361039 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 8592.898323 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2087.161366 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 13172.991071 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52507.350452 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52375.679644 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52150 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52100 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52293.621532 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52480.177481 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52147.435897 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52083.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52315.498401 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52343.435299 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52150 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52100 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52293.621532 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52480.177481 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52147.435897 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52083.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52315.498401 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52343.435299 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -163,61 +271,178 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 480000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 300775500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2539911500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 7561204499 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4981000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 124405850500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1891000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 7552193500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131964916000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 881564880 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31653443800 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32535008680 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4981000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 125287415380 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1891000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 39205637300 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164499924680 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000784 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000581 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.020177 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.040152 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001054 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.003056 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015463 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.079569 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.881098 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.792359 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.829102 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.502806 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.625511 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564202 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000784 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000581 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.020177 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.282457 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001054 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.003056 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015463 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.250680 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000784 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000581 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.020177 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.282457 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001054 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.003056 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015463 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.250680 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40021.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40100 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40078.452172 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40053.394784 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40012.820513 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40135.508407 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40046.075872 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.859883 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40016.640461 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.446408 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40075.892857 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40076.707350 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40053.012263 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40021.428571 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40100 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40078.452172 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40074.765164 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40012.820513 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40135.508407 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40051.587927 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40021.428571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40100 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40078.452172 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40074.765164 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40012.820513 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40135.508407 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40051.587927 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -471,9 +696,9 @@ system.cpu0.iew.iewDispNonSpecInsts 864933 # Nu system.cpu0.iew.iewIQFullEvents 62296 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 5639 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 20483 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 506934 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 506933 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 135852 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 642786 # Number of branch mispredicts detected at execute +system.cpu0.iew.branchMispredicts 642785 # Number of branch mispredicts detected at execute system.cpu0.iew.iewExecutedInsts 79552569 # Number of executed instructions system.cpu0.iew.iewExecLoadInsts 42849690 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 723060 # Number of squashed instructions skipped in execute @@ -491,7 +716,8 @@ system.cpu0.iew.wb_penalized 0 # nu system.cpu0.iew.wb_rate 0.132406 # insts written-back per cycle system.cpu0.iew.wb_fanout 0.537861 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 41923639 # The number of committed instructions +system.cpu0.commit.commitCommittedInsts 31935522 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 41923639 # The number of committed instructions system.cpu0.commit.commitSquashedInsts 10377261 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 1044424 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 567428 # The number of times a branch was mispredicted @@ -512,7 +738,8 @@ system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100 system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::total 108046246 # Number of insts commited each cycle -system.cpu0.commit.count 41923639 # Number of instructions committed +system.cpu0.commit.committedInsts 31935522 # Number of instructions committed +system.cpu0.commit.committedOps 41923639 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed system.cpu0.commit.refs 15936098 # Number of memory references committed system.cpu0.commit.loads 9243307 # Number of loads committed @@ -528,12 +755,13 @@ system.cpu0.rob.rob_writes 106372981 # Th system.cpu0.timesIdled 1454145 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.idleCycles 242719810 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.quiesceCycles 4812449027 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 41797812 # Number of Instructions Simulated -system.cpu0.committedInsts_total 41797812 # Number of Instructions Simulated -system.cpu0.cpi 8.433071 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.433071 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.118581 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.118581 # IPC: Total IPC of All Threads +system.cpu0.committedInsts 31809695 # Number of Instructions Simulated +system.cpu0.committedOps 41797812 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 31809695 # Number of Instructions Simulated +system.cpu0.cpi 11.081021 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 11.081021 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.090244 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.090244 # IPC: Total IPC of All Threads system.cpu0.int_regfile_reads 354190813 # number of integer regfile reads system.cpu0.int_regfile_writes 46128461 # number of integer regfile writes system.cpu0.fp_regfile_reads 3999 # number of floating regfile reads @@ -546,51 +774,39 @@ system.cpu0.icache.total_refs 5838964 # To system.cpu0.icache.sampled_refs 539299 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 10.826951 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 16020224000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 511.612990 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.999244 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 5838964 # number of ReadReq hits +system.cpu0.icache.occ_blocks::cpu0.inst 511.612990 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999244 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999244 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5838964 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 5838964 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 5838964 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu0.inst 5838964 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 5838964 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 5838964 # number of overall hits -system.cpu0.icache.overall_hits::1 0 # number of overall hits +system.cpu0.icache.overall_hits::cpu0.inst 5838964 # number of overall hits system.cpu0.icache.overall_hits::total 5838964 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 583385 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu0.inst 583385 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 583385 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 583385 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu0.inst 583385 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 583385 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 583385 # number of overall misses -system.cpu0.icache.overall_misses::1 0 # number of overall misses +system.cpu0.icache.overall_misses::cpu0.inst 583385 # number of overall misses system.cpu0.icache.overall_misses::total 583385 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 8740145988 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 8740145988 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 8740145988 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 6422349 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8740145988 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 8740145988 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 8740145988 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 8740145988 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 8740145988 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 8740145988 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6422349 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 6422349 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 6422349 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu0.inst 6422349 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 6422349 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 6422349 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6422349 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 6422349 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.090837 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.090837 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.090837 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14981.780450 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14981.780450 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14981.780450 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.090837 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.090837 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.090837 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14981.780450 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14981.780450 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14981.780450 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 1633991 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 240 # number of cycles access was blocked @@ -599,122 +815,108 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs 6808.295833 system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 29665 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 44065 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 44065 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 44065 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 539320 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 539320 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 539320 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 6552239991 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 6552239991 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 6552239991 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency 6685500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency 6685500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.083976 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.083976 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0.083976 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12149.076598 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12149.076598 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12149.076598 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.writebacks::writebacks 29665 # number of writebacks +system.cpu0.icache.writebacks::total 29665 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44065 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 44065 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 44065 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 44065 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 44065 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 44065 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 539320 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 539320 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 539320 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 539320 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 539320 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 539320 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6552239991 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6552239991 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6552239991 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6552239991 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6552239991 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6552239991 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6685500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 6685500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 6685500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 6685500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.083976 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.083976 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.083976 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12149.076598 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12149.076598 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12149.076598 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 372182 # number of replacements -system.cpu0.dcache.tagsinuse 487.975562 # Cycle average of tags in use +system.cpu0.dcache.tagsinuse 487.992960 # Cycle average of tags in use system.cpu0.dcache.total_refs 12779920 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 372694 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 34.290651 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 49147000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 487.992960 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -0.017397 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.953111 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::1 -0.000034 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 7966835 # number of ReadReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 487.992960 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.953111 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.953111 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7966835 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 7966835 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 4346487 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4346487 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 4346487 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 221211 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 221211 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 221211 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 199868 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 199868 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 199868 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 12313322 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 12313322 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 12313322 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 12313322 # number of overall hits -system.cpu0.dcache.overall_hits::1 0 # number of overall hits +system.cpu0.dcache.overall_hits::cpu0.data 12313322 # number of overall hits system.cpu0.dcache.overall_hits::total 12313322 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 463412 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu0.data 463412 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 463412 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 1864293 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1864293 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 1864293 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 10042 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10042 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 10042 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 7686 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7686 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 7686 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 2327705 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu0.data 2327705 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 2327705 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 2327705 # number of overall misses -system.cpu0.dcache.overall_misses::1 0 # number of overall misses +system.cpu0.dcache.overall_misses::cpu0.data 2327705 # number of overall misses system.cpu0.dcache.overall_misses::total 2327705 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 6478995500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 70420524827 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency 122158000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency 87202500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency 76899520327 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 76899520327 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 8430247 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6478995500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6478995500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 70420524827 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 70420524827 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 122158000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 122158000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 87202500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 87202500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 76899520327 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 76899520327 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 76899520327 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 76899520327 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8430247 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8430247 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 6210780 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6210780 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 6210780 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 231253 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 231253 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 231253 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 207554 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 207554 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 207554 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 14641027 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 14641027 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 14641027 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 14641027 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14641027 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14641027 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.054970 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.300171 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.043424 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.037031 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.158985 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.158985 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 13981.069761 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 37773.313973 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12164.708225 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11345.628415 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 33036.626345 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 33036.626345 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.054970 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.300171 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.043424 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037031 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.158985 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.158985 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13981.069761 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37773.313973 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12164.708225 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11345.628415 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33036.626345 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33036.626345 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 6780486 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 1857500 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 854 # number of cycles access was blocked @@ -723,59 +925,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7939.679157 system.cpu0.dcache.avg_blocked_cycles::no_targets 14511.718750 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 327766 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 223882 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 1685987 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits 318 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 1909869 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 1909869 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 239530 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 178306 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 9724 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 7685 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 417836 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 417836 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 2943060000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 6370530485 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 87975000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 64109000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 9313590485 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 9313590485 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 138958680000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1038766498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 139997446498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028413 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.028709 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.042049 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.037027 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.028539 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.028539 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12286.811673 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35728.076930 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9047.202797 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 8342.094990 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 22290.062333 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 22290.062333 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.writebacks::writebacks 327766 # number of writebacks +system.cpu0.dcache.writebacks::total 327766 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 223882 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 223882 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1685987 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1685987 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 318 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 318 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1909869 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1909869 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1909869 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1909869 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 239530 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 239530 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 178306 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 178306 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9724 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9724 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7685 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7685 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 417836 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 417836 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 417836 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 417836 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2943060000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2943060000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6370530485 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6370530485 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 87975000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 87975000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 64109000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 64109000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9313590485 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9313590485 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9313590485 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9313590485 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 138958680000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 138958680000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1038766498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1038766498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 139997446498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 139997446498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028413 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028709 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.042049 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028539 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028539 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12286.811673 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35728.076930 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9047.202797 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8342.094990 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22290.062333 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22290.062333 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses @@ -1043,7 +1252,8 @@ system.cpu1.iew.wb_penalized 0 # nu system.cpu1.iew.wb_rate 0.640894 # insts written-back per cycle system.cpu1.iew.wb_fanout 0.545985 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 38086237 # The number of committed instructions +system.cpu1.commit.commitCommittedInsts 30036983 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 38086237 # The number of committed instructions system.cpu1.commit.commitSquashedInsts 18573771 # The number of squashed insts skipped by commit system.cpu1.commit.commitNonSpecStalls 519501 # The number of times commit has been forced to stall to communicate backwards system.cpu1.commit.branchMispredicts 450480 # The number of times a branch was mispredicted @@ -1064,7 +1274,8 @@ system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100 system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::total 47701192 # Number of insts commited each cycle -system.cpu1.commit.count 38086237 # Number of instructions committed +system.cpu1.commit.committedInsts 30036983 # Number of instructions committed +system.cpu1.commit.committedOps 38086237 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed system.cpu1.commit.refs 12651383 # Number of memory references committed system.cpu1.commit.loads 7112761 # Number of loads committed @@ -1080,12 +1291,13 @@ system.cpu1.rob.rob_writes 116493771 # Th system.cpu1.timesIdled 450197 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.idleCycles 18365285 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.quiesceCycles 5095139417 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38061683 # Number of Instructions Simulated -system.cpu1.committedInsts_total 38061683 # Number of Instructions Simulated -system.cpu1.cpi 1.814944 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.814944 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.550981 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.550981 # IPC: Total IPC of All Threads +system.cpu1.committedInsts 30012429 # Number of Instructions Simulated +system.cpu1.committedOps 38061683 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 30012429 # Number of Instructions Simulated +system.cpu1.cpi 2.301707 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.301707 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.434460 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.434460 # IPC: Total IPC of All Threads system.cpu1.int_regfile_reads 222861231 # number of integer regfile reads system.cpu1.int_regfile_writes 47167724 # number of integer regfile writes system.cpu1.fp_regfile_reads 4217 # number of floating regfile reads @@ -1098,51 +1310,39 @@ system.cpu1.icache.total_refs 7684975 # To system.cpu1.icache.sampled_refs 486098 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 15.809518 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 74234723000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 498.788681 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.974197 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 7684975 # number of ReadReq hits +system.cpu1.icache.occ_blocks::cpu1.inst 498.788681 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974197 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974197 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7684975 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 7684975 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 7684975 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::cpu1.inst 7684975 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 7684975 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 7684975 # number of overall hits -system.cpu1.icache.overall_hits::1 0 # number of overall hits +system.cpu1.icache.overall_hits::cpu1.inst 7684975 # number of overall hits system.cpu1.icache.overall_hits::total 7684975 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 527035 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::cpu1.inst 527035 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 527035 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 527035 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::cpu1.inst 527035 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 527035 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 527035 # number of overall misses -system.cpu1.icache.overall_misses::1 0 # number of overall misses +system.cpu1.icache.overall_misses::cpu1.inst 527035 # number of overall misses system.cpu1.icache.overall_misses::total 527035 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 7752735997 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 7752735997 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 7752735997 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 8212010 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7752735997 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7752735997 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7752735997 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7752735997 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7752735997 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7752735997 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8212010 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 8212010 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 8212010 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::cpu1.inst 8212010 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 8212010 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 8212010 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8212010 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 8212010 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.064179 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.064179 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.064179 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 14710.097047 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 14710.097047 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 14710.097047 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.064179 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.064179 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.064179 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14710.097047 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14710.097047 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14710.097047 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 1321997 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 170 # number of cycles access was blocked @@ -1151,35 +1351,38 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs 7776.452941 system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 18538 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 40914 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 40914 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 40914 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 486121 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 486121 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 486121 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 5799471497 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 5799471497 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 5799471497 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency 2517500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency 2517500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.059196 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.059196 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.059196 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11930.098673 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11930.098673 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11930.098673 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.writebacks::writebacks 18538 # number of writebacks +system.cpu1.icache.writebacks::total 18538 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 40914 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 40914 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 40914 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 40914 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 40914 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 40914 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 486121 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 486121 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 486121 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 486121 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 486121 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 486121 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5799471497 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5799471497 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5799471497 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5799471497 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5799471497 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5799471497 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2517500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2517500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2517500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 2517500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.059196 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.059196 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.059196 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11930.098673 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11930.098673 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11930.098673 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 272200 # number of replacements system.cpu1.dcache.tagsinuse 447.953212 # Cycle average of tags in use @@ -1187,84 +1390,69 @@ system.cpu1.dcache.total_refs 10416163 # To system.cpu1.dcache.sampled_refs 272587 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 38.212252 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 66688833000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 447.953212 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.874909 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 7085363 # number of ReadReq hits +system.cpu1.dcache.occ_blocks::cpu1.data 447.953212 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.874909 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.874909 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 7085363 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 7085363 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 3139669 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3139669 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 3139669 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 75360 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 75360 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 75360 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 72622 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72622 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 72622 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 10225032 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::cpu1.data 10225032 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 10225032 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 10225032 # number of overall hits -system.cpu1.dcache.overall_hits::1 0 # number of overall hits +system.cpu1.dcache.overall_hits::cpu1.data 10225032 # number of overall hits system.cpu1.dcache.overall_hits::total 10225032 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 323287 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::cpu1.data 323287 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 323287 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 1273508 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1273508 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 1273508 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 12669 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 12669 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 12669 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 11046 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 11046 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 11046 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 1596795 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::cpu1.data 1596795 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 1596795 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 1596795 # number of overall misses -system.cpu1.dcache.overall_misses::1 0 # number of overall misses +system.cpu1.dcache.overall_misses::cpu1.data 1596795 # number of overall misses system.cpu1.dcache.overall_misses::total 1596795 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 5044696500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 46343696337 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency 148164500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency 87512500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency 51388392837 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 51388392837 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 7408650 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5044696500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5044696500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 46343696337 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 46343696337 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 148164500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 148164500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87512500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 87512500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 51388392837 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 51388392837 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 51388392837 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 51388392837 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7408650 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 7408650 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 4413177 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4413177 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 4413177 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 88029 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 88029 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 88029 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 83668 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83668 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 83668 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 11821827 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 11821827 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 11821827 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 11821827 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 11821827 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 11821827 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.043636 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.288569 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.143918 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.132022 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.135072 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.135072 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15604.390217 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 36390.581243 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11695.043018 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 7922.551150 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 32182.210514 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 32182.210514 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.043636 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.288569 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.143918 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.132022 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135072 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135072 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15604.390217 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36390.581243 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11695.043018 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7922.551150 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32182.210514 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32182.210514 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 13033547 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 5494000 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 3077 # number of cycles access was blocked @@ -1273,57 +1461,63 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4235.796880 system.cpu1.dcache.avg_blocked_cycles::no_targets 32898.203593 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 223077 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 133946 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 1157260 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits 1008 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 1291206 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 1291206 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 189341 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 116248 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 11661 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 11046 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 305589 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 305589 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 2489937000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 3452864547 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 99179500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 54297000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 5942801547 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 5942801547 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 8455613500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 41497603581 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 49953217081 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.025557 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.026341 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.132468 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.132022 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.025850 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.025850 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13150.543200 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29702.571631 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8505.231112 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 4915.535035 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 19447.040132 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 19447.040132 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.writebacks::writebacks 223077 # number of writebacks +system.cpu1.dcache.writebacks::total 223077 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 133946 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 133946 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1157260 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1157260 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1008 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1008 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1291206 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1291206 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1291206 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1291206 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 189341 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 189341 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 116248 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 116248 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11661 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11661 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 11046 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 11046 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 305589 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 305589 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 305589 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 305589 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2489937000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2489937000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3452864547 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3452864547 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 99179500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 99179500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 54297000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 54297000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5942801547 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5942801547 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5942801547 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5942801547 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 8455613500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 8455613500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41497603581 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41497603581 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 49953217081 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 49953217081 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025557 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026341 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.132468 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.132022 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.025850 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.025850 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13150.543200 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29702.571631 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8505.231112 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4915.535035 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19447.040132 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19447.040132 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -1331,38 +1525,6 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.avg_refs no_value # Average number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 0 # number of demand (read+write) misses -system.iocache.demand_misses::total 0 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 0 # number of overall misses -system.iocache.overall_misses::total 0 # number of overall misses -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1371,28 +1533,12 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 0 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1308174844926 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1308174844926 # number of overall MSHR uncacheable cycles -system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308174844926 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1308174844926 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308174844926 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1308174844926 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 55723 # number of quiesce instructions executed |