diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | 2810 |
1 files changed, 1402 insertions, 1408 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index ba015b214..977ccc85a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,16 +1,71 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.581528 # Number of seconds simulated -sim_ticks 2581527583500 # Number of ticks simulated -final_tick 2581527583500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.582310 # Number of seconds simulated +sim_ticks 2582310281500 # Number of ticks simulated +final_tick 2582310281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89313 # Simulator instruction rate (inst/s) -host_op_rate 115365 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3717496726 # Simulator tick rate (ticks/s) -host_mem_usage 390980 # Number of bytes of host memory used -host_seconds 694.43 # Real time elapsed on the host -sim_insts 62021206 # Number of instructions simulated -sim_ops 80112751 # Number of ops (including micro ops) simulated +host_inst_rate 62666 # Simulator instruction rate (inst/s) +host_op_rate 80652 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2566586582 # Simulator tick rate (ticks/s) +host_mem_usage 395816 # Number of bytes of host memory used +host_seconds 1006.13 # Real time elapsed on the host +sim_insts 63050246 # Number of instructions simulated +sim_ops 81146063 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 396544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4372212 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 425600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5220016 # Number of bytes read from this memory +system.physmem.bytes_read::total 129953444 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 396544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 425600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 822144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4241024 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7270160 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6196 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68388 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6650 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81589 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15105053 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66266 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 823550 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46290976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 153562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1693140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 273 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 164814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2021452 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50324488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 153562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 164814 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318375 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1642337 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6583 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1166450 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2815370 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1642337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46290976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 153562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1699723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 164814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3187902 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53139859 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory @@ -29,292 +84,237 @@ system.realview.nvmem.bw_inst_read::total 149 # I system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 124 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 395008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4372084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 425536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5226480 # Number of bytes read from this memory -system.physmem.bytes_read::total 129958756 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 395008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 425536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 820544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4244480 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7273616 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6172 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68386 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6649 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81690 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15105136 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66320 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823604 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46305011 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 153013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1693603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 164839 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2024569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50341804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 153013 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 164839 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317852 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1644174 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6585 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1166804 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2817563 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1644174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46305011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 153013 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1700189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 164839 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3191372 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53159367 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72536 # number of replacements -system.l2c.tagsinuse 53024.626088 # Cycle average of tags in use -system.l2c.total_refs 2019266 # Total number of references to valid blocks. -system.l2c.sampled_refs 137732 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.660834 # Average number of references to valid blocks. +system.l2c.replacements 72453 # number of replacements +system.l2c.tagsinuse 52989.750711 # Cycle average of tags in use +system.l2c.total_refs 1967154 # Total number of references to valid blocks. +system.l2c.sampled_refs 137652 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.290777 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37701.415204 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 3.259804 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000179 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4215.968317 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2959.624437 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 13.637835 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4028.150256 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4102.570055 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.575278 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000050 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 37689.434458 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.667894 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.004429 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4220.453796 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2953.326384 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 6.708393 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4009.126872 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4107.028485 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.575095 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000056 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064331 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.045160 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000208 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061465 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.062600 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809092 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 53338 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6106 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 398719 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 164464 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 78886 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6452 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 615129 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 199702 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1522796 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 645710 # number of Writeback hits -system.l2c.Writeback_hits::total 645710 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1043 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 806 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1849 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 213 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 143 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 356 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48030 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 59189 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107219 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 53338 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6106 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 398719 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 212494 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 78886 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6452 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 615129 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 258891 # number of demand (read+write) hits -system.l2c.demand_hits::total 1630015 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 53338 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6106 # number of overall hits -system.l2c.overall_hits::cpu0.inst 398719 # number of overall hits -system.l2c.overall_hits::cpu0.data 212494 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 78886 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6452 # number of overall hits -system.l2c.overall_hits::cpu1.inst 615129 # number of overall hits -system.l2c.overall_hits::cpu1.data 258891 # number of overall hits -system.l2c.overall_hits::total 1630015 # number of overall hits +system.l2c.occ_percent::cpu0.inst 0.064399 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.045064 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000102 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.061174 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.062668 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.808559 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 54491 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 6158 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 400629 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 165440 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 78380 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6682 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 615050 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 201442 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1528272 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 583270 # number of Writeback hits +system.l2c.Writeback_hits::total 583270 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1037 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 784 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1821 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 208 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 159 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 367 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48010 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 59262 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 107272 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 54491 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 6158 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 400629 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 213450 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 78380 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6682 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 615050 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 260704 # number of demand (read+write) hits +system.l2c.demand_hits::total 1635544 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 54491 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 6158 # number of overall hits +system.l2c.overall_hits::cpu0.inst 400629 # number of overall hits +system.l2c.overall_hits::cpu0.data 213450 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 78380 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6682 # number of overall hits +system.l2c.overall_hits::cpu1.inst 615050 # number of overall hits +system.l2c.overall_hits::cpu1.data 260704 # number of overall hits +system.l2c.overall_hits::total 1635544 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 9 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6044 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6302 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 21 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6609 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6068 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6301 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 6610 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 6328 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25314 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5683 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4287 # 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number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5579000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9891431999 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9891088499 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2133500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 153179360607 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 163078505106 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000169 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000164 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014920 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036676 # 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mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564021 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.566336 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000169 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000164 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014920 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000266 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010622 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.242479 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.092051 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000169 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000164 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014920 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000266 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010622 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.242479 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.092051 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 153181944383 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 163080745382 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000165 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000325 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014908 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036468 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000140 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030346 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016258 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.845639 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.846063 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.845822 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.789474 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.784261 # 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mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091738 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000165 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000325 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014908 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.246185 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000140 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.241009 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091738 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40401.085742 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40398.651864 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40726.665716 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40045.046630 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40055.516678 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40049.548646 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.827542 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40044.991511 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40043.191801 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41112.064586 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40939.462062 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41017.675701 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41131.535379 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40423.598914 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41007.797123 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40402.220460 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40740.913730 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40028.692132 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40049.083314 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.487487 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40021.794872 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40019.031142 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40020.618557 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41111.835957 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40931.189956 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41013.105098 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41048.190409 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40898.319063 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40973.227581 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41131.535379 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41050.012880 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41007.797123 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40890.905956 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40971.489573 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41048.190409 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40898.319063 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40973.227581 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41131.535379 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41050.012880 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41007.797123 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40890.905956 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40971.489573 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -509,27 +507,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9084255 # DTB read hits -system.cpu0.dtb.read_misses 36769 # DTB read misses -system.cpu0.dtb.write_hits 5284576 # DTB write hits -system.cpu0.dtb.write_misses 6773 # DTB write misses +system.cpu0.dtb.read_hits 9083896 # DTB read hits +system.cpu0.dtb.read_misses 37543 # DTB read misses +system.cpu0.dtb.write_hits 5286239 # DTB write hits +system.cpu0.dtb.write_misses 6882 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2261 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1412 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 383 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2244 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1393 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 382 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 588 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9121024 # DTB read accesses -system.cpu0.dtb.write_accesses 5291349 # DTB write accesses +system.cpu0.dtb.perms_faults 574 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9121439 # DTB read accesses +system.cpu0.dtb.write_accesses 5293121 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14368831 # DTB hits -system.cpu0.dtb.misses 43542 # DTB misses -system.cpu0.dtb.accesses 14412373 # DTB accesses -system.cpu0.itb.inst_hits 4421795 # ITB inst hits -system.cpu0.itb.inst_misses 5958 # ITB inst misses +system.cpu0.dtb.hits 14370135 # DTB hits +system.cpu0.dtb.misses 44425 # DTB misses +system.cpu0.dtb.accesses 14414560 # DTB accesses +system.cpu0.itb.inst_hits 4418601 # ITB inst hits +system.cpu0.itb.inst_misses 6114 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -538,542 +536,544 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1415 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1409 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1713 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1633 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4427753 # ITB inst accesses -system.cpu0.itb.hits 4421795 # DTB hits -system.cpu0.itb.misses 5958 # DTB misses -system.cpu0.itb.accesses 4427753 # DTB accesses -system.cpu0.numCycles 66112093 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4424715 # ITB inst accesses +system.cpu0.itb.hits 4418601 # DTB hits +system.cpu0.itb.misses 6114 # DTB misses +system.cpu0.itb.accesses 4424715 # DTB accesses +system.cpu0.numCycles 66354055 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6172143 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4680207 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 316413 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3902841 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 2861272 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6346252 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4857071 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 316053 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 4075974 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 3037671 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 700420 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 30889 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 12972431 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32579396 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6172143 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3561692 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7636967 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1568394 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 92289 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 21876805 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5742 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 73340 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 91549 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 175 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4419869 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 175391 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2999 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 43870869 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.963501 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.353712 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 700378 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 30829 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 12963003 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 33274045 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6346252 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3738049 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7812188 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1602844 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 89446 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 22023764 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5932 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 73578 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 90886 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 179 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4416774 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 175280 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3223 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 44209960 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.971808 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.352806 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 36242473 82.61% 82.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 623814 1.42% 84.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 820212 1.87% 85.90% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 686089 1.56% 87.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 622737 1.42% 88.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 578948 1.32% 90.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 720296 1.64% 91.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 370745 0.85% 92.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3205555 7.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 36406101 82.35% 82.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 622907 1.41% 83.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 820090 1.85% 85.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 691511 1.56% 87.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 794774 1.80% 88.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 578673 1.31% 90.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 721468 1.63% 91.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 370773 0.84% 92.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3203663 7.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 43870869 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.093359 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.492790 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 13461534 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 21912526 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6836712 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 603785 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1056312 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 995110 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 66550 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40827533 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 217718 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1056312 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 14066817 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6153021 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13456769 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6788701 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2349249 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 39593607 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1040 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 472233 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1335984 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 103 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39791095 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 179675714 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 179640853 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34861 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31537071 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8254023 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 463697 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 419128 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5673165 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7928571 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5881726 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1132931 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1238845 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37538443 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 794373 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37739879 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 92690 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6264606 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14354053 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 137507 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 43870869 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.860249 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.478315 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 44209960 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.095642 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.501462 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 13460475 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 22052761 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 7004876 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 606078 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1085770 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 992839 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 66349 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 41502146 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 217622 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1085770 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 14072541 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6178049 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13569314 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6948288 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2355998 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 40249124 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2572 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 473537 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1335703 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 188 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 40597200 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 181819083 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 181783808 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 35275 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31678350 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8918849 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 463403 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 418800 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5692374 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7927385 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5883720 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1132627 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1230816 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 38008933 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 947103 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 38247071 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 93468 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6756686 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 14324325 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 258267 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 44209960 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.865123 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.479533 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 28164784 64.20% 64.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6326126 14.42% 78.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3234526 7.37% 85.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2361316 5.38% 91.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2098246 4.78% 96.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 936106 2.13% 98.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 514694 1.17% 99.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 181493 0.41% 99.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53578 0.12% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 28324155 64.07% 64.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6346765 14.36% 78.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3236431 7.32% 85.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2507997 5.67% 91.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2107881 4.77% 96.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 937016 2.12% 98.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 515116 1.17% 99.47% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 180639 0.41% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53960 0.12% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 43870869 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 44209960 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27565 2.58% 2.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 466 0.04% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 837939 78.44% 81.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 202337 18.94% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27715 2.59% 2.59% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 460 0.04% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 839091 78.45% 81.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 202283 18.91% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 20407 0.05% 0.05% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22494595 59.60% 59.66% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 50051 0.13% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9563453 25.34% 85.13% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5610668 14.87% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22968400 60.05% 60.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 50115 0.13% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 11 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9563149 25.00% 85.33% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5612341 14.67% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37739879 # Type of FU issued -system.cpu0.iq.rate 0.570847 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1068307 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028307 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 120546534 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44606042 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34820056 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8333 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4740 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3893 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38783456 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4323 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 326383 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 38247071 # Type of FU issued +system.cpu0.iq.rate 0.576409 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1069549 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.027964 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 121902835 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 45721169 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 35306324 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8427 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4840 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3930 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 39259896 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4380 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 325721 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1507630 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4080 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13930 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 608245 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1504145 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3982 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13879 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 608088 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149509 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5404 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149487 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5263 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1056312 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4064319 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 129740 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 38471177 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 88757 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7928571 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5881726 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 461616 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 49674 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 17745 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13930 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 159357 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 144737 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 304094 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37337331 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9402148 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 402548 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1085770 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4069341 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 129560 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 39094255 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 87678 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7927385 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5883720 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 614122 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 49261 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 17662 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13879 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 160370 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 144551 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 304921 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37828601 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9401576 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 418470 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 138361 # number of nop insts executed -system.cpu0.iew.exec_refs 14958639 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4921687 # Number of branches executed -system.cpu0.iew.exec_stores 5556491 # Number of stores executed -system.cpu0.iew.exec_rate 0.564758 # Inst execution rate -system.cpu0.iew.wb_sent 37117116 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34823949 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18360594 # num instructions producing a value -system.cpu0.iew.wb_consumers 34980725 # num instructions consuming a value +system.cpu0.iew.exec_nop 138219 # number of nop insts executed +system.cpu0.iew.exec_refs 14960222 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5069889 # Number of branches executed +system.cpu0.iew.exec_stores 5558646 # Number of stores executed +system.cpu0.iew.exec_rate 0.570102 # Inst execution rate +system.cpu0.iew.wb_sent 37608832 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 35310254 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18670977 # num instructions producing a value +system.cpu0.iew.wb_consumers 35573590 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.526741 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.524877 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.532149 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.524855 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 24134633 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 31866160 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 6466683 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 656866 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 267750 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 42850944 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.743651 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.697776 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 24262280 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 31997725 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 6679991 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 688836 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 267429 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 43160582 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.741365 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.695624 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 30739496 71.74% 71.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6075340 14.18% 85.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1944692 4.54% 90.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1041937 2.43% 92.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 773699 1.81% 94.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 503770 1.18% 95.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 405337 0.95% 96.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 203427 0.47% 97.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1163246 2.71% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 31020137 71.87% 71.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6071618 14.07% 85.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1950463 4.52% 90.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1036843 2.40% 92.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 799662 1.85% 94.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 507487 1.18% 95.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 407135 0.94% 96.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 202137 0.47% 97.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1165100 2.70% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 42850944 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24134633 # Number of instructions committed -system.cpu0.commit.committedOps 31866160 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 43160582 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24262280 # Number of instructions committed +system.cpu0.commit.committedOps 31997725 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11694422 # Number of memory references committed -system.cpu0.commit.loads 6420941 # Number of loads committed -system.cpu0.commit.membars 234529 # Number of memory barriers committed -system.cpu0.commit.branches 4382702 # Number of branches committed +system.cpu0.commit.refs 11698872 # Number of memory references committed +system.cpu0.commit.loads 6423240 # Number of loads committed +system.cpu0.commit.membars 234547 # Number of memory barriers committed +system.cpu0.commit.branches 4415502 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28193395 # Number of committed integer instructions. -system.cpu0.commit.function_calls 499856 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1163246 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 28265931 # Number of committed integer instructions. +system.cpu0.commit.function_calls 499946 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1165100 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 79207972 # The number of ROB reads -system.cpu0.rob.rob_writes 77724528 # The number of ROB writes -system.cpu0.timesIdled 427936 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 22241224 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5096899290 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24053891 # Number of Instructions Simulated -system.cpu0.committedOps 31785418 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24053891 # Number of Instructions Simulated -system.cpu0.cpi 2.748499 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.748499 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.363835 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.363835 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 174526329 # number of integer regfile reads -system.cpu0.int_regfile_writes 34331240 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3280 # number of floating regfile reads -system.cpu0.fp_regfile_writes 898 # number of floating regfile writes -system.cpu0.misc_regfile_reads 46875879 # number of misc regfile reads -system.cpu0.misc_regfile_writes 527497 # number of misc regfile writes -system.cpu0.icache.replacements 406974 # number of replacements -system.cpu0.icache.tagsinuse 511.614338 # Cycle average of tags in use -system.cpu0.icache.total_refs 3978434 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 407486 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.763364 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6469268000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.614338 # Average occupied blocks per requestor +system.cpu0.rob.rob_reads 79788976 # The number of ROB reads +system.cpu0.rob.rob_writes 78443760 # The number of ROB writes +system.cpu0.timesIdled 426851 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 22144095 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5098222727 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 24181538 # Number of Instructions Simulated +system.cpu0.committedOps 31916983 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 24181538 # Number of Instructions Simulated +system.cpu0.cpi 2.743996 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.743996 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.364432 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.364432 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 176533858 # number of integer regfile reads +system.cpu0.int_regfile_writes 35079827 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3404 # number of floating regfile reads +system.cpu0.fp_regfile_writes 942 # number of floating regfile writes +system.cpu0.misc_regfile_reads 47584444 # number of misc regfile reads +system.cpu0.misc_regfile_writes 527516 # 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number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7186656997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7186656997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4419732 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4419732 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4419732 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4419732 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4419732 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4419732 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099847 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.099847 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099847 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.099847 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099847 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.099847 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16285.269811 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16285.269811 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16285.269811 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16285.269811 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16285.269811 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16285.269811 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1454497 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 3975135 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3975135 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3975135 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3975135 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3975135 # number of overall hits +system.cpu0.icache.overall_hits::total 3975135 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 441500 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 441500 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 441500 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 441500 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 441500 # number of overall misses +system.cpu0.icache.overall_misses::total 441500 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7129067996 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7129067996 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7129067996 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7129067996 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7129067996 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7129067996 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4416635 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4416635 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4416635 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4416635 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4416635 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4416635 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099963 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.099963 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099963 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.099963 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099963 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.099963 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16147.379379 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 16147.379379 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16147.379379 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 16147.379379 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16147.379379 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 16147.379379 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1348496 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 171 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 167 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 8505.830409 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 8074.826347 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 29234 # number of writebacks -system.cpu0.icache.writebacks::total 29234 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33802 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 33802 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 33802 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 33802 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 33802 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 33802 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 407496 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 407496 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 407496 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 407496 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 407496 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 407496 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5527499503 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5527499503 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5527499503 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5527499503 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5527499503 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5527499503 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 34106 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 34106 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 34106 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 34106 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 34106 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 34106 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 407394 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 407394 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 407394 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 407394 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 407394 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 407394 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5468654996 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5468654996 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5468654996 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5468654996 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5468654996 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5468654996 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8379000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8379000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8379000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 8379000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092199 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.092199 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.092199 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13564.549107 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13564.549107 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13564.549107 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092241 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092241 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092241 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.092241 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092241 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.092241 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13423.504018 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13423.504018 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13423.504018 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13423.504018 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13423.504018 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13423.504018 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 275761 # number of replacements -system.cpu0.dcache.tagsinuse 476.305820 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9551525 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276273 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.572778 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 275592 # number of replacements +system.cpu0.dcache.tagsinuse 476.837382 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9554493 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276104 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.604689 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 51448000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 476.305820 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.930285 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.930285 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5934693 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5934693 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3224707 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3224707 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174478 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183485 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179293 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 179293 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11154900 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11154900 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11154900 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11154900 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063330 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063330 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330828 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.330828 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.049088 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.049088 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043471 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043471 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178890 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.178890 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178890 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.178890 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18166.917546 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 18166.917546 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45047.276530 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45047.276530 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12728.155879 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12728.155879 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12023.992815 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12023.992815 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39642.175831 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39642.175831 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39642.175831 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39642.175831 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7140493 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1629000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1441 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 89 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4955.234559 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 18303.370787 # average number of cycles each access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 476.837382 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.931323 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.931323 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5935954 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5935954 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3226635 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3226635 # 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number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8985 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7776 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7776 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1994631 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1994631 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1994631 # number of overall misses +system.cpu0.dcache.overall_misses::total 1994631 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7261400500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 7261400500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71837415855 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 71837415855 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 113971500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 113971500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 93410500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 93410500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 79098816355 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 79098816355 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 79098816355 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 79098816355 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6336481 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6336481 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4820739 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4820739 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183390 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183390 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179324 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 179324 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11157220 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11157220 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11157220 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11157220 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063210 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063210 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330676 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.330676 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048994 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048994 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043363 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043363 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178775 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.178775 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178775 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.178775 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18129.615482 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 18129.615482 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45064.447398 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45064.447398 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12684.641068 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12684.641068 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12012.667181 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12012.667181 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39655.864345 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39655.864345 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39655.864345 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39655.864345 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 7527492 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1548500 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1462 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 87 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 5148.763338 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 17798.850575 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255942 # number of writebacks -system.cpu0.dcache.writebacks::total 255942 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211815 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 211815 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1463184 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1463184 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 509 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 509 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1674999 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1674999 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1674999 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1674999 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189440 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189440 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131061 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131061 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8498 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8498 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7791 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7791 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320501 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320501 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 320501 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 320501 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2806583905 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2806583905 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4685193022 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4685193022 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 80265007 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 80265007 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 69214057 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 69214057 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7491776927 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7491776927 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7491776927 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7491776927 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10315161000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10315161000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 849550399 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 849550399 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11164711399 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11164711399 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029899 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029899 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027197 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027197 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046314 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046314 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043454 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043454 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028732 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028732 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028732 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028732 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14815.159971 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14815.159971 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35748.186127 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35748.186127 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9445.164392 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9445.164392 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8883.847645 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8883.847645 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23375.206090 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23375.206090 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23375.206090 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23375.206090 # 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number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 320369 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2800937917 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2800937917 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4685815512 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4685815512 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79569505 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79569505 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 68924555 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 68924555 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7486753429 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7486753429 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7486753429 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7486753429 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10315126500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10315126500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 849486399 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 849486399 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11164612899 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11164612899 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029873 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029873 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027190 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027190 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046180 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046180 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043346 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043346 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028714 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028714 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028714 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028714 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14796.994664 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14796.994664 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35748.298814 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35748.298814 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9395.383753 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9395.383753 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8867.175479 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8867.175479 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23369.156907 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23369.156907 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23369.156907 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23369.156907 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1083,27 +1083,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43446349 # DTB read hits -system.cpu1.dtb.read_misses 46684 # DTB read misses -system.cpu1.dtb.write_hits 7088138 # DTB write hits -system.cpu1.dtb.write_misses 12274 # DTB write misses +system.cpu1.dtb.read_hits 43445270 # DTB read hits +system.cpu1.dtb.read_misses 46285 # DTB read misses +system.cpu1.dtb.write_hits 7088572 # DTB write hits +system.cpu1.dtb.write_misses 12217 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2545 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3731 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 361 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2504 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3688 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 371 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 673 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43493033 # DTB read accesses -system.cpu1.dtb.write_accesses 7100412 # DTB write accesses +system.cpu1.dtb.perms_faults 674 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43491555 # DTB read accesses +system.cpu1.dtb.write_accesses 7100789 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50534487 # DTB hits -system.cpu1.dtb.misses 58958 # DTB misses -system.cpu1.dtb.accesses 50593445 # DTB accesses -system.cpu1.itb.inst_hits 9221438 # ITB inst hits -system.cpu1.itb.inst_misses 6034 # ITB inst misses +system.cpu1.dtb.hits 50533842 # DTB hits +system.cpu1.dtb.misses 58502 # DTB misses +system.cpu1.dtb.accesses 50592344 # DTB accesses +system.cpu1.itb.inst_hits 9223213 # ITB inst hits +system.cpu1.itb.inst_misses 6180 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1112,121 +1112,121 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1610 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1615 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1730 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1780 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 9227472 # ITB inst accesses -system.cpu1.itb.hits 9221438 # DTB hits -system.cpu1.itb.misses 6034 # DTB misses -system.cpu1.itb.accesses 9227472 # DTB accesses -system.cpu1.numCycles 353824423 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 9229393 # ITB inst accesses +system.cpu1.itb.hits 9223213 # DTB hits +system.cpu1.itb.misses 6180 # DTB misses +system.cpu1.itb.accesses 9229393 # DTB accesses +system.cpu1.numCycles 355232424 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9470897 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 7703385 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 447489 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6420671 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5281203 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9848764 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 8083275 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 447123 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 6868345 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5662939 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 834152 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 50449 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 22167103 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 70445168 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9470897 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6115355 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14956565 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4597208 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 88094 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 73687570 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 6011 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 61739 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 141755 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 9219303 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 857673 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3541 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114241434 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.747913 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.114106 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 832004 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 49676 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 22148379 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 71952458 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9848764 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6494943 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 15333431 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4632908 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 88364 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 74838070 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5775 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 63991 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 141562 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 138 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 9221022 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 859641 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3677 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 115781579 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.750934 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.109459 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 99293168 86.92% 86.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 828706 0.73% 87.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1015866 0.89% 88.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2054648 1.80% 90.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1280264 1.12% 91.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 613123 0.54% 91.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2273093 1.99% 93.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 467514 0.41% 94.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 6415052 5.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 100456410 86.76% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 829573 0.72% 87.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1015846 0.88% 88.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2061622 1.78% 90.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1645380 1.42% 91.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 616095 0.53% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2274849 1.96% 94.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 467300 0.40% 94.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 6414504 5.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114241434 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.026767 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.199096 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 23740446 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 73499308 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 13432186 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 537783 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3031711 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1242419 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 102480 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 79700896 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 342426 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3031711 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 25267828 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33699109 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 35312301 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 12394168 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4536317 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 73261010 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 3244 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 714923 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3281779 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 33706 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 77426546 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 339504965 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 339445449 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59516 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49265102 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 28161444 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 486276 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 420659 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8155263 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 14019935 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8605996 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1069297 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1521896 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 66318588 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 855610 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 90596015 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 108958 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18341957 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 53651445 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 163223 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114241434 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.793022 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.525613 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 115781579 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.027725 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.202550 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 23776389 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 74601447 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 13781615 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 561009 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3061119 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1241407 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 102665 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 81190791 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 341149 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3061119 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 25333003 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33967991 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 36116187 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 12703540 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4599739 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 74711209 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 20422 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 719883 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3284162 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 33659 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 79078972 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 344223554 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 344164086 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59468 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50180386 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 28898586 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 486916 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 421354 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8389500 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 14026564 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8607423 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1068694 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1518812 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 67421543 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1209489 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 91958955 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 109721 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18898752 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 53543776 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 290002 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 115781579 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.794245 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.521941 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83094748 72.74% 72.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8828314 7.73% 80.46% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4518450 3.96% 84.42% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3737052 3.27% 87.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10664138 9.33% 97.02% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1972512 1.73% 98.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1063413 0.93% 99.68% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 282401 0.25% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 80406 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83973534 72.53% 72.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 9124499 7.88% 80.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4576997 3.95% 84.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 4009566 3.46% 87.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10699106 9.24% 97.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1974757 1.71% 98.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1060771 0.92% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 281863 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 80486 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114241434 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 115781579 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29108 0.37% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29310 0.37% 0.37% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 993 0.01% 0.38% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available @@ -1255,403 +1255,397 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7574349 95.84% 96.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 298565 3.78% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7573445 95.84% 96.23% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 298199 3.77% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 86745 0.10% 0.10% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 38337785 42.32% 42.41% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61539 0.07% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 4 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1698 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44639306 49.27% 91.76% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7468915 8.24% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313737 0.34% 0.34% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 39470238 42.92% 43.26% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61477 0.07% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1690 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 44643108 48.55% 91.88% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7468676 8.12% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 90596015 # Type of FU issued -system.cpu1.iq.rate 0.256048 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7903015 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.087234 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 303489486 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 85529327 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54443530 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14763 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8091 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6830 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 98404572 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7713 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 368848 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 91958955 # Type of FU issued +system.cpu1.iq.rate 0.258870 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7901947 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.085929 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 307754751 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 87542996 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 55769663 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14772 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8137 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6817 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 99539441 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7724 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 371642 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4030694 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6909 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 21919 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1587988 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4037130 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6814 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 21954 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1589436 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965710 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1045299 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31965709 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1043610 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3031711 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25598263 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 405605 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 67299344 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 135063 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 14019935 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8605996 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 545729 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 81019 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 7196 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 21919 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 232087 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 197105 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 429192 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87765278 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43831578 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2830737 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3061119 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25601852 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 406330 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 68756671 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 131432 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 14026564 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8607423 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 899609 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 81519 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 7124 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 21954 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 226065 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 196785 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 422850 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 89098857 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43830249 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2860098 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 125146 # number of nop insts executed -system.cpu1.iew.exec_refs 51224987 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7024509 # Number of branches executed -system.cpu1.iew.exec_stores 7393409 # Number of stores executed -system.cpu1.iew.exec_rate 0.248048 # Inst execution rate -system.cpu1.iew.wb_sent 86598496 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54450360 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30044182 # num instructions producing a value -system.cpu1.iew.wb_consumers 53342809 # num instructions consuming a value +system.cpu1.iew.exec_nop 125639 # number of nop insts executed +system.cpu1.iew.exec_refs 51224079 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7396455 # Number of branches executed +system.cpu1.iew.exec_stores 7393830 # Number of stores executed +system.cpu1.iew.exec_rate 0.250818 # Inst execution rate +system.cpu1.iew.wb_sent 87931251 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 55776480 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30792122 # num instructions producing a value +system.cpu1.iew.wb_consumers 54566321 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.153891 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.563228 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.157014 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.564306 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 38036954 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 48396972 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 18817114 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 692387 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 376510 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111258144 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.434997 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.402953 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 38938347 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 49298719 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 19014978 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 919487 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 376070 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 112768879 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.437166 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.403258 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94210177 84.68% 84.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8524716 7.66% 92.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2208233 1.98% 94.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1307974 1.18% 95.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1064973 0.96% 96.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 589982 0.53% 96.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1003368 0.90% 97.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 487910 0.44% 98.33% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1860811 1.67% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 95484340 84.67% 84.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8537208 7.57% 92.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2210726 1.96% 94.20% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1312266 1.16% 95.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1283048 1.14% 96.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 588048 0.52% 97.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1003635 0.89% 97.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 487845 0.43% 98.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1861763 1.65% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111258144 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38036954 # Number of instructions committed -system.cpu1.commit.committedOps 48396972 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 112768879 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38938347 # Number of instructions committed +system.cpu1.commit.committedOps 49298719 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17007249 # Number of memory references committed -system.cpu1.commit.loads 9989241 # Number of loads committed -system.cpu1.commit.membars 202226 # Number of memory barriers committed -system.cpu1.commit.branches 5993368 # Number of branches committed +system.cpu1.commit.refs 17007421 # Number of memory references committed +system.cpu1.commit.loads 9989434 # Number of loads committed +system.cpu1.commit.membars 202281 # Number of memory barriers committed +system.cpu1.commit.branches 6220621 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43235909 # Number of committed integer instructions. -system.cpu1.commit.function_calls 556157 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1860811 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 43690243 # Number of committed integer instructions. +system.cpu1.commit.function_calls 556165 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1861763 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 175585773 # The number of ROB reads -system.cpu1.rob.rob_writes 137553768 # The number of ROB writes -system.cpu1.timesIdled 1520299 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 239582989 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4808538839 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37967315 # Number of Instructions Simulated -system.cpu1.committedOps 48327333 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37967315 # Number of Instructions Simulated -system.cpu1.cpi 9.319185 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 9.319185 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.107306 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.107306 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 393921761 # number of integer regfile reads -system.cpu1.int_regfile_writes 56840694 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4925 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2334 # number of floating regfile writes -system.cpu1.misc_regfile_reads 90313719 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429414 # number of misc regfile writes -system.cpu1.icache.replacements 622931 # number of replacements -system.cpu1.icache.tagsinuse 498.760560 # Cycle average of tags in use -system.cpu1.icache.total_refs 8545880 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 623443 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.707556 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74633827000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.760560 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974142 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974142 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 8545880 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 8545880 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 8545880 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 8545880 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 8545880 # number of overall hits -system.cpu1.icache.overall_hits::total 8545880 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 673372 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 673372 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 673372 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 673372 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 673372 # number of overall misses -system.cpu1.icache.overall_misses::total 673372 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10716931993 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10716931993 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10716931993 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10716931993 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10716931993 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10716931993 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 9219252 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 9219252 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 9219252 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 9219252 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 9219252 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 9219252 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073040 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.073040 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073040 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.073040 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073040 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.073040 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15915.321684 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15915.321684 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15915.321684 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15915.321684 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15915.321684 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15915.321684 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1332494 # number of cycles access was blocked +system.cpu1.rob.rob_reads 178106600 # The number of ROB reads +system.cpu1.rob.rob_writes 139781050 # The number of ROB writes +system.cpu1.timesIdled 1519184 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 239450845 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4808685831 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38868708 # Number of Instructions Simulated +system.cpu1.committedOps 49229080 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38868708 # Number of Instructions Simulated +system.cpu1.cpi 9.139291 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 9.139291 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.109418 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.109418 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 398713179 # number of integer regfile reads +system.cpu1.int_regfile_writes 58485097 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4918 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2338 # number of floating regfile writes +system.cpu1.misc_regfile_reads 91819776 # number of misc regfile reads +system.cpu1.misc_regfile_writes 429481 # number of misc regfile writes +system.cpu1.icache.replacements 621812 # number of replacements +system.cpu1.icache.tagsinuse 498.762593 # Cycle average of tags in use +system.cpu1.icache.total_refs 8548797 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 622324 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.736891 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74633258000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.762593 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974146 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974146 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 8548797 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 8548797 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 8548797 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 8548797 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 8548797 # number of overall hits +system.cpu1.icache.overall_hits::total 8548797 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 672174 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 672174 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 672174 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 672174 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 672174 # number of overall misses +system.cpu1.icache.overall_misses::total 672174 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10613540997 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 10613540997 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 10613540997 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 10613540997 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 10613540997 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 10613540997 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 9220971 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 9220971 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 9220971 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 9220971 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 9220971 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 9220971 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.072896 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.072896 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.072896 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.072896 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.072896 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.072896 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15789.871368 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15789.871368 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15789.871368 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15789.871368 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15789.871368 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15789.871368 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1180997 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 205 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 198 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6499.970732 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 5964.631313 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 33068 # number of writebacks -system.cpu1.icache.writebacks::total 33068 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 49906 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 49906 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 49906 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 49906 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 49906 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 49906 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 623466 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 623466 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 623466 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 623466 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 623466 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 623466 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8227032008 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8227032008 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8227032008 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8227032008 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8227032008 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8227032008 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 49820 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 49820 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 49820 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 49820 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 49820 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 49820 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622354 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 622354 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 622354 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 622354 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 622354 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 622354 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8128418498 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8128418498 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8128418498 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8128418498 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8128418498 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8128418498 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3154000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3154000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3154000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 3154000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067627 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.067627 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.067627 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13195.638588 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13195.638588 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13195.638588 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067493 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067493 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067493 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.067493 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067493 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.067493 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13060.763646 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13060.763646 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13060.763646 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13060.763646 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13060.763646 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13060.763646 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 362729 # number of replacements -system.cpu1.dcache.tagsinuse 487.126779 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13112337 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 363073 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 36.114878 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 70483759000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.126779 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.951419 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.951419 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8613908 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8613908 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4252702 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4252702 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105106 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 105106 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100709 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 100709 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12866610 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12866610 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12866610 # number of overall hits -system.cpu1.dcache.overall_hits::total 12866610 # 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number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8114216000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 8114216000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66620735237 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 66620735237 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 166584000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 166584000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 94819000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 94819000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 74734951237 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 74734951237 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 74734951237 # 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miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118199 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118199 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097698 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097698 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134946 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.134946 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134946 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.134946 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19808.745418 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19808.745418 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41667.521656 # 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number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5620000 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6671 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 172 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4418.530205 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 32674.418605 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 327467 # number of writebacks -system.cpu1.dcache.writebacks::total 327467 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 179191 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 179191 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1432552 # 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number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12821 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10892 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10892 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 393799 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 393799 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 393799 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 393799 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3545762451 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3545762451 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5565749199 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5565749199 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 104395505 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104395505 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60832506 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60832506 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9111511650 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9111511650 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9111511650 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9111511650 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137004750500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137004750500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40571899654 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40571899654 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 177576650154 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 177576650154 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025597 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025597 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027839 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027839 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107393 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107393 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097591 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097591 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026479 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026479 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026479 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026479 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15350.019702 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15350.019702 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34186.598686 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34186.598686 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8142.539973 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8142.539973 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5585.062982 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5585.062982 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23137.467718 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23137.467718 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23137.467718 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23137.467718 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 327729 # number of writebacks +system.cpu1.dcache.writebacks::total 327729 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 179332 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 179332 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1432824 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1432824 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1447 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1612156 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1612156 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1612156 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1612156 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231283 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231283 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162795 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 162795 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12775 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12775 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10900 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10900 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394078 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394078 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394078 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394078 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3556387454 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3556387454 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5557887685 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5557887685 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 103446504 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 103446504 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60421505 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60421505 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9114275139 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9114275139 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9114275139 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9114275139 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137004022500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137004022500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40580989302 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40580989302 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 177585011802 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 177585011802 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025644 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025644 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027838 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027838 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106173 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106173 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097654 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097654 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026507 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026507 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15376.778466 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15376.778466 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34140.407783 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34140.407783 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8097.573699 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8097.573699 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5543.257339 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5543.257339 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23128.099359 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23128.099359 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23128.099359 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23128.099359 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1673,18 +1667,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305278151135 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1305278151135 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305278151135 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1305278151135 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305599683923 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1305599683923 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305599683923 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1305599683923 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43785 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43782 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53912 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 53899 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |