diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | 2990 |
1 files changed, 1493 insertions, 1497 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 6e759f59e..038e4aa5b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,75 +1,75 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.570834 # Number of seconds simulated -sim_ticks 2570833934500 # Number of ticks simulated -final_tick 2570833934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.569716 # Number of seconds simulated +sim_ticks 2569716290500 # Number of ticks simulated +final_tick 2569716290500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53678 # Simulator instruction rate (inst/s) -host_op_rate 69325 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2225327298 # Simulator tick rate (ticks/s) -host_mem_usage 390932 # Number of bytes of host memory used -host_seconds 1155.26 # Real time elapsed on the host -sim_insts 62012062 # Number of instructions simulated -sim_ops 80088895 # Number of ops (including micro ops) simulated +host_inst_rate 91215 # Simulator instruction rate (inst/s) +host_op_rate 117813 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3779331614 # Simulator tick rate (ticks/s) +host_mem_usage 391064 # Number of bytes of host memory used +host_seconds 679.94 # Real time elapsed on the host +sim_insts 62020337 # Number of instructions simulated +sim_ops 80105642 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 5376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 544832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4740532 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 3904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 654592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5942256 # Number of bytes read from this memory -system.physmem.bytes_read::total 131429540 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 544832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 654592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1199424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7146560 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 383040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4310004 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 438272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5311600 # Number of bytes read from this memory +system.physmem.bytes_read::total 129982372 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 383040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 438272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 821312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4277376 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 10175696 # Number of bytes written to this memory +system.physmem.bytes_written::total 7306512 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 84 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 8513 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 74143 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 61 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10228 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 92874 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15128117 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 111665 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 5985 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 67416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 83020 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15105505 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66834 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 868949 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46497622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 2091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 211928 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1843967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1519 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 254622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2311412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51123310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 211928 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 254622 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466551 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2779861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6613 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1171657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3958130 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2779861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46497622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2091 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 211928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1850579 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1519 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 254622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3483069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55081440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 824118 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46517845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 149059 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1677230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 170553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2066999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50582382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 149059 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 170553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 319612 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1664532 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6616 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1172167 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2843315 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1664532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46517845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 149059 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1683845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 374 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 170553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3239165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53425697 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory @@ -80,259 +80,259 @@ system.realview.nvmem.num_reads::cpu0.inst 1 # system.realview.nvmem.num_reads::cpu1.inst 5 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 124 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 125 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 149 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 124 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 125 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 149 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 124 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 125 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 130926 # number of replacements -system.l2c.tagsinuse 27576.629960 # Cycle average of tags in use -system.l2c.total_refs 1855308 # Total number of references to valid blocks. -system.l2c.sampled_refs 161029 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.521577 # Average number of references to valid blocks. +system.l2c.replacements 72902 # number of replacements +system.l2c.tagsinuse 52914.655952 # Cycle average of tags in use +system.l2c.total_refs 2024041 # Total number of references to valid blocks. +system.l2c.sampled_refs 138037 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.663032 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 15187.159331 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 17.600608 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.006762 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2177.920948 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 1032.752170 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 22.717912 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.014158 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4068.026765 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 5070.431306 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.231738 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000269 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 37560.940783 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.394478 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000176 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4213.394018 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2969.636370 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 12.170115 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.970249 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4028.311406 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4125.838357 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.573134 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000052 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.033232 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.015759 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000347 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.062073 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.077369 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.420786 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 51294 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5750 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 335682 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 133493 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 112013 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7283 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 702787 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 231603 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1579905 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 606768 # number of Writeback hits -system.l2c.Writeback_hits::total 606768 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 925 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1139 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2064 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 217 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 388 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 605 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 35350 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 66066 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 101416 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 51294 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5750 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 335682 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 168843 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 112013 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7283 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 702787 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 297669 # number of demand (read+write) hits -system.l2c.demand_hits::total 1681321 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 51294 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5750 # number of overall hits -system.l2c.overall_hits::cpu0.inst 335682 # number of overall hits -system.l2c.overall_hits::cpu0.data 168843 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 112013 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7283 # number of overall hits -system.l2c.overall_hits::cpu1.inst 702787 # number of overall hits -system.l2c.overall_hits::cpu1.data 297669 # number of overall hits -system.l2c.overall_hits::total 1681321 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 84 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 8376 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 8805 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 61 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 10197 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 12824 # number of ReadReq misses -system.l2c.ReadReq_misses::total 40353 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5201 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5819 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11020 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 788 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 600 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1388 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 65908 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 81633 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 147541 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 84 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 8376 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 74713 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 61 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 10197 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 94457 # number of demand (read+write) misses -system.l2c.demand_misses::total 187894 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 84 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.inst 8376 # number of overall misses -system.l2c.overall_misses::cpu0.data 74713 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 61 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 10197 # number of overall misses -system.l2c.overall_misses::cpu1.data 94457 # number of overall misses -system.l2c.overall_misses::total 187894 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 4383500 # 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average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40079.973669 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40062.103442 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40030.245747 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40045.281307 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40043.147208 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40061.666667 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.152738 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40033.493643 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40096.958338 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40068.608041 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40036.288257 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40147.214464 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40032.171376 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40073.893963 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40035.795240 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40038.703587 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.173243 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40042.580645 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40066.724437 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40052.884615 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40031.482973 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40090.180180 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40063.981694 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 41000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40081.124979 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40031.329090 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40036.288257 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40147.214464 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40085.694438 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40065.495375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 41000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40081.124979 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40031.329090 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40147.214464 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40085.694438 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40065.495375 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -537,27 +537,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7530160 # DTB read hits -system.cpu0.dtb.read_misses 32787 # DTB read misses -system.cpu0.dtb.write_hits 4446652 # DTB write hits -system.cpu0.dtb.write_misses 6213 # DTB write misses +system.cpu0.dtb.read_hits 12222008 # DTB read hits +system.cpu0.dtb.read_misses 34799 # DTB read misses +system.cpu0.dtb.write_hits 5155654 # DTB write hits +system.cpu0.dtb.write_misses 4970 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2035 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 4401 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 226 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2546 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1270 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 369 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 789 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7562947 # DTB read accesses -system.cpu0.dtb.write_accesses 4452865 # DTB write accesses +system.cpu0.dtb.perms_faults 661 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12256807 # DTB read accesses +system.cpu0.dtb.write_accesses 5160624 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 11976812 # DTB hits -system.cpu0.dtb.misses 39000 # DTB misses -system.cpu0.dtb.accesses 12015812 # DTB accesses -system.cpu0.itb.inst_hits 3834120 # ITB inst hits -system.cpu0.itb.inst_misses 4594 # ITB inst misses +system.cpu0.dtb.hits 17377662 # DTB hits +system.cpu0.dtb.misses 39769 # DTB misses +system.cpu0.dtb.accesses 17417431 # DTB accesses +system.cpu0.itb.inst_hits 4312814 # ITB inst hits +system.cpu0.itb.inst_misses 5659 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -566,542 +566,542 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1377 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1615 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1800 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1550 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 3838714 # ITB inst accesses -system.cpu0.itb.hits 3834120 # DTB hits -system.cpu0.itb.misses 4594 # DTB misses -system.cpu0.itb.accesses 3838714 # DTB accesses -system.cpu0.numCycles 55537360 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4318473 # ITB inst accesses +system.cpu0.itb.hits 4312814 # DTB hits +system.cpu0.itb.misses 5659 # DTB misses +system.cpu0.itb.accesses 4318473 # DTB accesses +system.cpu0.numCycles 91755333 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 5204671 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 3944570 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 296840 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3413720 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 2557176 # Number of BTB hits +system.cpu0.BPredUnit.lookups 5952266 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4505075 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 304047 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3800923 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2764349 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 459948 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 62294 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 10542481 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 27454720 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5204671 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3017124 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 6462624 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1388283 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 64249 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 17511747 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 6585 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 32170 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 74952 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 276 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 3831976 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 163321 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3020 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 35682594 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.003010 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.394306 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 686219 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 29965 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 12225669 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 31634782 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5952266 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3450568 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7438203 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1498517 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 86111 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 25429329 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5796 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 56004 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 89121 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 253 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4310960 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 168036 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2895 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 46396814 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.887686 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.274992 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 29226357 81.91% 81.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 522599 1.46% 83.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 706764 1.98% 85.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 578503 1.62% 86.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 534782 1.50% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 477839 1.34% 89.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 574033 1.61% 91.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 347894 0.97% 92.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2713823 7.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 38966492 83.99% 83.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 608768 1.31% 85.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 793531 1.71% 87.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 678621 1.46% 88.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 615872 1.33% 89.80% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 550838 1.19% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 680018 1.47% 92.45% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 365085 0.79% 93.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3137589 6.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 35682594 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.093715 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.494347 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 10901751 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 17564449 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 5807943 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 476099 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 932352 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 836954 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 56324 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 34505102 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 181228 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 932352 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 11416627 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 4596309 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 11321409 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 5748941 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1666956 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 33335658 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 999 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 358087 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 883877 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 110 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 33439844 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 151572898 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 151532196 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 40702 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 25794881 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 7644963 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 390853 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 354451 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4284069 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 6465672 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 4994701 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 841470 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 890235 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 31482040 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 658671 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 31606585 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 78774 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5676384 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13082280 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 117406 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 35682594 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.885770 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.514582 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 46396814 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.064871 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.344773 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12690058 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 25456221 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6703467 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 545759 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1001309 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 958631 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 66338 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 39766150 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 219028 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1001309 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 13289637 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 7972865 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15343248 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6631332 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2158423 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38589176 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 848 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 416461 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1242307 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 106 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 38596643 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175113710 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175069465 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 44245 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30775876 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 7820767 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 452714 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 409285 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5195885 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7781233 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5757511 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1120127 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1192401 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36577178 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 791583 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 40176979 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 83237 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5967561 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13599049 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 145097 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 46396814 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.865943 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.513269 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 22866556 64.08% 64.08% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4972769 13.94% 78.02% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 2602679 7.29% 85.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 1960706 5.49% 90.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1807368 5.07% 95.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 768762 2.15% 98.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 499053 1.40% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 158868 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 45833 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 30520128 65.78% 65.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5937185 12.80% 78.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3046653 6.57% 85.14% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2264959 4.88% 90.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2893477 6.24% 96.26% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 928258 2.00% 98.26% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 563400 1.21% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 186019 0.40% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 56735 0.12% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 35682594 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 46396814 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26479 2.83% 2.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 454 0.05% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 724595 77.49% 80.37% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 183504 19.63% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 26385 1.46% 1.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 453 0.03% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 1567613 86.92% 88.41% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 209022 11.59% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14281 0.05% 0.05% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 18849345 59.64% 59.68% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 42325 0.13% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 8 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 650 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.82% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 7946092 25.14% 84.96% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 4753870 15.04% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 25309 0.06% 0.06% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 21935197 54.60% 54.66% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48039 0.12% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 725 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.78% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 12687286 31.58% 86.36% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5480393 13.64% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 31606585 # Type of FU issued -system.cpu0.iq.rate 0.569105 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 935032 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.029583 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 99937037 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 37821084 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 28987180 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 10596 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 5532 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 4395 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 32521589 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5747 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 248744 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 40176979 # Type of FU issued +system.cpu0.iq.rate 0.437871 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1803473 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.044888 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 128665759 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 43343315 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34031138 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11205 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6096 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 4927 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 41949154 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5989 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 311358 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1245744 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3732 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 10021 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 530307 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1414489 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4027 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13694 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 607908 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 1901421 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5034 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 5397304 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5188 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 932352 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 3503280 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 78441 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 32200235 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 121893 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 6465672 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 4994701 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 398658 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 37609 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4704 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 10021 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 177778 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 116282 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 294060 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 31219910 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 7794602 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 386675 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1001309 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 6077720 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 124694 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37485087 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 95046 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7781233 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5757511 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 467034 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 52649 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4313 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13694 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 153875 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 138964 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 292839 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 39778235 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 12530314 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 398744 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 59524 # number of nop insts executed -system.cpu0.iew.exec_refs 12495671 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4074655 # Number of branches executed -system.cpu0.iew.exec_stores 4701069 # Number of stores executed -system.cpu0.iew.exec_rate 0.562142 # Inst execution rate -system.cpu0.iew.wb_sent 31018630 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 28991575 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 15563441 # num instructions producing a value -system.cpu0.iew.wb_consumers 30561631 # num instructions consuming a value +system.cpu0.iew.exec_nop 116326 # number of nop insts executed +system.cpu0.iew.exec_refs 17957262 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4780864 # Number of branches executed +system.cpu0.iew.exec_stores 5426948 # Number of stores executed +system.cpu0.iew.exec_rate 0.433525 # Inst execution rate +system.cpu0.iew.wb_sent 39572300 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34036065 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18213937 # num instructions producing a value +system.cpu0.iew.wb_consumers 35297892 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.522019 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.509248 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.370944 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.516006 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 19778635 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 26259365 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 5789320 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 541265 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 257580 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 34779040 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.755034 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.721723 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 23601687 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 31186721 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 6143896 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 646486 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 256571 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 45430638 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.686469 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.654503 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 24914736 71.64% 71.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 4928764 14.17% 85.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1604217 4.61% 90.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 793137 2.28% 92.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 618967 1.78% 94.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 369015 1.06% 95.54% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 397376 1.14% 96.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 185067 0.53% 97.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 967761 2.78% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33717084 74.22% 74.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5850006 12.88% 87.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1884843 4.15% 91.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 960822 2.11% 93.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 731888 1.61% 94.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 454898 1.00% 95.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 476885 1.05% 97.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 212485 0.47% 97.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1141727 2.51% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 34779040 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 19778635 # Number of instructions committed -system.cpu0.commit.committedOps 26259365 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 45430638 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23601687 # Number of instructions committed +system.cpu0.commit.committedOps 31186721 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 9684322 # Number of memory references committed -system.cpu0.commit.loads 5219928 # Number of loads committed -system.cpu0.commit.membars 194188 # Number of memory barriers committed -system.cpu0.commit.branches 3591028 # Number of branches committed -system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 23338580 # Number of committed integer instructions. -system.cpu0.commit.function_calls 422336 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 967761 # number cycles where commit BW limit reached +system.cpu0.commit.refs 11516347 # Number of memory references committed +system.cpu0.commit.loads 6366744 # Number of loads committed +system.cpu0.commit.membars 228774 # Number of memory barriers committed +system.cpu0.commit.branches 4268909 # Number of branches committed +system.cpu0.commit.fp_insts 4838 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 27636133 # Number of committed integer instructions. +system.cpu0.commit.function_calls 492618 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1141727 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 65245448 # The number of ROB reads -system.cpu0.rob.rob_writes 65031517 # The number of ROB writes -system.cpu0.timesIdled 363170 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 19854766 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5085481268 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 19754081 # Number of Instructions Simulated -system.cpu0.committedOps 26234811 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 19754081 # Number of Instructions Simulated -system.cpu0.cpi 2.811437 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.811437 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.355690 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.355690 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 145547438 # number of integer regfile reads -system.cpu0.int_regfile_writes 28450023 # number of integer regfile writes -system.cpu0.fp_regfile_reads 4554 # number of floating regfile reads -system.cpu0.fp_regfile_writes 434 # number of floating regfile writes -system.cpu0.misc_regfile_reads 38991088 # number of misc regfile reads -system.cpu0.misc_regfile_writes 443778 # number of misc regfile writes -system.cpu0.icache.replacements 345092 # number of replacements -system.cpu0.icache.tagsinuse 511.631515 # Cycle average of tags in use -system.cpu0.icache.total_refs 3456613 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 345604 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 10.001658 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6336390000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.631515 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999280 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999280 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3456613 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3456613 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3456613 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3456613 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3456613 # number of overall hits -system.cpu0.icache.overall_hits::total 3456613 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 375216 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 375216 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 375216 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 375216 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 375216 # number of overall misses -system.cpu0.icache.overall_misses::total 375216 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5700257984 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5700257984 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5700257984 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5700257984 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5700257984 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5700257984 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 3831829 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 3831829 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 3831829 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 3831829 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 3831829 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 3831829 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097921 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.097921 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097921 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.097921 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097921 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.097921 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15191.937401 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15191.937401 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15191.937401 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15191.937401 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1854487 # number of cycles access was blocked +system.cpu0.rob.rob_reads 80832744 # The number of ROB reads +system.cpu0.rob.rob_writes 75665562 # The number of ROB writes +system.cpu0.timesIdled 511317 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 45358519 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5047039822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23536584 # Number of Instructions Simulated +system.cpu0.committedOps 31121618 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23536584 # Number of Instructions Simulated +system.cpu0.cpi 3.898413 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.898413 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.256515 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.256515 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 183926116 # number of integer regfile reads +system.cpu0.int_regfile_writes 33429350 # number of integer regfile writes +system.cpu0.fp_regfile_reads 4511 # number of floating regfile reads +system.cpu0.fp_regfile_writes 934 # number of floating regfile writes +system.cpu0.misc_regfile_reads 45525801 # number of misc regfile reads +system.cpu0.misc_regfile_writes 515221 # number of misc regfile writes +system.cpu0.icache.replacements 402234 # number of replacements +system.cpu0.icache.tagsinuse 511.630403 # Cycle average of tags in use +system.cpu0.icache.total_refs 3875529 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 402746 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.622762 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6260006000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.630403 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999278 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999278 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3875529 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3875529 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3875529 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3875529 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3875529 # number of overall hits +system.cpu0.icache.overall_hits::total 3875529 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 435289 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 435289 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 435289 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 435289 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 435289 # number of overall misses +system.cpu0.icache.overall_misses::total 435289 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6419795491 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6419795491 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6419795491 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6419795491 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6419795491 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6419795491 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4310818 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4310818 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4310818 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4310818 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4310818 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4310818 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100976 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100976 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100976 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100976 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100976 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100976 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14748.352223 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14748.352223 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14748.352223 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14748.352223 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14748.352223 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14748.352223 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1456992 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 217 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 163 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 8546.023041 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 8938.601227 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 19422 # number of writebacks -system.cpu0.icache.writebacks::total 19422 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 29600 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 29600 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 29600 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 29600 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 29600 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 29600 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 345616 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 345616 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 345616 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 345616 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 345616 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 345616 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4268453987 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4268453987 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4268453987 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4268453987 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4268453987 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4268453987 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7615500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7615500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7615500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7615500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090196 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.090196 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.090196 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12350.278885 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 31582 # number of writebacks +system.cpu0.icache.writebacks::total 31582 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 32527 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 32527 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 32527 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 32527 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 32527 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 32527 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 402762 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 402762 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 402762 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 402762 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 402762 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 402762 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4809385492 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4809385492 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4809385492 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4809385492 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4809385492 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4809385492 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7376000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7376000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7376000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7376000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093431 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093431 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093431 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093431 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093431 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093431 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11941.011049 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11941.011049 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11941.011049 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11941.011049 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11941.011049 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11941.011049 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 232498 # number of replacements -system.cpu0.dcache.tagsinuse 430.308093 # Cycle average of tags in use -system.cpu0.dcache.total_refs 7750511 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 232862 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.283709 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 49672000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 430.308093 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.840445 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.840445 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 4805960 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 4805960 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 2599019 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 2599019 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 154744 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 154744 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 152410 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 152410 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7404979 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 7404979 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7404979 # number of overall hits -system.cpu0.dcache.overall_hits::total 7404979 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 332693 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 332693 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1446995 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1446995 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8853 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8853 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7938 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7938 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1779688 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1779688 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1779688 # number of overall misses -system.cpu0.dcache.overall_misses::total 1779688 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4680931500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4680931500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 59628860399 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 59628860399 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 99729000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 99729000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 85543000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 85543000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 64309791899 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 64309791899 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 64309791899 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 64309791899 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5138653 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 5138653 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4046014 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4046014 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 163597 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 163597 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160348 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 160348 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9184667 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 9184667 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9184667 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 9184667 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.064743 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.064743 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.357635 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.357635 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054115 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054115 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049505 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049505 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.193767 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.193767 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.193767 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.193767 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14069.822629 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14069.822629 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41208.753589 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41208.753589 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11264.994917 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11264.994917 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10776.392038 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10776.392038 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36135.430423 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36135.430423 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 3548990 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1931000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 344 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10316.831395 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 20542.553191 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 272390 # number of replacements +system.cpu0.dcache.tagsinuse 477.646995 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9259935 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 272772 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.947528 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 49645000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 477.646995 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.932904 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.932904 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5751664 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5751664 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3128629 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3128629 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172667 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 172667 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 169954 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 169954 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8880293 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8880293 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8880293 # number of overall hits +system.cpu0.dcache.overall_hits::total 8880293 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 380393 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 380393 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1568163 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1568163 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9112 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9112 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7881 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7881 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1948556 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1948556 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1948556 # number of overall misses +system.cpu0.dcache.overall_misses::total 1948556 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5112833000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5112833000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 57745298395 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 57745298395 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100839000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 100839000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 84292000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 84292000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 62858131395 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 62858131395 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 62858131395 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 62858131395 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6132057 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6132057 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4696792 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4696792 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 181779 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 181779 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 177835 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 177835 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10828849 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10828849 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10828849 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10828849 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062034 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.062034 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333880 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333880 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.050127 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.050127 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044316 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044316 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.179941 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.179941 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.179941 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.179941 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13440.922940 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13440.922940 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 36823.530714 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 36823.530714 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11066.615452 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11066.615452 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10695.597005 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10695.597005 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32258.827252 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32258.827252 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32258.827252 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32258.827252 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 3762493 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1470000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 438 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 79 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8590.166667 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 18607.594937 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 208397 # number of writebacks -system.cpu0.dcache.writebacks::total 208397 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 174332 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 174332 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1328335 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1328335 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 667 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 667 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1502667 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1502667 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1502667 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1502667 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 158361 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 158361 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 118660 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 118660 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8186 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8186 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7931 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7931 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 277021 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 277021 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 277021 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 277021 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2036266500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2036266500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4269140489 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4269140489 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66637500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66637500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 61703000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 61703000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6305406989 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6305406989 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6305406989 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6305406989 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9221981000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9221981000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 843217391 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 843217391 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10065198391 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10065198391 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030818 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030818 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029328 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029328 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.050038 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.050038 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049461 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.049461 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.030161 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030161 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.383693 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.383693 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35977.924229 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35977.924229 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8140.422673 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8140.422673 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7779.977304 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7779.977304 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 253456 # number of writebacks +system.cpu0.dcache.writebacks::total 253456 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 195063 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 195063 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1436472 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1436472 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 621 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 621 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1631535 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1631535 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1631535 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1631535 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 185330 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 185330 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131691 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131691 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8491 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8491 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7877 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7877 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 317021 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 317021 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 317021 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 317021 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2232196000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2232196000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4281157492 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4281157492 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67651500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67651500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 60619000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 60619000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6513353492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6513353492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6513353492 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6513353492 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 24166586500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 24166586500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 850308391 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 850308391 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 25016894891 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 25016894891 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030223 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030223 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028038 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028038 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046711 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046711 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044294 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044294 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029276 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029276 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029276 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029276 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12044.439648 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12044.439648 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32509.112179 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32509.112179 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7967.436109 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7967.436109 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7695.696331 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7695.696331 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20545.495384 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20545.495384 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20545.495384 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20545.495384 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1111,27 +1111,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 45335988 # DTB read hits -system.cpu1.dtb.read_misses 67766 # DTB read misses -system.cpu1.dtb.write_hits 7974825 # DTB write hits -system.cpu1.dtb.write_misses 20571 # DTB write misses +system.cpu1.dtb.read_hits 40314372 # DTB read hits +system.cpu1.dtb.read_misses 47835 # DTB read misses +system.cpu1.dtb.write_hits 7207214 # DTB write hits +system.cpu1.dtb.write_misses 14308 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2707 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 7654 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 597 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2204 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3789 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 426 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 1825 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 45403754 # DTB read accesses -system.cpu1.dtb.write_accesses 7995396 # DTB write accesses +system.cpu1.dtb.perms_faults 618 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 40362207 # DTB read accesses +system.cpu1.dtb.write_accesses 7221522 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 53310813 # DTB hits -system.cpu1.dtb.misses 88337 # DTB misses -system.cpu1.dtb.accesses 53399150 # DTB accesses -system.cpu1.itb.inst_hits 10447082 # ITB inst hits -system.cpu1.itb.inst_misses 7775 # ITB inst misses +system.cpu1.dtb.hits 47521586 # DTB hits +system.cpu1.dtb.misses 62143 # DTB misses +system.cpu1.dtb.accesses 47583729 # DTB accesses +system.cpu1.itb.inst_hits 9199147 # ITB inst hits +system.cpu1.itb.inst_misses 6537 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1140,546 +1140,542 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1562 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1398 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 5028 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1778 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 10454857 # ITB inst accesses -system.cpu1.itb.hits 10447082 # DTB hits -system.cpu1.itb.misses 7775 # DTB misses -system.cpu1.itb.accesses 10454857 # DTB accesses -system.cpu1.numCycles 361402922 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 9205684 # ITB inst accesses +system.cpu1.itb.hits 9199147 # DTB hits +system.cpu1.itb.misses 6537 # DTB misses +system.cpu1.itb.accesses 9205684 # DTB accesses +system.cpu1.numCycles 321589455 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 11186826 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 8978228 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 659649 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 7702930 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 6115228 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9609219 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7804241 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 456907 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 6466725 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5325877 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 914050 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 143881 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 24238168 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 79362685 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 11186826 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 7029278 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 17037334 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 5514806 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 104106 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 74528918 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 113982 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 165536 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 10441784 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 854309 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 4213 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 119977470 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.807329 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.185858 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 844527 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 50619 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 21504333 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 71435147 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9609219 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6170404 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 15136389 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4734420 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 89053 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 66067639 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5715 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 64771 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 143196 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 87 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 9197098 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 766779 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3914 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 106241109 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.815152 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.196213 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 102950411 85.81% 85.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 1027065 0.86% 86.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1252290 1.04% 87.71% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2222542 1.85% 89.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1450508 1.21% 90.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 763655 0.64% 91.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2450140 2.04% 93.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 546027 0.46% 93.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 7314832 6.10% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 91113370 85.76% 85.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 835957 0.79% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1038807 0.98% 87.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2054123 1.93% 89.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1283354 1.21% 90.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 639035 0.60% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2277082 2.14% 93.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 459375 0.43% 93.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 6540006 6.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 119977470 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030954 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.219596 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 25932861 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 74439661 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15341871 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 600655 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3662422 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1558576 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 123600 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 90136794 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 402223 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3662422 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 27545183 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32824542 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 37049772 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 14316379 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4579172 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 83629464 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2956 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 679775 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3317472 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 46248 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 88354418 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 386338466 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 386288470 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 49996 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 54988347 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 33366070 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 602019 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 524737 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8626692 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 16066963 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 9656417 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1282659 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1811239 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 75062782 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1031692 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 98462898 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 155624 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 21632122 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 61142717 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 223849 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 119977470 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.820678 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.544702 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 106241109 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.029880 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.222131 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 23013271 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 65947642 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 13617278 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 534194 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3128724 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1272359 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 103085 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 80569967 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 342001 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3128724 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 24438096 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 29197230 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 32706540 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 12706787 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4063732 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 74758294 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2356 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 627503 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2908939 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 45012 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 79187879 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 346602336 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 346555262 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 47074 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50022423 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 29165455 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 496148 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 429704 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7532124 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 14054260 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8745175 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1095062 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1520090 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 67170682 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 857343 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 88258087 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 108704 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18559774 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 53338169 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 154632 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 106241109 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.830734 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.556038 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 85994383 71.68% 71.68% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 9640016 8.03% 79.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 5133014 4.28% 83.99% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 4263453 3.55% 87.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 11149849 9.29% 96.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 2119505 1.77% 98.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1269612 1.06% 99.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 309202 0.26% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 98436 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 76008182 71.54% 71.54% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8446540 7.95% 79.49% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4482838 4.22% 83.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3826420 3.60% 87.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 9985833 9.40% 96.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1963466 1.85% 98.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1174590 1.11% 99.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 267511 0.25% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 85729 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 119977470 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 106241109 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 44202 0.54% 0.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 979 0.01% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7732056 95.26% 95.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 339451 4.18% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 34820 0.48% 0.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 995 0.01% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 6868408 95.11% 95.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 317335 4.39% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 92819 0.09% 0.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 43271411 43.95% 44.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 69911 0.07% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 29 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 39 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1782 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.11% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 46626317 47.35% 91.47% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 8400570 8.53% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 81809 0.09% 0.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 39074007 44.27% 44.37% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 63191 0.07% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 5 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1634 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.44% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 41444924 46.96% 91.40% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7592491 8.60% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 98462898 # Type of FU issued -system.cpu1.iq.rate 0.272446 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 8116688 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.082434 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 325251459 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 97743765 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 61686980 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12182 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6832 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5554 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 106480420 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6347 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 431690 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 88258087 # Type of FU issued +system.cpu1.iq.rate 0.274443 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7221558 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.081823 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 290137702 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 86602000 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 55480726 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11865 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6384 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5360 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 95391603 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6233 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 377691 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4883583 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 7497 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 24780 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1835710 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4014151 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6631 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 21303 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1605227 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 32214526 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1149867 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 28717238 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1149940 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3662422 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25277331 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 367624 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 76304263 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 229674 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 16066963 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 9656417 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 636963 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 63488 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 8504 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 24780 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 400468 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 244624 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 645092 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 95561838 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 45782046 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2901060 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3128724 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 22478642 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 328290 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 68173106 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 141945 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 14054260 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8745175 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 539434 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 62530 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3755 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 21303 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 237741 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 202628 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 440369 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 85609132 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 40707747 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2648955 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 209789 # number of nop insts executed -system.cpu1.iew.exec_refs 54078244 # number of memory reference insts executed -system.cpu1.iew.exec_branches 8068913 # Number of branches executed -system.cpu1.iew.exec_stores 8296198 # Number of stores executed -system.cpu1.iew.exec_rate 0.264419 # Inst execution rate -system.cpu1.iew.wb_sent 94191755 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 61692534 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 33977338 # num instructions producing a value -system.cpu1.iew.wb_consumers 61891561 # num instructions consuming a value +system.cpu1.iew.exec_nop 145081 # number of nop insts executed +system.cpu1.iew.exec_refs 48220727 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7143156 # Number of branches executed +system.cpu1.iew.exec_stores 7512980 # Number of stores executed +system.cpu1.iew.exec_rate 0.266206 # Inst execution rate +system.cpu1.iew.wb_sent 84396881 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 55486086 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30755357 # num instructions producing a value +system.cpu1.iew.wb_consumers 55849815 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.170703 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.548982 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.172537 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.550680 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 42383808 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 53979911 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 22261112 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 807843 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 569017 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 116371049 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.463860 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.434767 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 38569031 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 49069302 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 19027054 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 702711 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 384240 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 103162057 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.475653 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.464816 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 97273421 83.59% 83.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 9394437 8.07% 91.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2575050 2.21% 93.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1580988 1.36% 95.23% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1207821 1.04% 96.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 698590 0.60% 96.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1120414 0.96% 97.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 516932 0.44% 98.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 2003396 1.72% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 86125230 83.49% 83.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8314170 8.06% 91.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2284328 2.21% 93.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1318858 1.28% 95.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1066734 1.03% 96.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 616185 0.60% 96.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1058049 1.03% 97.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 494277 0.48% 98.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1884226 1.83% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 116371049 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 42383808 # Number of instructions committed -system.cpu1.commit.committedOps 53979911 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 103162057 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38569031 # Number of instructions committed +system.cpu1.commit.committedOps 49069302 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 19004087 # Number of memory references committed -system.cpu1.commit.loads 11183380 # Number of loads committed -system.cpu1.commit.membars 242516 # Number of memory barriers committed -system.cpu1.commit.branches 6784179 # Number of branches committed -system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 48067133 # Number of committed integer instructions. -system.cpu1.commit.function_calls 633379 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 2003396 # number cycles where commit BW limit reached +system.cpu1.commit.refs 17180057 # Number of memory references committed +system.cpu1.commit.loads 10040109 # Number of loads committed +system.cpu1.commit.membars 207982 # Number of memory barriers committed +system.cpu1.commit.branches 6108113 # Number of branches committed +system.cpu1.commit.fp_insts 5310 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 43785233 # Number of committed integer instructions. +system.cpu1.commit.function_calls 563417 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1884226 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 189385035 # The number of ROB reads -system.cpu1.rob.rob_writes 156267900 # The number of ROB writes -system.cpu1.timesIdled 1564769 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 241425452 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4780203327 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 42257981 # Number of Instructions Simulated -system.cpu1.committedOps 53854084 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 42257981 # Number of Instructions Simulated -system.cpu1.cpi 8.552300 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.552300 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.116928 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.116928 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 430079753 # number of integer regfile reads -system.cpu1.int_regfile_writes 64515100 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4419 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2066 # number of floating regfile writes -system.cpu1.misc_regfile_reads 102262967 # number of misc regfile reads -system.cpu1.misc_regfile_writes 513108 # number of misc regfile writes -system.cpu1.icache.replacements 714529 # number of replacements -system.cpu1.icache.tagsinuse 498.761723 # Cycle average of tags in use -system.cpu1.icache.total_refs 9665211 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 715041 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.517003 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74296656000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.761723 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974144 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974144 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 9665211 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 9665211 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 9665211 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 9665211 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 9665211 # number of overall hits -system.cpu1.icache.overall_hits::total 9665211 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 776521 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 776521 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 776521 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 776521 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 776521 # number of overall misses -system.cpu1.icache.overall_misses::total 776521 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11390030990 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 11390030990 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 11390030990 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 11390030990 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 11390030990 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 11390030990 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 10441732 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 10441732 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 10441732 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 10441732 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 10441732 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 10441732 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074367 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.074367 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074367 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.074367 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074367 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.074367 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14668.026995 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14668.026995 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14668.026995 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14668.026995 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1572992 # number of cycles access was blocked +system.cpu1.rob.rob_reads 168322862 # The number of ROB reads +system.cpu1.rob.rob_writes 139443210 # The number of ROB writes +system.cpu1.timesIdled 1396987 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 215348346 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4817788385 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38483753 # Number of Instructions Simulated +system.cpu1.committedOps 48984024 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38483753 # Number of Instructions Simulated +system.cpu1.cpi 8.356499 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.356499 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.119667 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.119667 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 385614321 # number of integer regfile reads +system.cpu1.int_regfile_writes 58138574 # number of integer regfile writes +system.cpu1.fp_regfile_reads 3969 # number of floating regfile reads +system.cpu1.fp_regfile_writes 1880 # number of floating regfile writes +system.cpu1.misc_regfile_reads 91635789 # number of misc regfile reads +system.cpu1.misc_regfile_writes 441645 # number of misc regfile writes +system.cpu1.icache.replacements 628575 # number of replacements +system.cpu1.icache.tagsinuse 498.649539 # Cycle average of tags in use +system.cpu1.icache.total_refs 8518604 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 629087 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.541218 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 73946666000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.649539 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.973925 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.973925 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 8518604 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 8518604 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 8518604 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 8518604 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 8518604 # number of overall hits +system.cpu1.icache.overall_hits::total 8518604 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 678443 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 678443 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 678443 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 678443 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 678443 # number of overall misses +system.cpu1.icache.overall_misses::total 678443 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9864551499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 9864551499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 9864551499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 9864551499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 9864551499 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 9864551499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 9197047 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 9197047 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 9197047 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 9197047 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 9197047 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 9197047 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073767 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.073767 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073767 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.073767 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073767 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.073767 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14539.985672 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14539.985672 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14539.985672 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14539.985672 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14539.985672 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14539.985672 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 932999 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 238 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 153 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6609.210084 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 6098.032680 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 32858 # 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number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 715076 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8506439492 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8506439492 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8506439492 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8506439492 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8506439492 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8506439492 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2572500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2572500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2572500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 2572500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068483 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.068483 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.068483 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11895.853716 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 30976 # number of writebacks +system.cpu1.icache.writebacks::total 30976 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 49327 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 49327 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 49327 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 49327 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 49327 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 49327 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 629116 # 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number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2676000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2676000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2676000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 2676000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068404 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068404 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068404 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.068404 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068404 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.068404 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11747.122151 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11747.122151 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11747.122151 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11747.122151 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11747.122151 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11747.122151 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 417022 # number of replacements -system.cpu1.dcache.tagsinuse 464.475329 # Cycle average of tags in use -system.cpu1.dcache.total_refs 15242379 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 417534 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 36.505719 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 72565634000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 464.475329 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.907178 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.907178 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 10057492 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10057492 # 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number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 57173185397 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 177446500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 177446500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 91928500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 91928500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 64316759897 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 64316759897 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 64316759897 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 64316759897 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 10530495 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 10530495 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6615371 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6615371 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 141213 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 141213 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 130601 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 130601 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 17145866 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 17145866 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 17145866 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 17145866 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044917 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.044917 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.260965 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.260965 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104573 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104573 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081010 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.081010 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.128275 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.128275 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.128275 # 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average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 29243.132109 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29243.132109 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 29243.132109 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 15169067 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5303000 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 149 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4702.128642 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 35590.604027 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 365990 # number of replacements +system.cpu1.dcache.tagsinuse 486.374853 # Cycle average of tags in use +system.cpu1.dcache.total_refs 13437990 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 366502 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 36.665530 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70078369000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 486.374853 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.949951 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.949951 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8795505 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8795505 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4385128 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4385128 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 106581 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 106581 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 102282 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 102282 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 13180633 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 13180633 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 13180633 # number of overall hits +system.cpu1.dcache.overall_hits::total 13180633 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 408153 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 408153 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1582783 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1582783 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13916 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13916 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10800 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10800 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1990936 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1990936 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1990936 # number of overall misses +system.cpu1.dcache.overall_misses::total 1990936 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5766799000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5766799000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 55285236443 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 55285236443 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 141367500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 141367500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 89573500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 89573500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 61052035443 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 61052035443 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 61052035443 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 61052035443 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9203658 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9203658 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5967911 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5967911 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 120497 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 120497 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 113082 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 113082 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 15171569 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 15171569 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 15171569 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 15171569 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044347 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.044347 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.265216 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.265216 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115488 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115488 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095506 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095506 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131228 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.131228 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131228 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.131228 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14129.012895 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14129.012895 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34929.132069 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34929.132069 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10158.630354 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10158.630354 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8293.842593 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8293.842593 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30664.991463 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 30664.991463 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30664.991463 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 30664.991463 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 12254574 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5966500 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3013 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 167 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4067.233322 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 35727.544910 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 346093 # number of writebacks -system.cpu1.dcache.writebacks::total 346093 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 202550 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 202550 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1548902 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1548902 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1254 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1254 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1751452 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1751452 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1751452 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1751452 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 270453 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 270453 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 177475 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 177475 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13513 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13513 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10575 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10575 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 447928 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 447928 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 447928 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 447928 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3409672000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3409672000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5551338067 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5551338067 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 121446000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 121446000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60146500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60146500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8961010067 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8961010067 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8961010067 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8961010067 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 138179503000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 138179503000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41662340533 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41662340533 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179841843533 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179841843533 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025683 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025683 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026828 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026828 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.095692 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.095692 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080972 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.080972 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026125 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026125 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12607.262630 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12607.262630 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31279.549610 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31279.549610 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8987.345519 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8987.345519 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5687.612293 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5687.612293 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 330007 # number of writebacks +system.cpu1.dcache.writebacks::total 330007 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172901 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 172901 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1420692 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1420692 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1265 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1265 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1593593 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1593593 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1593593 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1593593 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 235252 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 235252 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162091 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 162091 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12651 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12651 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10796 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10796 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 397343 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 397343 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 397343 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 397343 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2772800000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2772800000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5167139074 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5167139074 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88580000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88580000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57154000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57154000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7939939074 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7939939074 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7939939074 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7939939074 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 123239389500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 123239389500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41654166350 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41654166350 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 164893555850 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 164893555850 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025561 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025561 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027160 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027160 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104990 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104990 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095471 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095471 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026190 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026190 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026190 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026190 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11786.509785 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11786.509785 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31878.013425 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31878.013425 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7001.818038 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7001.818038 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5293.997777 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5293.997777 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19982.581986 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19982.581986 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19982.581986 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19982.581986 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1701,18 +1697,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308180699879 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1308180699879 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308180699879 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1308180699879 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308136748055 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1308136748055 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308136748055 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1308136748055 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 36058 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 42935 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 61621 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 54742 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |