diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | 6154 |
1 files changed, 3080 insertions, 3074 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 1b6a9683d..787619867 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,166 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.627261 # Number of seconds simulated -sim_ticks 2627260787000 # Number of ticks simulated -final_tick 2627260787000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.837504 # Number of seconds simulated +sim_ticks 2837504217500 # Number of ticks simulated +final_tick 2837504217500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73269 # Simulator instruction rate (inst/s) -host_op_rate 88893 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1598642516 # Simulator tick rate (ticks/s) -host_mem_usage 609448 # Number of bytes of host memory used -host_seconds 1643.43 # Real time elapsed on the host -sim_insts 120413300 # Number of instructions simulated -sim_ops 146090184 # Number of ops (including micro ops) simulated +host_inst_rate 89459 # Simulator instruction rate (inst/s) +host_op_rate 108491 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2108642938 # Simulator tick rate (ticks/s) +host_mem_usage 665360 # Number of bytes of host memory used +host_seconds 1345.65 # Real time elapsed on the host +sim_insts 120381204 # Number of instructions simulated +sim_ops 145991739 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 1536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1139008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1190376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8167488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1298560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1282472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8427712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 326368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 665684 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 594880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 172400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 575316 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 374464 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12087580 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1139008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 326368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1465376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8694784 # Number of bytes written to this memory +system.physmem.bytes_read::total 12134316 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1298560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 172400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1470960 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8568768 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8712348 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 24 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 20044 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 19120 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 127617 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8586332 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 28 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 22537 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20559 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 131683 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5167 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10422 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 9295 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2762 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9010 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5851 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 191724 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 135856 # Number of write requests responded to by this memory +system.physmem.num_reads::total 192455 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 133887 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140247 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 433534 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 453086 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3108747 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 124224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 253376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 226426 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4600830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 433534 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 124224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 557758 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3309448 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6670 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3316134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3309448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 585 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 433534 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 459756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3108747 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 124224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 253391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 226426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7916964 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 191724 # Number of read requests accepted -system.physmem.writeReqs 140247 # Number of write requests accepted -system.physmem.readBursts 191724 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 140247 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12260288 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue -system.physmem.bytesWritten 8725248 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12087580 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8712348 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_writes::total 138278 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 457642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 451972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2970114 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 60758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 202754 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 131969 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4276405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 457642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 60758 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3019826 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3026016 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3019826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 457642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 458148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2970114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 60758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 202768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 131969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7302420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 192456 # Number of read requests accepted +system.physmem.writeReqs 138278 # Number of write requests accepted +system.physmem.readBursts 192456 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 138278 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12307136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9984 # Total number of bytes read from write queue +system.physmem.bytesWritten 8599232 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12134380 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8586332 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 156 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 50731 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11367 # Per bank write bursts -system.physmem.perBankRdBursts::1 11306 # Per bank write bursts -system.physmem.perBankRdBursts::2 12534 # Per bank write bursts -system.physmem.perBankRdBursts::3 11925 # Per bank write bursts -system.physmem.perBankRdBursts::4 14392 # Per bank write bursts -system.physmem.perBankRdBursts::5 11995 # Per bank write bursts -system.physmem.perBankRdBursts::6 12528 # Per bank write bursts -system.physmem.perBankRdBursts::7 12413 # Per bank write bursts -system.physmem.perBankRdBursts::8 12465 # Per bank write bursts -system.physmem.perBankRdBursts::9 12343 # Per bank write bursts -system.physmem.perBankRdBursts::10 12048 # Per bank write bursts -system.physmem.perBankRdBursts::11 11291 # Per bank write bursts -system.physmem.perBankRdBursts::12 11598 # Per bank write bursts -system.physmem.perBankRdBursts::13 11714 # Per bank write bursts -system.physmem.perBankRdBursts::14 10851 # Per bank write bursts -system.physmem.perBankRdBursts::15 10797 # Per bank write bursts -system.physmem.perBankWrBursts::0 8020 # Per bank write bursts -system.physmem.perBankWrBursts::1 8176 # Per bank write bursts -system.physmem.perBankWrBursts::2 9316 # Per bank write bursts -system.physmem.perBankWrBursts::3 8567 # Per bank write bursts -system.physmem.perBankWrBursts::4 8317 # Per bank write bursts -system.physmem.perBankWrBursts::5 8617 # Per bank write bursts -system.physmem.perBankWrBursts::6 9080 # Per bank write bursts -system.physmem.perBankWrBursts::7 8981 # Per bank write bursts -system.physmem.perBankWrBursts::8 9059 # Per bank write bursts -system.physmem.perBankWrBursts::9 8883 # Per bank write bursts -system.physmem.perBankWrBursts::10 8732 # Per bank write bursts -system.physmem.perBankWrBursts::11 8494 # Per bank write bursts -system.physmem.perBankWrBursts::12 8573 # Per bank write bursts -system.physmem.perBankWrBursts::13 8275 # Per bank write bursts -system.physmem.perBankWrBursts::14 7766 # Per bank write bursts -system.physmem.perBankWrBursts::15 7476 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 65662 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11960 # Per bank write bursts +system.physmem.perBankRdBursts::1 11050 # Per bank write bursts +system.physmem.perBankRdBursts::2 12052 # Per bank write bursts +system.physmem.perBankRdBursts::3 12058 # Per bank write bursts +system.physmem.perBankRdBursts::4 14137 # Per bank write bursts +system.physmem.perBankRdBursts::5 12072 # Per bank write bursts +system.physmem.perBankRdBursts::6 12490 # Per bank write bursts +system.physmem.perBankRdBursts::7 12293 # Per bank write bursts +system.physmem.perBankRdBursts::8 12129 # Per bank write bursts +system.physmem.perBankRdBursts::9 11971 # Per bank write bursts +system.physmem.perBankRdBursts::10 11835 # Per bank write bursts +system.physmem.perBankRdBursts::11 10924 # Per bank write bursts +system.physmem.perBankRdBursts::12 11792 # Per bank write bursts +system.physmem.perBankRdBursts::13 12532 # Per bank write bursts +system.physmem.perBankRdBursts::14 11740 # Per bank write bursts +system.physmem.perBankRdBursts::15 11264 # Per bank write bursts +system.physmem.perBankWrBursts::0 8435 # Per bank write bursts +system.physmem.perBankWrBursts::1 7998 # Per bank write bursts +system.physmem.perBankWrBursts::2 8830 # Per bank write bursts +system.physmem.perBankWrBursts::3 8684 # Per bank write bursts +system.physmem.perBankWrBursts::4 8112 # Per bank write bursts +system.physmem.perBankWrBursts::5 8575 # Per bank write bursts +system.physmem.perBankWrBursts::6 8926 # Per bank write bursts +system.physmem.perBankWrBursts::7 8709 # Per bank write bursts +system.physmem.perBankWrBursts::8 8491 # Per bank write bursts +system.physmem.perBankWrBursts::9 8366 # Per bank write bursts +system.physmem.perBankWrBursts::10 8474 # Per bank write bursts +system.physmem.perBankWrBursts::11 8070 # Per bank write bursts +system.physmem.perBankWrBursts::12 8488 # Per bank write bursts +system.physmem.perBankWrBursts::13 8576 # Per bank write bursts +system.physmem.perBankWrBursts::14 8125 # Per bank write bursts +system.physmem.perBankWrBursts::15 7504 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 2627260507500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 2837503950500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) -system.physmem.readPktSize::4 3086 # Read request sizes (log2) +system.physmem.readPktSize::4 3087 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 188059 # Read request sizes (log2) +system.physmem.readPktSize::6 188790 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 135856 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 61031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 73227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10004 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7158 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6223 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5068 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4443 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 829 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 578 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 273 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 133887 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 61458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 73949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9980 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 792 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -188,160 +188,159 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9044 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86649 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 242.189431 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 136.582911 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.571271 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46399 53.55% 53.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16583 19.14% 72.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5986 6.91% 79.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3348 3.86% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2763 3.19% 86.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1550 1.79% 88.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1005 1.16% 89.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 914 1.05% 90.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8101 9.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86649 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6686 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.651211 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 549.102387 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6684 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6686 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6686 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.390667 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.828394 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.276627 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5432 81.24% 81.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 492 7.36% 88.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 97 1.45% 90.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 153 2.29% 92.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 34 0.51% 92.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 125 1.87% 94.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 42 0.63% 95.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 20 0.30% 95.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 24 0.36% 96.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 25 0.37% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.09% 96.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.09% 96.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 159 2.38% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.09% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 24 0.36% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 8 0.12% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.04% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.03% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.12% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6686 # Writes before turning the bus around for reads -system.physmem.totQLat 6416960776 # Total ticks spent queuing -system.physmem.totMemAccLat 10008842026 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 957835000 # Total ticks spent in databus transfers -system.physmem.avgQLat 33497.21 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52247.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.67 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.32 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.60 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.32 # Average system write bandwidth in MiByte/s +system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 86935 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 240.482751 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 135.610645 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.163398 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46710 53.73% 53.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16982 19.53% 73.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5795 6.67% 79.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3191 3.67% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2666 3.07% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1598 1.84% 88.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 941 1.08% 89.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 911 1.05% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8141 9.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86935 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6558 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.322812 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 574.114177 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6556 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6558 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6558 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.488411 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.922621 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.969935 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5288 80.63% 80.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 495 7.55% 88.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 103 1.57% 89.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 154 2.35% 92.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 30 0.46% 92.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 130 1.98% 94.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 43 0.66% 95.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 19 0.29% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 29 0.44% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 20 0.30% 96.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 10 0.15% 96.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 12 0.18% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 145 2.21% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 7 0.11% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.08% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 33 0.50% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 10 0.15% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.15% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6558 # Writes before turning the bus around for reads +system.physmem.totQLat 6213827144 # Total ticks spent queuing +system.physmem.totMemAccLat 9819433394 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 961495000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32313.19 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 51063.10 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.03 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.03 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing -system.physmem.readRowHits 159898 # Number of row buffer hits during reads -system.physmem.writeRowHits 81351 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.66 # Row buffer hit rate for writes -system.physmem.avgGap 7914126.56 # Average gap between requests -system.physmem.pageHitRate 73.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 337168440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 183970875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 767988000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 447599520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 171599840880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 75926466675 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1509753884250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1759016918640 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.525234 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2511501025755 # Time in different power states -system.physmem_0.memoryStateTime::REF 87729980000 # Time in different power states +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.17 # Average write queue length when enqueuing +system.physmem.readRowHits 160530 # Number of row buffer hits during reads +system.physmem.writeRowHits 79197 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.93 # Row buffer hit rate for writes +system.physmem.avgGap 8579414.12 # Average gap between requests +system.physmem.pageHitRate 73.38 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 333396000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 181912500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 765273600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 442383120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185331978000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 80482301685 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1631904131250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1899441376155 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.405614 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2714718220190 # Time in different power states +system.physmem_0.memoryStateTime::REF 94750240000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 28029087995 # Time in different power states +system.physmem_0.memoryStateTime::ACT 28035696060 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 317898000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 173456250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 726226800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 435831840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 171599840880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 75533290650 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1510098775500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1758885319920 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.475144 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2512077352355 # Time in different power states -system.physmem_1.memoryStateTime::REF 87729980000 # Time in different power states +system.physmem_1.actEnergy 323832600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 176694375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 734658600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 428289120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185331978000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80147926575 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1632197442750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1899340822020 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.370176 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2715209176165 # Time in different power states +system.physmem_1.memoryStateTime::REF 94750240000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27453418145 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27544740085 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory @@ -352,30 +351,30 @@ system.realview.nvmem.bytes_inst_read::total 320 system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 49 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 73 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 122 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 49 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 73 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 122 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 49 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 73 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 122 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 22632354 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14659623 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 908184 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 13749139 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 10145845 # Number of BTB hits +system.cpu0.branchPred.lookups 53984881 # Number of BP lookups +system.cpu0.branchPred.condPredicted 25029279 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1031275 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 32703051 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 24288553 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 73.792584 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3729563 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 29268 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 74.269991 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15579180 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 33867 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -406,78 +405,90 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 62082 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 62082 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 23874 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18654 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 19554 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 42528 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 489.830229 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 2960.338749 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 41379 97.30% 97.30% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 822 1.93% 99.23% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 148 0.35% 99.58% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 139 0.33% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 71885 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 71885 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26706 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21113 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 24066 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 47819 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 500.773751 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 3132.734175 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 46517 97.28% 97.28% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 936 1.96% 99.23% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 174 0.36% 99.60% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 150 0.31% 99.91% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::32768-40959 13 0.03% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.05% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-73727 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 42528 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 15147 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 9846.471248 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 8208.075631 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 8231.250252 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 15054 99.39% 99.39% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 70 0.46% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 21 0.14% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 15147 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 97524095656 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.460762 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.504971 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 97474132156 99.95% 99.95% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 37222000 0.04% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 6333500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 3452500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 1280500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 673000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 722500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 263000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 16500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 97524095656 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5018 79.05% 79.05% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1330 20.95% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6348 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 62082 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.04% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::106496-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::114688-122879 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 47819 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 18759 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 11059.171598 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9588.566879 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7711.880133 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 18631 99.32% 99.32% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 106 0.57% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 16 0.09% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 4 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 18759 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 84429292764 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.657402 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.487897 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 29095217424 34.46% 34.46% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 55270258340 65.46% 99.92% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2 29607500 0.04% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::3 15656000 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4 4826500 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::5 2762000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6 4173000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::7 1494500 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8 1031000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::9 697500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10 703000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::11 393500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12 1099500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::13 296000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14 143000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::15 934000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 84429292764 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5818 79.12% 79.12% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1535 20.88% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 7353 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71885 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 62082 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6348 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71885 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7353 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6348 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 68430 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7353 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 79238 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 16776749 # DTB read hits -system.cpu0.dtb.read_misses 53234 # DTB read misses -system.cpu0.dtb.write_hits 13912942 # DTB write hits -system.cpu0.dtb.write_misses 8848 # DTB write misses +system.cpu0.dtb.read_hits 24461690 # DTB read hits +system.cpu0.dtb.read_misses 61076 # DTB read misses +system.cpu0.dtb.write_hits 18142518 # DTB write hits +system.cpu0.dtb.write_misses 10809 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3447 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 80 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2058 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3811 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 171 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2460 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 829 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 16829983 # DTB read accesses -system.cpu0.dtb.write_accesses 13921790 # DTB write accesses +system.cpu0.dtb.perms_faults 1016 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 24522766 # DTB read accesses +system.cpu0.dtb.write_accesses 18153327 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 30689691 # DTB hits -system.cpu0.dtb.misses 62082 # DTB misses -system.cpu0.dtb.accesses 30751773 # DTB accesses +system.cpu0.dtb.hits 42604208 # DTB hits +system.cpu0.dtb.misses 71885 # DTB misses +system.cpu0.dtb.accesses 42676093 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -507,53 +518,56 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 10470 # Table walker walks requested -system.cpu0.itb.walker.walksShort 10470 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4275 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6082 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 113 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 10357 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 430.336970 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 2100.288015 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 9961 96.18% 96.18% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 126 1.22% 97.39% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 203 1.96% 99.35% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 38 0.37% 99.72% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 13 0.13% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 10 0.10% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::36864-40959 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 10357 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2692 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 11506.129272 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 10069.776184 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6522.127356 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 2498 92.79% 92.79% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 161 5.98% 98.77% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 32 1.19% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2692 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 20202424328 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.966577 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.179934 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 675884500 3.35% 3.35% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 19525926328 96.65% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 564000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 49500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 20202424328 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2260 87.63% 87.63% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 319 12.37% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2579 # Table walker page sizes translated +system.cpu0.itb.walker.walks 10900 # Table walker walks requested +system.cpu0.itb.walker.walksShort 10900 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4234 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6533 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 133 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 10767 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 543.187517 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 2520.119999 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 10263 95.32% 95.32% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 147 1.37% 96.68% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 248 2.30% 98.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 60 0.56% 99.54% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 13 0.12% 99.67% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 18 0.17% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 11 0.10% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::28672-32767 3 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 10767 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 3015 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 13136.152570 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 12059.608238 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6103.776811 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 2740 90.88% 90.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 236 7.83% 98.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 36 1.19% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-65535 2 0.07% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 3015 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 20004739824 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.958205 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.200359 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 836985000 4.18% 4.18% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 19166939824 95.81% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 745000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 20004739824 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2539 88.10% 88.10% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 343 11.90% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2882 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10470 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10470 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10900 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10900 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2579 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2579 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 13049 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 35710587 # ITB inst hits -system.cpu0.itb.inst_misses 10470 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2882 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2882 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 13782 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 74221386 # ITB inst hits +system.cpu0.itb.inst_misses 10900 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -562,1046 +576,1042 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2356 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2623 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1940 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 35721057 # ITB inst accesses -system.cpu0.itb.hits 35710587 # DTB hits -system.cpu0.itb.misses 10470 # DTB misses -system.cpu0.itb.accesses 35721057 # DTB accesses -system.cpu0.numCycles 126659372 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 74232286 # ITB inst accesses +system.cpu0.itb.hits 74221386 # DTB hits +system.cpu0.itb.misses 10900 # DTB misses +system.cpu0.itb.accesses 74232286 # DTB accesses +system.cpu0.numCycles 211089412 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 17871987 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 106431260 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 22632354 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 13875408 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 101673133 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2651880 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 146874 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 68068 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 354842 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 428688 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 93530 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 35711195 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 256145 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 4738 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 121963062 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.052824 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.258485 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 21154368 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 200477778 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 53984881 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 39867733 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 180634648 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 5887980 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 163875 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 73228 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 386540 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 467083 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 106682 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 74221667 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 284223 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 5134 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 205930414 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.189818 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.306225 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 62962688 51.62% 51.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 20162814 16.53% 68.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 8269817 6.78% 74.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 30567743 25.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 98513446 47.84% 47.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 31147875 15.13% 62.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 14935472 7.25% 70.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 61333621 29.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 121963062 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.178687 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.840295 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18684987 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58693341 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 38833256 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4747637 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1003841 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 2912386 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 326313 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 104496141 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3704345 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1003841 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 24126481 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12572099 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 34554184 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 38013567 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 11692890 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 99684423 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 977099 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1404281 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 150386 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 54053 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 7679999 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 103244507 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 455598825 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 114217475 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9462 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 92488092 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 10756412 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1189033 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1051673 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11830745 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 17693579 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 15395073 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1633265 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2155883 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 96874005 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1635627 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 95096979 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 454397 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 8909178 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 20852751 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 116081 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 121963062 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.779720 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.027198 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 205930414 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.255744 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.949729 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26441792 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 111116512 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 60639193 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 5147176 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2585741 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 3185045 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 362773 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 158832709 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4189276 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 2585741 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 35360438 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 13326930 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 85149071 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 56726750 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 12781484 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 141877128 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1133387 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1508513 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 170712 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 63171 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 8443572 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 146064106 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 654194105 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 157626069 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 10971 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 133804111 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12259992 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 2731692 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 2584898 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 22953113 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 25474104 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 19753680 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1758400 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2611655 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 138738893 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1764680 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 136614694 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 514032 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11572613 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 23827744 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 127449 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 205930414 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.663402 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.962674 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 68765776 56.38% 56.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 22213388 18.21% 74.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 21122370 17.32% 91.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 8807290 7.22% 99.14% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1054209 0.86% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 29 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 127115623 61.73% 61.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 34474239 16.74% 78.47% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 32051807 15.56% 94.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 11118185 5.40% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1170514 0.57% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 46 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 121963062 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 205930414 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 8813581 40.35% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 132 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5351630 24.50% 64.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 7678552 35.15% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 11113465 43.69% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 76 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5930869 23.32% 67.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8390890 32.99% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2272 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 62602265 65.83% 65.83% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 87841 0.09% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 7143 0.01% 65.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 65.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.93% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 17444547 18.34% 84.28% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 14952910 15.72% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2315 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 92049537 67.38% 67.38% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 112728 0.08% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 8149 0.01% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 25196866 18.44% 85.91% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 19245098 14.09% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 95096979 # Type of FU issued -system.cpu0.iq.rate 0.750809 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 21843895 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.229701 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 334422549 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 107425966 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 93117016 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 32763 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11378 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 9790 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 116917216 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 21386 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 346137 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 136614694 # Type of FU issued +system.cpu0.iq.rate 0.647189 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 25435300 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.186183 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 505071342 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 152083684 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 132900099 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 37792 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 13226 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 11443 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 162023237 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 24442 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 380983 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1858057 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2517 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18608 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 952368 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2125903 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2726 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 20804 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1085884 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 100941 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 343903 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 121982 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 393712 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1003841 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1765434 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 210085 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 98680740 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2585741 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1952892 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 228879 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 140712950 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 17693579 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 15395073 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 848677 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 24988 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 163669 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18608 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 265563 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 373947 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 639510 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 94079743 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 17020662 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 955277 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 25474104 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 19753680 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 902814 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 28763 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 175994 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 20804 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 314280 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 420638 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 734918 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 135458636 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 24717807 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1084310 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 171108 # number of nop insts executed -system.cpu0.iew.exec_refs 31795600 # number of memory reference insts executed -system.cpu0.iew.exec_branches 15818182 # Number of branches executed -system.cpu0.iew.exec_stores 14774938 # Number of stores executed -system.cpu0.iew.exec_rate 0.742778 # Inst execution rate -system.cpu0.iew.wb_sent 93557624 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 93126806 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 48392376 # num instructions producing a value -system.cpu0.iew.wb_consumers 80015738 # num instructions consuming a value +system.cpu0.iew.exec_nop 209377 # number of nop insts executed +system.cpu0.iew.exec_refs 43763584 # number of memory reference insts executed +system.cpu0.iew.exec_branches 26159060 # Number of branches executed +system.cpu0.iew.exec_stores 19045777 # Number of stores executed +system.cpu0.iew.exec_rate 0.641712 # Inst execution rate +system.cpu0.iew.wb_sent 134853240 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 132911542 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 67798610 # num instructions producing a value +system.cpu0.iew.wb_consumers 109653581 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.735254 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.604786 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.629646 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.618298 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 7942186 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1519546 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 586085 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 120319586 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.745699 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.465434 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10465758 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1637231 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 673026 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 202620964 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.637065 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.337510 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 78400270 65.16% 65.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 23370127 19.42% 84.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 7855137 6.53% 91.11% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3041175 2.53% 93.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 3186617 2.65% 96.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 1413825 1.18% 97.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1097896 0.91% 98.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 521063 0.43% 98.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1433476 1.19% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 140811364 69.49% 69.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 34122035 16.84% 86.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 12973971 6.40% 92.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3422170 1.69% 94.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 4965504 2.45% 96.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 2761485 1.36% 98.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1431161 0.71% 98.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 576287 0.28% 99.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1556987 0.77% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 120319586 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 74552173 # Number of instructions committed -system.cpu0.commit.committedOps 89722144 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 202620964 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 106609467 # Number of instructions committed +system.cpu0.commit.committedOps 129082799 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 30278227 # Number of memory references committed -system.cpu0.commit.loads 15835522 # Number of loads committed -system.cpu0.commit.membars 627502 # Number of memory barriers committed -system.cpu0.commit.branches 15222627 # Number of branches committed -system.cpu0.commit.fp_insts 9772 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 77510355 # Number of committed integer instructions. -system.cpu0.commit.function_calls 1849810 # Number of function calls committed. +system.cpu0.commit.refs 42015997 # Number of memory references committed +system.cpu0.commit.loads 23348201 # Number of loads committed +system.cpu0.commit.membars 664671 # Number of memory barriers committed +system.cpu0.commit.branches 25482813 # Number of branches committed +system.cpu0.commit.fp_insts 11428 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 112616062 # Number of committed integer instructions. +system.cpu0.commit.function_calls 4882659 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 59351234 66.15% 66.15% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 85540 0.10% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 7143 0.01% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 15835522 17.65% 83.90% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 14442705 16.10% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 86948458 67.36% 67.36% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 110195 0.09% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 8149 0.01% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 23348201 18.09% 85.54% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 18667796 14.46% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 89722144 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1433476 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 212523033 # The number of ROB reads -system.cpu0.rob.rob_writes 196970686 # The number of ROB writes -system.cpu0.timesIdled 126988 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 4696310 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5127862528 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 74430479 # Number of Instructions Simulated -system.cpu0.committedOps 89600450 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.701714 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.701714 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.587643 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.587643 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 104622739 # number of integer regfile reads -system.cpu0.int_regfile_writes 56501496 # number of integer regfile writes -system.cpu0.fp_regfile_reads 8247 # number of floating regfile reads -system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes -system.cpu0.cc_regfile_reads 331476991 # number of cc regfile reads -system.cpu0.cc_regfile_writes 38443016 # number of cc regfile writes -system.cpu0.misc_regfile_reads 169856708 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1190913 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 672498 # number of replacements -system.cpu0.dcache.tags.tagsinuse 485.161129 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 27296512 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 673010 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 40.558851 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 129082799 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1556987 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 317266716 # The number of ROB reads +system.cpu0.rob.rob_writes 282405799 # The number of ROB writes +system.cpu0.timesIdled 139400 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5158998 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5463919353 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 106457624 # Number of Instructions Simulated +system.cpu0.committedOps 128930956 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.982849 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.982849 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.504325 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.504325 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 146869793 # number of integer regfile reads +system.cpu0.int_regfile_writes 83863812 # number of integer regfile writes +system.cpu0.fp_regfile_reads 9544 # number of floating regfile reads +system.cpu0.fp_regfile_writes 2721 # number of floating regfile writes +system.cpu0.cc_regfile_reads 478325864 # number of cc regfile reads +system.cpu0.cc_regfile_writes 51342401 # number of cc regfile writes +system.cpu0.misc_regfile_reads 283146795 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1260752 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 750420 # number of replacements +system.cpu0.dcache.tags.tagsinuse 496.151485 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 38802198 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 750932 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.672053 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 426635500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.161129 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947580 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.947580 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.151485 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.969046 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.969046 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 60152551 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 60152551 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 14711290 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 14711290 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 11396766 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 11396766 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 295733 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 295733 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354236 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 354236 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 350938 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 350938 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26108056 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 26108056 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26403789 # number of overall hits -system.cpu0.dcache.overall_hits::total 26403789 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 611234 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 611234 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1805910 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1805910 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141308 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 141308 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24174 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 24174 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21176 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 21176 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2417144 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2417144 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2558452 # number of overall misses -system.cpu0.dcache.overall_misses::total 2558452 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9073163500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 9073163500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32396978375 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 32396978375 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 391326000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 391326000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 534289500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 534289500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 728500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 728500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 41470141875 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 41470141875 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 41470141875 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 41470141875 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15322524 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 15322524 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 13202676 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 13202676 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 437041 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 437041 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378410 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 378410 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 372114 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 372114 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 28525200 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 28525200 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 28962241 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 28962241 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039891 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.039891 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136784 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.136784 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323329 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323329 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.063883 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.063883 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056907 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056907 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084737 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.084737 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088338 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.088338 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14844.009823 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14844.009823 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17939.420223 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17939.420223 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16187.887813 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16187.887813 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25230.898187 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25230.898187 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 83743288 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 83743288 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 22166108 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 22166108 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15386838 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15386838 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 316240 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 316240 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 371193 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 371193 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 369806 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 369806 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 37552946 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 37552946 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 37869186 # number of overall hits +system.cpu0.dcache.overall_hits::total 37869186 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 688329 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 688329 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1970797 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1970797 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 153398 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 153398 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 26102 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 26102 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20247 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20247 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2659126 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2659126 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2812524 # number of overall misses +system.cpu0.dcache.overall_misses::total 2812524 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9979901000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 9979901000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36499508368 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 36499508368 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 419269000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 419269000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 539016500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 539016500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 316500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 316500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 46479409368 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 46479409368 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 46479409368 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 46479409368 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 22854437 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 22854437 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 17357635 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 17357635 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 469638 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 469638 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 397295 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 397295 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 390053 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 390053 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 40212072 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 40212072 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 40681710 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 40681710 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030118 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.030118 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.113541 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.113541 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.326630 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.326630 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065699 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065699 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051908 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051908 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.066128 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.066128 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.069135 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.069135 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14498.736796 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14498.736796 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18520.176542 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18520.176542 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16062.715501 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16062.715501 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26622.042772 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26622.042772 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17156.669969 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 17156.669969 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16209.075595 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 16209.075595 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1312 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 5225040 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 49 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 192315 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.775510 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 27.169176 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17479.205336 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 17479.205336 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16525.871199 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 16525.871199 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1220 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 5610117 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 53 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 211671 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.018868 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 26.503947 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 490431 # number of writebacks -system.cpu0.dcache.writebacks::total 490431 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 244715 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 244715 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1493725 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1493725 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18048 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18048 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1738440 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1738440 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1738440 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1738440 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 366519 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 366519 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312185 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 312185 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 97992 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 97992 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6126 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6126 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21176 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 21176 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 678704 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 678704 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 776696 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 776696 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17958 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17958 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16709 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16709 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34667 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34667 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4650113000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4650113000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6789940400 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6789940400 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1696741500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1696741500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97425500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97425500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 513125500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 513125500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 716500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 716500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11440053400 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11440053400 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13136794900 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13136794900 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3760775500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3760775500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2938081500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2938081500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6698857000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6698857000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023920 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023920 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023646 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023646 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224217 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224217 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016189 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016189 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056907 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056907 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023793 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023793 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026818 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026818 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12687.235860 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12687.235860 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21749.733011 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21749.733011 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17315.102253 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17315.102253 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15903.607574 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15903.607574 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24231.464866 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24231.464866 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 750420 # number of writebacks +system.cpu0.dcache.writebacks::total 750420 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 277928 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 277928 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1634691 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1634691 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 19352 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 19352 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1912619 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1912619 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1912619 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1912619 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 410401 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 410401 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 336106 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 336106 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 107319 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 107319 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6750 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6750 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20247 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20247 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 746507 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 746507 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 853826 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 853826 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31838 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31838 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28498 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28498 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60336 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60336 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5125711500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5125711500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7684887402 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7684887402 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1795459000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1795459000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 109420000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 109420000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 518776500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 518776500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 309500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 309500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12810598902 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12810598902 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14606057902 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 14606057902 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6629004500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6629004500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5396257500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5396257500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12025262000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12025262000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017957 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017957 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019364 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019364 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228514 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228514 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016990 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016990 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051908 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051908 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018564 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.018564 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020988 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.020988 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12489.520006 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12489.520006 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22864.475499 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22864.475499 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16730.113028 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16730.113028 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16210.370370 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16210.370370 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25622.388502 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25622.388502 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16855.732985 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16855.732985 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16913.689397 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16913.689397 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209420.620336 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209420.620336 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175838.260818 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175838.260818 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 193234.401592 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193234.401592 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17160.721737 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17160.721737 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17106.597717 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17106.597717 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208210.456059 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208210.456059 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189355.656537 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189355.656537 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199304.925749 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199304.925749 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1200820 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.709969 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 34456109 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1201332 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 28.681588 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8093069500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.709969 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999434 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999434 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1310169 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.377289 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 72850689 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1310681 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 55.582319 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 8207375500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.377289 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998784 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998784 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 72616555 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 72616555 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 34456109 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 34456109 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 34456109 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 34456109 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 34456109 # number of overall hits -system.cpu0.icache.overall_hits::total 34456109 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1251492 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1251492 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1251492 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1251492 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1251492 # number of overall misses -system.cpu0.icache.overall_misses::total 1251492 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13477536890 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13477536890 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13477536890 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13477536890 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13477536890 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13477536890 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 35707601 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 35707601 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 35707601 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 35707601 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 35707601 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 35707601 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.035048 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.035048 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.035048 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.035048 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.035048 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.035048 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10769.175424 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10769.175424 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10769.175424 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10769.175424 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10769.175424 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10769.175424 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1798735 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 149746644 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 149746644 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 72850689 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 72850689 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 72850689 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 72850689 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 72850689 # number of overall hits +system.cpu0.icache.overall_hits::total 72850689 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1367277 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1367277 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1367277 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1367277 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1367277 # number of overall misses +system.cpu0.icache.overall_misses::total 1367277 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14942894261 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14942894261 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14942894261 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14942894261 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14942894261 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14942894261 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 74217966 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 74217966 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 74217966 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 74217966 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 74217966 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 74217966 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.018422 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.018422 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.018422 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.018422 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.018422 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.018422 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10928.944362 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10928.944362 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10928.944362 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10928.944362 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10928.944362 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10928.944362 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2021185 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 1804 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 112593 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 126207 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.975549 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.014841 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets 120.266667 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 50137 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 50137 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 50137 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 50137 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 50137 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 50137 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1201355 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1201355 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1201355 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1201355 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1201355 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1201355 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1310169 # number of writebacks +system.cpu0.icache.writebacks::total 1310169 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 56563 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 56563 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 56563 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 56563 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 56563 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 56563 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1310714 # 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number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12113813705 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12113813705 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12113813705 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12113813705 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 420637998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 420637998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 420637998 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 420637998 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033644 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033644 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033644 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.033644 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033644 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.033644 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10083.458849 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10083.458849 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10083.458849 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10083.458849 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10083.458849 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10083.458849 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140025.964714 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140025.964714 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140025.964714 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140025.964714 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13414113616 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 13414113616 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13414113616 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 13414113616 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13414113616 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 13414113616 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 420651998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 420651998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 420651998 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 420651998 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017660 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017660 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017660 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.017660 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017660 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.017660 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10234.203355 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10234.203355 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10234.203355 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10234.203355 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10234.203355 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10234.203355 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140030.625166 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140030.625166 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1767941 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1770755 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 2568 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1920430 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1923198 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 2526 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # 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Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 9237.046322 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.824240 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.088026 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3962.897629 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1653.213235 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1171.975059 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.563785 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000783 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # 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Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14677.549696 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.049066 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.660096 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1408.912909 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.895847 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000735 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000101 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.085993 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.982676 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1016 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15129 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 23 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 340 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 424 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 229 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4597 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7301 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2771 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.065979 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.924133 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 63212919 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 63212919 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 49275 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12221 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 61496 # 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number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12221 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1150269 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 555536 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1767301 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 49275 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12221 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1150269 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 555536 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1767301 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 406 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 160 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 566 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27413 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 27413 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19541 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19541 # number of SCUpgradeReq misses +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 499 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4650 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7772 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2079 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062012 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.923401 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 69513277 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 69513277 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 60951 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 14637 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 75588 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 505486 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 505486 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1521984 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1521984 # number of WritebackClean hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 205294 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 205294 # 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number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 631908 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1962905 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 405 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 157 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 562 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55507 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 55507 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20246 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 20246 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 72546 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 72546 # 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mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.489763 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.489763 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.922834 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.922834 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158543 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158543 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042497 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042497 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.208708 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.208708 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008172 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.012842 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042497 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191011 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.095702 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008172 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.012842 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042497 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191011 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.152150 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.152150 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042140 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042140 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184874 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.184874 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.006585 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.010612 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042140 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.173460 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.089168 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.006585 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.010612 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042140 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.173460 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.213492 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24360.837438 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20305.031447 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23219.469027 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89557.677124 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 89557.677124 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 32682.978879 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32682.978879 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18064.019037 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18064.019037 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 625999 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 625999 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57218.002951 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57218.002951 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 60574.842304 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 60574.842304 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26869.500117 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26869.500117 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24360.837438 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20305.031447 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 60574.842304 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35755.485450 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 42370.378910 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24360.837438 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20305.031447 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 60574.842304 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35755.485450 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89557.677124 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 68405.133252 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132525.466045 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201415.469429 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 191543.054098 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 168173.586810 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 168173.586810 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132525.466045 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 185393.355699 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 181177.509543 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.207675 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26845.297030 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19630.573248 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24826.203209 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82913.548852 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 82913.548852 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26305.339867 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26305.339867 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18059.641361 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18059.641361 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 254999 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 254999 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57253.797365 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57253.797365 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 62622.175514 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62622.175514 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28583.126123 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28583.126123 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26845.297030 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19630.573248 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 62622.175514 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37354.260919 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44458.479333 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26845.297030 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19630.573248 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 62622.175514 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37354.260919 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82913.548852 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66402.273009 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200200.625039 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194366.224671 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181741.366482 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181741.366482 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191481.917296 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188686.035081 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 3900428 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1972103 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 30395 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 166078 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 165928 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 150 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 98608 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1819240 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 16709 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 16709 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 685334 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1450937 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 287419 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 90627 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43495 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114961 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 22 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 33 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 273601 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 270191 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1201355 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 557036 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3216 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3585963 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2443651 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28820 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 110863 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6169297 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 76933952 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82016191 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 49524 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 198724 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 159198391 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 860528 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4738789 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.052471 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.223116 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 4274202 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2158357 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 33137 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 328935 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 324390 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4545 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 121088 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2005227 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28498 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28498 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 739211 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1521984 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 210746 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 317495 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 85916 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42642 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113550 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 299038 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 295760 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1310714 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 595848 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3361 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3912120 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2727113 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 130288 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6801615 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 166153536 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 103357964 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 59176 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 245424 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 269816100 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1019832 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3249125 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.119614 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.328792 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 4490292 94.76% 94.76% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 248347 5.24% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 150 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2865028 88.18% 88.18% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 379552 11.68% 99.86% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4545 0.14% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4738789 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2495889948 # Layer occupancy (ticks) -system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 112738429 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3249125 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 4275785445 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115025120 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1805438687 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1969663813 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1156413493 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1293120190 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 16448481 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 17309980 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 61214934 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 68982399 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 35362528 # Number of BP lookups -system.cpu1.branchPred.condPredicted 12650645 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 376011 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 19640345 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 15643376 # Number of BTB hits +system.cpu1.branchPred.lookups 4001540 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2313487 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 245860 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2018567 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1484210 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 79.649191 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 12652559 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 10779 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.527904 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 788035 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 5731 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1631,90 +1641,87 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 24283 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 24283 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11247 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5966 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 7070 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 17213 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 473.798873 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 2831.806000 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 16574 96.29% 96.29% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 219 1.27% 97.56% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 229 1.33% 98.89% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 75 0.44% 99.33% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 20 0.12% 99.44% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 24 0.14% 99.58% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 7 0.04% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 43 0.25% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 17 0.10% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 3 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 15963 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 15963 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8440 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3082 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 4441 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 11522 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 609.182434 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3297.605064 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 10996 95.43% 95.43% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 174 1.51% 96.94% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 184 1.60% 98.54% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 58 0.50% 99.05% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 13 0.11% 99.16% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 21 0.18% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 5 0.04% 99.38% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 47 0.41% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 21 0.18% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::36864-40959 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 17213 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5394 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 10976.177234 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9365.976538 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 8403.035892 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 4813 89.23% 89.23% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 520 9.64% 98.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-49151 49 0.91% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-65535 4 0.07% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-147455 3 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::147456-163839 4 0.07% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::212992-229375 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5394 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 75766592176 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.320474 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.469554 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 51526613188 68.01% 68.01% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 24219637488 31.97% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2 12480500 0.02% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::3 3766000 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4 1197500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::5 815500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6 985500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::7 293500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8 146000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::9 224500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10 83500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::11 76500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12 137000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::13 18000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14 22000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::15 95500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 75766592176 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1932 75.85% 75.85% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 615 24.15% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2547 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24283 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 11522 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 3235 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11713.446677 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10455.998129 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6677.373091 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 2744 84.82% 84.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 453 14.00% 98.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-49151 32 0.99% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-65535 5 0.15% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 3235 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 75555560672 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.169680 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.377976 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 62765308336 83.07% 83.07% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 12774698836 16.91% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2 10450000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::3 2017500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4 1080000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::5 463500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6 984500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::7 133500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8 33500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::9 93000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10 18000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::11 18000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12 88500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::13 11000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14 24500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::15 138000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 75555560672 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1230 72.78% 72.78% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 460 27.22% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1690 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15963 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24283 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2547 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15963 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1690 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2547 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 26830 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1690 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 17653 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 11209013 # DTB read hits -system.cpu1.dtb.read_misses 21079 # DTB read misses -system.cpu1.dtb.write_hits 7325054 # DTB write hits -system.cpu1.dtb.write_misses 3204 # DTB write misses +system.cpu1.dtb.read_hits 3544820 # DTB read hits +system.cpu1.dtb.read_misses 14056 # DTB read misses +system.cpu1.dtb.write_hits 3033862 # DTB write hits +system.cpu1.dtb.write_misses 1907 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2001 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 73 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 612 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1651 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 51 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 364 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 367 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 11230092 # DTB read accesses -system.cpu1.dtb.write_accesses 7328258 # DTB write accesses +system.cpu1.dtb.perms_faults 252 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3558876 # DTB read accesses +system.cpu1.dtb.write_accesses 3035769 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 18534067 # DTB hits -system.cpu1.dtb.misses 24283 # DTB misses -system.cpu1.dtb.accesses 18558350 # DTB accesses +system.cpu1.dtb.hits 6578682 # DTB hits +system.cpu1.dtb.misses 15963 # DTB misses +system.cpu1.dtb.accesses 6594645 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1744,57 +1751,60 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 6861 # Table walker walks requested -system.cpu1.itb.walker.walksShort 6861 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4105 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2676 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 80 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 6781 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 216.855921 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 1684.274104 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-4095 6669 98.35% 98.35% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-8191 39 0.58% 98.92% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-12287 44 0.65% 99.57% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-16383 12 0.18% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-20479 5 0.07% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-24575 5 0.07% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-28671 2 0.03% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::28672-32767 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-36863 3 0.04% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 6781 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1249 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11729.383507 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10507.790303 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6381.189280 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 353 28.26% 28.26% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 814 65.17% 93.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 24 1.92% 95.36% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 32 2.56% 97.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-40959 17 1.36% 99.28% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 7 0.56% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.08% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::73728-81919 1 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1249 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 15604919032 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.958751 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.198933 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 643875264 4.13% 4.13% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 14960875268 95.87% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 148500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 20000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 15604919032 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 997 85.29% 85.29% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 172 14.71% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1169 # Table walker page sizes translated +system.cpu1.itb.walker.walks 6382 # Table walker walks requested +system.cpu1.itb.walker.walksShort 6382 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4076 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2250 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 56 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 6326 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 181.394246 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 1406.259305 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-4095 6214 98.23% 98.23% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-8191 59 0.93% 99.16% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-12287 37 0.58% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-16383 6 0.09% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-20479 4 0.06% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-24575 2 0.03% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-28671 3 0.05% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::36864-40959 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 6326 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 893 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11600.783875 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10727.998992 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5550.111041 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 41 4.59% 4.59% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 147 16.46% 21.05% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 548 61.37% 82.42% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 107 11.98% 94.40% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 11 1.23% 95.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 5 0.56% 96.19% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 19 2.13% 98.32% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 3 0.34% 98.66% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.11% 98.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.56% 99.33% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.34% 99.66% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::53248-57343 2 0.22% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.11% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 893 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 11098487732 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.931053 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.253398 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 765303264 6.90% 6.90% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 10333090968 93.10% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 93500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 11098487732 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 693 82.80% 82.80% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 144 17.20% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 837 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6861 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6861 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6382 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6382 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1169 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1169 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 8030 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 45813094 # ITB inst hits -system.cpu1.itb.inst_misses 6861 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 837 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 837 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 7219 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 7191521 # ITB inst hits +system.cpu1.itb.inst_misses 6382 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1803,1043 +1813,1040 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1199 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 901 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 526 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 347 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 45819955 # ITB inst accesses -system.cpu1.itb.hits 45813094 # DTB hits -system.cpu1.itb.misses 6861 # DTB misses -system.cpu1.itb.accesses 45819955 # DTB accesses -system.cpu1.numCycles 115872528 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7197903 # ITB inst accesses +system.cpu1.itb.hits 7191521 # DTB hits +system.cpu1.itb.misses 6382 # DTB misses +system.cpu1.itb.accesses 7197903 # DTB accesses +system.cpu1.numCycles 32425900 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 11244647 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 115696053 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 35362528 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 28295935 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 100513645 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3955668 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 92958 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 43827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 218813 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 324785 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 35760 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 45812479 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 133633 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2410 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114452269 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.250587 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.333322 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 8095443 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 21322301 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4001540 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 2272245 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 22576717 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 701366 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 87665 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 29928 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 190452 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 273109 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 16492 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7191191 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 105174 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2314 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 31620489 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.824543 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.195918 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 53787165 47.00% 47.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 15397458 13.45% 60.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 8067873 7.05% 67.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 37199773 32.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 19556210 61.85% 61.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 4372737 13.83% 75.68% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1374906 4.35% 80.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 6316636 19.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114452269 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.305185 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.998477 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 14331089 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 67536075 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 29425449 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1338809 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1820847 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 912295 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 160061 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 74627346 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1451044 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1820847 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 19084331 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2925531 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 61205079 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 25977648 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3438833 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 61437487 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 313811 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 329328 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 50880 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 21104 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 2227690 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 61781071 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 288761968 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 65715217 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 1660 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 58198437 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 3582634 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1923301 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1845273 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 13635165 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 11552975 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7780383 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 701343 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 925146 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 60392573 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 653667 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 59853310 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 146761 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 4556505 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 7374621 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 54925 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114452269 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.522954 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.862457 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 31620489 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.123406 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.657570 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 6635373 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 16232056 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 7605382 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 916534 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 231144 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 619166 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 122135 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 20047523 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 930312 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 231144 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 7872130 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2262020 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11428772 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 7266376 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2560047 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 19035604 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 152359 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 204838 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 28045 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 12601 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1704098 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 18785965 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 89036414 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 21967957 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 16823959 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1962006 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 364639 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 299553 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2452699 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 3781052 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 3343720 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 554765 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 448879 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 18340674 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 508914 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 18185979 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 84059 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1788804 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 4127246 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 41236 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 31620489 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.575133 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.924807 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 77949624 68.11% 68.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 17744881 15.50% 83.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 14511556 12.68% 96.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3899540 3.41% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 346643 0.30% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 25 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 20837444 65.90% 65.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 5408008 17.10% 83.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3574976 11.31% 94.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 1572233 4.97% 99.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 227820 0.72% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114452269 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 31620489 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3494882 44.84% 44.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 604 0.01% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1953801 25.07% 69.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 2345303 30.09% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 1135208 27.60% 27.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 664 0.02% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1335102 32.46% 60.07% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1642689 39.93% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 67 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 40748712 68.08% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 52853 0.09% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4129 0.01% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 11462159 19.15% 87.33% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7585390 12.67% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 24 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 11205359 61.62% 61.62% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 26215 0.14% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 3128 0.02% 61.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.78% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 3726030 20.49% 82.27% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 3225223 17.73% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 59853310 # Type of FU issued -system.cpu1.iq.rate 0.516544 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7794590 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.130228 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 242094525 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 65611557 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 57714006 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 5715 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2046 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 1784 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 67644200 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 3633 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 110002 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 18185979 # Type of FU issued +system.cpu1.iq.rate 0.560847 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4113663 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.226200 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 72190169 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 20646412 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 17793804 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 22299618 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 72560 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 628284 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 842 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 10885 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 426405 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 346468 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 605 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 8056 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 274891 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 57089 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 100676 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 35566 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 53462 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1820847 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 727831 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 179449 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 61101449 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 231144 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 519259 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 154115 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 18866238 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 11552975 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7780383 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 331927 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 11154 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 159363 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 10885 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 82141 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 153260 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 235401 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59500982 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 11329735 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 328066 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 3781052 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 3343720 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 266301 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 6646 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 141712 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 8056 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 30125 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 104168 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 134293 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 17982694 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 3650056 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 187326 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 55209 # number of nop insts executed -system.cpu1.iew.exec_refs 18836194 # number of memory reference insts executed -system.cpu1.iew.exec_branches 12894851 # Number of branches executed -system.cpu1.iew.exec_stores 7506459 # Number of stores executed -system.cpu1.iew.exec_rate 0.513504 # Inst execution rate -system.cpu1.iew.wb_sent 59314333 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 57715790 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 28288530 # num instructions producing a value -system.cpu1.iew.wb_consumers 43462608 # num instructions consuming a value +system.cpu1.iew.exec_nop 16650 # number of nop insts executed +system.cpu1.iew.exec_refs 6820794 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2588349 # Number of branches executed +system.cpu1.iew.exec_stores 3170738 # Number of stores executed +system.cpu1.iew.exec_rate 0.554578 # Inst execution rate +system.cpu1.iew.wb_sent 17880625 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 17793804 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 8844802 # num instructions producing a value +system.cpu1.iew.wb_consumers 13735859 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.498097 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.650871 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.548753 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.643921 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 4228906 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 598742 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 219024 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 112407306 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.502841 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.169324 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1618894 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 467678 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 126321 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 31256140 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.545936 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.299262 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 84196637 74.90% 74.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 15782926 14.04% 88.94% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6506905 5.79% 94.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 899885 0.80% 95.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 2238894 1.99% 97.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 1696394 1.51% 99.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 469505 0.42% 99.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 157300 0.14% 99.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 458860 0.41% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 23000082 73.59% 73.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 4925249 15.76% 89.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1442060 4.61% 93.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 538119 1.72% 95.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 452265 1.45% 97.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 297433 0.95% 98.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 181915 0.58% 98.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 99730 0.32% 98.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 319287 1.02% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 112407306 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 46016034 # Number of instructions committed -system.cpu1.commit.committedOps 56522947 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 31256140 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 13926644 # Number of instructions committed +system.cpu1.commit.committedOps 17063847 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 18278669 # Number of memory references committed -system.cpu1.commit.loads 10924691 # Number of loads committed -system.cpu1.commit.membars 232005 # Number of memory barriers committed -system.cpu1.commit.branches 12685356 # Number of branches committed -system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 50487985 # Number of committed integer instructions. -system.cpu1.commit.function_calls 3456157 # Number of function calls committed. +system.cpu1.commit.refs 6503413 # Number of memory references committed +system.cpu1.commit.loads 3434584 # Number of loads committed +system.cpu1.commit.membars 191656 # Number of memory barriers committed +system.cpu1.commit.branches 2466066 # Number of branches committed +system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 15229015 # Number of committed integer instructions. +system.cpu1.commit.function_calls 413334 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 38188356 67.56% 67.56% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 51793 0.09% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4129 0.01% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 10924691 19.33% 86.99% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 7353978 13.01% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 10531890 61.72% 61.72% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 25416 0.15% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 3128 0.02% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 3434584 20.13% 82.02% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 3068829 17.98% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 56522947 # Class of committed instruction -system.cpu1.commit.bw_lim_events 458860 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 152481338 # The number of ROB reads -system.cpu1.rob.rob_writes 123545319 # The number of ROB writes -system.cpu1.timesIdled 68699 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1420259 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5138082707 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 45982821 # Number of Instructions Simulated -system.cpu1.committedOps 56489734 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.519909 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.519909 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.396840 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.396840 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 62666330 # number of integer regfile reads -system.cpu1.int_regfile_writes 39173045 # number of integer regfile writes -system.cpu1.fp_regfile_reads 1381 # number of floating regfile reads -system.cpu1.fp_regfile_writes 516 # number of floating regfile writes -system.cpu1.cc_regfile_reads 211754483 # number of cc regfile reads -system.cpu1.cc_regfile_writes 18307351 # number of cc regfile writes -system.cpu1.misc_regfile_reads 158297998 # number of misc regfile reads -system.cpu1.misc_regfile_writes 426234 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 227119 # number of replacements -system.cpu1.dcache.tags.tagsinuse 480.780000 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 17377933 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 227440 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 76.406670 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 89481619000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 480.780000 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.939023 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.939023 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 24 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.626953 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 36531516 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 36531516 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 10502192 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10502192 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6578620 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6578620 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65191 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 65191 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88541 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 88541 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80577 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 80577 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 17080812 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 17080812 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 17146003 # number of overall hits -system.cpu1.dcache.overall_hits::total 17146003 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 257246 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 257246 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 477990 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 477990 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35676 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 35676 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19120 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 19120 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23513 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23513 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 735236 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 735236 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 770912 # number of overall misses -system.cpu1.dcache.overall_misses::total 770912 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4397234500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 4397234500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13204055417 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 13204055417 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 384125500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 384125500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 615714500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 615714500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2019500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2019500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 17601289917 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 17601289917 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 17601289917 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 17601289917 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 10759438 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 10759438 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7056610 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7056610 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 100867 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 100867 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 107661 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 107661 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 104090 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 104090 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 17816048 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 17816048 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 17916915 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 17916915 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023909 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.023909 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.067736 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.067736 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.353693 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.353693 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177594 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177594 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225891 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225891 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.041268 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.041268 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043027 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043027 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17093.499996 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 17093.499996 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27624.124808 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 27624.124808 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20090.245816 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20090.245816 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26186.131076 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26186.131076 # average StoreCondReq miss latency +system.cpu1.commit.op_class_0::total 17063847 # Class of committed instruction +system.cpu1.commit.bw_lim_events 319287 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 48731479 # The number of ROB reads +system.cpu1.rob.rob_writes 37726129 # The number of ROB writes +system.cpu1.timesIdled 54512 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 805411 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5642014046 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 13923580 # Number of Instructions Simulated +system.cpu1.committedOps 17060783 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.328848 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.328848 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.429397 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.429397 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 20183446 # number of integer regfile reads +system.cpu1.int_regfile_writes 11616875 # number of integer regfile writes +system.cpu1.cc_regfile_reads 64541382 # number of cc regfile reads +system.cpu1.cc_regfile_writes 5516447 # number of cc regfile writes +system.cpu1.misc_regfile_reads 46291245 # number of misc regfile reads +system.cpu1.misc_regfile_writes 345789 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 150536 # number of replacements +system.cpu1.dcache.tags.tagsinuse 478.106753 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 5837857 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 150895 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 38.688207 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 89621465500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.106753 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.933802 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.933802 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 351 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 12869097 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 12869097 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3072993 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3072993 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2528751 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2528751 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42878 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 42878 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70516 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 70516 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61926 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 61926 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 5601744 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 5601744 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 5644622 # number of overall hits +system.cpu1.dcache.overall_hits::total 5644622 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 178967 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 178967 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 316584 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 316584 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23990 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 23990 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17392 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17392 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23411 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23411 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 495551 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 495551 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 519541 # number of overall misses +system.cpu1.dcache.overall_misses::total 519541 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3311567500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3311567500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11108580447 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 11108580447 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 357363500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 357363500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 641574000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 641574000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 819500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 819500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 14420147947 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 14420147947 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 14420147947 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 14420147947 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3251960 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3251960 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2845335 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2845335 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66868 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 66868 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87908 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 87908 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85337 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 85337 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 6097295 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 6097295 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 6164163 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 6164163 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.055034 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.055034 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.111264 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.111264 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.358767 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.358767 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.197843 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.197843 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274336 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274336 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.081274 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.081274 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.084284 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.084284 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18503.788408 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 18503.788408 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35088.887774 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 35088.887774 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20547.579347 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20547.579347 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27404.809705 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27404.809705 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23939.646477 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23939.646477 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22831.775763 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 22831.775763 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 342 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1982545 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 37 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 49131 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.243243 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 40.352222 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29099.220760 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 29099.220760 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27755.553358 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 27755.553358 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 351 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1652938 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 24 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 30246 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 14.625000 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 54.649805 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 137800 # number of writebacks -system.cpu1.dcache.writebacks::total 137800 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 93990 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 93990 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 374320 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 374320 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13607 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13607 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 468310 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 468310 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 468310 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 468310 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163256 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 163256 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103670 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 103670 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32269 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 32269 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5513 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5513 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23513 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23513 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 266926 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 266926 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 299195 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 299195 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17062 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17062 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14341 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31403 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31403 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2326061500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2326061500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3203086933 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3203086933 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 553503000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 553503000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 109001000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 109001000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 592222500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 592222500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1998500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1998500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5529148433 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5529148433 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6082651433 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6082651433 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2940631000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2940631000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2452626000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2452626000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5393257000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5393257000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015173 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.015173 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014691 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014691 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.319916 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.319916 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051207 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051207 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225891 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225891 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014982 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.014982 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016699 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.016699 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14247.938820 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14247.938820 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30896.951220 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30896.951220 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17152.778208 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17152.778208 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19771.630691 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19771.630691 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25187.024199 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25187.024199 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 150537 # number of writebacks +system.cpu1.dcache.writebacks::total 150537 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 62639 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 62639 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 238187 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 238187 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12480 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12480 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 300826 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 300826 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 300826 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 300826 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116328 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 116328 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 78397 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 78397 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23066 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 23066 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4912 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4912 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23411 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23411 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 194725 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 194725 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 217791 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 217791 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3053 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3053 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2412 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2412 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5465 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5465 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1734233000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1734233000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2786620456 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2786620456 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 403892500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 403892500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 94891500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 94891500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 618171000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 618171000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 811500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 811500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4520853456 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4520853456 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4924745956 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4924745956 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 433886500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 433886500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 300722000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 300722000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 734608500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 734608500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035772 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035772 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027553 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027553 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.344948 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.344948 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055877 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055877 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274336 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274336 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031936 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031936 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035332 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035332 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14908.130459 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14908.130459 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35544.988405 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35544.988405 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17510.296540 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17510.296540 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19318.302117 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19318.302117 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26405.151425 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26405.151425 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20714.162101 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20714.162101 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20330.057097 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20330.057097 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172349.724534 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172349.724534 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171021.964995 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171021.964995 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171743.368468 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 171743.368468 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23216.605243 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23216.605243 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22612.256503 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22612.256503 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142118.080576 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142118.080576 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124677.446103 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124677.446103 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134420.585544 # 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Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 559207 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.428858 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6611589 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 559719 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 11.812336 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 79408312500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.428858 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975447 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975447 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 92297132 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 92297132 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 45113050 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 45113050 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 45113050 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 45113050 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 45113050 # number of overall hits -system.cpu1.icache.overall_hits::total 45113050 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 699105 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 699105 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 699105 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 699105 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 699105 # number of overall misses -system.cpu1.icache.overall_misses::total 699105 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6808598319 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6808598319 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6808598319 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6808598319 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6808598319 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6808598319 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 45812155 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 45812155 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 45812155 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 45812155 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 45812155 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 45812155 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.015260 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.015260 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.015260 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.015260 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.015260 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.015260 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9739.021061 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9739.021061 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9739.021061 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9739.021061 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9739.021061 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9739.021061 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 778427 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 223 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 55737 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.966073 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 111.500000 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 14941719 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 14941719 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 6611589 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6611589 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6611589 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6611589 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6611589 # number of overall hits +system.cpu1.icache.overall_hits::total 6611589 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 579409 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 579409 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 579409 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 579409 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 579409 # number of overall misses +system.cpu1.icache.overall_misses::total 579409 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5260271690 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5260271690 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5260271690 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5260271690 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5260271690 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5260271690 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7190998 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7190998 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7190998 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7190998 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7190998 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7190998 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.080574 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.080574 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.080574 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.080574 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.080574 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.080574 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9078.684815 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9078.684815 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9078.684815 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9078.684815 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9078.684815 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9078.684815 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 508858 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 41527 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.253666 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 26283 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 26283 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 26283 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 26283 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 26283 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 26283 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 672822 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 672822 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 672822 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 672822 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 672822 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 672822 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable -system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable -system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses -system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6167077156 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6167077156 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6167077156 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6167077156 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6167077156 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6167077156 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13506000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13506000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13506000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 13506000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014687 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014687 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014687 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014687 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014687 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014687 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9165.986184 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9165.986184 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9165.986184 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9165.986184 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9165.986184 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9165.986184 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132411.764706 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132411.764706 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132411.764706 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132411.764706 # average overall mshr uncacheable latency +system.cpu1.icache.writebacks::writebacks 559207 # number of writebacks +system.cpu1.icache.writebacks::total 559207 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 19686 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 19686 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 19686 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 19686 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 19686 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 19686 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 559723 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 559723 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 559723 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 559723 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 559723 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 559723 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 103 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 103 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 103 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 103 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4814325924 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4814325924 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4814325924 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4814325924 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4814325924 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4814325924 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14117999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14117999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14117999 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 14117999 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.077837 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.077837 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.077837 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.077837 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.077837 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.077837 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8601.265133 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8601.265133 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8601.265133 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8601.265133 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8601.265133 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8601.265133 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137067.951456 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137067.951456 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137067.951456 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137067.951456 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 262736 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 263407 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 604 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 109440 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 110020 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 525 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 68017 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 62303 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15536.648070 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1677232 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 76854 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 21.823614 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 49988 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 32853 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15122.347980 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1241496 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 48030 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 25.848345 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 6569.267487 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 14.374590 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.390464 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4943.655897 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2538.739672 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1470.219959 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.400956 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000877 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000024 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.301737 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.154952 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.089735 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.948282 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1250 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 33 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13268 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 890 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 342 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14684.371026 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 11.723090 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.949001 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 423.304863 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.896263 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000716 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000180 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.025836 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.922995 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 986 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14139 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 660 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 322 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8543 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4263 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.076294 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002014 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.809814 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 30842090 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 30842090 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19102 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7340 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 26442 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 137798 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 137798 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1915 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1915 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1089 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1089 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 37080 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 37080 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 650319 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 650319 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 128580 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 128580 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 19102 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7340 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 650319 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 165660 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 842421 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19102 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7340 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 650319 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 165660 # number of overall hits -system.cpu1.l2cache.overall_hits::total 842421 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 434 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 283 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 717 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29244 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29244 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22424 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22424 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36071 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 36071 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 22492 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 22492 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 72430 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 72430 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 434 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 283 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 22492 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 108501 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 131710 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 434 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 283 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 22492 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 108501 # number of overall misses -system.cpu1.l2cache.overall_misses::total 131710 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10853500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5913500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 16767000 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 593983499 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 593983499 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 472238000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 472238000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1967000 # 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number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3745713491 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 5010755991 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10853500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5913500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1248275500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3745713491 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 5010755991 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 19536 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7623 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 27159 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 137799 # 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number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 704907496 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.034409 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.037935 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.035700 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.938541 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.938541 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.953685 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.953685 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.471080 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.471080 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.033402 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.033402 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.359509 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.359509 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022164 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035419 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033402 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.389279 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.133351 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022164 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035419 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033402 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.389279 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999957 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999957 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.632294 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.632294 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018625 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018625 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.449928 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.449928 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.034409 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.037935 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018625 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.496837 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.139105 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.034409 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.037935 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018625 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.496837 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.170100 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19019.630485 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15294.444444 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17588.904694 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50628.280594 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50628.280594 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23586.650185 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23586.650185 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18516.656261 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18516.656261 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46182.211259 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46182.211259 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 49490.633204 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49490.633204 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 19284.639756 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 19284.639756 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19019.630485 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15294.444444 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 49490.633204 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27969.486924 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31636.488495 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19019.630485 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15294.444444 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 49490.633204 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27969.486924 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50628.280594 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 35739.609590 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124911.764706 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164333.255187 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164098.986250 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163506.624224 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163506.624224 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124911.764706 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 163955.752571 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163829.344485 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.164464 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16127.586207 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14386.281588 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15450.140449 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57294.005503 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 57294.005503 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20607.194467 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20607.194467 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18882.401948 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18882.401948 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 187625 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 187625 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47100.974776 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47100.974776 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 53199.903981 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 53199.903981 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16826.176342 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16826.176342 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16127.586207 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14386.281588 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 53199.903981 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26736.795746 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29224.667682 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16127.586207 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14386.281588 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 53199.903981 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26736.795746 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57294.005503 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33552.662529 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134022.436947 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133876.901141 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117077.941957 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117077.941957 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126543.915096 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126599.765805 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 1911239 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 964293 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 15206 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 115900 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 115705 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 195 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 49800 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 965132 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 14341 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 14341 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 177279 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 810351 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 43777 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 73201 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42982 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 89676 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 33 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 81502 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 78977 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 672822 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 286780 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 213 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2005740 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1027154 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17080 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 42715 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3092689 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 43061536 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29508655 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30492 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 78144 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 72678827 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 390895 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2268265 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.069071 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.253913 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 1523677 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 769701 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12410 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 171538 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 169858 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1680 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 26336 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 768409 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2412 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2412 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 120538 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 604293 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 90253 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 23776 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71073 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41600 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85044 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 57287 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 54410 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 559723 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 223005 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 24 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1668415 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 728070 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 15878 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 27246 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2439609 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 70944752 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24680600 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29208 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50568 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 95705128 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 366083 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1123000 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.171945 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.381277 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 2111789 93.10% 93.10% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 156281 6.89% 99.99% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 195 0.01% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 931586 82.96% 82.96% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 189734 16.90% 99.85% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1680 0.15% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2268265 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1127589981 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 88549490 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1123000 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1483438992 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80062850 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1009459749 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 839820234 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 464204253 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 323064197 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 9470972 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 8585980 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 23200956 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 14617972 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31010 # Transaction distribution -system.iobus.trans_dist::ReadResp 31010 # Transaction distribution -system.iobus.trans_dist::WriteReq 59422 # Transaction distribution -system.iobus.trans_dist::WriteResp 59422 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31018 # Transaction distribution +system.iobus.trans_dist::ReadResp 31018 # Transaction distribution +system.iobus.trans_dist::WriteReq 59424 # Transaction distribution +system.iobus.trans_dist::WriteResp 59424 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2855,16 +2862,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180864 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180884 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2880,67 +2887,67 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40405000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 111500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 31500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 15500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 90500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 504000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 581000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 49500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6141000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 169500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 34081000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 124500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186507978 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186321543 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 31500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.440882 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.554671 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 256003407000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.440882 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.902555 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.902555 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 256310853000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.554671 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.909667 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.909667 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2954,14 +2961,14 @@ system.iocache.demand_misses::realview.ide 252 # system.iocache.demand_misses::total 252 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 252 # number of overall misses system.iocache.overall_misses::total 252 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32773877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32773877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4715888101 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4715888101 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32773877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32773877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32773877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32773877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32664376 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32664376 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4736716167 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4736716167 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32664376 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32664376 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32664376 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32664376 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2978,19 +2985,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 130055.067460 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 130055.067460 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130186.840244 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130186.840244 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130055.067460 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130055.067460 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130055.067460 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130055.067460 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 42 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129620.539683 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129620.539683 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130761.819981 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130761.819981 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 129620.539683 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129620.539683 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 129620.539683 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129620.539683 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 734 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 91 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 4.200000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.065934 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -3004,14 +3011,14 @@ system.iocache.demand_mshr_misses::realview.ide 252 system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 20173877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 20173877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2904688101 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2904688101 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 20173877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 20173877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 20173877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 20173877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 20064376 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 20064376 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2925516167 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2925516167 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 20064376 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 20064376 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 20064376 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 20064376 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -3020,603 +3027,602 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80055.067460 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 80055.067460 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80186.840244 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80186.840244 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80055.067460 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80055.067460 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80055.067460 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80055.067460 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79620.539683 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 79620.539683 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80761.819981 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80761.819981 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 79620.539683 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 79620.539683 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 79620.539683 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 79620.539683 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 129384 # number of replacements -system.l2c.tags.tagsinuse 63948.068698 # Cycle average of tags in use -system.l2c.tags.total_refs 411864 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 193785 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.125366 # Average number of references to valid blocks. +system.l2c.tags.replacements 124125 # number of replacements +system.l2c.tags.tagsinuse 63228.123175 # Cycle average of tags in use +system.l2c.tags.total_refs 440353 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 188206 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.339739 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12531.983329 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.494639 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 2.048364 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 6442.782513 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2029.980541 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34279.633489 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.674973 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.902888 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3492.124605 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1459.870620 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3683.572737 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.191223 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000221 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000031 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.098309 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.030975 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.523066 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000163 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 13402.508661 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.314049 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.063314 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8220.125540 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2863.958869 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34966.595872 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.597372 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909987 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1640.209162 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 501.782314 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1607.058034 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.204506 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000279 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.125429 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043701 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.533548 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000085 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.053286 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.022276 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.056207 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.975770 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 30986 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 30 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 33385 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 130 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6088 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 24764 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 427 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5063 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 27875 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.472809 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000458 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.509415 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5503227 # Number of tag accesses -system.l2c.tags.data_accesses 5503227 # Number of data accesses -system.l2c.Writeback_hits::writebacks 228886 # number of Writeback hits -system.l2c.Writeback_hits::total 228886 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2462 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 805 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3267 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 259 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 106 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 365 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3934 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2169 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 6103 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 184 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 77 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 33993 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 45721 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45094 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 77 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 41 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 17373 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11135 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 7486 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 161181 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 184 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 77 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 33993 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 49655 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 45094 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 77 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 41 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 17373 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 13304 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 7486 # number of demand (read+write) hits -system.l2c.demand_hits::total 167284 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 184 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 77 # number of overall hits -system.l2c.overall_hits::cpu0.inst 33993 # number of overall hits -system.l2c.overall_hits::cpu0.data 49655 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 45094 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 77 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 41 # number of overall hits -system.l2c.overall_hits::cpu1.inst 17373 # number of overall hits -system.l2c.overall_hits::cpu1.data 13304 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 7486 # number of overall hits -system.l2c.overall_hits::total 167284 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 8340 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3970 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12310 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 899 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1200 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2099 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 10813 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8272 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19085 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 24 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 5 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 17052 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 7978 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 127774 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 14 # number of ReadSharedReq misses +system.l2c.tags.occ_percent::cpu1.inst 0.025028 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.007657 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.024522 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.964785 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 30882 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 33176 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 142 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5961 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 24779 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 587 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4232 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 28320 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.471222 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000351 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.506226 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6006105 # Number of tag accesses +system.l2c.tags.data_accesses 6006105 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 259490 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 259490 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 32553 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1866 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 34419 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2126 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 980 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3106 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4199 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1537 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5736 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 245 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 135 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 35685 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 48934 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 48260 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 39 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 11 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 7748 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 5393 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 2770 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 149220 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 245 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 135 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 35685 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 53133 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 48260 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 39 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 11 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 7748 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 6930 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 2770 # number of demand (read+write) hits +system.l2c.demand_hits::total 154956 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 245 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 135 # number of overall hits +system.l2c.overall_hits::cpu0.inst 35685 # number of overall hits +system.l2c.overall_hits::cpu0.data 53133 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 48260 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 39 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 11 # number of overall hits +system.l2c.overall_hits::cpu1.inst 7748 # number of overall hits +system.l2c.overall_hits::cpu1.data 6930 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 2770 # number of overall hits +system.l2c.overall_hits::total 154956 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 9737 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2474 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 12211 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 860 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1323 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2183 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11128 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8036 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 19164 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 28 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 19547 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 9127 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 131840 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 6 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 5084 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 2174 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 9295 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 169401 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 24 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17052 # 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mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.529772 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75444.184652 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75349.496474 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75413.647522 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77427.701891 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76740 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 77034.542163 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 142007.953389 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123717.238878 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 134080.220068 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130916.666667 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 120800 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122503.372493 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 128931.436450 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148098.213322 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 126892.857143 # average ReadSharedReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.230244 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.570046 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.261870 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.288011 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.574468 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.412743 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.726039 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.839444 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.769639 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.102564 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.021739 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.353853 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.157197 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.732038 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.133333 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.083333 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.256236 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.151510 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.678692 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.532585 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.102564 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.021739 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.353853 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.275999 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.732038 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.133333 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.083333 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.256236 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.564944 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.678692 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.549735 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.102564 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.021739 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.353853 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.275999 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.732038 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.133333 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.083333 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.256236 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.564944 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.678692 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.549735 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75545.445209 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75297.493937 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75495.209238 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77613.373256 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76659.486017 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 77035.273019 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141701.923077 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123108.138377 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 133905.030265 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 137428.571429 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122524.560018 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 128226.416128 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 146825.506022 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 125166.666667 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125223.852669 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129307.957682 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166785.010005 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144712.780285 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130916.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 120800 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122503.372493 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136456.122612 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148098.213322 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126892.857143 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124118.869337 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130717.030114 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 170077.143394 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 143383.206188 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 137428.571429 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122524.560018 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135629.795112 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 146825.506022 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125166.666667 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125223.852669 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124880.767758 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166785.010005 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 143636.137449 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130916.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 120800 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122503.372493 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136456.122612 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148098.213322 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126892.857143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124118.869337 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123922.380264 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 170077.143394 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 142423.155007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 137428.571429 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122524.560018 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135629.795112 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 146825.506022 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125166.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125223.852669 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124880.767758 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166785.010005 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 143636.137449 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114525.299601 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183415.330215 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106887.254902 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146359.370420 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 161200.679380 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 151171.017895 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146506.380448 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149016.571337 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114525.299601 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 167874.031154 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106887.254902 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 146426.512803 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 155731.543232 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124118.869337 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123922.380264 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 170077.143394 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 142423.155007 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182200.248131 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116137.868852 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171355.441505 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164737.386413 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100066.751244 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159690.942802 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173952.160203 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109040.919810 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 166122.879936 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 38123 # Transaction distribution -system.membus.trans_dist::ReadResp 207766 # Transaction distribution -system.membus.trans_dist::WriteReq 31050 # Transaction distribution -system.membus.trans_dist::WriteResp 31050 # Transaction distribution -system.membus.trans_dist::Writeback 135856 # Transaction distribution -system.membus.trans_dist::CleanEvict 15674 # Transaction distribution -system.membus.trans_dist::UpgradeReq 78082 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41568 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14509 # Transaction distribution +system.membus.trans_dist::ReadReq 37995 # Transaction distribution +system.membus.trans_dist::ReadResp 208280 # Transaction distribution +system.membus.trans_dist::WriteReq 30910 # Transaction distribution +system.membus.trans_dist::WriteResp 30910 # Transaction distribution +system.membus.trans_dist::WritebackDirty 133887 # Transaction distribution +system.membus.trans_dist::CleanEvict 14956 # Transaction distribution +system.membus.trans_dist::UpgradeReq 74359 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40536 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14484 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 38794 # Transaction distribution -system.membus.trans_dist::ReadExResp 18985 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 169644 # Transaction distribution +system.membus.trans_dist::ReadExReq 38707 # Transaction distribution +system.membus.trans_dist::ReadExResp 19074 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 170286 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14282 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661810 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 784044 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13724 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 655631 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 777327 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108934 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 892978 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 886261 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18481720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18673398 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18402504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18593084 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20991542 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 125523 # Total snoops (count) -system.membus.snoop_fanout::samples 585264 # Request fanout histogram +system.membus.pkt_size::total 20911228 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 120617 # Total snoops (count) +system.membus.snoop_fanout::samples 578108 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 585264 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 578108 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 585264 # Request fanout histogram -system.membus.reqLayer0.occupancy 81621000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 578108 # Request fanout histogram +system.membus.reqLayer0.occupancy 81934000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11798981 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11360491 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 986725496 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 977870256 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1119474906 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1121733386 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64610767 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64044757 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -3659,56 +3665,56 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 957960 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 483276 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 165836 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 22284 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 21444 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 840 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 38126 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 494242 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31050 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31050 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 364748 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 86802 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 81249 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41933 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 123182 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 33 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 33 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50538 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50538 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 456132 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 989446 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 534228 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 146104 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 20085 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 19207 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 878 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 37998 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 475278 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30910 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30910 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 393382 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 89983 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 108688 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43642 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 152330 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50244 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50244 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 437296 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1043214 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 384499 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1427713 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31299443 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6394691 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 37694134 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 458404 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1229453 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.314167 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.465653 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1240411 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 256111 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1496522 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34963008 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3945788 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 38908796 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 440874 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 905624 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.341764 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.476341 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 844039 68.65% 68.65% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 384574 31.28% 99.93% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 840 0.07% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 596992 65.92% 65.92% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 307754 33.98% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 878 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1229453 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 827244513 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 905624 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 871666747 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 355623 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 356120 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 603608816 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 657174901 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 273833055 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 205942747 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 2086 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 1875 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2733 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2747 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |