diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | 3022 |
1 files changed, 1590 insertions, 1432 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 6d0b522dc..50e1ba197 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,71 +1,229 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.603785 # Number of seconds simulated -sim_ticks 2603784540500 # Number of ticks simulated -final_tick 2603784540500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.003417 # Number of seconds simulated +sim_ticks 1003417221500 # Number of ticks simulated +final_tick 1003417221500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66983 # Simulator instruction rate (inst/s) -host_op_rate 86203 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2766471262 # Simulator tick rate (ticks/s) -host_mem_usage 391460 # Number of bytes of host memory used -host_seconds 941.19 # Real time elapsed on the host -sim_insts 63043892 # Number of instructions simulated -sim_ops 81133946 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory +host_inst_rate 74785 # Simulator instruction rate (inst/s) +host_op_rate 96230 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1214309093 # Simulator tick rate (ticks/s) +host_mem_usage 406952 # Number of bytes of host memory used +host_seconds 826.33 # Real time elapsed on the host +sim_insts 61797296 # Number of instructions simulated +sim_ops 79517775 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 44040192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 398208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4365108 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 424768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5242032 # Number of bytes read from this memory -system.physmem.bytes_read::total 131542884 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 398208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 424768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 822976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4259200 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 410432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4376692 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 404672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5217200 # Number of bytes read from this memory +system.physmem.bytes_read::total 54451236 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 410432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 404672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4253056 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7288336 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7280144 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 5505024 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6222 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68277 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6637 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81933 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15301920 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66550 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6413 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68458 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6323 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81545 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5667795 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66454 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823834 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46513268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 152934 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1676447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 163135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2013236 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50519881 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 152934 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 163135 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316069 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1635773 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6529 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1156830 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2799132 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1635773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46513268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 152934 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1682976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 163135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3170066 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53319012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory +system.physmem.num_writes::total 823226 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43890209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 128 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 409034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 4361787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 403294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5199432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54265798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 409034 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 403294 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 812328 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4238572 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 16942 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2999837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7255351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4238572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43890209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 409034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4378729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 403294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 8199269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 61521149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5667795 # Total number of read requests seen +system.physmem.writeReqs 823226 # Total number of write requests seen +system.physmem.cpureqs 281286 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 362738880 # Total number of bytes read from memory +system.physmem.bytesWritten 52686464 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 54451236 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7280144 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 148 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 12596 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 354151 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 354519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 354412 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 354404 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 354227 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 354027 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 353803 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 353914 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 354718 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 354198 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 354245 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 354391 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 354136 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 354309 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 354144 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 354049 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50660 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50996 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50931 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50952 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51753 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51624 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51424 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51487 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51960 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51682 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51566 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51627 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51620 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51748 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51624 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51572 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 1152068 # Number of times wr buffer was full causing retry +system.physmem.totGap 1003416092000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 105 # Categorize read packet sizes +system.physmem.readPktSize::3 5505024 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 162666 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 1908840 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 66454 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 12596 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 5540802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 75454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 13035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 3176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 46980948909 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 148397952909 # Sum of mem lat for all requests +system.physmem.totBusLat 22670588000 # Total cycles spent in databus access +system.physmem.totBankLat 78746416000 # Total cycles spent in bank access +system.physmem.avgQLat 8289.32 # Average queueing delay per request +system.physmem.avgBankLat 13894.02 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 26183.34 # Average memory access latency +system.physmem.avgRdBW 361.50 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 52.51 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 54.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 7.26 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.59 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 11.87 # Average write queue length over time +system.physmem.readRowHits 5638305 # Number of row buffer hits during reads +system.physmem.writeRowHits 788804 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 95.82 # Row buffer hit rate for writes +system.physmem.avgGap 154585.25 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -75,246 +233,246 @@ system.realview.nvmem.bytes_inst_read::total 448 system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72716 # number of replacements -system.l2c.tagsinuse 53054.127627 # Cycle average of tags in use -system.l2c.total_refs 1921007 # Total number of references to valid blocks. -system.l2c.sampled_refs 137887 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.931748 # Average number of references to valid blocks. +system.realview.nvmem.bw_read::cpu0.inst 64 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 383 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 446 # 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number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3565367321 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6696083083 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 808528 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93002 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 250453593 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2613960813 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 830528 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 264569298 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3565367321 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6696083083 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4694165 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12372746053 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1876066 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154362129001 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166741445285 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 997094235 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 17119323408 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 18116417643 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4694165 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13369840288 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1876066 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171481452409 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184857862928 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000465 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015839 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036423 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000291 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010400 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.029938 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016984 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.820488 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.823672 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.821821 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.772137 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.738574 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.758967 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569218 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564317 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.566528 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000465 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015839 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.245795 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000291 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010400 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.242862 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.096019 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000465 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015839 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.245795 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000291 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010400 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.242862 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.096019 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 53901.866667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39862.102976 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 41253.392641 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 55368.533333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42142.290220 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45448.244336 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 42172.627649 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10089.580595 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10197.245919 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10134.732129 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10038.441896 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.319307 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10030.758034 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37077.415004 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42906.932935 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40264.319659 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53901.866667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39862.102976 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37453.051352 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55368.533333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42142.290220 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43095.384144 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40553.319947 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53901.866667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39862.102976 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37453.051352 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55368.533333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42142.290220 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43095.384144 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40553.319947 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -507,27 +665,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9065848 # DTB read hits -system.cpu0.dtb.read_misses 36360 # DTB read misses -system.cpu0.dtb.write_hits 5285915 # DTB write hits -system.cpu0.dtb.write_misses 6625 # DTB write misses +system.cpu0.dtb.read_hits 8990701 # DTB read hits +system.cpu0.dtb.read_misses 35639 # DTB read misses +system.cpu0.dtb.write_hits 5196869 # DTB write hits +system.cpu0.dtb.write_misses 6420 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2165 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1231 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 342 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2140 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1264 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 358 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9102208 # DTB read accesses -system.cpu0.dtb.write_accesses 5292540 # DTB write accesses +system.cpu0.dtb.perms_faults 552 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9026340 # DTB read accesses +system.cpu0.dtb.write_accesses 5203289 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14351763 # DTB hits -system.cpu0.dtb.misses 42985 # DTB misses -system.cpu0.dtb.accesses 14394748 # DTB accesses -system.cpu0.itb.inst_hits 4413372 # ITB inst hits -system.cpu0.itb.inst_misses 5476 # ITB inst misses +system.cpu0.dtb.hits 14187570 # DTB hits +system.cpu0.dtb.misses 42059 # DTB misses +system.cpu0.dtb.accesses 14229629 # DTB accesses +system.cpu0.itb.inst_hits 4354083 # ITB inst hits +system.cpu0.itb.inst_misses 5531 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -536,538 +694,538 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1374 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1363 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1472 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1565 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4418848 # ITB inst accesses -system.cpu0.itb.hits 4413372 # DTB hits -system.cpu0.itb.misses 5476 # DTB misses -system.cpu0.itb.accesses 4418848 # DTB accesses -system.cpu0.numCycles 70012496 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4359614 # ITB inst accesses +system.cpu0.itb.hits 4354083 # DTB hits +system.cpu0.itb.misses 5531 # DTB misses +system.cpu0.itb.accesses 4359614 # DTB accesses +system.cpu0.numCycles 68779590 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6217398 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4733750 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 327130 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 4014715 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 3051469 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6151354 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4687077 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 326469 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3738602 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 3006788 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 700588 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 31775 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 12151517 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 33217564 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6217398 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3752057 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7806548 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1581421 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 67728 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 22157211 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5913 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 54633 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 92488 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4411708 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 171100 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2593 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 43471985 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.986228 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.366083 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 689169 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 32083 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 11912972 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32706056 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6151354 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3695957 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7689921 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1565411 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 62995 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 21287015 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4643 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 56402 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 90248 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 164 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4352320 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 172729 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2628 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 42226826 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.000152 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.378860 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35673429 82.06% 82.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 623255 1.43% 83.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 822107 1.89% 85.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 699884 1.61% 87.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 794381 1.83% 88.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 577438 1.33% 90.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 719535 1.66% 91.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 371399 0.85% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3190557 7.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34545116 81.81% 81.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 600326 1.42% 83.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 813270 1.93% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 699242 1.66% 86.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 789636 1.87% 88.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 563805 1.34% 90.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 711205 1.68% 91.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 369975 0.88% 92.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3134251 7.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 43471985 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088804 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.474452 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12679354 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 22114744 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7023055 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 583785 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1071047 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 976895 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 65884 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 41430285 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 215511 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1071047 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 13270486 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5876098 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14061413 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6963478 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2229463 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 40231881 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2342 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 440788 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1249784 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 63 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 40621534 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 181781749 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 181747462 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34287 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31667723 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8953810 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 461246 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 417498 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5499956 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7912486 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5888217 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1140849 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1237786 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37992607 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 949484 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 38225982 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 89034 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6781394 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14357702 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 260797 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 43471985 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.879325 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.495049 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 42226826 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.089436 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.475520 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12413850 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21262916 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6920770 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 571279 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1058011 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 957289 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 65649 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40810463 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 214284 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1058011 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12995838 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5806909 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13316140 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6858946 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2190982 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39610027 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2116 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 435032 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1231897 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 105 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39982485 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 178864927 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 178830724 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34203 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31105315 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8877169 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 451261 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 410052 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5376793 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7771036 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5796008 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1117778 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1234382 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37385936 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 932152 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37680469 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 87348 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6705798 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 14225412 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 253293 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 42226826 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.892335 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.502142 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 27798434 63.95% 63.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6055917 13.93% 77.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3289826 7.57% 85.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2491193 5.73% 91.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2118698 4.87% 96.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 969648 2.23% 98.28% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 500024 1.15% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 192302 0.44% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 55943 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26789201 63.44% 63.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5974229 14.15% 77.59% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3183905 7.54% 85.13% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2487856 5.89% 91.02% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2118052 5.02% 96.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 933005 2.21% 98.25% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 499456 1.18% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 188083 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53039 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 43471985 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 42226826 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25214 2.35% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 458 0.04% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.39% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 837969 78.03% 80.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 210208 19.58% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 25386 2.38% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 456 0.04% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 843676 78.98% 81.40% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 198710 18.60% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22961950 60.07% 60.21% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 49879 0.13% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 15 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 12 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9545903 24.97% 85.31% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5615312 14.69% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22597326 59.97% 60.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48684 0.13% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 696 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9468734 25.13% 85.37% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5512785 14.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 38225982 # Type of FU issued -system.cpu0.iq.rate 0.545988 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1073849 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028092 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 121121114 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 45731569 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 35283041 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8365 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4658 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3880 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 39243245 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4372 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 321528 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37680469 # Type of FU issued +system.cpu0.iq.rate 0.547844 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1068228 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028350 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 118776881 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 45031578 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34706639 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8278 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4652 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3873 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38692178 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4305 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 310856 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1492825 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3508 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13401 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 615446 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1466992 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3639 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12971 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 614314 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149535 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5390 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192663 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5266 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1071047 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4218607 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 98464 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 39061403 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 95550 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7912486 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5888217 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 616723 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40108 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2851 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13401 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 172679 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 129654 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 302333 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37800204 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9383648 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 425778 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1058011 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4168228 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 100403 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38437075 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 94997 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7771036 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5796008 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 609484 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39021 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3188 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12971 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 173285 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 127529 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 300814 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37265519 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9306913 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 414950 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 119312 # number of nop insts executed -system.cpu0.iew.exec_refs 14941647 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4991029 # Number of branches executed -system.cpu0.iew.exec_stores 5557999 # Number of stores executed -system.cpu0.iew.exec_rate 0.539907 # Inst execution rate -system.cpu0.iew.wb_sent 37583639 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 35286921 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18740450 # num instructions producing a value -system.cpu0.iew.wb_consumers 35992151 # num instructions consuming a value +system.cpu0.iew.exec_nop 118987 # number of nop insts executed +system.cpu0.iew.exec_refs 14762216 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4927541 # Number of branches executed +system.cpu0.iew.exec_stores 5455303 # Number of stores executed +system.cpu0.iew.exec_rate 0.541811 # Inst execution rate +system.cpu0.iew.wb_sent 37049261 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34710512 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18431396 # num instructions producing a value +system.cpu0.iew.wb_consumers 35371181 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.504009 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520682 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.504663 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.521085 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6642216 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 688687 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 262418 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 42437322 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.753690 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.709171 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6565608 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 678859 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 262014 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 41204670 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.762989 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.718954 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 30360862 71.54% 71.54% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5984991 14.10% 85.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1981270 4.67% 90.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1011467 2.38% 92.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 801137 1.89% 94.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 524678 1.24% 95.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 395620 0.93% 96.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 217374 0.51% 97.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1159923 2.73% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29337596 71.20% 71.20% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5890386 14.30% 85.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1942613 4.71% 90.21% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 987342 2.40% 92.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 788686 1.91% 94.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 508616 1.23% 95.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 388471 0.94% 96.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 215239 0.52% 97.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1145721 2.78% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 42437322 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24255943 # Number of instructions committed -system.cpu0.commit.committedOps 31984592 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 41204670 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23832067 # Number of instructions committed +system.cpu0.commit.committedOps 31438729 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11692432 # Number of memory references committed -system.cpu0.commit.loads 6419661 # Number of loads committed -system.cpu0.commit.membars 234476 # Number of memory barriers committed -system.cpu0.commit.branches 4345348 # Number of branches committed +system.cpu0.commit.refs 11485738 # Number of memory references committed +system.cpu0.commit.loads 6304044 # Number of loads committed +system.cpu0.commit.membars 231899 # Number of memory barriers committed +system.cpu0.commit.branches 4278221 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28253924 # Number of committed integer instructions. -system.cpu0.commit.function_calls 499843 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1159923 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27759030 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489603 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1145721 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 79019948 # The number of ROB reads -system.cpu0.rob.rob_writes 78326882 # The number of ROB writes -system.cpu0.timesIdled 363516 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26540511 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5137512787 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24175201 # Number of Instructions Simulated -system.cpu0.committedOps 31903850 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24175201 # Number of Instructions Simulated -system.cpu0.cpi 2.896046 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.896046 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.345298 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.345298 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 176381452 # number of integer regfile reads -system.cpu0.int_regfile_writes 35063385 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3376 # number of floating regfile reads -system.cpu0.fp_regfile_writes 954 # number of floating regfile writes -system.cpu0.misc_regfile_reads 47472836 # number of misc regfile reads -system.cpu0.misc_regfile_writes 527620 # number of misc regfile writes -system.cpu0.icache.replacements 404634 # number of replacements -system.cpu0.icache.tagsinuse 511.577738 # Cycle average of tags in use -system.cpu0.icache.total_refs 3973841 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 405146 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.808417 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 7097415000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.577738 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999175 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999175 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3973841 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3973841 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3973841 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3973841 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3973841 # number of overall hits -system.cpu0.icache.overall_hits::total 3973841 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 437728 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 437728 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 437728 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 437728 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 437728 # number of overall misses -system.cpu0.icache.overall_misses::total 437728 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5954762997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5954762997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5954762997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5954762997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5954762997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5954762997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4411569 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4411569 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4411569 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4411569 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4411569 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4411569 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099223 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.099223 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099223 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.099223 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099223 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.099223 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13603.797328 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13603.797328 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13603.797328 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13603.797328 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13603.797328 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13603.797328 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2654 # number of cycles access was blocked +system.cpu0.rob.rob_reads 77195085 # The number of ROB reads +system.cpu0.rob.rob_writes 77069186 # The number of ROB writes +system.cpu0.timesIdled 361877 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26552764 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 1938011770 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23751325 # Number of Instructions Simulated +system.cpu0.committedOps 31357987 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23751325 # Number of Instructions Simulated +system.cpu0.cpi 2.895821 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.895821 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.345325 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.345325 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 173747096 # number of integer regfile reads +system.cpu0.int_regfile_writes 34492759 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3279 # number of floating regfile reads +system.cpu0.fp_regfile_writes 922 # number of floating regfile writes +system.cpu0.misc_regfile_reads 46707854 # number of misc regfile reads +system.cpu0.misc_regfile_writes 520465 # number of misc regfile writes +system.cpu0.icache.replacements 396840 # number of replacements +system.cpu0.icache.tagsinuse 510.969252 # Cycle average of tags in use +system.cpu0.icache.total_refs 3922693 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 397352 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.872086 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6841145000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.969252 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.997987 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.997987 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3922693 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3922693 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3922693 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3922693 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3922693 # number of overall hits +system.cpu0.icache.overall_hits::total 3922693 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 429491 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 429491 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 429491 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 429491 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 429491 # number of overall misses +system.cpu0.icache.overall_misses::total 429491 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5849216498 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5849216498 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5849216498 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5849216498 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5849216498 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5849216498 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4352184 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4352184 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4352184 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4352184 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4352184 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4352184 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.098684 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.098684 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.098684 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.098684 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.098684 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.098684 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13618.950101 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13618.950101 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13618.950101 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13618.950101 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13618.950101 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13618.950101 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2652 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 144 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 155 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.430556 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.109677 # 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miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.176819 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.176819 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13798.343115 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13798.343115 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40684.869896 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40684.869896 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9968.774570 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9968.774570 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9459.638943 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9459.638943 # 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number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 173763 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171376 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 171376 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8989204 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8989204 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8989204 # number of overall hits +system.cpu0.dcache.overall_hits::total 8989204 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 389353 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 389353 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1581371 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1581371 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8785 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8785 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7460 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7460 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1970724 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1970724 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1970724 # number of overall misses +system.cpu0.dcache.overall_misses::total 1970724 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5365294500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5365294500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60617239867 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60617239867 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88017500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88017500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46837000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46837000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 65982534367 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 65982534367 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 65982534367 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 65982534367 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6218068 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6218068 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4741860 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4741860 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182548 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 182548 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 178836 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 178836 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10959928 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10959928 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10959928 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10959928 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062616 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.062616 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333492 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333492 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048124 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048124 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.041714 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.041714 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.179812 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.179812 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.179812 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.179812 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13780.026095 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13780.026095 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38332.080117 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38332.080117 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10019.066591 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10019.066591 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6278.418231 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6278.418231 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33481.367440 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33481.367440 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33481.367440 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33481.367440 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8182 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3189 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 586 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 79 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.962457 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 40.367089 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255914 # number of writebacks -system.cpu0.dcache.writebacks::total 255914 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 200897 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 200897 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449259 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1449259 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 477 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 477 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1650156 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1650156 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1650156 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1650156 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189112 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189112 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131030 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131030 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8426 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8426 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7752 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7752 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320142 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320142 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 320142 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 320142 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2327531500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2327531500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4469430491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4469430491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67004000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67004000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 57855500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 57855500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6796961991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6796961991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6796961991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6796961991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13432598000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13432598000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1289898395 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1289898395 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14722496395 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14722496395 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029900 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029900 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027195 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027195 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045915 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045915 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043227 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043227 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028730 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028730 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028730 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028730 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12307.688037 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12307.688037 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34109.978562 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34109.978562 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7952.053169 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7952.053169 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7463.299794 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7463.299794 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21231.084928 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21231.084928 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21231.084928 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21231.084928 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256407 # number of writebacks +system.cpu0.dcache.writebacks::total 256407 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 200970 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 200970 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1450977 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1450977 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 427 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 427 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1651947 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1651947 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1651947 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1651947 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188383 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188383 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130394 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130394 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8358 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8358 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7458 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7458 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 318777 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 318777 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 318777 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 318777 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2337539000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2337539000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4029396491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4029396491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66744000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66744000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31921000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31921000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6366935491 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6366935491 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6366935491 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6366935491 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13497539000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13497539000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1126787391 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1126787391 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14624326391 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14624326391 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030296 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030296 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027498 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027498 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045785 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045785 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.041703 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.041703 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029086 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029086 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029086 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029086 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12408.439190 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12408.439190 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30901.701696 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30901.701696 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7985.642498 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7985.642498 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4280.101904 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4280.101904 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19973.007748 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19973.007748 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19973.007748 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19973.007748 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1077,27 +1235,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43411799 # DTB read hits -system.cpu1.dtb.read_misses 44882 # DTB read misses -system.cpu1.dtb.write_hits 7014123 # DTB write hits -system.cpu1.dtb.write_misses 11858 # DTB write misses +system.cpu1.dtb.read_hits 42793425 # DTB read hits +system.cpu1.dtb.read_misses 43166 # DTB read misses +system.cpu1.dtb.write_hits 6855715 # DTB write hits +system.cpu1.dtb.write_misses 11673 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2347 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3336 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 317 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2301 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3409 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 352 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 658 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43456681 # DTB read accesses -system.cpu1.dtb.write_accesses 7025981 # DTB write accesses +system.cpu1.dtb.perms_faults 655 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42836591 # DTB read accesses +system.cpu1.dtb.write_accesses 6867388 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50425922 # DTB hits -system.cpu1.dtb.misses 56740 # DTB misses -system.cpu1.dtb.accesses 50482662 # DTB accesses -system.cpu1.itb.inst_hits 9129638 # ITB inst hits -system.cpu1.itb.inst_misses 6055 # ITB inst misses +system.cpu1.dtb.hits 49649140 # DTB hits +system.cpu1.dtb.misses 54839 # DTB misses +system.cpu1.dtb.accesses 49703979 # DTB accesses +system.cpu1.itb.inst_hits 7790428 # ITB inst hits +system.cpu1.itb.inst_misses 6195 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1106,122 +1264,122 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1576 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1551 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1653 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1608 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 9135693 # ITB inst accesses -system.cpu1.itb.hits 9129638 # DTB hits -system.cpu1.itb.misses 6055 # DTB misses -system.cpu1.itb.accesses 9135693 # DTB accesses -system.cpu1.numCycles 413048277 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7796623 # ITB inst accesses +system.cpu1.itb.hits 7790428 # DTB hits +system.cpu1.itb.misses 6195 # DTB misses +system.cpu1.itb.accesses 7796623 # DTB accesses +system.cpu1.numCycles 407481845 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9610060 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 7888453 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 467347 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6680212 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5602853 # Number of BTB hits +system.cpu1.BPredUnit.lookups 8945563 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7276620 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 457303 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 6059330 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5044901 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 834872 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 50683 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 20902821 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 71155819 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9610060 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6437725 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 15200148 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4519747 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 75962 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 79085155 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5881 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 48956 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 142448 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 113 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 9127576 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 837727 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3443 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 118542872 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.725366 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.076680 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 808900 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 49599 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 19209398 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 61160390 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8945563 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5853801 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13372143 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3528800 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 72716 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77592776 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4530 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 48363 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 137630 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 183 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7788411 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 558980 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3579 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 112853111 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.663918 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.993452 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 103350754 87.18% 87.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 840912 0.71% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1013712 0.86% 88.75% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2056350 1.73% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1628340 1.37% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 605586 0.51% 92.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2262195 1.91% 94.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 445115 0.38% 94.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 6339908 5.35% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 99488795 88.16% 88.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 820731 0.73% 88.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 982302 0.87% 89.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1718236 1.52% 91.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1416689 1.26% 92.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 588425 0.52% 93.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1946926 1.73% 94.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 433337 0.38% 95.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5457670 4.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 118542872 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.023266 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.172270 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 22607772 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 78712094 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 13698658 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 543937 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2980411 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1178240 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 102814 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 80488884 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 342985 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2980411 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 24131061 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32829819 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 41497762 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 12625753 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4478066 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 74194515 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 19311 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 694411 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3187694 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 34028 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 78612274 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 341980095 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 341920829 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59266 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50181552 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 28430722 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 479709 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 419295 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8182404 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13956070 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8535310 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1073815 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1496663 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 66987245 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1207542 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 91662010 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 107326 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18596353 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 52788554 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 287891 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 118542872 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.773239 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.509704 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 112853111 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.021953 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.150094 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20594111 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 77223821 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12189210 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 529456 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2316513 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1140486 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 100773 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 70872122 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 333080 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2316513 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 21811188 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 31999564 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40913868 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11406608 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4405370 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 66851676 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 19516 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 679552 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3147713 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 33677 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 70148588 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 306845192 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 306785894 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59298 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49106817 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 21041771 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 463027 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 405725 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7962793 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12778752 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8032472 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1035556 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1464082 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 61394803 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1176532 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 88185041 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 108507 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 14048968 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 37726295 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 276552 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 112853111 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.781414 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519020 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 87045508 73.43% 73.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8827320 7.45% 80.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4565356 3.85% 84.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3971386 3.35% 88.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10748062 9.07% 97.14% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1958505 1.65% 98.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1059536 0.89% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 289761 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 77438 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 82669825 73.25% 73.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8481760 7.52% 80.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4273659 3.79% 84.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3671895 3.25% 87.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10427666 9.24% 97.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1949609 1.73% 98.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1042899 0.92% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 262209 0.23% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 73589 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 118542872 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 112853111 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 27804 0.35% 0.35% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 991 0.01% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 26972 0.34% 0.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 996 0.01% 0.36% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.36% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.36% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.36% # attempts to use FU when none available @@ -1249,395 +1407,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.36% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.36% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.36% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.36% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7575099 95.91% 96.28% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 294066 3.72% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7550123 96.09% 96.44% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 279583 3.56% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 313737 0.34% 0.34% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 39285679 42.86% 43.20% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61425 0.07% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1694 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.27% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44600762 48.66% 91.93% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7398685 8.07% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313997 0.36% 0.36% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36904735 41.85% 42.21% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59478 0.07% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1462 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.27% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43687858 49.54% 91.82% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7217483 8.18% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 91662010 # Type of FU issued -system.cpu1.iq.rate 0.221916 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7897960 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.086164 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 309913949 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 86800137 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 55536555 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14796 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8070 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6801 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 99238492 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7741 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 357612 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 88185041 # Type of FU issued +system.cpu1.iq.rate 0.216415 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7857674 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.089104 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 297228981 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 76628774 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53465228 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15030 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8076 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6856 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 95720841 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7877 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 343881 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3966417 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 4317 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17649 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1516764 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3018668 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4236 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17116 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1176826 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31964885 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1028430 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31906521 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 692078 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2980411 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24884610 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 372296 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 68300564 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 134907 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13956070 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8535310 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 896808 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 67508 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3396 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17649 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 244559 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 171299 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 415858 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 88842251 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43794323 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2819759 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2316513 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24121346 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 362647 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 62677152 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 130612 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12778752 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8032472 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 873727 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 64946 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3806 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17116 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 239035 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 168853 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 407888 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86386034 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43162344 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1799007 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105777 # number of nop insts executed -system.cpu1.iew.exec_refs 51113945 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7256967 # Number of branches executed -system.cpu1.iew.exec_stores 7319622 # Number of stores executed -system.cpu1.iew.exec_rate 0.215089 # Inst execution rate -system.cpu1.iew.wb_sent 87693649 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 55543356 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30809625 # num instructions producing a value -system.cpu1.iew.wb_consumers 54951337 # num instructions consuming a value +system.cpu1.iew.exec_nop 105817 # number of nop insts executed +system.cpu1.iew.exec_refs 50303914 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6949979 # Number of branches executed +system.cpu1.iew.exec_stores 7141570 # Number of stores executed +system.cpu1.iew.exec_rate 0.212000 # Inst execution rate +system.cpu1.iew.wb_sent 85560494 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53472084 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29815301 # num instructions producing a value +system.cpu1.iew.wb_consumers 53181116 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.134472 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560671 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131226 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560637 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 18558974 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 919651 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 366370 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 115610884 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.426428 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.387814 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 14046998 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 899980 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 358444 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 110583599 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.436135 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.404322 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 98380656 85.10% 85.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8456019 7.31% 92.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2240447 1.94% 94.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1287846 1.11% 95.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1284560 1.11% 96.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 584416 0.51% 97.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1022455 0.88% 97.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 531646 0.46% 98.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1822839 1.58% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 93772628 84.80% 84.80% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8260056 7.47% 92.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2160964 1.95% 94.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1246626 1.13% 95.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1244768 1.13% 96.47% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 580382 0.52% 97.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 994186 0.90% 97.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 530445 0.48% 98.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1793544 1.62% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 115610884 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38938330 # Number of instructions committed -system.cpu1.commit.committedOps 49299735 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 110583599 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38115610 # Number of instructions committed +system.cpu1.commit.committedOps 48229427 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17008199 # Number of memory references committed -system.cpu1.commit.loads 9989653 # Number of loads committed -system.cpu1.commit.membars 202304 # Number of memory barriers committed -system.cpu1.commit.branches 6136573 # Number of branches committed -system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43691789 # Number of committed integer instructions. -system.cpu1.commit.function_calls 556207 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1822839 # number cycles where commit BW limit reached +system.cpu1.commit.refs 16615730 # Number of memory references committed +system.cpu1.commit.loads 9760084 # Number of loads committed +system.cpu1.commit.membars 196512 # Number of memory barriers committed +system.cpu1.commit.branches 5981373 # Number of branches committed +system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 42745221 # Number of committed integer instructions. +system.cpu1.commit.function_calls 536771 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1793544 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 180532357 # The number of ROB reads -system.cpu1.rob.rob_writes 138785705 # The number of ROB writes -system.cpu1.timesIdled 1423841 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294505405 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4793867333 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38868691 # Number of Instructions Simulated -system.cpu1.committedOps 49230096 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38868691 # Number of Instructions Simulated -system.cpu1.cpi 10.626761 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.626761 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.094102 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.094102 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 397649399 # number of integer regfile reads -system.cpu1.int_regfile_writes 58356680 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4927 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2334 # number of floating regfile writes -system.cpu1.misc_regfile_reads 90861332 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429704 # number of misc regfile writes -system.cpu1.icache.replacements 621691 # number of replacements -system.cpu1.icache.tagsinuse 498.705536 # Cycle average of tags in use -system.cpu1.icache.total_refs 8457096 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 622203 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.592181 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74944474500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.705536 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974034 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974034 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 8457096 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 8457096 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 8457096 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 8457096 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 8457096 # number of overall hits -system.cpu1.icache.overall_hits::total 8457096 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 670427 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 670427 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 670427 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 670427 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 670427 # number of overall misses -system.cpu1.icache.overall_misses::total 670427 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8963788993 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8963788993 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8963788993 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8963788993 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8963788993 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8963788993 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 9127523 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 9127523 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 9127523 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 9127523 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 9127523 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 9127523 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073451 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.073451 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073451 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.073451 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073451 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.073451 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13370.268490 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13370.268490 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13370.268490 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13370.268490 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13370.268490 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13370.268490 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2125 # number of cycles access was blocked +system.cpu1.rob.rob_reads 169976861 # The number of ROB reads +system.cpu1.rob.rob_writes 126957772 # The number of ROB writes +system.cpu1.timesIdled 1410203 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 294628734 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1598708296 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38045971 # Number of Instructions Simulated +system.cpu1.committedOps 48159788 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38045971 # Number of Instructions Simulated +system.cpu1.cpi 10.710250 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.710250 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.093369 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.093369 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 386616069 # number of integer regfile reads +system.cpu1.int_regfile_writes 55621377 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5021 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes +system.cpu1.misc_regfile_reads 80414047 # number of misc regfile reads +system.cpu1.misc_regfile_writes 414877 # number of misc regfile writes +system.cpu1.icache.replacements 603717 # number of replacements +system.cpu1.icache.tagsinuse 477.821623 # Cycle average of tags in use +system.cpu1.icache.total_refs 7136949 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 604229 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 11.811662 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74643061500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 477.821623 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.933245 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.933245 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7136949 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7136949 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7136949 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7136949 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7136949 # number of overall hits +system.cpu1.icache.overall_hits::total 7136949 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 651410 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 651410 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 651410 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 651410 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 651410 # number of overall misses +system.cpu1.icache.overall_misses::total 651410 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8713848493 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8713848493 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8713848493 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8713848493 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8713848493 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8713848493 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7788359 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7788359 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7788359 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7788359 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7788359 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7788359 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.083639 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.083639 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.083639 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.083639 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.083639 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.083639 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13376.903169 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13376.903169 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13376.903169 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13376.903169 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13376.903169 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13376.903169 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2264 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 190 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 195 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.184211 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.610256 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48189 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 48189 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 48189 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 48189 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 48189 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 48189 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622238 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 622238 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 622238 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 622238 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 622238 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 622238 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7328903994 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7328903994 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7328903994 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7328903994 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7328903994 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7328903994 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3208500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3208500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3208500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3208500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068172 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068172 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068172 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.068172 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068172 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.068172 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11778.297041 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11778.297041 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11778.297041 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11778.297041 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11778.297041 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11778.297041 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 47151 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 47151 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 47151 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 47151 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 47151 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 47151 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 604259 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 604259 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 604259 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 604259 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 604259 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 604259 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7123176495 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7123176495 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7123176495 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7123176495 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7123176495 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7123176495 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2925000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2925000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2925000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 2925000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.077585 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.077585 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.077585 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.077585 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.077585 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.077585 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11788.283658 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11788.283658 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11788.283658 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11788.283658 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11788.283658 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11788.283658 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 363699 # number of replacements -system.cpu1.dcache.tagsinuse 487.062362 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13149394 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 364069 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 36.117862 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 71012585000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.062362 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.951294 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.951294 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8615849 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8615849 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4289025 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4289025 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 104659 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 104659 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100738 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 100738 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12904874 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12904874 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12904874 # number of overall hits -system.cpu1.dcache.overall_hits::total 12904874 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 398775 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 398775 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1559814 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1559814 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14251 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14251 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10935 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10935 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1958589 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1958589 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1958589 # number of overall misses -system.cpu1.dcache.overall_misses::total 1958589 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5911762000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5911762000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 56390406018 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 56390406018 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131021000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 131021000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 76240500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 76240500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 62302168018 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 62302168018 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 62302168018 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 62302168018 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9014624 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9014624 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5848839 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5848839 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 118910 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 118910 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111673 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 111673 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14863463 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14863463 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14863463 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14863463 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044236 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.044236 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.266688 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.266688 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119847 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119847 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097920 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097920 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131772 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.131772 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131772 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.131772 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14824.805968 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14824.805968 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36152.006597 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 36152.006597 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9193.810961 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9193.810961 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6972.153635 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6972.153635 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31809.720170 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 31809.720170 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31809.720170 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 31809.720170 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 24015 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 11108 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3240 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.412037 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 66.119048 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 361595 # number of replacements +system.cpu1.dcache.tagsinuse 471.853912 # Cycle average of tags in use +system.cpu1.dcache.total_refs 12785596 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 361945 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.324693 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70722416000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 471.853912 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.921590 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.921590 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8396303 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8396303 # 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number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1556734 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14120 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14120 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10568 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10568 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1953254 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1953254 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1953254 # number of overall misses +system.cpu1.dcache.overall_misses::total 1953254 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5917747500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5917747500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 64024313001 # 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average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 35807.969932 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35807.969932 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 35807.969932 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 27667 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 15981 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3202 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 157 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.640537 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 101.789809 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 328533 # number of writebacks -system.cpu1.dcache.writebacks::total 328533 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 166830 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 166830 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1397003 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1397003 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1431 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1431 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1563833 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1563833 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1563833 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1563833 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231945 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231945 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162811 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 162811 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12820 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12820 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10928 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10928 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394756 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 394756 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394756 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394756 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2840785000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2840785000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5178833227 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5178833227 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89705500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89705500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 54384500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 54384500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8019618227 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8019618227 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8019618227 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8019618227 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169259240500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169259240500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40718348836 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40718348836 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 209977589336 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 209977589336 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025730 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025730 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027836 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027836 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107813 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107813 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097857 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097857 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026559 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026559 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026559 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026559 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12247.666473 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12247.666473 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31808.865660 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31808.865660 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6997.308892 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6997.308892 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4976.619693 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4976.619693 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20315.380202 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20315.380202 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20315.380202 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20315.380202 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 325945 # number of writebacks +system.cpu1.dcache.writebacks::total 325945 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 167650 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 167650 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1394870 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1394870 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1440 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1440 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1562520 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1562520 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1562520 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1562520 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228870 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228870 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161864 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161864 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12680 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12680 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10565 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10565 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 390734 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 390734 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 390734 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 390734 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2822036500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2822036500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5251302714 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5251302714 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90148000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90148000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32112000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32112000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8073339214 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8073339214 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8073339214 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8073339214 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168945425000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168945425000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 26941470024 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 26941470024 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195886895024 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195886895024 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026029 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026029 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028353 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028353 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.108401 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.108401 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096945 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096945 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026944 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026944 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026944 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026944 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12330.303229 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12330.303229 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32442.684686 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32442.684686 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7109.463722 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7109.463722 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3039.469948 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3039.469948 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20661.982868 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20661.982868 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20661.982868 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20661.982868 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1659,18 +1817,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1218779341193 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1218779341193 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1218779341193 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1218779341193 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 421898642152 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 421898642152 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 421898642152 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 421898642152 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43799 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43084 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53911 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 52242 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |