diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | 3172 |
1 files changed, 1584 insertions, 1588 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index ee857cd58..5f98a27d9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,155 +1,173 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.102937 # Number of seconds simulated -sim_ticks 1102936899000 # Number of ticks simulated -final_tick 1102936899000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.602779 # Number of seconds simulated +sim_ticks 2602778916500 # Number of ticks simulated +final_tick 2602778916500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56405 # Simulator instruction rate (inst/s) -host_op_rate 72609 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1010130266 # Simulator tick rate (ticks/s) -host_mem_usage 440004 # Number of bytes of host memory used -host_seconds 1091.88 # Real time elapsed on the host -sim_insts 61587196 # Number of instructions simulated -sim_ops 79280303 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory +host_inst_rate 24161 # Simulator instruction rate (inst/s) +host_op_rate 31106 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1001764915 # Simulator tick rate (ticks/s) +host_mem_usage 444424 # Number of bytes of host memory used +host_seconds 2598.19 # Real time elapsed on the host +sim_insts 62774383 # Number of instructions simulated +sim_ops 80820330 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 148 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 148 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 148 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 408960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4359540 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 395584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4382196 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 406528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5228208 # Number of bytes read from this memory -system.physmem.bytes_read::total 59164324 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 408960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 406528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 815488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4242368 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 426624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5245232 # Number of bytes read from this memory +system.physmem.bytes_read::total 131562340 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 395584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 426624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 822208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4273600 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7269712 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7302736 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6390 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68190 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6181 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68544 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6352 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81717 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257533 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66287 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6666 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81983 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15302224 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66775 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823123 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44208136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 370792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3952665 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 368587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4740260 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53642528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 370792 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 368587 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 739379 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3846429 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2729389 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6591231 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3846429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44208136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 232 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 370792 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3968078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 368587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7469649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60233760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257533 # Total number of read requests seen -system.physmem.writeReqs 823123 # Total number of write requests seen -system.physmem.cpureqs 241438 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400482112 # Total number of bytes read from memory -system.physmem.bytesWritten 52679872 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59164324 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7269712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 127 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12571 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391437 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 390831 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391593 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391498 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 390850 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 390980 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 391704 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391387 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 390658 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 390771 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 391161 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 391176 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390450 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 390424 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 391246 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51442 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51251 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51666 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51519 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50946 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51023 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51720 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52026 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51302 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51417 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51816 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51807 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51192 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51881 # Track writes on a per bank basis +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 824059 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46531239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 151985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1683660 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 163911 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2015243 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50546875 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 151985 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 163911 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315896 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1641937 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6531 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1157277 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2805746 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1641937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46531239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 151985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1690192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 163911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3172520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53352621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15302224 # Total number of read requests seen +system.physmem.writeReqs 824059 # Total number of write requests seen +system.physmem.cpureqs 244149 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 979342336 # Total number of bytes read from memory +system.physmem.bytesWritten 52739776 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131562340 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7302736 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 337 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 14071 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 956626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 956229 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956838 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956744 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 956129 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 956236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956861 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956721 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955985 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 956063 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 956435 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956372 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955730 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 955657 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 956452 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51554 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51377 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51697 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51535 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50985 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51049 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51663 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52119 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51405 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51482 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51861 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51782 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51276 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51190 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51930 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32625 # Number of times wr buffer was full causing retry -system.physmem.totGap 1102935703000 # Total gap between requests +system.physmem.numWrRetry 32645 # Number of times wr buffer was full causing retry +system.physmem.totGap 2602777722500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes -system.physmem.readPktSize::3 6094848 # Categorize read packet sizes +system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 162580 # Categorize read packet sizes +system.physmem.readPktSize::6 163303 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 756836 # Categorize write packet sizes +system.physmem.writePktSize::2 757284 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66287 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 494185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 430784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 392337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1441558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1085468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1097761 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1063978 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 26861 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24868 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 44400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 63675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 44199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 11871 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 15313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 7884 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66775 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1059619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 995756 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 964447 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3596573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2710922 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2723432 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2682017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 62131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 60256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 110205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 159682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109728 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17046 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 12933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -160,322 +178,304 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2995 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 3034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32641 # What write queue length does an incoming req see -system.physmem.totQLat 199281441500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 239111429000 # Sum of mem lat for all requests -system.physmem.totBusLat 31287030000 # Total cycles spent in databus access -system.physmem.totBankLat 8542957500 # Total cycles spent in bank access -system.physmem.avgQLat 31847.29 # Average queueing delay per request -system.physmem.avgBankLat 1365.26 # Average bank access latency per request +system.physmem.wrQLenPdf::4 3062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32658 # What write queue length does an incoming req see +system.physmem.totQLat 398163291750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 491955679250 # Sum of mem lat for all requests +system.physmem.totBusLat 76509435000 # Total cycles spent in databus access +system.physmem.totBankLat 17282952500 # Total cycles spent in bank access +system.physmem.avgQLat 26020.54 # Average queueing delay per request +system.physmem.avgBankLat 1129.47 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38212.55 # Average memory access latency -system.physmem.avgRdBW 363.11 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 47.76 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.64 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.59 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 32150.00 # Average memory access latency +system.physmem.avgRdBW 376.27 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.26 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.55 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.81 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.21 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.22 # Average read queue length over time -system.physmem.avgWrQLen 11.59 # Average write queue length over time -system.physmem.readRowHits 6213376 # Number of row buffer hits during reads -system.physmem.writeRowHits 799550 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads +system.physmem.busUtil 3.10 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.19 # Average read queue length over time +system.physmem.avgWrQLen 12.56 # Average write queue length over time +system.physmem.readRowHits 15222567 # Number of row buffer hits during reads +system.physmem.writeRowHits 800487 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.14 # Row buffer hit rate for writes -system.physmem.avgGap 155767.45 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72282 # number of replacements -system.l2c.tagsinuse 53744.299693 # Cycle average of tags in use -system.l2c.total_refs 1841477 # Total number of references to valid blocks. -system.l2c.sampled_refs 137500 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.392560 # Average number of references to valid blocks. +system.physmem.avgGap 161399.73 # Average gap between requests +system.l2c.replacements 73011 # number of replacements +system.l2c.tagsinuse 53067.424425 # Cycle average of tags in use +system.l2c.total_refs 1872250 # Total number of references to valid blocks. +system.l2c.sampled_refs 138181 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.549258 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39371.893894 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 5.466670 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 1.665850 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4003.284493 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2820.568488 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 11.108443 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.919823 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3725.007986 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3804.384047 # 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Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.955179 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4039.578813 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4118.949534 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.575955 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000084 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.063991 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.044998 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000214 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.061639 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.062850 # 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average ReadReq mshr uncacheable latency @@ -678,38 +678,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 6001640 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4577059 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 296005 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3758008 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2912273 # Number of BTB hits +system.cpu0.branchPred.lookups 6065134 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4623218 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 295247 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3783915 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2943990 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.495125 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 673236 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28713 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.802752 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 682666 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28697 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8910999 # DTB read hits -system.cpu0.dtb.read_misses 29151 # DTB read misses -system.cpu0.dtb.write_hits 5140269 # DTB write hits -system.cpu0.dtb.write_misses 5702 # DTB write misses +system.cpu0.dtb.read_hits 8964880 # DTB read hits +system.cpu0.dtb.read_misses 29505 # DTB read misses +system.cpu0.dtb.write_hits 5211507 # DTB write hits +system.cpu0.dtb.write_misses 5768 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1812 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1035 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 300 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1820 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1111 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 256 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 584 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8940150 # DTB read accesses -system.cpu0.dtb.write_accesses 5145971 # DTB write accesses +system.cpu0.dtb.perms_faults 587 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8994385 # DTB read accesses +system.cpu0.dtb.write_accesses 5217275 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14051268 # DTB hits -system.cpu0.dtb.misses 34853 # DTB misses -system.cpu0.dtb.accesses 14086121 # DTB accesses -system.cpu0.itb.inst_hits 4221147 # ITB inst hits -system.cpu0.itb.inst_misses 5166 # ITB inst misses +system.cpu0.dtb.hits 14176387 # DTB hits +system.cpu0.dtb.misses 35273 # DTB misses +system.cpu0.dtb.accesses 14211660 # DTB accesses +system.cpu0.itb.inst_hits 4271941 # ITB inst hits +system.cpu0.itb.inst_misses 5082 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -718,534 +718,534 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1340 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1454 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1395 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4226313 # ITB inst accesses -system.cpu0.itb.hits 4221147 # DTB hits -system.cpu0.itb.misses 5166 # DTB misses -system.cpu0.itb.accesses 4226313 # DTB accesses -system.cpu0.numCycles 67826289 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4277023 # ITB inst accesses +system.cpu0.itb.hits 4271941 # DTB hits +system.cpu0.itb.misses 5082 # DTB misses +system.cpu0.itb.accesses 4277023 # DTB accesses +system.cpu0.numCycles 68310391 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11756286 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32014298 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6001640 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3585509 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7517140 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1455004 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 67247 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20650253 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4770 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 46433 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 85685 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 203 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4219566 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157765 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2202 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41172573 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.004783 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.385116 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11985780 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32442629 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6065134 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3626656 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7605462 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1460769 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 62659 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 21080761 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5794 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46842 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 87230 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 220 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4270468 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157226 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2109 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41924364 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.999512 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.380874 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33662869 81.76% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 565639 1.37% 83.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 818038 1.99% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 675166 1.64% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 774675 1.88% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 559568 1.36% 90.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 667522 1.62% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 352154 0.86% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3096942 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34326103 81.88% 81.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 570380 1.36% 83.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 823787 1.96% 85.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 686899 1.64% 86.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 778226 1.86% 88.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 563231 1.34% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 676382 1.61% 91.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 356953 0.85% 92.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3142403 7.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41172573 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088485 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.472004 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12265416 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20593296 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6819123 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 513990 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 980748 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 935580 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64947 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40010595 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213478 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 980748 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12833750 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5743138 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12737000 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6715008 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2162929 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38912871 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1796 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 435724 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1235455 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 48 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39264355 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175753145 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175718969 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34176 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30934227 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8330127 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411039 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370083 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5348370 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7652222 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5686978 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1127413 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1231482 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36837080 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895317 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37247377 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80474 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6286180 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13172304 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256448 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41172573 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.904665 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.512453 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41924364 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088788 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.474930 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12503811 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21012915 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6898585 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 522974 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 986079 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 948336 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64663 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40543036 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 211520 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 986079 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 13078116 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5721380 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13152385 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6797650 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2188754 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39433741 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1845 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 443177 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1244404 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 41 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39808870 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 178177695 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 178143549 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34146 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31430562 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8378307 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 419823 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 376669 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5441918 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7757618 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5774212 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1139116 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1209168 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37348543 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 904610 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37701629 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 81879 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6330369 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13296779 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 257143 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41924364 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.899277 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.510411 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26032414 63.23% 63.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5734790 13.93% 77.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3160933 7.68% 84.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2474953 6.01% 90.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2097868 5.10% 95.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 946815 2.30% 98.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 486964 1.18% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 184157 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53679 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26590532 63.43% 63.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5818938 13.88% 77.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3210799 7.66% 84.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2498063 5.96% 90.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2114705 5.04% 95.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 942628 2.25% 98.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 502674 1.20% 99.41% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 189300 0.45% 99.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 56725 0.14% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41172573 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41924364 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26092 2.44% 2.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 452 0.04% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 843251 78.76% 81.24% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 200824 18.76% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 26752 2.49% 2.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 460 0.04% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 840001 78.12% 80.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 208012 19.35% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22332748 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46981 0.13% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9367267 25.15% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5447389 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22644819 60.06% 60.20% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48004 0.13% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9425277 25.00% 85.33% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5530613 14.67% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37247377 # Type of FU issued -system.cpu0.iq.rate 0.549158 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1070619 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028743 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 116844627 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44026356 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34344813 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8420 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4690 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3883 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38261309 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4408 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 307850 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37701629 # Type of FU issued +system.cpu0.iq.rate 0.551916 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1075225 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028519 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 118511451 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44591434 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34839098 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8242 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4622 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3868 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38720352 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4288 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 316630 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1374402 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2480 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12973 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 535370 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1380313 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2666 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13062 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 544614 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192711 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5613 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149563 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5584 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 980748 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4124012 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 98712 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37850539 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 85674 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7652222 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5686978 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571475 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40167 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2962 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12973 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149952 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 118190 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 268142 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36871873 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9226575 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 375504 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 986079 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4106132 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 100687 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38371433 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 85430 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7757618 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5774212 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 577195 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40897 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3001 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13062 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150158 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117749 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267907 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37323557 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9281925 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 378072 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118142 # number of nop insts executed -system.cpu0.iew.exec_refs 14626690 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4856874 # Number of branches executed -system.cpu0.iew.exec_stores 5400115 # Number of stores executed -system.cpu0.iew.exec_rate 0.543622 # Inst execution rate -system.cpu0.iew.wb_sent 36677250 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34348696 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18291021 # num instructions producing a value -system.cpu0.iew.wb_consumers 35196356 # num instructions consuming a value +system.cpu0.iew.exec_nop 118280 # number of nop insts executed +system.cpu0.iew.exec_refs 14765828 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4915455 # Number of branches executed +system.cpu0.iew.exec_stores 5483903 # Number of stores executed +system.cpu0.iew.exec_rate 0.546382 # Inst execution rate +system.cpu0.iew.wb_sent 37128467 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34842966 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18565053 # num instructions producing a value +system.cpu0.iew.wb_consumers 35706535 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.506422 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519685 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.510068 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.519934 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6101158 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638869 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232197 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40191825 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.778547 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.740754 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6140110 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 647467 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 231710 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40938285 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.775989 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.737548 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28520633 70.96% 70.96% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5717076 14.22% 85.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1914444 4.76% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 974820 2.43% 92.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 784169 1.95% 94.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 523265 1.30% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 386798 0.96% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 217938 0.54% 97.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1152682 2.87% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29080513 71.04% 71.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5796475 14.16% 85.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1964427 4.80% 89.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 998229 2.44% 92.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 793584 1.94% 94.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 517255 1.26% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 395614 0.97% 96.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 224138 0.55% 97.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1168050 2.85% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40191825 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23681661 # Number of instructions committed -system.cpu0.commit.committedOps 31291235 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40938285 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24057849 # Number of instructions committed +system.cpu0.commit.committedOps 31767677 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11429428 # Number of memory references committed -system.cpu0.commit.loads 6277820 # Number of loads committed -system.cpu0.commit.membars 229679 # Number of memory barriers committed -system.cpu0.commit.branches 4245347 # Number of branches committed +system.cpu0.commit.refs 11606903 # Number of memory references committed +system.cpu0.commit.loads 6377305 # Number of loads committed +system.cpu0.commit.membars 231785 # Number of memory barriers committed +system.cpu0.commit.branches 4305044 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27647557 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489379 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1152682 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 28078801 # Number of committed integer instructions. +system.cpu0.commit.function_calls 498475 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1168050 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75580359 # The number of ROB reads -system.cpu0.rob.rob_writes 75767781 # The number of ROB writes -system.cpu0.timesIdled 360539 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26653716 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2138005786 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23600919 # Number of Instructions Simulated -system.cpu0.committedOps 31210493 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23600919 # Number of Instructions Simulated -system.cpu0.cpi 2.873883 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.873883 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.347961 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.347961 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171874490 # number of integer regfile reads -system.cpu0.int_regfile_writes 34096600 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3230 # number of floating regfile reads -system.cpu0.fp_regfile_writes 872 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13012666 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451076 # number of misc regfile writes -system.cpu0.icache.replacements 392591 # number of replacements -system.cpu0.icache.tagsinuse 511.076357 # Cycle average of tags in use -system.cpu0.icache.total_refs 3795579 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 393103 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.655431 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.076357 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998196 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998196 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3795579 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3795579 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3795579 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3795579 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3795579 # number of overall hits -system.cpu0.icache.overall_hits::total 3795579 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 423854 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 423854 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 423854 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 423854 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 423854 # number of overall misses -system.cpu0.icache.overall_misses::total 423854 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5804082997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5804082997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5804082997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5804082997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5804082997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5804082997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4219433 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4219433 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4219433 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4219433 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4219433 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4219433 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100453 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100453 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100453 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100453 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100453 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100453 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13693.590239 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13693.590239 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13693.590239 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13693.590239 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13693.590239 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13693.590239 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2620 # number of cycles access was blocked +system.cpu0.rob.rob_reads 76811981 # The number of ROB reads +system.cpu0.rob.rob_writes 76803371 # The number of ROB writes +system.cpu0.timesIdled 362519 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26386027 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5137205074 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23977107 # Number of Instructions Simulated +system.cpu0.committedOps 31686935 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23977107 # Number of Instructions Simulated +system.cpu0.cpi 2.848984 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.848984 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.351002 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.351002 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 174070948 # number of integer regfile reads +system.cpu0.int_regfile_writes 34592870 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3226 # number of floating regfile reads +system.cpu0.fp_regfile_writes 898 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13195358 # number of misc regfile reads +system.cpu0.misc_regfile_writes 457522 # number of misc regfile writes +system.cpu0.icache.replacements 399011 # number of replacements +system.cpu0.icache.tagsinuse 511.581015 # Cycle average of tags in use +system.cpu0.icache.total_refs 3839482 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 399523 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.610165 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6567370000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.581015 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999182 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999182 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3839482 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3839482 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3839482 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3839482 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3839482 # number of overall hits +system.cpu0.icache.overall_hits::total 3839482 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 430854 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 430854 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 430854 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 430854 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 430854 # number of overall misses +system.cpu0.icache.overall_misses::total 430854 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5887932497 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5887932497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5887932497 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5887932497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5887932497 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5887932497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4270336 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4270336 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4270336 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4270336 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4270336 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4270336 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100895 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100895 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100895 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100895 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100895 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100895 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13665.725506 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13665.725506 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13665.725506 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13665.725506 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13665.725506 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13665.725506 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2816 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 151 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.124183 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.649007 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30736 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30736 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30736 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30736 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30736 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30736 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393118 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 393118 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 393118 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 393118 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 393118 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 393118 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4745929997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4745929997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4745929997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4745929997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4745929997 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4745929997 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7902000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7902000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7902000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7902000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093168 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093168 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093168 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093168 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093168 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093168 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12072.532921 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12072.532921 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12072.532921 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12072.532921 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12072.532921 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12072.532921 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31313 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 31313 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 31313 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 31313 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 31313 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 31313 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 399541 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 399541 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 399541 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 399541 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 399541 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 399541 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4811758497 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4811758497 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4811758497 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4811758497 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4811758497 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4811758497 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7889500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7889500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7889500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7889500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093562 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093562 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093562 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093562 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093562 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093562 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12043.215833 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12043.215833 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12043.215833 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12043.215833 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12043.215833 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12043.215833 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 276649 # number of replacements -system.cpu0.dcache.tagsinuse 460.596566 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9262154 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 277161 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.417956 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 43509000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 460.596566 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.899603 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.899603 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5782081 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5782081 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3160908 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3160908 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139098 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139098 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137052 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137052 # 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number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6408210492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6408210492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6408210492 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6408210492 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514784000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514784000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180269878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180269878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695053878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695053878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030610 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030610 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027485 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027485 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056197 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056197 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051798 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051798 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029252 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029252 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029252 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029252 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12602.443256 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12602.443256 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30872.215216 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30872.215216 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7974.488568 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7974.488568 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4220.715908 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4220.715908 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6411840492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6411840492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6411840492 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6411840492 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13437088000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13437088000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1251489878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1251489878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14688577878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14688577878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030152 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030152 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027193 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027193 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056490 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056490 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053487 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053487 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028867 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028867 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028867 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028867 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12489.639253 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12489.639253 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30992.884012 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30992.884012 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7973.568019 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7973.568019 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4472.458720 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4472.458720 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20060.136147 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20060.136147 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20060.136147 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20060.136147 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20059.003757 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20059.003757 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20059.003757 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20059.003757 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1253,38 +1253,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9057370 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7441884 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 409640 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6090561 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5229548 # Number of BTB hits +system.cpu1.branchPred.lookups 9260108 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7598823 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 418413 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6211409 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5330705 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 85.863158 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 772754 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42888 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.821188 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 799378 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 44339 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42905047 # DTB read hits -system.cpu1.dtb.read_misses 36603 # DTB read misses -system.cpu1.dtb.write_hits 6822006 # DTB write hits -system.cpu1.dtb.write_misses 10721 # DTB write misses +system.cpu1.dtb.read_hits 43181625 # DTB read hits +system.cpu1.dtb.read_misses 38342 # DTB read misses +system.cpu1.dtb.write_hits 6975478 # DTB write hits +system.cpu1.dtb.write_misses 10879 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2003 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2568 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 298 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3080 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 279 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 647 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42941650 # DTB read accesses -system.cpu1.dtb.write_accesses 6832727 # DTB write accesses +system.cpu1.dtb.perms_faults 684 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43219967 # DTB read accesses +system.cpu1.dtb.write_accesses 6986357 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49727053 # DTB hits -system.cpu1.dtb.misses 47324 # DTB misses -system.cpu1.dtb.accesses 49774377 # DTB accesses -system.cpu1.itb.inst_hits 8402267 # ITB inst hits -system.cpu1.itb.inst_misses 5496 # ITB inst misses +system.cpu1.dtb.hits 50157103 # DTB hits +system.cpu1.dtb.misses 49221 # DTB misses +system.cpu1.dtb.accesses 50206324 # DTB accesses +system.cpu1.itb.inst_hits 8542294 # ITB inst hits +system.cpu1.itb.inst_misses 5605 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1293,534 +1293,530 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1533 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1556 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1566 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8407763 # ITB inst accesses -system.cpu1.itb.hits 8402267 # DTB hits -system.cpu1.itb.misses 5496 # DTB misses -system.cpu1.itb.accesses 8407763 # DTB accesses -system.cpu1.numCycles 408754758 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8547899 # ITB inst accesses +system.cpu1.itb.hits 8542294 # DTB hits +system.cpu1.itb.misses 5605 # DTB misses +system.cpu1.itb.accesses 8547899 # DTB accesses +system.cpu1.numCycles 410577330 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19786435 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 66033865 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9057370 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6002302 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14145991 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3963679 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 66957 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77248735 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42710 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 129584 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 102 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8400411 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 741502 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2853 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114126440 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.700482 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.044104 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 20304470 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 67058817 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9260108 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6130083 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14383842 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4002399 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 71431 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77735291 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5936 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42666 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 133916 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 201 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8540383 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 747213 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2975 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 115405308 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.704397 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.049572 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 99987714 87.61% 87.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 797074 0.70% 88.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 939049 0.82% 89.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1891067 1.66% 90.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1525429 1.34% 92.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 571908 0.50% 92.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2134670 1.87% 94.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410312 0.36% 94.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5869217 5.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 101028811 87.54% 87.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 815655 0.71% 88.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 964627 0.84% 89.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1914792 1.66% 90.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1533608 1.33% 92.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 591916 0.51% 92.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2159319 1.87% 94.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 420670 0.36% 94.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5975910 5.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114126440 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022158 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.161549 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21303172 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 76905866 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12788673 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 523903 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2604826 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1105931 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 97877 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 75200071 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 325666 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2604826 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22687981 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 31933680 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40739903 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11832589 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4327461 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 69726432 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18789 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 667798 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3085321 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 1194 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 73678442 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 321083951 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 321025301 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 58650 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49043171 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24635271 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 445050 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 388065 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7869897 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13205633 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8143981 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1031020 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1549372 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 63452075 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1154123 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89105675 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94570 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16177961 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45638243 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 273609 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114126440 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.780763 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.519063 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 115405308 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022554 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.163328 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21846277 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 77383941 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 13006148 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 540398 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2628544 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1139252 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 100555 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 76481536 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 334945 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2628544 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 23246660 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32001614 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 41094778 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 12051133 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4382579 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 70980554 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18812 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 684543 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3106754 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 398 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 74967908 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 326797465 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 326738119 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59346 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50107015 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24860893 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 461639 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 401710 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8025653 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13466262 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8327830 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1061558 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1475331 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 64680036 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1175419 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 90315471 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 95817 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16379719 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 46059622 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 276388 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 115405308 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.782594 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.520017 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83740358 73.38% 73.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8394887 7.36% 80.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4311710 3.78% 84.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3761165 3.30% 87.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10575130 9.27% 97.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1975219 1.73% 98.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1022890 0.90% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 270730 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 74351 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 84537407 73.25% 73.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8582035 7.44% 80.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4411988 3.82% 84.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3834760 3.32% 87.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10634435 9.21% 97.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1994605 1.73% 98.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1053936 0.91% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 278337 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 77805 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114126440 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 115405308 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29540 0.38% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 995 0.01% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7547716 95.90% 96.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 292001 3.71% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32501 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 990 0.01% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7572486 95.74% 96.16% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 303829 3.84% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37588774 42.18% 42.54% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59166 0.07% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.60% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43972144 49.35% 91.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7170135 8.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 38327866 42.44% 42.79% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61115 0.07% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1704 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.85% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 44265466 49.01% 91.87% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7345367 8.13% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89105675 # Type of FU issued -system.cpu1.iq.rate 0.217993 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7870252 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088325 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 300334896 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 80792722 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53591705 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14852 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8010 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6792 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96654176 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7819 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 342901 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 90315471 # Type of FU issued +system.cpu1.iq.rate 0.219972 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7909806 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.087580 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 304076071 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 82244261 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54749584 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14863 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8084 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6852 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 97903555 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7790 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 356637 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3454829 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3906 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17123 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1307403 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3487877 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4207 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17725 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1325961 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31911868 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 888624 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31951985 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 889967 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2604826 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24177502 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 360064 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 64710295 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 111591 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13205633 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8143981 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 865041 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 65040 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3489 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17123 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 203707 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 155314 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 359021 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86656699 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43274731 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2448976 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2628544 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24227901 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 361425 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 65958607 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 113659 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13466262 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8327830 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 878933 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 66066 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3533 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17725 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 207255 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 158224 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 365479 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87865625 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43564360 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2449846 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104097 # number of nop insts executed -system.cpu1.iew.exec_refs 50382465 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6984824 # Number of branches executed -system.cpu1.iew.exec_stores 7107734 # Number of stores executed -system.cpu1.iew.exec_rate 0.212002 # Inst execution rate -system.cpu1.iew.wb_sent 85679792 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53598497 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29912489 # num instructions producing a value -system.cpu1.iew.wb_consumers 53377026 # num instructions consuming a value +system.cpu1.iew.exec_nop 103152 # number of nop insts executed +system.cpu1.iew.exec_refs 50845626 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7156733 # Number of branches executed +system.cpu1.iew.exec_stores 7281266 # Number of stores executed +system.cpu1.iew.exec_rate 0.214005 # Inst execution rate +system.cpu1.iew.wb_sent 86881552 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54756436 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30516075 # num instructions producing a value +system.cpu1.iew.wb_consumers 54547350 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131126 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560400 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.133364 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.559442 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16097351 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880514 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 313181 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111521614 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.431660 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.399918 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16276380 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 899031 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 319402 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 112776764 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.436287 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.405749 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94783688 84.99% 84.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8232715 7.38% 92.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2113496 1.90% 94.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1251152 1.12% 95.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1245297 1.12% 96.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 569963 0.51% 97.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1001738 0.90% 97.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 503665 0.45% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1819900 1.63% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 95648521 84.81% 84.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8417489 7.46% 92.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2180084 1.93% 94.21% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1287029 1.14% 95.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1270394 1.13% 96.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 584036 0.52% 96.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1018862 0.90% 97.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 513430 0.46% 98.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1856919 1.65% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111521614 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38055916 # Number of instructions committed -system.cpu1.commit.committedOps 48139449 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 112776764 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38866915 # Number of instructions committed +system.cpu1.commit.committedOps 49203034 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16587382 # Number of memory references committed -system.cpu1.commit.loads 9750804 # Number of loads committed -system.cpu1.commit.membars 190065 # Number of memory barriers committed -system.cpu1.commit.branches 5966253 # Number of branches committed -system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42675584 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534450 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1819900 # number cycles where commit BW limit reached +system.cpu1.commit.refs 16980254 # Number of memory references committed +system.cpu1.commit.loads 9978385 # Number of loads committed +system.cpu1.commit.membars 195514 # Number of memory barriers committed +system.cpu1.commit.branches 6118836 # Number of branches committed +system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 43616937 # Number of committed integer instructions. +system.cpu1.commit.function_calls 553185 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1856919 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 172894643 # The number of ROB reads -system.cpu1.rob.rob_writes 131171187 # The number of ROB writes -system.cpu1.timesIdled 1407429 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294628318 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1796480472 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37986277 # Number of Instructions Simulated -system.cpu1.committedOps 48069810 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37986277 # Number of Instructions Simulated -system.cpu1.cpi 10.760590 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.760590 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092932 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092932 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 387762774 # number of integer regfile reads -system.cpu1.int_regfile_writes 56160786 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4853 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2312 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18458538 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405362 # number of misc regfile writes -system.cpu1.icache.replacements 596198 # number of replacements -system.cpu1.icache.tagsinuse 480.885955 # Cycle average of tags in use -system.cpu1.icache.total_refs 7759207 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 596710 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.003313 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74225092500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 480.885955 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.939230 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.939230 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7759207 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7759207 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7759207 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7759207 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7759207 # number of overall hits -system.cpu1.icache.overall_hits::total 7759207 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 641153 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 641153 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 641153 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 641153 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 641153 # number of overall misses -system.cpu1.icache.overall_misses::total 641153 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8644043496 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8644043496 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8644043496 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8644043496 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8644043496 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8644043496 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8400360 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8400360 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8400360 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8400360 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8400360 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8400360 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076324 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.076324 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076324 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.076324 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076324 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.076324 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13482.029244 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13482.029244 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13482.029244 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13482.029244 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13482.029244 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13482.029244 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2220 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 167 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.293413 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 175333256 # The number of ROB reads +system.cpu1.rob.rob_writes 133679925 # The number of ROB writes +system.cpu1.timesIdled 1420320 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 295172022 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4794342654 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38797276 # Number of Instructions Simulated +system.cpu1.committedOps 49133395 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38797276 # Number of Instructions Simulated +system.cpu1.cpi 10.582633 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.582633 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.094494 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.094494 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 393458890 # number of integer regfile reads +system.cpu1.int_regfile_writes 57301820 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4905 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2316 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18908919 # number of misc regfile reads +system.cpu1.misc_regfile_writes 419175 # number of misc regfile writes +system.cpu1.icache.replacements 613709 # number of replacements +system.cpu1.icache.tagsinuse 498.827741 # Cycle average of tags in use +system.cpu1.icache.total_refs 7879826 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 614221 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 12.828975 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74226336500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.827741 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974273 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974273 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7879826 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7879826 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7879826 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7879826 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7879826 # number of overall hits +system.cpu1.icache.overall_hits::total 7879826 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 660506 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 660506 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 660506 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 660506 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 660506 # number of overall misses +system.cpu1.icache.overall_misses::total 660506 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8908973494 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8908973494 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8908973494 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8908973494 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8908973494 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8908973494 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8540332 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8540332 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8540332 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8540332 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8540332 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8540332 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.077340 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.077340 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.077340 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.077340 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.077340 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.077340 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13488.103808 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13488.103808 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13488.103808 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13488.103808 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13488.103808 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13488.103808 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2847 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 1026 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 181 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.729282 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 1026 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44405 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44405 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44405 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44405 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44405 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44405 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596748 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 596748 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 596748 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 596748 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 596748 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 596748 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7076621996 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7076621996 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7076621996 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7076621996 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7076621996 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7076621996 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3098500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3098500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3098500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3098500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071038 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071038 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071038 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071038 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071038 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071038 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11858.643843 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11858.643843 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11858.643843 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11858.643843 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11858.643843 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11858.643843 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46258 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 46258 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 46258 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 46258 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 46258 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 46258 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 614248 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 614248 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 614248 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 614248 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 614248 # 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average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11851.698329 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11851.698329 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11851.698329 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 359991 # number of replacements -system.cpu1.dcache.tagsinuse 474.520156 # Cycle average of tags in use -system.cpu1.dcache.total_refs 12670892 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 360323 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 35.165371 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 70354132000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 474.520156 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.926797 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.926797 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8303862 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8303862 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4138320 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4138320 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97526 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97526 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 111496 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105443 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105443 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14397159 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14397159 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14397159 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14397159 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045963 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045963 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273117 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273117 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125296 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125296 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100794 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100794 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135789 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135789 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135789 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135789 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15260.461634 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15260.461634 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39678.225880 # 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Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.949910 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.949910 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8515751 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8515751 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4271525 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4271525 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 100014 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 100014 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97065 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 97065 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12787276 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12787276 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12787276 # number of overall hits +system.cpu1.dcache.overall_hits::total 12787276 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 404538 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 404538 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1563969 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1563969 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14182 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14182 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10922 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10922 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1968507 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1968507 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1968507 # number of overall misses +system.cpu1.dcache.overall_misses::total 1968507 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6180682000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6180682000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61609358019 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 61609358019 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131994000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 131994000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58853500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 58853500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 67790040019 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 67790040019 # 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number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14755783 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14755783 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14755783 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045350 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045350 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268010 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.268010 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124190 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124190 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101142 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101142 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.133406 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.133406 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133406 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.133406 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15278.371871 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15278.371871 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39392.953453 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39392.953453 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9307.149908 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9307.149908 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5388.527742 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5388.527742 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34437.286745 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34437.286745 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34437.286745 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34437.286745 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 29332 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 12945 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3336 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 164 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.792566 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 78.932927 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324138 # number of writebacks -system.cpu1.dcache.writebacks::total 324138 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172104 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 172104 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1393517 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1393517 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1456 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1456 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1565621 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1565621 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1565621 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1565621 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227953 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 227953 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161403 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161403 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12514 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12514 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10624 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10624 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389356 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389356 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389356 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389356 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2849477500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2849477500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5127514196 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5127514196 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88527000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88527000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32740500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32740500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7976991696 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7976991696 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7976991696 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7976991696 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989374500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989374500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35732843580 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35732843580 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204722218080 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204722218080 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026190 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026190 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028350 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028350 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112237 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112237 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100756 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100756 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027044 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027044 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027044 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027044 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12500.285146 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12500.285146 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31768.394615 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31768.394615 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7074.236855 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7074.236855 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3081.748870 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3081.748870 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20487.655760 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20487.655760 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20487.655760 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20487.655760 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 327755 # number of writebacks +system.cpu1.dcache.writebacks::total 327755 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 173193 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 173193 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1400907 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1400907 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1451 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1451 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1574100 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1574100 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1574100 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1574100 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231345 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231345 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163062 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 163062 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12731 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12731 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10917 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10917 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394407 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394407 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394407 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394407 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2902469000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2902469000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5146576709 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5146576709 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90486500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90486500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 37019500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 37019500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8049045709 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8049045709 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8049045709 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8049045709 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169298073000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169298073000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35738645182 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35738645182 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 205036718182 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 205036718182 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025935 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025935 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027943 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027943 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111484 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111484 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101096 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101096 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026729 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026729 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026729 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026729 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12546.063239 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12546.063239 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31562.085029 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31562.085029 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7107.572068 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7107.572068 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3390.995695 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3390.995695 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20407.968695 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20407.968695 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20407.968695 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20407.968695 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1842,18 +1838,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540238105555 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 540238105555 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540238105555 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 540238105555 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1245278858614 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1245278858614 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1245278858614 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1245278858614 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41724 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 42369 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48854 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 50346 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |