diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | 6151 |
1 files changed, 3078 insertions, 3073 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index ab0dc0047..a281a2cd6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,161 +1,161 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.826111 # Number of seconds simulated -sim_ticks 2826111083000 # Number of ticks simulated -final_tick 2826111083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.826595 # Number of seconds simulated +sim_ticks 2826594924500 # Number of ticks simulated +final_tick 2826594924500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93135 # Simulator instruction rate (inst/s) -host_op_rate 112984 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2190118612 # Simulator tick rate (ticks/s) -host_mem_usage 627176 # Number of bytes of host memory used -host_seconds 1290.39 # Real time elapsed on the host -sim_insts 120180681 # Number of instructions simulated -sim_ops 145794019 # Number of ops (including micro ops) simulated +host_inst_rate 79087 # Simulator instruction rate (inst/s) +host_op_rate 95944 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1861516367 # Simulator tick rate (ticks/s) +host_mem_usage 623016 # Number of bytes of host memory used +host_seconds 1518.44 # Real time elapsed on the host +sim_insts 120088860 # Number of instructions simulated +sim_ops 145685275 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 1920 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1301824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1315176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8404800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1324752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1304168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8428096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 186528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 599252 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 416192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 175008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 586900 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 427200 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12227420 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1301824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 186528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1488352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8794944 # Number of bytes written to this memory +system.physmem.bytes_read::total 12249452 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1324752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 175008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1499760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8803008 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8812508 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 30 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8820572 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 22588 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21070 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 131325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 22950 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 131689 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2982 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9384 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6503 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2802 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9191 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6675 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193909 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 137421 # Number of write requests responded to by this memory +system.physmem.num_reads::total 194257 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 137547 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141812 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 679 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 141938 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 657 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 460641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 465366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2973981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 468674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 461392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2981713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 91 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 66002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 212041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 147267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 61915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 207635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 151136 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4326589 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 460641 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 66002 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 526643 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3112031 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6201 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4333643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 468674 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 61915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 530589 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3114351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6200 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3118245 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3112031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3120565 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3114351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 657 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 460641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 471567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2973981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 468674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 467592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2981713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 66002 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 212055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 147267 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 61915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 207649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 151136 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7444834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 193910 # Number of read requests accepted -system.physmem.writeReqs 141812 # Number of write requests accepted -system.physmem.readBursts 193910 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 141812 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12399936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10304 # Total number of bytes read from write queue -system.physmem.bytesWritten 8824960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12227484 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8812508 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::total 7454207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 194258 # Number of read requests accepted +system.physmem.writeReqs 141938 # Number of write requests accepted +system.physmem.readBursts 194258 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 141938 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12422976 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue +system.physmem.bytesWritten 8833536 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12249516 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8820572 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12140 # Per bank write bursts -system.physmem.perBankRdBursts::1 12135 # Per bank write bursts -system.physmem.perBankRdBursts::2 12398 # Per bank write bursts -system.physmem.perBankRdBursts::3 12886 # Per bank write bursts -system.physmem.perBankRdBursts::4 14558 # Per bank write bursts -system.physmem.perBankRdBursts::5 12353 # Per bank write bursts -system.physmem.perBankRdBursts::6 12494 # Per bank write bursts -system.physmem.perBankRdBursts::7 12590 # Per bank write bursts -system.physmem.perBankRdBursts::8 12207 # Per bank write bursts -system.physmem.perBankRdBursts::9 12490 # Per bank write bursts -system.physmem.perBankRdBursts::10 11644 # Per bank write bursts -system.physmem.perBankRdBursts::11 10772 # Per bank write bursts -system.physmem.perBankRdBursts::12 11273 # Per bank write bursts -system.physmem.perBankRdBursts::13 11534 # Per bank write bursts -system.physmem.perBankRdBursts::14 11359 # Per bank write bursts -system.physmem.perBankRdBursts::15 10916 # Per bank write bursts -system.physmem.perBankWrBursts::0 8885 # Per bank write bursts -system.physmem.perBankWrBursts::1 8987 # Per bank write bursts -system.physmem.perBankWrBursts::2 9257 # Per bank write bursts -system.physmem.perBankWrBursts::3 9509 # Per bank write bursts -system.physmem.perBankWrBursts::4 8433 # Per bank write bursts -system.physmem.perBankWrBursts::5 8902 # Per bank write bursts -system.physmem.perBankWrBursts::6 9078 # Per bank write bursts -system.physmem.perBankWrBursts::7 8908 # Per bank write bursts -system.physmem.perBankWrBursts::8 8674 # Per bank write bursts -system.physmem.perBankWrBursts::9 9007 # Per bank write bursts -system.physmem.perBankWrBursts::10 8474 # Per bank write bursts -system.physmem.perBankWrBursts::11 8031 # Per bank write bursts -system.physmem.perBankWrBursts::12 8318 # Per bank write bursts -system.physmem.perBankWrBursts::13 8000 # Per bank write bursts -system.physmem.perBankWrBursts::14 7983 # Per bank write bursts -system.physmem.perBankWrBursts::15 7444 # Per bank write bursts +system.physmem.perBankRdBursts::0 12130 # Per bank write bursts +system.physmem.perBankRdBursts::1 12140 # Per bank write bursts +system.physmem.perBankRdBursts::2 12480 # Per bank write bursts +system.physmem.perBankRdBursts::3 12151 # Per bank write bursts +system.physmem.perBankRdBursts::4 14882 # Per bank write bursts +system.physmem.perBankRdBursts::5 12677 # Per bank write bursts +system.physmem.perBankRdBursts::6 12709 # Per bank write bursts +system.physmem.perBankRdBursts::7 12606 # Per bank write bursts +system.physmem.perBankRdBursts::8 11844 # Per bank write bursts +system.physmem.perBankRdBursts::9 11522 # Per bank write bursts +system.physmem.perBankRdBursts::10 11334 # Per bank write bursts +system.physmem.perBankRdBursts::11 10175 # Per bank write bursts +system.physmem.perBankRdBursts::12 11497 # Per bank write bursts +system.physmem.perBankRdBursts::13 12486 # Per bank write bursts +system.physmem.perBankRdBursts::14 11961 # Per bank write bursts +system.physmem.perBankRdBursts::15 11515 # Per bank write bursts +system.physmem.perBankWrBursts::0 8842 # Per bank write bursts +system.physmem.perBankWrBursts::1 8923 # Per bank write bursts +system.physmem.perBankWrBursts::2 9151 # Per bank write bursts +system.physmem.perBankWrBursts::3 8834 # Per bank write bursts +system.physmem.perBankWrBursts::4 8743 # Per bank write bursts +system.physmem.perBankWrBursts::5 9257 # Per bank write bursts +system.physmem.perBankWrBursts::6 9174 # Per bank write bursts +system.physmem.perBankWrBursts::7 9022 # Per bank write bursts +system.physmem.perBankWrBursts::8 8380 # Per bank write bursts +system.physmem.perBankWrBursts::9 8199 # Per bank write bursts +system.physmem.perBankWrBursts::10 8228 # Per bank write bursts +system.physmem.perBankWrBursts::11 7543 # Per bank write bursts +system.physmem.perBankWrBursts::12 8493 # Per bank write bursts +system.physmem.perBankWrBursts::13 8795 # Per bank write bursts +system.physmem.perBankWrBursts::14 8486 # Per bank write bursts +system.physmem.perBankWrBursts::15 7954 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 2826110796000 # Total gap between requests +system.physmem.numWrRetry 65 # Number of times write queue was full causing retry +system.physmem.totGap 2826594637500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) -system.physmem.readPktSize::4 3086 # Read request sizes (log2) +system.physmem.readPktSize::4 3091 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 190245 # Read request sizes (log2) +system.physmem.readPktSize::6 190588 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 137421 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 59620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12745 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8439 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6358 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 930 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 679 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 262 # What read queue length does an incoming req see +system.physmem.writePktSize::6 137547 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 58416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12705 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6655 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4753 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 747 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 270 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see @@ -189,162 +189,179 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 84734 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 250.487785 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 142.325533 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 306.970890 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 42837 50.55% 50.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17738 20.93% 71.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6168 7.28% 78.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3519 4.15% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2713 3.20% 86.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1549 1.83% 87.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 945 1.12% 89.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1056 1.25% 90.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8209 9.69% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 84734 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6846 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.300175 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 562.386287 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6844 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8191 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 156 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 84597 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 251.267917 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 142.709069 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.432600 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 42654 50.42% 50.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17739 20.97% 71.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6092 7.20% 78.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3470 4.10% 82.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2903 3.43% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1534 1.81% 87.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 962 1.14% 89.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 998 1.18% 90.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8245 9.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 84597 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6823 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.448923 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 563.375084 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6821 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6846 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6846 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.141689 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.636499 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.164291 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5708 83.38% 83.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 378 5.52% 88.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 91 1.33% 90.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 47 0.69% 90.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 276 4.03% 94.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 33 0.48% 95.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 21 0.31% 95.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 23 0.34% 96.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 19 0.28% 96.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 10 0.15% 96.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.03% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.13% 96.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 166 2.42% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 9 0.13% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 11 0.16% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.09% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.04% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.03% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.04% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 3 0.04% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.10% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6846 # Writes before turning the bus around for reads -system.physmem.totQLat 6600075879 # Total ticks spent queuing -system.physmem.totMemAccLat 10232869629 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 968745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34065.08 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52815.08 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.39 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s +system.physmem.rdPerTurnAround::total 6823 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6823 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.229225 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.516304 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.191757 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5762 84.45% 84.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 386 5.66% 90.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 77 1.13% 91.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 44 0.64% 91.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 244 3.58% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 18 0.26% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 14 0.21% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.18% 96.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.25% 96.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.03% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.07% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.12% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 140 2.05% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.07% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 10 0.15% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 12 0.18% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.04% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.06% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.04% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 8 0.12% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.03% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.19% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.06% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.06% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6823 # Writes before turning the bus around for reads +system.physmem.totQLat 10063104165 # Total ticks spent queuing +system.physmem.totMemAccLat 13702647915 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 970545000 # Total ticks spent in databus transfers +system.physmem.avgQLat 51842.28 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 70592.18 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.13 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.33 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.81 # Average write queue length when enqueuing -system.physmem.readRowHits 161373 # Number of row buffer hits during reads -system.physmem.writeRowHits 85531 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.02 # Row buffer hit rate for writes -system.physmem.avgGap 8418008.94 # Average gap between requests -system.physmem.pageHitRate 74.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 338612400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 184758750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 792121200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 466294320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184587446160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 79311033765 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1626092117250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1891772383845 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.392029 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2705053539598 # Time in different power states -system.physmem_0.memoryStateTime::REF 94369860000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 26681946652 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 301976640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 164769000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 719113200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 427232880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184587446160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 78534447525 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626773333250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1891508318655 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.298592 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2706191706230 # Time in different power states -system.physmem_1.memoryStateTime::REF 94369860000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 25549496770 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.32 # Average write queue length when enqueuing +system.physmem.readRowHits 161915 # Number of row buffer hits during reads +system.physmem.writeRowHits 85621 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.41 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.03 # Row buffer hit rate for writes +system.physmem.avgGap 8407579.62 # Average gap between requests +system.physmem.pageHitRate 74.52 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 318172680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 169112790 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 726673500 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 375558120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4535428560.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4774700760 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 244257600 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 9148762200 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6477825120 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 667571113185 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 694343780025 # Total energy per rank (pJ) +system.physmem_0.averagePower 245.646723 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2815396783365 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 428149701 # Time in different power states +system.physmem_0.memoryStateTime::REF 1926538000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2778550744250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 16869300047 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8757031934 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 20063160568 # Time in different power states +system.physmem_1.actEnergy 285849900 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 151932825 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 659264760 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 344927160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4569848400.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4671042840 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 250741920 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 8727797820 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 6816319680 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 667684488600 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 694164121065 # Total energy per rank (pJ) +system.physmem_1.averagePower 245.583162 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2815694283339 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 440101951 # Time in different power states +system.physmem_1.memoryStateTime::REF 1941710000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2778803468000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 17750764755 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8518829210 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 19140050584 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory @@ -363,30 +380,30 @@ system.realview.nvmem.bw_inst_read::total 102 # I system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 23913557 # Number of BP lookups -system.cpu0.branchPred.condPredicted 15655751 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 926443 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 14584665 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 9536401 # Number of BTB hits +system.cpu0.branchPred.lookups 53161527 # Number of BP lookups +system.cpu0.branchPred.condPredicted 24432585 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 935077 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 32150468 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 13984916 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.386493 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3854213 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 33180 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 1360238 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 1204672 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 155566 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 48773 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 43.498328 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15489494 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 33173 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 10133739 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 9977658 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 156081 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 49006 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -416,84 +433,83 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 65918 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 65918 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25327 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18922 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 21669 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 44249 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 506.926710 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 3129.335275 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 43005 97.19% 97.19% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 929 2.10% 99.29% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 148 0.33% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 108 0.24% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 23 0.05% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 20 0.05% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 13 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 66483 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 66483 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25519 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 19054 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 21910 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 44573 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 499.046508 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 3114.296115 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 43354 97.27% 97.27% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 917 2.06% 99.32% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 125 0.28% 99.60% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 116 0.26% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 24 0.05% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.05% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 14 0.03% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 44249 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 16055 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 11307.848022 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9898.999015 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6813.334576 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 14595 90.91% 90.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1294 8.06% 98.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 134 0.83% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 9 0.06% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 17 0.11% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::114688-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 16055 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 85920956152 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.541941 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.508329 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 85862493152 99.93% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 40323000 0.05% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 8212500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 5190500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 2626000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 844500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 886000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 336500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 44000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 85920956152 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5102 78.63% 78.63% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1387 21.37% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6489 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65918 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 44573 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 16394 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 11498.017567 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9809.718618 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 10152.442305 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 14883 90.78% 90.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1339 8.17% 98.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 129 0.79% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 18 0.11% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.01% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::114688-131071 6 0.04% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::245760-262143 16 0.10% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 16394 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 86404933652 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.566419 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.506005 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 86345641152 99.93% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 41095500 0.05% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 8202000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 4970000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 2695000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 946000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 940000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 429500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 14500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 86404933652 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5203 78.33% 78.33% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1439 21.67% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6642 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66483 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65918 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6489 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66483 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6642 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6489 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 72407 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6642 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 73125 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17729387 # DTB read hits -system.cpu0.dtb.read_misses 55806 # DTB read misses -system.cpu0.dtb.write_hits 14606301 # DTB write hits -system.cpu0.dtb.write_misses 10112 # DTB write misses +system.cpu0.dtb.read_hits 23680324 # DTB read hits +system.cpu0.dtb.read_misses 56461 # DTB read misses +system.cpu0.dtb.write_hits 17598903 # DTB write hits +system.cpu0.dtb.write_misses 10022 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3431 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 353 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2188 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3449 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 156 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2246 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 939 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17785193 # DTB read accesses -system.cpu0.dtb.write_accesses 14616413 # DTB write accesses +system.cpu0.dtb.perms_faults 902 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 23736785 # DTB read accesses +system.cpu0.dtb.write_accesses 17608925 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 32335688 # DTB hits -system.cpu0.dtb.misses 65918 # DTB misses -system.cpu0.dtb.accesses 32401606 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 41279227 # DTB hits +system.cpu0.dtb.misses 66483 # DTB misses +system.cpu0.dtb.accesses 41345710 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -523,58 +539,58 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 10845 # Table walker walks requested -system.cpu0.itb.walker.walksShort 10845 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3752 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6021 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 1072 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 9773 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 438.606364 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 2276.348067 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 9409 96.28% 96.28% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 161 1.65% 97.92% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 121 1.24% 99.16% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 47 0.48% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 7 0.07% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 16 0.16% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 6 0.06% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-36863 4 0.04% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::36864-40959 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 9773 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 3657 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12272.627837 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11484.483595 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 4878.254960 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 514 14.06% 14.06% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 2884 78.86% 92.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 170 4.65% 97.57% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 55 1.50% 99.07% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 31 0.85% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 3657 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 21495635712 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.820169 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.384194 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 3866725500 17.99% 17.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 17627832712 82.01% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 1008500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 69000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 21495635712 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2254 87.20% 87.20% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 331 12.80% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2585 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 11041 # Table walker walks requested +system.cpu0.itb.walker.walksShort 11041 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4028 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5930 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 1083 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 9958 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 410.574413 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 2129.037976 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 9588 96.28% 96.28% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 186 1.87% 98.15% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 118 1.18% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 38 0.38% 99.72% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 5 0.05% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 15 0.15% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 9958 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 3663 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12262.353262 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11250.035596 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5522.553888 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 663 18.10% 18.10% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 2695 73.57% 91.67% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 173 4.72% 96.40% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 79 2.16% 98.55% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 49 1.34% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.08% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 3663 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 21980185712 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.834654 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.371618 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 3635314000 16.54% 16.54% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 18343952712 83.46% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 868500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 50500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 21980185712 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2243 86.94% 86.94% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 337 13.06% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2580 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10845 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10845 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11041 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11041 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2585 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2585 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 13430 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 37503849 # ITB inst hits -system.cpu0.itb.inst_misses 10845 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2580 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2580 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 13621 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 72829698 # ITB inst hits +system.cpu0.itb.inst_misses 11041 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -583,1055 +599,1039 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2291 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2280 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1944 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1929 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 37514694 # ITB inst accesses -system.cpu0.itb.hits 37503849 # DTB hits -system.cpu0.itb.misses 10845 # DTB misses -system.cpu0.itb.accesses 37514694 # DTB accesses -system.cpu0.numPwrStateTransitions 3712 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1856 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1487215700.959052 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23895599673.728432 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1080 58.19% 58.19% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 769 41.43% 99.62% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 72840739 # ITB inst accesses +system.cpu0.itb.hits 72829698 # DTB hits +system.cpu0.itb.misses 11041 # DTB misses +system.cpu0.itb.accesses 72840739 # DTB accesses +system.cpu0.numPwrStateTransitions 3740 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1870 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1456796210.372727 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23672658216.113400 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1093 58.45% 58.45% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 772 41.28% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499971395296 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1856 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 65838742020 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2760272340980 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 131678547 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499970757520 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1870 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 102386011103 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724208913397 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 204773026 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 19262499 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 112028029 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 23913557 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 14595286 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 106047706 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2739238 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 149116 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 57008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 423158 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 407524 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 94244 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 37503537 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 259263 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 5228 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 127810874 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.056272 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.258048 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 20714269 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 196101622 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 53161527 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 39452068 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 175603283 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 5698298 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 148281 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 57647 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 420719 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 418648 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 100050 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 72829386 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 258768 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 5384 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 200312046 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.196487 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.307164 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 65678610 51.39% 51.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 21331326 16.69% 68.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 8731054 6.83% 74.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 32069884 25.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 95293979 47.57% 47.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 30393228 15.17% 62.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 14596992 7.29% 70.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 60027847 29.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 127810874 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.181606 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.850769 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 19867897 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 60850603 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 41086114 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4967748 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1038512 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3035925 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 335186 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 110135169 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3776324 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1038512 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 25520251 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12577304 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 37369361 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 40264186 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 11041260 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 105172145 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1006076 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1476626 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 165177 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 58768 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 6832387 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 109365921 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 480109573 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 120259513 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9447 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 98266494 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 11099416 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1228555 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1085594 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12372656 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 18663457 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 16076197 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1697816 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2228906 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 102290291 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1693186 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 100457201 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 451571 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9045594 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 21384310 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 120136 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 127810874 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.785983 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.028831 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 200312046 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.259612 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.957654 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 25714917 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 108196913 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 58914772 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4966892 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2518552 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 3065050 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 334861 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 154468947 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3822056 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 2518552 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 34338225 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12857218 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 83619486 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 55122113 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 11856452 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 137773765 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1037168 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1494015 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 163408 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 59807 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 7647937 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 141868428 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 635547314 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 152852010 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9442 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 130675877 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 11192540 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 2699923 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 2556575 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 22590232 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 24607184 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 19088589 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1696558 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2229617 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 134839557 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1714900 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 132985122 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 452743 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10598058 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 21682682 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 119247 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 200312046 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.663890 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.961819 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 71664386 56.07% 56.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 23315575 18.24% 74.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 22454220 17.57% 91.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 9273638 7.26% 99.14% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1103003 0.86% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 52 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 123495652 61.65% 61.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 33655276 16.80% 78.45% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 31282184 15.62% 94.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 10750314 5.37% 99.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1128564 0.56% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 56 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 127810874 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 200312046 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 9324082 40.55% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 74 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5582954 24.28% 64.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8086742 35.17% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 10816144 43.95% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 73 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5628152 22.87% 66.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8167261 33.18% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 66279940 65.98% 65.98% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 93468 0.09% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 8018 0.01% 66.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.08% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 18419781 18.34% 84.42% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 15653721 15.58% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 89847428 67.56% 67.56% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 110447 0.08% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 1 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 7864 0.01% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.65% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 24369410 18.32% 85.98% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 18647698 14.02% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 100457201 # Type of FU issued -system.cpu0.iq.rate 0.762897 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 22993852 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.228892 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 352138149 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 113036952 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 98428366 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 32549 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11294 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 9716 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 123427553 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 21227 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 365954 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 132985122 # Type of FU issued +system.cpu0.iq.rate 0.649427 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 24611630 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.185071 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 491314323 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 147160457 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 129454820 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 32339 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11262 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 9717 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 157573424 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 21055 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 367821 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1901526 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2478 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 19250 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 882682 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1916447 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2461 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 19267 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 901714 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 110051 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 360569 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 120909 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 362204 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1038512 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1592668 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 210705 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 104136429 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2518552 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1651189 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 246744 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 136707359 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 18663457 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 16076197 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 876152 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 28505 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 158159 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 19250 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 253073 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 398879 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 651952 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 99436169 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 17977378 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 955231 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 24607184 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 19088589 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 876464 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 27795 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 194810 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 19267 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 261439 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 400306 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 661745 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 131953488 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 23926851 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 965273 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 152952 # number of nop insts executed -system.cpu0.iew.exec_refs 33471315 # number of memory reference insts executed -system.cpu0.iew.exec_branches 16838084 # Number of branches executed -system.cpu0.iew.exec_stores 15493937 # Number of stores executed -system.cpu0.iew.exec_rate 0.755143 # Inst execution rate -system.cpu0.iew.wb_sent 98890175 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 98438082 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 51269761 # num instructions producing a value -system.cpu0.iew.wb_consumers 84681895 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.747564 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.605439 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 8044326 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1573050 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 595336 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 126126769 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.753686 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.472161 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 152902 # number of nop insts executed +system.cpu0.iew.exec_refs 42414312 # number of memory reference insts executed +system.cpu0.iew.exec_branches 25613561 # Number of branches executed +system.cpu0.iew.exec_stores 18487461 # Number of stores executed +system.cpu0.iew.exec_rate 0.644389 # Inst execution rate +system.cpu0.iew.wb_sent 131398393 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 129464537 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 66052971 # num instructions producing a value +system.cpu0.iew.wb_consumers 106772912 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.632234 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.618630 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 9569777 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1595653 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 604480 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 197147849 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.639512 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.336739 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 81783872 64.84% 64.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 24707932 19.59% 84.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 8259395 6.55% 90.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3211630 2.55% 93.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 3438301 2.73% 96.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 1493917 1.18% 97.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1163537 0.92% 98.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 551177 0.44% 98.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1517008 1.20% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 136598241 69.29% 69.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 33559109 17.02% 86.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 12649949 6.42% 92.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3238672 1.64% 94.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 4912875 2.49% 96.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 2898818 1.47% 98.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1203082 0.61% 98.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 557487 0.28% 99.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1529616 0.78% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 126126769 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 79016795 # Number of instructions committed -system.cpu0.commit.committedOps 95059926 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 197147849 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 104125280 # Number of instructions committed +system.cpu0.commit.committedOps 126078442 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 31955445 # Number of memory references committed -system.cpu0.commit.loads 16761930 # Number of loads committed -system.cpu0.commit.membars 647782 # Number of memory barriers committed -system.cpu0.commit.branches 16235143 # Number of branches committed +system.cpu0.commit.refs 40877611 # Number of memory references committed +system.cpu0.commit.loads 22690736 # Number of loads committed +system.cpu0.commit.membars 648887 # Number of memory barriers committed +system.cpu0.commit.branches 25008531 # Number of branches committed system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 81982870 # Number of committed integer instructions. -system.cpu0.commit.function_calls 1931434 # Number of function calls committed. +system.cpu0.commit.int_insts 110051272 # Number of committed integer instructions. +system.cpu0.commit.function_calls 4840996 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 63005341 66.28% 66.28% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 91123 0.10% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 8017 0.01% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 16761930 17.63% 84.02% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 15193515 15.98% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 85084925 67.49% 67.49% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 108043 0.09% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 7863 0.01% 67.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.58% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 22690736 18.00% 85.57% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 18186875 14.43% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 95059926 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1517008 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 223519030 # The number of ROB reads -system.cpu0.rob.rob_writes 207883288 # The number of ROB writes -system.cpu0.timesIdled 136700 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3867673 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5520543918 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 78894743 # Number of Instructions Simulated -system.cpu0.committedOps 94937874 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.669041 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.669041 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.599147 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.599147 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 110427579 # number of integer regfile reads -system.cpu0.int_regfile_writes 59611828 # number of integer regfile writes -system.cpu0.fp_regfile_reads 8185 # number of floating regfile reads +system.cpu0.commit.op_class_0::total 126078442 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1529616 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 307952651 # The number of ROB reads +system.cpu0.rob.rob_writes 274451297 # The number of ROB writes +system.cpu0.timesIdled 137106 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 4460980 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5448417066 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 104003228 # Number of Instructions Simulated +system.cpu0.committedOps 125956390 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.968910 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.968910 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.507895 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.507895 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 142940096 # number of integer regfile reads +system.cpu0.int_regfile_writes 81795281 # number of integer regfile writes +system.cpu0.fp_regfile_reads 8203 # number of floating regfile reads system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes -system.cpu0.cc_regfile_reads 350340790 # number of cc regfile reads -system.cpu0.cc_regfile_writes 41062621 # number of cc regfile writes -system.cpu0.misc_regfile_reads 252371624 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1225237 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 711089 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.347987 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 28802334 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 711601 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 40.475398 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 278078500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.347987 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965523 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.965523 # Average percentage of cache occupancy +system.cpu0.cc_regfile_reads 465685863 # number of cc regfile reads +system.cpu0.cc_regfile_writes 49834738 # number of cc regfile writes +system.cpu0.misc_regfile_reads 394201906 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1226279 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 711042 # number of replacements +system.cpu0.dcache.tags.tagsinuse 497.782039 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 37710898 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 711554 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.997943 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 296154500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.782039 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.972231 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.972231 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63463455 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63463455 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 15558905 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15558905 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 12019658 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 12019658 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 308619 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 308619 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363044 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 363044 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361281 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361281 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 27578563 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 27578563 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 27887182 # number of overall hits -system.cpu0.dcache.overall_hits::total 27887182 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 648058 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 648058 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1895809 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1895809 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147818 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 147818 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25317 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 25317 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20174 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20174 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2543867 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2543867 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2691685 # number of overall misses -system.cpu0.dcache.overall_misses::total 2691685 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8928091500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 8928091500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29690163364 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 29690163364 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 404195500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 404195500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 475433000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 475433000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 570500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 570500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 38618254864 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 38618254864 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 38618254864 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 38618254864 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16206963 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16206963 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 13915467 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 13915467 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456437 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 456437 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388361 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 388361 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381455 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381455 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30122430 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30122430 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30578867 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30578867 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039986 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.039986 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136238 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.136238 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323852 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323852 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065189 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065189 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052887 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052887 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084451 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.084451 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088024 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.088024 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13776.685883 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13776.685883 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15660.946522 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15660.946522 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15965.378994 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15965.378994 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23566.620402 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23566.620402 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 81278285 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 81278285 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 21483760 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 21483760 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15003255 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15003255 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307803 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 307803 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363087 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 363087 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361616 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361616 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 36487015 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 36487015 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 36794818 # number of overall hits +system.cpu0.dcache.overall_hits::total 36794818 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 647587 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 647587 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1894796 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1894796 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148778 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 148778 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25560 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 25560 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20165 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20165 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2542383 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2542383 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2691161 # number of overall misses +system.cpu0.dcache.overall_misses::total 2691161 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9361035000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 9361035000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33017805879 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 33017805879 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 412521000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 412521000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 476921000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 476921000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 443000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 443000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 42378840879 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 42378840879 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 42378840879 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 42378840879 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 22131347 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 22131347 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 16898051 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 16898051 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456581 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 456581 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388647 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 388647 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381781 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381781 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 39029398 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 39029398 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 39485979 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 39485979 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029261 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.029261 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.112131 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.112131 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325852 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325852 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065767 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065767 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052818 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052818 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065140 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.065140 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068155 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.068155 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14455.254661 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14455.254661 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17425.520150 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17425.520150 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16139.319249 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16139.319249 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23650.929829 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23650.929829 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15180.925286 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15180.925286 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14347.241547 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14347.241547 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1034 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 4271446 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 202383 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.541667 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 21.105755 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 711089 # number of writebacks -system.cpu0.dcache.writebacks::total 711089 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260039 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 260039 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1570278 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1570278 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18696 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18696 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1830317 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1830317 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1830317 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1830317 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 388019 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 388019 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325531 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 325531 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101607 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 101607 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6621 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6621 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20174 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20174 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 713550 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 713550 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 815157 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 815157 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20336 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20336 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19032 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19032 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39368 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39368 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4833813000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4833813000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5968230399 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5968230399 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1672759500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1672759500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104692000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104692000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 455274000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 455274000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 555500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 555500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10802043399 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10802043399 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12474802899 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12474802899 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4534406000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4534406000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4534406000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4534406000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023941 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023941 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023393 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023393 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222609 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222609 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017049 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017049 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052887 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052887 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023688 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023688 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026658 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026658 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12457.670887 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12457.670887 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18333.831184 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18333.831184 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16463.034043 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16463.034043 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15812.112974 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15812.112974 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22567.363934 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22567.363934 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16668.944403 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16668.944403 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15747.419377 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15747.419377 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 660 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4996394 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 33 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 202489 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 20 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 24.674891 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 711042 # number of writebacks +system.cpu0.dcache.writebacks::total 711042 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260652 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 260652 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1569869 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1569869 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18798 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18798 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1830521 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1830521 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1830521 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1830521 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 386935 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 386935 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324927 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 324927 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102518 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 102518 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6762 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6762 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20165 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20165 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 711862 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 711862 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 814380 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 814380 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31782 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31782 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28457 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28457 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60239 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60239 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5003581000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5003581000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6626488404 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6626488404 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1706140000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1706140000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 107183000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 107183000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 456767000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 456767000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 432000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 432000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11630069404 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11630069404 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13336209404 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13336209404 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6624172500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6624172500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6624172500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6624172500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017484 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017484 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019229 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019229 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224534 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224534 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017399 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017399 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052818 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052818 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018239 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.018239 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020625 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.020625 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12931.321798 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12931.321798 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20393.775845 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20393.775845 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16642.345734 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16642.345734 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15850.783792 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15850.783792 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22651.475329 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22651.475329 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15138.453366 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15138.453366 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15303.558577 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15303.558577 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222974.331235 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222974.331235 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115179.993904 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115179.993904 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1254577 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.762789 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36189840 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1255088 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 28.834504 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6511134000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762789 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999537 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999537 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16337.533685 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16337.533685 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16375.904865 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16375.904865 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208425.287899 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208425.287899 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109964.848354 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109964.848354 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1252192 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.757674 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 71518552 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1252703 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 57.091387 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6585004000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.757674 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999527 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999527 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 130 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 76255085 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 76255085 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 36189843 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36189843 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36189843 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36189843 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36189843 # number of overall hits -system.cpu0.icache.overall_hits::total 36189843 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1310126 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1310126 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1310126 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1310126 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1310126 # number of overall misses -system.cpu0.icache.overall_misses::total 1310126 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13674177457 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13674177457 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13674177457 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13674177457 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13674177457 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13674177457 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 37499969 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 37499969 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 37499969 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 37499969 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 37499969 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 37499969 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034937 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.034937 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034937 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.034937 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034937 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.034937 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10437.299509 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10437.299509 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10437.299509 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10437.299509 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10437.299509 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10437.299509 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1615389 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 855 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 113956 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.175550 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 85.500000 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1254577 # number of writebacks -system.cpu0.icache.writebacks::total 1254577 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54978 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 54978 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 54978 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 54978 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 54978 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 54978 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1255148 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1255148 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1255148 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1255148 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1255148 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1255148 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12423139434 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12423139434 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12423139434 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12423139434 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12423139434 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12423139434 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 269145498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 269145498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 269145498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 269145498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033471 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033471 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033471 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.033471 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033471 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.033471 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9897.748659 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9897.748659 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9897.748659 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9897.748659 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9897.748659 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9897.748659 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1846782 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1849282 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 2270 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.tags.tag_accesses 146904258 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 146904258 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 71518555 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 71518555 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 71518555 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 71518555 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 71518555 # number of overall hits +system.cpu0.icache.overall_hits::total 71518555 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1307201 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1307201 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1307201 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1307201 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1307201 # number of overall misses +system.cpu0.icache.overall_misses::total 1307201 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14223203310 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14223203310 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14223203310 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14223203310 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14223203310 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14223203310 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 72825756 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 72825756 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 72825756 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 72825756 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 72825756 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 72825756 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017950 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.017950 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017950 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.017950 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017950 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.017950 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10880.655163 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10880.655163 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10880.655163 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10880.655163 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10880.655163 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10880.655163 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1774060 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1996 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 116060 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.285714 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 153.538462 # average number of cycles each access was blocked +system.cpu0.icache.writebacks::writebacks 1252192 # number of writebacks +system.cpu0.icache.writebacks::total 1252192 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54454 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 54454 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 54454 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 54454 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 54454 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 54454 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1252747 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1252747 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1252747 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1252747 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1252747 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1252747 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 3008 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 3008 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12840860811 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12840860811 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12840860811 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12840860811 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12840860811 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12840860811 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 287646998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 287646998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 287646998 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 287646998 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017202 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017202 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017202 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.017202 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017202 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.017202 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10250.162891 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10250.162891 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10250.162891 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10250.162891 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10250.162891 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10250.162891 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95627.326463 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95627.326463 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1846192 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1848788 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 2354 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 236718 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 273792 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15633.615902 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1886952 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 289401 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.520199 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 238916 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 272116 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15645.226913 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1883031 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 287760 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.543755 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14449.190897 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.342760 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.746834 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1171.335411 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.881909 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000753 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000046 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.071493 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.954200 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 271 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14543.018555 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.670469 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.025524 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1089.512365 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.887635 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000712 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000063 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.066499 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.954909 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 261 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15328 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 66 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15373 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 61 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 120 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 81 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 311 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1438 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7629 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4500 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1450 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.016541 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 79 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 318 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1446 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7384 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4965 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1260 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.015930 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.935547 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 67735071 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 67735071 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55557 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13221 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 68778 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 483131 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 483131 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1451301 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1451301 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 4 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 221119 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 221119 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1183848 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1183848 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 387908 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 387908 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55557 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13221 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1183848 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 609027 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1861653 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55557 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13221 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1183848 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 609027 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1861653 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 499 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 185 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 684 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55776 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 55776 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20170 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 20170 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 48817 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 48817 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3546000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3350952500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5045019998 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 8411811498 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 12293000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3546000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3350952500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5045019998 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17363724717 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 25775536215 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265086000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6369584000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6634670000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 265086000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6369584000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6634670000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009077 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.014923 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010199 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999928 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999928 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159667 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159667 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056741 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056741 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.216654 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.216654 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008884 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013501 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056741 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.196574 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.106420 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008884 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013501 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056741 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.196574 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158377 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158377 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056611 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056611 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.215206 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.215206 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009077 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.014923 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056611 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.195208 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.105901 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009077 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.014923 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056611 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.195208 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.233472 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20918.262150 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 57534.711912 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 57534.711912 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17299.214716 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17299.214716 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15017.203768 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15017.203768 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 110499.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 110499.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40813.341067 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40813.341067 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 40940.561110 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 40940.561110 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24257.326226 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24257.326226 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 40940.561110 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28995.783226 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32794.577145 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 40940.561110 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28995.783226 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 57534.711912 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46257.816810 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 214957.194138 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197865.825442 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111038.648141 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 108989.414930 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 4083931 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2062737 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 216422 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 214567 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1855 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 102316 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1901889 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19032 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19032 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 714747 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1482534 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 90142 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 335134 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 87548 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42677 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 113494 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 288350 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 285091 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1255148 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 586492 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3253 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3770830 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2574893 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29200 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119227 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6494150 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160667312 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98708808 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53624 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 224224 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 259653968 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 933771 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 18925704 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 3041721 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.089004 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.286883 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231756 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24246.548323 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17909.090909 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22466.666667 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66098.421047 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 66098.421047 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17257.843753 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17257.843753 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15088.941185 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15088.941185 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52429.478915 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52429.478915 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47251.752048 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47251.752048 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26304.300160 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26304.300160 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24246.548323 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17909.090909 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47251.752048 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33763.117023 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38054.574604 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24246.548323 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17909.090909 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47251.752048 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33763.117023 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66098.421047 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53283.753527 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200414.826002 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 190706.237425 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105738.541476 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104900.943918 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 4079155 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2060991 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31388 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 213571 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 211819 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1752 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 114320 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1911393 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28457 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28457 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 712151 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1482098 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 89271 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 330960 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87226 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42590 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113358 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 287646 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284122 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1252747 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 585259 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3214 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3763658 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2614734 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29156 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119485 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6527033 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160361408 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98721444 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53072 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 223432 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 259359356 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 926756 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 18862496 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3052726 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.087981 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.285286 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2772852 91.16% 91.16% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 267014 8.78% 99.94% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1855 0.06% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2785896 91.26% 91.26% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 265078 8.68% 99.94% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1752 0.06% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3041721 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 4067278494 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3052726 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 4077518993 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 114026414 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 113316466 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1886176090 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1882577097 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1218391120 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1233739845 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 15802982 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 15895485 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 63205426 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 63655441 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 33853439 # Number of BP lookups -system.cpu1.branchPred.condPredicted 11509465 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 280542 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 18730917 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5987349 # Number of BTB hits +system.cpu1.branchPred.lookups 4630228 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2728889 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 266806 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2406642 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1541904 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 31.965061 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 12496464 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7318 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 9007806 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 8970953 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 36853 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 10907 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 64.068690 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 874664 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7405 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 249240 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 213278 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 35962 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 10619 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1661,89 +1661,93 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 21636 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 21636 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8665 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5933 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 7038 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 14598 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 649.780792 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3376.631612 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 13908 95.27% 95.27% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 186 1.27% 96.55% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 234 1.60% 98.15% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 108 0.74% 98.89% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 46 0.32% 99.21% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 30 0.21% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 8 0.05% 99.47% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 66 0.45% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 4 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 4 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 21137 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 21137 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8393 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5852 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 6892 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 14245 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 645.419445 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3393.467484 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 13571 95.27% 95.27% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 196 1.38% 96.64% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 230 1.61% 98.26% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 102 0.72% 98.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 28 0.20% 99.17% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 27 0.19% 99.36% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 10 0.07% 99.43% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 64 0.45% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 5 0.04% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::36864-40959 10 0.07% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 14598 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5531 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11435.002712 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10101.039860 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6336.393968 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1833 33.14% 33.14% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3041 54.98% 88.12% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 457 8.26% 96.38% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 138 2.50% 98.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 31 0.56% 99.44% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 23 0.42% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 4 0.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5531 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 68460974968 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.179525 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.388721 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 68438733968 99.97% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 17027000 0.02% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 2383000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 1817500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 437500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 205000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 153500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 216500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 1000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 68460974968 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1927 75.51% 75.51% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 625 24.49% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2552 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21636 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 14245 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5483 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11374.338866 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9975.216104 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6340.433585 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1893 34.52% 34.52% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2927 53.38% 87.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 431 7.86% 95.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 169 3.08% 98.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 33 0.60% 99.45% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 24 0.44% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 5 0.09% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5483 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 77531116060 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.220578 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.418371 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 60476667848 78.00% 78.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 17032378712 21.97% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2 12865500 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::3 4248000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4 1183000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::5 1086000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6 1322500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::7 461500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8 217000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::9 174500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10 136000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::11 33500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12 198000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::13 27000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14 21000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::15 96000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 77531116060 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1915 74.80% 74.80% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 645 25.20% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2560 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21137 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21636 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2552 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21137 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2560 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2552 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 24188 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2560 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 23697 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10130487 # DTB read hits -system.cpu1.dtb.read_misses 18672 # DTB read misses -system.cpu1.dtb.write_hits 6476473 # DTB write hits -system.cpu1.dtb.write_misses 2964 # DTB write misses +system.cpu1.dtb.read_hits 4149269 # DTB read hits +system.cpu1.dtb.read_misses 18244 # DTB read misses +system.cpu1.dtb.write_hits 3464998 # DTB write hits +system.cpu1.dtb.write_misses 2893 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1961 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 63 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 385 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1955 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 48 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 410 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 370 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10149159 # DTB read accesses -system.cpu1.dtb.write_accesses 6479437 # DTB write accesses +system.cpu1.dtb.perms_faults 410 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 4167513 # DTB read accesses +system.cpu1.dtb.write_accesses 3467891 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16606960 # DTB hits -system.cpu1.dtb.misses 21636 # DTB misses -system.cpu1.dtb.accesses 16628596 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 7614267 # DTB hits +system.cpu1.dtb.misses 21137 # DTB misses +system.cpu1.dtb.accesses 7635404 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1773,57 +1777,63 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 6064 # Table walker walks requested -system.cpu1.itb.walker.walksShort 6064 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2840 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2623 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 601 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 5463 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 343.950211 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 2166.504505 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-4095 5312 97.24% 97.24% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-8191 57 1.04% 98.28% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-12287 43 0.79% 99.07% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-16383 29 0.53% 99.60% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-20479 6 0.11% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-24575 5 0.09% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-28671 5 0.09% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::28672-32767 5 0.09% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-36863 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 5463 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1764 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12147.108844 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11115.999882 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5636.944380 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 277 15.70% 15.70% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 1298 73.58% 89.29% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 111 6.29% 95.58% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 59 3.34% 98.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-40959 9 0.51% 99.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 7 0.40% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-57343 2 0.11% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 5745 # Table walker walks requested +system.cpu1.itb.walker.walksShort 5745 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2522 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2644 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 579 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 5166 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 354.045683 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 2100.129090 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-2047 4967 96.15% 96.15% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::2048-4095 43 0.83% 96.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-6143 47 0.91% 97.89% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::6144-8191 21 0.41% 98.30% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-10239 19 0.37% 98.66% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::10240-12287 23 0.45% 99.11% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-14335 19 0.37% 99.48% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::14336-16383 7 0.14% 99.61% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-18431 6 0.12% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::18432-20479 1 0.02% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-22527 4 0.08% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::22528-24575 1 0.02% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.04% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::26624-28671 3 0.06% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::28672-30719 3 0.06% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 5166 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1734 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12119.088812 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10982.617612 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5990.262254 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 321 18.51% 18.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 1223 70.53% 89.04% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 108 6.23% 95.27% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 58 3.34% 98.62% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 14 0.81% 99.42% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 4 0.23% 99.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-57343 5 0.29% 99.94% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1764 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 16901758916 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.861276 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.345783 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 2345411264 13.88% 13.88% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 14555617152 86.12% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 730500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 16901758916 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 989 85.04% 85.04% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 174 14.96% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1163 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 1734 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 17381208916 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.871345 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.334946 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 2236929264 12.87% 12.87% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 15143532152 87.13% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 747500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 17381208916 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 985 85.28% 85.28% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 170 14.72% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1155 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6064 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6064 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5745 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5745 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1163 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1163 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 7227 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 43493383 # ITB inst hits -system.cpu1.itb.inst_misses 6064 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1155 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1155 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 6900 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 8164971 # ITB inst hits +system.cpu1.itb.inst_misses 5745 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1832,1023 +1842,1024 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1129 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1122 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 581 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 574 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 43499447 # ITB inst accesses -system.cpu1.itb.hits 43493383 # DTB hits -system.cpu1.itb.misses 6064 # DTB misses -system.cpu1.itb.accesses 43499447 # DTB accesses -system.cpu1.numPwrStateTransitions 5513 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2757 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1005805033.413856 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25768715425.209221 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1955 70.91% 70.91% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 798 28.94% 99.85% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 8170716 # ITB inst accesses +system.cpu1.itb.hits 8164971 # DTB hits +system.cpu1.itb.misses 5745 # DTB misses +system.cpu1.itb.accesses 8170716 # DTB accesses +system.cpu1.numPwrStateTransitions 5463 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2732 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1028238405.084919 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25963867647.326580 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1944 71.16% 71.16% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 782 28.62% 99.78% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 959983620244 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2757 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 53106605878 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2773004477122 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 106214002 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 959984033604 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2732 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 17447601808 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2809147322692 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 34895980 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 10283907 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 108683336 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 33853439 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 27454766 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 92513470 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3739662 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 81877 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 30058 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 180666 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 303073 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 23077 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 43492215 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 108878 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2205 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 105285959 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.278787 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.339334 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 8706814 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 24545743 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4630228 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 2629846 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 24236084 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 776070 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 77763 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 35252 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 165739 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 299959 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23654 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8163829 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 107624 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2029 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 33933300 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.881300 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.218696 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 48617714 46.18% 46.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 13927599 13.23% 59.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7511266 7.13% 66.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 35229380 33.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 20192419 59.51% 59.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 4836103 14.25% 73.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1645003 4.85% 78.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 7259775 21.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 105285959 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.318729 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.023249 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 13161149 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 62754723 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 26539387 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1087783 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1742917 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 736717 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 129511 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 67619846 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1094387 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1742917 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17542611 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2352209 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 57806856 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 23225004 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2616362 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 54744976 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 213737 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 258070 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 37169 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 15433 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1611507 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 54654605 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 258629758 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 58168286 # Number of integer rename lookups +system.cpu1.fetch.rateDist::total 33933300 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.132687 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.703397 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 7185713 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 16755217 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 8648276 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1081250 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 262844 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 705359 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 127834 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 23145137 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1030723 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 262844 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 8592488 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2388926 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11714810 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8302740 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2671492 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 21985761 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 184128 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 260119 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 36299 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 16259 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1667149 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 21955593 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 102445019 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 25352022 # Number of integer rename lookups system.cpu1.rename.fp_rename_lookups 1683 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 52142746 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2511859 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1875660 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1802517 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 13071586 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 10382439 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6812181 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 622946 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 790955 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 53883918 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 580977 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 53654093 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 93763 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 3608749 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 5111945 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 44050 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 105285959 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.509603 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.847754 # Number of insts issued each cycle +system.cpu1.rename.CommittedMaps 19598713 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2356880 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 406325 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 333389 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2861472 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 4400097 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 3772059 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 619281 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 624174 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 21175375 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 559463 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 20999121 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 90560 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2005952 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 4627057 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 43664 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 33933300 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.618835 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.947092 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 72150462 68.53% 68.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 16497460 15.67% 84.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 13036209 12.38% 96.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3323109 3.16% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 278707 0.26% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 21549433 63.51% 63.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6114741 18.02% 81.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4178352 12.31% 93.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 1835426 5.41% 99.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 255342 0.75% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 6 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 105285959 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 33933300 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2901953 45.47% 45.47% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 671 0.01% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1666030 26.11% 71.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1813313 28.41% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 1405486 29.50% 29.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 669 0.01% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1602534 33.64% 63.16% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1754875 36.84% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 36596131 68.21% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45838 0.09% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 3311 0.01% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 10338451 19.27% 87.57% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6670296 12.43% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 12960054 61.72% 61.72% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 27621 0.13% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 3265 0.02% 61.86% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.86% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.86% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.86% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 4356029 20.74% 82.61% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 3652086 17.39% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 53654093 # Type of FU issued -system.cpu1.iq.rate 0.505151 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 6381967 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.118947 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 219063644 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 58081406 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 51689844 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 6231 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2072 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 1788 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 60031897 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 4097 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 89933 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 20999121 # Type of FU issued +system.cpu1.iq.rate 0.601763 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4763564 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.226846 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 80779382 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 23748142 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 20541259 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 6284 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2076 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 1790 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 25758471 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 4148 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 87109 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 434041 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 639 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 9872 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 275866 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 405898 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 640 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 9457 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 249525 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 52151 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 77961 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 40585 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 76754 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1742917 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 520776 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 103336 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 54505946 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 262844 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 543765 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 103558 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 21775845 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 10382439 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6812181 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 296650 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 7746 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 89089 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 9872 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 44543 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 120099 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 164642 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 53411917 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 10242028 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 220561 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 4400097 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 3772059 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 296163 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 7694 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 88949 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 9457 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 34239 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 118390 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 152629 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 20771745 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 4261184 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 206260 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 41051 # number of nop insts executed -system.cpu1.iew.exec_refs 16861277 # number of memory reference insts executed -system.cpu1.iew.exec_branches 11793508 # Number of branches executed -system.cpu1.iew.exec_stores 6619249 # Number of stores executed -system.cpu1.iew.exec_rate 0.502871 # Inst execution rate -system.cpu1.iew.wb_sent 53270244 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 51691632 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 25129407 # num instructions producing a value -system.cpu1.iew.wb_consumers 38339279 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.486674 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.655448 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 3369485 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 536927 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 153628 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 103395222 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.492179 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.152090 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 41007 # number of nop insts executed +system.cpu1.iew.exec_refs 7864490 # number of memory reference insts executed +system.cpu1.iew.exec_branches 3010595 # Number of branches executed +system.cpu1.iew.exec_stores 3603306 # Number of stores executed +system.cpu1.iew.exec_rate 0.595248 # Inst execution rate +system.cpu1.iew.wb_sent 20641556 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 20543049 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 10275425 # num instructions producing a value +system.cpu1.iew.wb_consumers 16109782 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.588694 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.637838 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 1795274 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 515799 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 141615 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 33527734 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.589415 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.349112 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 77830115 75.27% 75.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 14293086 13.82% 89.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6071280 5.87% 94.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 693599 0.67% 95.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1980010 1.91% 97.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 1625143 1.57% 99.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 382099 0.37% 99.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 124911 0.12% 99.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 394979 0.38% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 24087304 71.84% 71.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 5545630 16.54% 88.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1675188 5.00% 93.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 660381 1.97% 95.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 508267 1.52% 96.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 330740 0.99% 97.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 223183 0.67% 98.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 117603 0.35% 98.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 379438 1.13% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 103395222 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 41318794 # Number of instructions committed -system.cpu1.commit.committedOps 50889001 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 33527734 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 16118487 # Number of instructions committed +system.cpu1.commit.committedOps 19761740 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16484713 # Number of memory references committed -system.cpu1.commit.loads 9948398 # Number of loads committed -system.cpu1.commit.membars 208127 # Number of memory barriers committed -system.cpu1.commit.branches 11637916 # Number of branches committed +system.cpu1.commit.refs 7516733 # Number of memory references committed +system.cpu1.commit.loads 3994199 # Number of loads committed +system.cpu1.commit.membars 208310 # Number of memory barriers committed +system.cpu1.commit.branches 2858693 # Number of branches committed system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 45745086 # Number of committed integer instructions. -system.cpu1.commit.function_calls 3368055 # Number of function calls committed. +system.cpu1.commit.int_insts 17575462 # Number of committed integer instructions. +system.cpu1.commit.function_calls 459876 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 34356210 67.51% 67.51% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 44767 0.09% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 3311 0.01% 67.61% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.61% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.61% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.61% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 9948398 19.55% 87.16% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 6536315 12.84% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 12215165 61.81% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 26577 0.13% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 3265 0.02% 61.96% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.96% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.96% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.96% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 3994199 20.21% 82.17% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 3522534 17.83% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 50889001 # Class of committed instruction -system.cpu1.commit.bw_lim_events 394979 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 137189075 # The number of ROB reads -system.cpu1.rob.rob_writes 110398979 # The number of ROB writes -system.cpu1.timesIdled 58975 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 928043 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5545446856 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 41285938 # Number of Instructions Simulated -system.cpu1.committedOps 50856145 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.572644 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.572644 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.388705 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.388705 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 55995090 # number of integer regfile reads -system.cpu1.int_regfile_writes 35603094 # number of integer regfile writes -system.cpu1.fp_regfile_reads 1401 # number of floating regfile reads +system.cpu1.commit.op_class_0::total 19761740 # Class of committed instruction +system.cpu1.commit.bw_lim_events 379438 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 53719965 # The number of ROB reads +system.cpu1.rob.rob_writes 43510270 # The number of ROB writes +system.cpu1.timesIdled 58110 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 962680 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5617725351 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 16085632 # Number of Instructions Simulated +system.cpu1.committedOps 19728885 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.169388 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.169388 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.460959 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.460959 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 23317955 # number of integer regfile reads +system.cpu1.int_regfile_writes 13332838 # number of integer regfile writes +system.cpu1.fp_regfile_reads 1403 # number of floating regfile reads system.cpu1.fp_regfile_writes 516 # number of floating regfile writes -system.cpu1.cc_regfile_reads 190376100 # number of cc regfile reads -system.cpu1.cc_regfile_writes 15518701 # number of cc regfile writes -system.cpu1.misc_regfile_reads 209095836 # number of misc regfile reads -system.cpu1.misc_regfile_writes 386203 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 187149 # number of replacements -system.cpu1.dcache.tags.tagsinuse 469.748213 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 15687000 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 187502 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 83.663108 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 93899473000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.748213 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917477 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.917477 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 353 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.689453 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 32860265 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 32860265 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 9540081 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 9540081 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 5893568 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 5893568 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48959 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 48959 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77987 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 77987 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70168 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70168 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 15433649 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 15433649 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 15482608 # number of overall hits -system.cpu1.dcache.overall_hits::total 15482608 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 215586 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 215586 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 396166 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 396166 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30156 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30156 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18335 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18335 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23429 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23429 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 611752 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 611752 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 641908 # number of overall misses -system.cpu1.dcache.overall_misses::total 641908 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3514528500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3514528500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9742278459 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 9742278459 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 360181500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 360181500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 551095500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 551095500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 166500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 166500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13256806959 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13256806959 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13256806959 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13256806959 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9755667 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9755667 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6289734 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6289734 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79115 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79115 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96322 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96322 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93597 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 93597 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 16045401 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 16045401 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 16124516 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 16124516 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022099 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.022099 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062986 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.062986 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381167 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381167 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190351 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190351 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.250318 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250318 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038126 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.038126 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039809 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.039809 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16302.211183 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16302.211183 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24591.404762 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 24591.404762 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19644.477775 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19644.477775 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23521.938623 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23521.938623 # average StoreCondReq miss latency +system.cpu1.cc_regfile_reads 74580678 # number of cc regfile reads +system.cpu1.cc_regfile_writes 6681708 # number of cc regfile writes +system.cpu1.misc_regfile_reads 69976526 # number of misc regfile reads +system.cpu1.misc_regfile_writes 387406 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 185136 # number of replacements +system.cpu1.dcache.tags.tagsinuse 468.617373 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6737062 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 185477 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 36.322897 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 89354157500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.617373 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.915268 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.915268 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 326 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.666016 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 14947542 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14947542 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 3587773 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3587773 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2897885 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2897885 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49072 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49072 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78768 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78768 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70845 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 70845 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6485658 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6485658 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6534730 # number of overall hits +system.cpu1.dcache.overall_hits::total 6534730 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 212319 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 212319 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 390908 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 390908 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 29887 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 29887 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18355 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 18355 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23465 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23465 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 603227 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 603227 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 633114 # number of overall misses +system.cpu1.dcache.overall_misses::total 633114 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3545506500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3545506500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9944995958 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 9944995958 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362846000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 362846000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 551070500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 551070500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 640500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 640500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13490502458 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13490502458 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13490502458 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13490502458 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3800092 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3800092 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3288793 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3288793 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 78959 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 78959 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97123 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97123 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94310 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94310 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 7088885 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7088885 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7167844 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7167844 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.055872 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.055872 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.118861 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.118861 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.378513 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.378513 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.188987 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.188987 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248807 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248807 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085095 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.085095 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.088327 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.088327 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16698.960055 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16698.960055 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25440.758332 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25440.758332 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19768.237537 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19768.237537 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23484.785851 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23484.785851 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21670.230680 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 21670.230680 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20652.191527 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20652.191527 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 350 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1431753 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 38 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 39808 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.210526 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 35.966464 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 187150 # number of writebacks -system.cpu1.dcache.writebacks::total 187150 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79090 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 79090 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306284 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 306284 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13036 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13036 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 385374 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 385374 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 385374 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 385374 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136496 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 136496 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 89882 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 89882 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28741 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 28741 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5299 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5299 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23429 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23429 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 226378 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 226378 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 255119 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 255119 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14517 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14517 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11855 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11855 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26372 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26372 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1963325500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1963325500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2363104967 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2363104967 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 488593500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 488593500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 93065000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 93065000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 527670500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 527670500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 162500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 162500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4326430467 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4326430467 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4815023967 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4815023967 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2528366000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2528366000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2528366000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2528366000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013991 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013991 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014290 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014290 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.363281 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.363281 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055013 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055013 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.250318 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250318 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014109 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.014109 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015822 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.015822 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14383.758498 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14383.758498 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26291.192530 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26291.192530 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16999.878223 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16999.878223 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17562.747688 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17562.747688 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22522.109352 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22522.109352 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22363.890307 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 22363.890307 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21308.172711 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21308.172711 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 334 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1473013 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 39225 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.823529 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 37.552913 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 185136 # number of writebacks +system.cpu1.dcache.writebacks::total 185136 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 77580 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 77580 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 301933 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 301933 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13088 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13088 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 379513 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 379513 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 379513 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 379513 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134739 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 134739 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 88975 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 88975 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28539 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 28539 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5267 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5267 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23465 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23465 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 223714 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 223714 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 252253 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 252253 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3386 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3386 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2740 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2740 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6126 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6126 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1970715500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1970715500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2395378969 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2395378969 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 480267000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 480267000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 94406500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 94406500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 527620500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 527620500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 625500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 625500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4366094469 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4366094469 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4846361469 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4846361469 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 459425000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 459425000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 459425000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 459425000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035457 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035457 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027054 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027054 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361441 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361441 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054230 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054230 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248807 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248807 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031558 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031558 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035192 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035192 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14626.169854 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14626.169854 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26921.932779 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26921.932779 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16828.445285 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16828.445285 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17924.150370 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17924.150370 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22485.425101 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22485.425101 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19111.532335 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19111.532335 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18873.639231 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18873.639231 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174165.874492 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174165.874492 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95873.123009 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95873.123009 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 589510 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.449637 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 42880129 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 590022 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 72.675475 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 79021423000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.449637 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975488 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975488 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19516.411440 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19516.411440 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19212.304587 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19212.304587 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135683.697578 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 135683.697578 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 74995.919034 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 74995.919034 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 583486 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.437314 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 7557735 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 583998 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 12.941371 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 79127078000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.437314 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975464 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975464 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 87573930 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 87573930 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 42880129 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 42880129 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 42880129 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 42880129 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 42880129 # number of overall hits -system.cpu1.icache.overall_hits::total 42880129 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 611823 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 611823 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 611823 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 611823 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 611823 # number of overall misses -system.cpu1.icache.overall_misses::total 611823 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5700309356 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5700309356 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5700309356 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5700309356 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5700309356 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5700309356 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 43491952 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 43491952 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 43491952 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 43491952 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 43491952 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 43491952 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014067 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014067 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014067 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014067 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014067 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014067 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9316.925575 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9316.925575 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9316.925575 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9316.925575 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9316.925575 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9316.925575 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 502398 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 16911139 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 16911139 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 7557735 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7557735 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7557735 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7557735 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7557735 # number of overall hits +system.cpu1.icache.overall_hits::total 7557735 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 605833 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 605833 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 605833 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 605833 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 605833 # number of overall misses +system.cpu1.icache.overall_misses::total 605833 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5683938295 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5683938295 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5683938295 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5683938295 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5683938295 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5683938295 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8163568 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8163568 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8163568 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8163568 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8163568 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8163568 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074212 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.074212 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074212 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.074212 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074212 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.074212 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9382.021605 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9382.021605 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9382.021605 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9382.021605 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9382.021605 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9382.021605 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 514122 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 42118 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 41357 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.928344 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.431318 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 589510 # number of writebacks -system.cpu1.icache.writebacks::total 589510 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 21797 # 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number of writebacks +system.cpu1.icache.writebacks::total 583486 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 21830 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 21830 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 21830 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 21830 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 21830 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 21830 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 584003 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 584003 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 584003 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 584003 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 584003 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 584003 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 101 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 101 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5243631193 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5243631193 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5243631193 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5243631193 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5243631193 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5243631193 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8747999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8747999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8747999 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8747999 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013566 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013566 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013566 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.013566 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013566 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.013566 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8887.118861 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8887.118861 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8887.118861 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8887.118861 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8887.118861 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8887.118861 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86613.851485 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86613.851485 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86613.851485 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86613.851485 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 195371 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 196016 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 576 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5223422114 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5223422114 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5223422114 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5223422114 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5223422114 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5223422114 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9321999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9321999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9321999 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9321999 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071538 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071538 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071538 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071538 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071538 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071538 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8944.170003 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8944.170003 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8944.170003 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8944.170003 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8944.170003 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8944.170003 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92297.019802 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92297.019802 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92297.019802 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92297.019802 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 192037 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 192612 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 514 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 57640 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 44567 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14592.313259 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 696647 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 58721 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.863677 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 57820 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 43247 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14634.111672 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 688069 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 57318 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 12.004414 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14188.463877 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 10.825483 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.061403 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 390.962497 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.865995 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000661 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000126 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023862 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.890644 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 294 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 30 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13830 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 181 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 105 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14183.524826 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 11.708728 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.055002 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 436.823115 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.865694 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000715 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026662 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.893195 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 321 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13723 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 183 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 133 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1785 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8625 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3420 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017944 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001831 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.844116 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 27388422 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 27388422 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 17107 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6359 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 23466 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 113848 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 113848 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 650456 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 650456 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 26908 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 26908 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 565476 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 565476 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99207 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 99207 # 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number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 513000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 513000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1175287000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1175287000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 794529500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 794529500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1211572499 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1211572499 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 8154500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4235000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 794529500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2386859499 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3193778499 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 8154500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4235000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 794529500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2386859499 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1120294346 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4314072845 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8564000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 432303000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 440867000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8564000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 432303000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 440867000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.029253 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046120 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.033802 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.550959 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.550959 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.041590 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041590 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.417775 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.417775 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.027680 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.044034 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.041590 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.452812 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153839 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.027680 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.044034 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.041590 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.452812 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.546381 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.546381 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.040822 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040822 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.419871 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.419871 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.029253 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046120 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.040822 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.453267 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153553 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.029253 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046120 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.040822 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.453267 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183275 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15346.794872 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41062.935524 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41062.935524 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15478.018461 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15478.018461 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15006.316958 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15006.316958 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183602 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16374.497992 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14603.448276 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15722.715736 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44579.958058 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44579.958058 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15354.338666 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15354.338666 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14973.513744 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14973.513744 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33744.960910 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33744.960910 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31362.871348 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31362.871348 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16784.184169 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16784.184169 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31362.871348 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22213.147876 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23897.821570 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31362.871348 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22213.147876 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41062.935524 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26654.734523 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79108.910891 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166162.395812 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165560.918046 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 79108.910891 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91467.446534 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91420.296151 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1661462 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 840058 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12360 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 115637 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106952 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8685 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 43235 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 842502 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11855 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11855 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 146735 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 662812 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 29649 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 30154 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 72596 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41626 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86297 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 68185 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 65527 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 590026 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 275295 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 251 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1769762 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 885483 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14740 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38125 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2708110 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 75491792 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29665722 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 26616 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70376 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 105254506 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 347103 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 4899396 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1195777 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.122893 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.349738 # Request fanout histogram +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 35586.719554 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 35586.719554 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33327.579698 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33327.579698 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17122.279522 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17122.279522 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16374.497992 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14603.448276 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33327.579698 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22997.894697 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24870.952536 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16374.497992 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14603.448276 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33327.579698 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22997.894697 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44579.958058 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28096.655324 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84792.079208 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 127673.656232 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126431.603097 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84792.079208 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 70568.560235 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 70799.261282 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1644268 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 831312 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 115055 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106415 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8640 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 31394 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 822139 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2740 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2740 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 144852 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 655914 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 29483 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 30330 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71834 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41698 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85505 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 67721 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 64923 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 584003 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 271211 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 307 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1751691 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 836213 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14098 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37121 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2639123 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 74720720 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29257698 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25152 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 68096 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 104071666 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 343275 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 4808780 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1162877 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.125522 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.353024 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1057509 88.44% 88.44% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 129583 10.84% 99.27% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 8685 0.73% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1025550 88.19% 88.19% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 128687 11.07% 99.26% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 8640 0.74% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1195777 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1635737987 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1162877 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1604189995 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 81718473 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80522049 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 885241795 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 876204799 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 395391898 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 375699214 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 8093984 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 7819481 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 20543974 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 20111970 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31012 # Transaction distribution system.iobus.trans_dist::ReadResp 31012 # Transaction distribution system.iobus.trans_dist::WriteReq 59421 # Transaction distribution @@ -2899,33 +2910,33 @@ system.iobus.pkt_size_system.bridge.master::total 162794 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40381000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 40380000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 111500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 325000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 328000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 88000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 575500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 570500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) @@ -2933,32 +2944,32 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6080500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6100500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33803000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33792000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187681355 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187796551 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.555440 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.553749 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 255145986000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.555440 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.909715 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.909715 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 255488373000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.553749 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.909609 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.909609 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328284 # Number of tag accesses system.iocache.tags.data_accesses 328284 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2967,14 +2978,14 @@ system.iocache.demand_misses::realview.ide 36476 # system.iocache.demand_misses::total 36476 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36476 # number of overall misses system.iocache.overall_misses::total 36476 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32543877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32543877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4303510478 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4303510478 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4336054355 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4336054355 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4336054355 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4336054355 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 40604377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 40604377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4366091174 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4366091174 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4406695551 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4406695551 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4406695551 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4406695551 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2991,19 +3002,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129142.369048 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129142.369048 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118802.740669 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118802.740669 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118874.173566 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118874.173566 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118874.173566 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118874.173566 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 161128.480159 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 161128.480159 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120530.343805 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120530.343805 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120810.822212 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120810.822212 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120810.822212 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120810.822212 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 23 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 5.750000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks @@ -3015,14 +3026,14 @@ system.iocache.demand_mshr_misses::realview.ide 36476 system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19943877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19943877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2489987873 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2489987873 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2509931750 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2509931750 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2509931750 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2509931750 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 28004377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 28004377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2552566881 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2552566881 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2580571258 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2580571258 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2580571258 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2580571258 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -3031,618 +3042,612 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79142.369048 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 79142.369048 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68738.622819 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68738.622819 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68810.498684 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68810.498684 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68810.498684 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68810.498684 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 136926 # number of replacements -system.l2c.tags.tagsinuse 65153.135165 # Cycle average of tags in use -system.l2c.tags.total_refs 554455 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 202299 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.740770 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 87124800000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 6156.009081 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 17.876446 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.073086 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8059.392106 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 7027.702710 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37061.403814 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.474451 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.906071 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1853.985065 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2995.751440 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1972.560896 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.093933 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000273 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 111128.480159 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 111128.480159 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70466.179356 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70466.179356 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70747.101053 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70747.101053 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70747.101053 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70747.101053 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 137609 # number of replacements +system.l2c.tags.tagsinuse 65136.051895 # Cycle average of tags in use +system.l2c.tags.total_refs 548833 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 202971 # 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Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.572430 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.028290 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.045712 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030099 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994158 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 33193 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32156 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 172 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5974 # 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Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4634 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 27347 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.506485 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.490662 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6339538 # Number of tag accesses -system.l2c.tags.data_accesses 6339538 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 263091 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 263091 # 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number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 21642 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 13232 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5163 # number of demand (read+write) hits -system.l2c.demand_hits::total 201360 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 230 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 86 # number of overall hits -system.l2c.overall_hits::cpu0.inst 51619 # number of overall hits -system.l2c.overall_hits::cpu0.data 62092 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 47216 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 63 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 17 # number of overall hits -system.l2c.overall_hits::cpu1.inst 21642 # number of overall hits -system.l2c.overall_hits::cpu1.data 13232 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5163 # 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average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 77375 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75611.687414 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80673.431734 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96406.532990 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86700 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73944.858586 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 88467.280064 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77375 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75611.687414 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75042.809864 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 95286.265989 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86700 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73944.858586 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 88467.280064 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77375 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75611.687414 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75042.809864 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 95286.265989 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196956.087726 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61099.009901 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148192.365991 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167436.910471 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101739.966470 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61099.009901 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81567.901703 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 92312.727880 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 505464 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 284514 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.012974 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.058317 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.017804 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.033141 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.044944 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.038507 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.737512 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.859255 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.784528 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.104693 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027273 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.281343 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.139636 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740529 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.056338 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.113777 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078286 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581345 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.470961 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.104693 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027273 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.281343 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.249970 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740529 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.056338 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.113777 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.415753 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581345 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.490865 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.104693 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027273 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.281343 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.249970 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740529 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.056338 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.113777 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.415753 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581345 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.490865 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22259.668508 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20685.567010 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21710.431655 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26375 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 22187.500000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24153.061224 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 137616.578778 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 81790.674966 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 114003.691327 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126396.551724 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 94964.840818 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 105678.857876 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115345.399549 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 215875 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 96493.178835 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113259.938838 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 141315.508015 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113151.993367 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126396.551724 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 94964.840818 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123068.175224 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115345.399549 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 215875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 96493.178835 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 85155.766296 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 141315.508015 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 113238.401516 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126396.551724 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 94964.840818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123068.175224 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115345.399549 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 215875 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 96493.178835 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85155.766296 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 141315.508015 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 113238.401516 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182412.592065 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66782.178218 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 109767.070647 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166861.720777 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96240.591660 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66782.178218 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 60647.068431 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 91929.949202 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 504773 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 283620 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 572 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 37954 # Transaction distribution -system.membus.trans_dist::ReadResp 209195 # Transaction distribution -system.membus.trans_dist::WriteReq 30887 # Transaction distribution -system.membus.trans_dist::WriteResp 30887 # Transaction distribution -system.membus.trans_dist::WritebackDirty 137421 # Transaction distribution -system.membus.trans_dist::CleanEvict 16935 # Transaction distribution -system.membus.trans_dist::UpgradeReq 65286 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 38770 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 38274 # Transaction distribution +system.membus.trans_dist::ReadResp 210079 # Transaction distribution +system.membus.trans_dist::WriteReq 31197 # Transaction distribution +system.membus.trans_dist::WriteResp 31197 # Transaction distribution +system.membus.trans_dist::WritebackDirty 137547 # Transaction distribution +system.membus.trans_dist::CleanEvict 17007 # Transaction distribution +system.membus.trans_dist::UpgradeReq 64594 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38710 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 39566 # Transaction distribution -system.membus.trans_dist::ReadExResp 19573 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 171242 # Transaction distribution +system.membus.trans_dist::ReadExReq 38808 # Transaction distribution +system.membus.trans_dist::ReadExResp 19352 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 171806 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13620 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 638853 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 760423 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14870 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 638456 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 761276 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 833372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 834225 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18721784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18912106 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29740 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18751880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18944702 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21230250 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123250 # Total snoops (count) +system.membus.pkt_size::total 21262846 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 122284 # Total snoops (count) system.membus.snoopTraffic 36480 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 419934 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012350 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.110440 # Request fanout histogram +system.membus.snoop_fanout::samples 419616 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012440 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.110839 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 414748 98.77% 98.77% # Request fanout histogram -system.membus.snoop_fanout::1 5186 1.23% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 414396 98.76% 98.76% # Request fanout histogram +system.membus.snoop_fanout::1 5220 1.24% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 419934 # Request fanout histogram -system.membus.reqLayer0.occupancy 81570000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 419616 # Request fanout histogram +system.membus.reqLayer0.occupancy 81572000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11357000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12355500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 987545766 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 987789803 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1099710840 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1102143190 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1385881 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1335877 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3674,81 +3679,81 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1051858 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 557134 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 188416 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 28173 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 27109 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1064 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 37957 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 525508 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30887 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30887 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 364306 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 131438 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 111511 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43584 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 155095 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50612 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50612 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 487554 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4612 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1267106 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 367019 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1634125 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36291756 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5905726 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 42197482 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 390713 # Total snoops (count) -system.toL2Bus.snoopTraffic 15836620 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 903686 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.404217 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.493133 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1044068 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 554075 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 185190 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 28829 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 27647 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1182 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826594924500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 38277 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 522605 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31197 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31197 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 362967 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 130325 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 110585 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43604 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 154189 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50073 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50073 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 484331 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4646 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1303151 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 320962 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1624113 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36235416 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5679078 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 41914494 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 390245 # Total snoops (count) +system.toL2Bus.snoopTraffic 15796172 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 900374 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.402074 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.492987 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 539465 59.70% 59.70% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 363157 40.19% 99.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1064 0.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 539539 59.92% 59.92% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 359653 39.94% 99.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1182 0.13% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 903686 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 901600874 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 900374 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 896925065 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 355623 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 679704118 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 692605391 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 260937433 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 242340870 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1856 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 1870 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2757 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2732 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |