diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | 3130 |
1 files changed, 1548 insertions, 1582 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 85477463e..e24b483f1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,173 +1,151 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.602779 # Number of seconds simulated -sim_ticks 2602778916500 # Number of ticks simulated -final_tick 2602778916500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.102958 # Number of seconds simulated +sim_ticks 1102958416500 # Number of ticks simulated +final_tick 1102958416500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48820 # Simulator instruction rate (inst/s) -host_op_rate 62855 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2024215186 # Simulator tick rate (ticks/s) -host_mem_usage 443440 # Number of bytes of host memory used -host_seconds 1285.82 # Real time elapsed on the host -sim_insts 62774383 # Number of instructions simulated -sim_ops 80820330 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 148 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 148 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 148 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 395584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4382196 # Number of bytes read from this memory +host_inst_rate 66795 # Simulator instruction rate (inst/s) +host_op_rate 85978 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1196309321 # Simulator tick rate (ticks/s) +host_mem_usage 404244 # Number of bytes of host memory used +host_seconds 921.97 # Real time elapsed on the host +sim_insts 61582525 # Number of instructions simulated +sim_ops 79269125 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 410752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4380596 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 426624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5245232 # Number of bytes read from this memory -system.physmem.bytes_read::total 131562340 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 395584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 426624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 822208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4273600 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 405056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5224880 # Number of bytes read from this memory +system.physmem.bytes_read::total 59182180 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 410752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 405056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815808 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4259968 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7302736 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6181 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68544 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory +system.physmem.bytes_written::total 7287312 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6418 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68519 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6666 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81983 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15302224 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66775 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6329 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81665 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257812 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66562 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 824059 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46531239 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 151985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1683660 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 163911 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2015243 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50546875 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 151985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 163911 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315896 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1641937 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6531 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1157277 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2805746 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1641937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46531239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 151985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1690192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 163911 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3172520 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53352621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15302224 # Total number of read requests seen -system.physmem.writeReqs 824059 # Total number of write requests seen -system.physmem.cpureqs 244149 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 979342336 # Total number of bytes read from memory -system.physmem.bytesWritten 52739776 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131562340 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7302736 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 337 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 14071 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956809 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 956626 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 956229 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956838 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956744 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 956129 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 956236 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956861 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955985 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 956063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 956435 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956372 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955730 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955657 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 956452 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51554 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51697 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51535 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50985 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51049 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51663 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52119 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51405 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51482 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51861 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51782 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51276 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51190 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51930 # Track writes on a per bank basis +system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory +system.physmem.num_writes::total 823398 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44207273 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 754 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 372409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3971678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 367245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4737150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53657671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 372409 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 367245 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 739654 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3862311 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2729336 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6607060 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3862311 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44207273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 372409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3987091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 367245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7466486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60264731 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257812 # Total number of read requests seen +system.physmem.writeReqs 823398 # Total number of write requests seen +system.physmem.cpureqs 242000 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 400499968 # Total number of bytes read from memory +system.physmem.bytesWritten 52697472 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59182180 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7287312 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 78 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 12579 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391407 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391213 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 390854 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 391610 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391518 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 390872 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 390926 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 391637 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391404 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 390705 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 390857 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 391237 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 390526 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 390472 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 391263 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51413 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51231 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51006 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51680 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51540 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50963 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50973 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51665 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52039 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51352 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51495 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51885 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51842 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51248 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51173 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51893 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32645 # Number of times wr buffer was full causing retry -system.physmem.totGap 2602777722500 # Total gap between requests +system.physmem.numWrRetry 32627 # Number of times wr buffer was full causing retry +system.physmem.totGap 1102957282500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes -system.physmem.readPktSize::3 15138816 # Categorize read packet sizes +system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163303 # Categorize read packet sizes +system.physmem.readPktSize::6 162859 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 757284 # Categorize write packet sizes +system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66775 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1059619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 995756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 964447 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3596573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2710922 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2723432 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2682017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 62131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 60256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 110205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 159682 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17046 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 12933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66562 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 493912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 430569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 391898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1441588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1085856 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1098172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1064332 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26910 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24845 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 44429 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 63782 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 44273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12054 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 11817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 15280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 7853 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -178,304 +156,308 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32658 # What write queue length does an incoming req see -system.physmem.totQLat 398163291750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 491955679250 # Sum of mem lat for all requests -system.physmem.totBusLat 76509435000 # Total cycles spent in databus access -system.physmem.totBankLat 17282952500 # Total cycles spent in bank access -system.physmem.avgQLat 26020.54 # Average queueing delay per request -system.physmem.avgBankLat 1129.47 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32643 # What write queue length does an incoming req see +system.physmem.totQLat 199244474250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 239068869250 # Sum of mem lat for all requests +system.physmem.totBusLat 31288670000 # Total cycles spent in databus access +system.physmem.totBankLat 8535725000 # Total cycles spent in bank access +system.physmem.avgQLat 31839.72 # Average queueing delay per request +system.physmem.avgBankLat 1364.03 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32150.00 # Average memory access latency -system.physmem.avgRdBW 376.27 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.26 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.55 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.81 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 38203.74 # Average memory access latency +system.physmem.avgRdBW 363.11 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 47.78 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 53.66 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.10 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 12.56 # Average write queue length over time -system.physmem.readRowHits 15222567 # Number of row buffer hits during reads -system.physmem.writeRowHits 800487 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.48 # Row buffer hit rate for reads +system.physmem.busUtil 3.21 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.22 # Average read queue length over time +system.physmem.avgWrQLen 10.41 # Average write queue length over time +system.physmem.readRowHits 6213843 # Number of row buffer hits during reads +system.physmem.writeRowHits 799878 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.14 # Row buffer hit rate for writes -system.physmem.avgGap 161399.73 # Average gap between requests -system.l2c.replacements 73011 # number of replacements -system.l2c.tagsinuse 53067.424425 # Cycle average of tags in use -system.l2c.total_refs 1872250 # Total number of references to valid blocks. -system.l2c.sampled_refs 138181 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.549258 # Average number of references to valid blocks. +system.physmem.avgGap 155758.31 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 72564 # number of replacements +system.l2c.tagsinuse 53751.759262 # Cycle average of tags in use +system.l2c.total_refs 1839556 # Total number of references to valid blocks. +system.l2c.sampled_refs 137761 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.353242 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37745.757624 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 5.485079 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000341 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4193.697813 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2948.995369 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 14.004673 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.955179 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4039.578813 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4118.949534 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.575955 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000084 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 39378.859227 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 4.194190 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.010198 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4015.520084 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2826.859367 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 10.896267 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3720.882915 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3794.537014 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.600874 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000064 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.063991 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.044998 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000214 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061639 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.062850 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809745 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 23032 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4492 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 392957 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 165711 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 32830 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5777 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 607042 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 201661 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1433502 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 582954 # number of Writeback hits -system.l2c.Writeback_hits::total 582954 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1024 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 725 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1749 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 207 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 160 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 367 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 47437 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 59291 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106728 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 23032 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4492 # 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number of overall hits -system.l2c.overall_hits::cpu1.data 260952 # number of overall hits -system.l2c.overall_hits::total 1540230 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6061 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6334 # number of ReadReq misses +system.l2c.occ_percent::cpu0.inst 0.061272 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.043134 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000166 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.056776 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.057900 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.820187 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 21638 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4069 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 385706 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166655 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30870 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5056 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 589485 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 198042 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1401521 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 580941 # number of Writeback hits +system.l2c.Writeback_hits::total 580941 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1130 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 742 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1872 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 193 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 147 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 340 # 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number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 27099351040 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667566747 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167081540152 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050379735 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25959313642 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 27009693377 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5286835 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13449883784 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13457228273 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1838032 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180930876545 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 194387885196 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000607 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000445 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015177 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036601 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000518 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000173 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010792 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030486 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017377 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.846362 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.857283 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.851086 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787037 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.786667 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.786876 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.572882 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564575 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.568307 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000607 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000445 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015177 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.246983 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000518 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000173 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010792 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.241777 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.097210 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000607 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000445 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015177 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.246983 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000518 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000173 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010792 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.241777 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.097210 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54286.714286 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 43832.092470 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44684.445609 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70706.823529 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47213.702552 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 50339.321823 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 46579.558575 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10047.776990 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10160.455339 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10096.868047 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10038.233987 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.328814 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47213.702552 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41791.513525 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40439.697501 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54286.714286 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43832.092470 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37884.859474 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70706.823529 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47213.702552 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41791.513525 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40439.697501 # average overall mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180626880389 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 194091233529 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000600 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000737 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016053 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036774 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010551 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030623 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017685 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.819805 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836239 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.826699 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.768585 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.738899 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.756621 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569180 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.565125 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.566956 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000600 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000737 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016053 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.245405 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010551 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.243756 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098744 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000600 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000737 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016053 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.245405 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010551 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.243756 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098744 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54135.615385 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 43065.487685 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45112.000157 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 60927.470588 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47991.177696 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 50778.834905 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 46739.928982 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10056.507489 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10156.562681 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10098.960918 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10082.088924 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10070.694712 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10077.604541 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37457.263254 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41132.477559 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39466.861514 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54135.615385 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43065.487685 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38154.832462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 60927.470588 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47991.177696 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41861.113151 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40577.207474 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54135.615385 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43065.487685 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38154.832462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 60927.470588 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47991.177696 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41861.113151 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40577.207474 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -678,38 +648,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 6065134 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4623218 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 295247 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3783915 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2943990 # Number of BTB hits +system.cpu0.branchPred.lookups 5991996 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4570590 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 295222 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3736406 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2908427 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.802752 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 682666 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28697 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.840229 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 670993 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28752 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8964880 # DTB read hits -system.cpu0.dtb.read_misses 29505 # DTB read misses -system.cpu0.dtb.write_hits 5211507 # DTB write hits -system.cpu0.dtb.write_misses 5768 # DTB write misses +system.cpu0.dtb.read_hits 8901229 # DTB read hits +system.cpu0.dtb.read_misses 28750 # DTB read misses +system.cpu0.dtb.write_hits 5135502 # DTB write hits +system.cpu0.dtb.write_misses 5613 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1820 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1111 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 256 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1817 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 968 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 587 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8994385 # DTB read accesses -system.cpu0.dtb.write_accesses 5217275 # DTB write accesses +system.cpu0.dtb.perms_faults 548 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8929979 # DTB read accesses +system.cpu0.dtb.write_accesses 5141115 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14176387 # DTB hits -system.cpu0.dtb.misses 35273 # DTB misses -system.cpu0.dtb.accesses 14211660 # DTB accesses -system.cpu0.itb.inst_hits 4271941 # ITB inst hits -system.cpu0.itb.inst_misses 5082 # ITB inst misses +system.cpu0.dtb.hits 14036731 # DTB hits +system.cpu0.dtb.misses 34363 # DTB misses +system.cpu0.dtb.accesses 14071094 # DTB accesses +system.cpu0.itb.inst_hits 4213364 # ITB inst hits +system.cpu0.itb.inst_misses 5048 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -718,534 +688,530 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1340 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1344 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1395 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1487 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4277023 # ITB inst accesses -system.cpu0.itb.hits 4271941 # DTB hits -system.cpu0.itb.misses 5082 # DTB misses -system.cpu0.itb.accesses 4277023 # DTB accesses -system.cpu0.numCycles 68310391 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4218412 # ITB inst accesses +system.cpu0.itb.hits 4213364 # DTB hits +system.cpu0.itb.misses 5048 # DTB misses +system.cpu0.itb.accesses 4218412 # DTB accesses +system.cpu0.numCycles 67828518 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11985780 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32442629 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6065134 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3626656 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7605462 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1460769 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 62659 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 21080761 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5794 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 46842 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 87230 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 220 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4270468 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157226 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2109 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41924364 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.999512 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.380874 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11769514 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 31989018 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5991996 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3579420 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7508503 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1450801 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 60684 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20631180 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 48154 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 85409 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4211784 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 156653 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2012 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41149957 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.004329 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.384713 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34326103 81.88% 81.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 570380 1.36% 83.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 823787 1.96% 85.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 686899 1.64% 86.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 778226 1.86% 88.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 563231 1.34% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 676382 1.61% 91.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 356953 0.85% 92.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3142403 7.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33648798 81.77% 81.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 562155 1.37% 83.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 818096 1.99% 85.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 677471 1.65% 86.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 773499 1.88% 88.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 558438 1.36% 90.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 664363 1.61% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 352105 0.86% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3095032 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41924364 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088788 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.474930 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12503811 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 21012915 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6898585 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 522974 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 986079 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 948336 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64663 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40543036 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 211520 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 986079 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 13078116 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5721380 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13152385 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6797650 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2188754 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 39433741 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1845 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 443177 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1244404 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 41 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39808870 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 178177695 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 178143549 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34146 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31430562 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8378307 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 419823 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 376669 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5441918 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7757618 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5774212 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1139116 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1209168 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37348543 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 904610 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37701629 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 81879 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6330369 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13296779 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 257143 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41924364 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.899277 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.510411 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41149957 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088340 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.471616 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12268271 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20578267 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6812810 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 512754 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 977855 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 934513 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64660 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 39970940 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212731 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 977855 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12837244 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5740254 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12723807 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6707246 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2163551 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38872652 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1850 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 437651 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1233683 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39221318 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175562913 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175528548 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34365 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30916412 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8304905 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 410995 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 369967 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5350401 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7642102 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5682819 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1122438 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1201311 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36799804 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 894837 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37219527 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80251 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6274775 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13129416 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256270 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41149957 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.904485 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.513383 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26590532 63.43% 63.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5818938 13.88% 77.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3210799 7.66% 84.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2498063 5.96% 90.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2114705 5.04% 95.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 942628 2.25% 98.21% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 502674 1.20% 99.41% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 189300 0.45% 99.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 56725 0.14% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26028016 63.25% 63.25% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5729313 13.92% 77.17% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3155280 7.67% 84.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2465546 5.99% 90.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2105206 5.12% 95.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 932712 2.27% 98.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 494007 1.20% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 184426 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 55451 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41924364 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41149957 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26752 2.49% 2.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 460 0.04% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 840001 78.12% 80.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 208012 19.35% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 26761 2.50% 2.50% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 453 0.04% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 841654 78.63% 81.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 201534 18.83% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22644819 60.06% 60.20% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48004 0.13% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9425277 25.00% 85.33% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5530613 14.67% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22319985 59.97% 60.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46930 0.13% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9357970 25.14% 85.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5441771 14.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37701629 # Type of FU issued -system.cpu0.iq.rate 0.551916 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1075225 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028519 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 118511451 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44591434 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34839098 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8242 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4622 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3868 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38720352 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4288 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 316630 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37219527 # Type of FU issued +system.cpu0.iq.rate 0.548730 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1070402 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028759 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 116765436 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 43977253 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34319519 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8378 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4660 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3869 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38233387 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4393 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 306639 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1380313 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2666 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13062 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 544614 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1370211 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2367 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13030 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 536244 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149563 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5584 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192745 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5335 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 986079 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4106132 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 100687 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 38371433 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 85430 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7757618 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5774212 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 577195 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40897 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3001 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13062 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150158 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117749 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 267907 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37323557 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9281925 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 378072 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 977855 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4123044 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 98683 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37812695 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 84467 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7642102 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5682819 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571073 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39963 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2983 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13030 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 149756 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117796 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267552 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36844879 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9216416 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 374648 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118280 # number of nop insts executed -system.cpu0.iew.exec_refs 14765828 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4915455 # Number of branches executed -system.cpu0.iew.exec_stores 5483903 # Number of stores executed -system.cpu0.iew.exec_rate 0.546382 # Inst execution rate -system.cpu0.iew.wb_sent 37128467 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34842966 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18565053 # num instructions producing a value -system.cpu0.iew.wb_consumers 35706535 # num instructions consuming a value +system.cpu0.iew.exec_nop 118054 # number of nop insts executed +system.cpu0.iew.exec_refs 14611375 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4852197 # Number of branches executed +system.cpu0.iew.exec_stores 5394959 # Number of stores executed +system.cpu0.iew.exec_rate 0.543206 # Inst execution rate +system.cpu0.iew.wb_sent 36651456 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34323388 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18278983 # num instructions producing a value +system.cpu0.iew.wb_consumers 35164474 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.510068 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519934 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.506032 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.519814 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6140110 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 647467 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 231710 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40938285 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.775989 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.737548 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6082175 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638567 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 231668 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40172102 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.778393 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.739779 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 29080513 71.04% 71.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5796475 14.16% 85.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1964427 4.80% 89.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 998229 2.44% 92.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 793584 1.94% 94.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 517255 1.26% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 395614 0.97% 96.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 224138 0.55% 97.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1168050 2.85% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28502177 70.95% 70.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5716215 14.23% 85.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1915316 4.77% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 977454 2.43% 92.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 784200 1.95% 94.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 521856 1.30% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 386686 0.96% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 221286 0.55% 97.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1146912 2.85% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40938285 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24057849 # Number of instructions committed -system.cpu0.commit.committedOps 31767677 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40172102 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23670658 # Number of instructions committed +system.cpu0.commit.committedOps 31269703 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11606903 # Number of memory references committed -system.cpu0.commit.loads 6377305 # Number of loads committed -system.cpu0.commit.membars 231785 # Number of memory barriers committed -system.cpu0.commit.branches 4305044 # Number of branches committed +system.cpu0.commit.refs 11418466 # Number of memory references committed +system.cpu0.commit.loads 6271891 # Number of loads committed +system.cpu0.commit.membars 229601 # Number of memory barriers committed +system.cpu0.commit.branches 4243665 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28078801 # Number of committed integer instructions. -system.cpu0.commit.function_calls 498475 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1168050 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27627466 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489162 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1146912 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 76811981 # The number of ROB reads -system.cpu0.rob.rob_writes 76803371 # The number of ROB writes -system.cpu0.timesIdled 362519 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26386027 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5137205074 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23977107 # Number of Instructions Simulated -system.cpu0.committedOps 31686935 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23977107 # Number of Instructions Simulated -system.cpu0.cpi 2.848984 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.848984 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.351002 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.351002 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 174070948 # number of integer regfile reads -system.cpu0.int_regfile_writes 34592870 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3226 # number of floating regfile reads +system.cpu0.rob.rob_reads 75526096 # The number of ROB reads +system.cpu0.rob.rob_writes 75683450 # The number of ROB writes +system.cpu0.timesIdled 360623 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26678561 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2138046604 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23589916 # Number of Instructions Simulated +system.cpu0.committedOps 31188961 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23589916 # Number of Instructions Simulated +system.cpu0.cpi 2.875318 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.875318 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.347788 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.347788 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171729807 # number of integer regfile reads +system.cpu0.int_regfile_writes 34069963 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3242 # number of floating regfile reads system.cpu0.fp_regfile_writes 898 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13196303 # number of misc regfile reads -system.cpu0.misc_regfile_writes 457522 # number of misc regfile writes -system.cpu0.icache.replacements 399011 # number of replacements -system.cpu0.icache.tagsinuse 511.581015 # Cycle average of tags in use -system.cpu0.icache.total_refs 3839482 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 399523 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.610165 # Average number of references to valid blocks. +system.cpu0.misc_regfile_reads 13000351 # number of misc regfile reads +system.cpu0.misc_regfile_writes 450996 # number of misc regfile writes +system.cpu0.icache.replacements 392023 # number of replacements +system.cpu0.icache.tagsinuse 511.011023 # Cycle average of tags in use +system.cpu0.icache.total_refs 3788789 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 392535 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.652105 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6567370000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.581015 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999182 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999182 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3839482 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3839482 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3839482 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3839482 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3839482 # number of overall hits -system.cpu0.icache.overall_hits::total 3839482 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 430854 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 430854 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 430854 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 430854 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 430854 # number of overall misses -system.cpu0.icache.overall_misses::total 430854 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5887932497 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5887932497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5887932497 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5887932497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5887932497 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5887932497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4270336 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4270336 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4270336 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4270336 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4270336 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4270336 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100895 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100895 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100895 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100895 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100895 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100895 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13665.725506 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13665.725506 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13665.725506 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13665.725506 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13665.725506 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13665.725506 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2816 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 511.011023 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.998068 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998068 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3788789 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3788789 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3788789 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3788789 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3788789 # number of overall hits +system.cpu0.icache.overall_hits::total 3788789 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 422860 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 422860 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 422860 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 422860 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 422860 # number of overall misses +system.cpu0.icache.overall_misses::total 422860 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5794359497 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5794359497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5794359497 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5794359497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5794359497 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5794359497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4211649 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4211649 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4211649 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4211649 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4211649 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4211649 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100402 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100402 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100402 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100402 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100402 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100402 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13702.784602 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13702.784602 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13702.784602 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13702.784602 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13702.784602 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13702.784602 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2670 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 151 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 161 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.649007 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.583851 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31313 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 31313 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 31313 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 31313 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 31313 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 31313 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 399541 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 399541 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 399541 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 399541 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 399541 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 399541 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4811758497 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4811758497 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4811758497 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4811758497 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4811758497 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4811758497 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30304 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30304 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30304 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30304 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30304 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30304 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392556 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 392556 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 392556 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 392556 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 392556 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 392556 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4741290497 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4741290497 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4741290497 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4741290497 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4741290497 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4741290497 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7889500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7889500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7889500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7889500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093562 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093562 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093562 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093562 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093562 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093562 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12043.215833 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12043.215833 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12043.215833 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12043.215833 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12043.215833 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12043.215833 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093207 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093207 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093207 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093207 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093207 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093207 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12077.997781 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12077.997781 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12077.997781 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12077.997781 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12077.997781 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12077.997781 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 274797 # number of replacements -system.cpu0.dcache.tagsinuse 481.556098 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9422136 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 275309 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.223858 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 275942 # number of replacements +system.cpu0.dcache.tagsinuse 461.279186 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9251897 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276454 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.466316 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 43505000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 481.556098 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.940539 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.940539 # 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number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6411840492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6411840492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6411840492 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6411840492 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13437088000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13437088000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1251489878 # 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average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7973.568019 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4472.458720 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4472.458720 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20059.003757 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20059.003757 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20059.003757 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20059.003757 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256402 # number of writebacks +system.cpu0.dcache.writebacks::total 256402 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204348 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 204348 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1452057 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1452057 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 461 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 461 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1656405 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1656405 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1656405 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1656405 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188618 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188618 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130257 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130257 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8323 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8323 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7482 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7482 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 318875 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 318875 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 318875 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 318875 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2375120000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2375120000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4054292491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4054292491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66886000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66886000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31600000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31600000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6429412491 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6429412491 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6429412491 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6429412491 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13513828500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13513828500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180296878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180296878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14694125378 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14694125378 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030581 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030581 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027482 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027482 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056303 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056303 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051774 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051774 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029234 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029234 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029234 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029234 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12592.223436 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12592.223436 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31125.332926 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31125.332926 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8036.284993 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8036.284993 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4223.469661 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4223.469661 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20162.798874 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20162.798874 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20162.798874 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20162.798874 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1253,38 +1219,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9260108 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7598823 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 418413 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6211409 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5330705 # Number of BTB hits +system.cpu1.branchPred.lookups 9066051 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7453207 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 407044 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6058627 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5236584 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 85.821188 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 799378 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 44339 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 86.431860 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 771955 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42437 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43181625 # DTB read hits -system.cpu1.dtb.read_misses 38342 # DTB read misses -system.cpu1.dtb.write_hits 6975478 # DTB write hits -system.cpu1.dtb.write_misses 10879 # DTB write misses +system.cpu1.dtb.read_hits 42902362 # DTB read hits +system.cpu1.dtb.read_misses 36935 # DTB read misses +system.cpu1.dtb.write_hits 6824519 # DTB write hits +system.cpu1.dtb.write_misses 10718 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3080 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 279 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2005 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2714 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 302 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 684 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43219967 # DTB read accesses -system.cpu1.dtb.write_accesses 6986357 # DTB write accesses +system.cpu1.dtb.perms_faults 645 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42939297 # DTB read accesses +system.cpu1.dtb.write_accesses 6835237 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50157103 # DTB hits -system.cpu1.dtb.misses 49221 # DTB misses -system.cpu1.dtb.accesses 50206324 # DTB accesses -system.cpu1.itb.inst_hits 8542294 # ITB inst hits -system.cpu1.itb.inst_misses 5605 # ITB inst misses +system.cpu1.dtb.hits 49726881 # DTB hits +system.cpu1.dtb.misses 47653 # DTB misses +system.cpu1.dtb.accesses 49774534 # DTB accesses +system.cpu1.itb.inst_hits 8392998 # ITB inst hits +system.cpu1.itb.inst_misses 5431 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1293,114 +1259,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1533 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1531 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1566 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1493 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8547899 # ITB inst accesses -system.cpu1.itb.hits 8542294 # DTB hits -system.cpu1.itb.misses 5605 # DTB misses -system.cpu1.itb.accesses 8547899 # DTB accesses -system.cpu1.numCycles 410577330 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8398429 # ITB inst accesses +system.cpu1.itb.hits 8392998 # DTB hits +system.cpu1.itb.misses 5431 # DTB misses +system.cpu1.itb.accesses 8398429 # DTB accesses +system.cpu1.numCycles 408779942 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 20304470 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 67058817 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9260108 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6130083 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14383842 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4002399 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 71431 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77735291 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5936 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42666 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 133916 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 201 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8540383 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 747213 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2975 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 115405308 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.704397 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.049572 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19814855 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 66055643 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9066051 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6008539 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14146730 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3957386 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 64683 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77267641 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42583 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 129813 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 133 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8391200 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 740435 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2770 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114169430 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.700459 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.044215 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 101028811 87.54% 87.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 815655 0.71% 88.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 964627 0.84% 89.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1914792 1.66% 90.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1533608 1.33% 92.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 591916 0.51% 92.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2159319 1.87% 94.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 420670 0.36% 94.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5975910 5.18% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 100030180 87.62% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 795116 0.70% 88.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 937715 0.82% 89.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1888304 1.65% 90.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1526967 1.34% 92.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 578073 0.51% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2128721 1.86% 94.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 409818 0.36% 94.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5874536 5.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 115405308 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022554 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.163328 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21846277 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 77383941 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 13006148 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 540398 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2628544 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1139252 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 100555 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 76481536 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 334945 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2628544 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 23246660 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32001614 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 41094778 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 12051133 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4382579 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 70980554 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18812 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 684543 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3106754 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 398 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 74967908 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 326797465 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 326738119 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59346 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50107015 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24860893 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 461639 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 401710 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8025653 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13466262 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8327830 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1061558 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1475331 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 64680036 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1175419 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 90315471 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 95817 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16379719 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 46059622 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 276388 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 115405308 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.782594 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.520017 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114169430 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022178 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.161592 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21335636 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 76916914 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12791603 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 523584 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2601693 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1104215 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98013 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 75225150 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 326089 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2601693 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22720139 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 31942959 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40740266 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11835652 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4328721 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 69758398 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18799 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 669077 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3086745 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 378 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 73725482 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 321189458 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 321130296 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59162 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49052273 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24673209 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444958 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 387932 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7868643 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13207791 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8146456 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1036357 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1539549 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 63487430 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1157915 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89117422 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94398 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16230957 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45692140 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277223 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114169430 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.780572 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.518996 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 84537407 73.25% 73.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8582035 7.44% 80.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4411988 3.82% 84.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3834760 3.32% 87.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10634435 9.21% 97.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1994605 1.73% 98.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1053936 0.91% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 278337 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 77805 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83779617 73.38% 73.38% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8401659 7.36% 80.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4300327 3.77% 84.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3769049 3.30% 87.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10578609 9.27% 97.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1966316 1.72% 98.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1028949 0.90% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 270980 0.24% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 73924 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 115405308 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114169430 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32501 0.41% 0.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 990 0.01% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 31906 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 996 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available @@ -1428,395 +1394,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7572486 95.74% 96.16% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 303829 3.84% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7548325 95.86% 96.28% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 292902 3.72% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 38327866 42.44% 42.79% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61115 0.07% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1704 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.85% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44265466 49.01% 91.87% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7345367 8.13% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37601994 42.19% 42.55% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59184 0.07% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.61% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43968762 49.34% 91.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7172015 8.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 90315471 # Type of FU issued -system.cpu1.iq.rate 0.219972 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7909806 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.087580 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 304076071 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 82244261 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54749584 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14863 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8084 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6852 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 97903555 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7790 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 356637 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89117422 # Type of FU issued +system.cpu1.iq.rate 0.218008 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7874129 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088357 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300405264 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 80884614 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53615647 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15005 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8070 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6847 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96669700 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7919 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 342898 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3487877 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 4207 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17725 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1325961 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3454228 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3835 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 16932 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1307521 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31951985 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 889967 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31906117 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 888056 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2628544 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24227901 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 361425 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 65958607 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 113659 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13466262 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8327830 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 878933 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 66066 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3533 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17725 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 207255 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 158224 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 365479 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87865625 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43564360 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2449846 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2601693 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24180087 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 359608 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 64749015 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 111417 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13207791 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8146456 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869148 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 64619 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3744 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 16932 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 200731 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 155107 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 355838 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86675355 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43272699 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2442067 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 103152 # number of nop insts executed -system.cpu1.iew.exec_refs 50845626 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7156733 # Number of branches executed -system.cpu1.iew.exec_stores 7281266 # Number of stores executed -system.cpu1.iew.exec_rate 0.214005 # Inst execution rate -system.cpu1.iew.wb_sent 86881552 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54756436 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30516075 # num instructions producing a value -system.cpu1.iew.wb_consumers 54547350 # num instructions consuming a value +system.cpu1.iew.exec_nop 103670 # number of nop insts executed +system.cpu1.iew.exec_refs 50383092 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6989591 # Number of branches executed +system.cpu1.iew.exec_stores 7110393 # Number of stores executed +system.cpu1.iew.exec_rate 0.212034 # Inst execution rate +system.cpu1.iew.wb_sent 85698110 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53622494 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29929482 # num instructions producing a value +system.cpu1.iew.wb_consumers 53410166 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.133364 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.559442 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131177 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560371 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16276380 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 899031 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 319402 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 112776764 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.436287 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.405749 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16109317 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880692 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 310619 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111567737 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.431575 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.399552 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 95648521 84.81% 84.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8417489 7.46% 92.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2180084 1.93% 94.21% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1287029 1.14% 95.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1270394 1.13% 96.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 584036 0.52% 96.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1018862 0.90% 97.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 513430 0.46% 98.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1856919 1.65% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94819418 84.99% 84.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8239382 7.39% 92.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2114964 1.90% 94.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1255344 1.13% 95.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1246323 1.12% 96.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 567268 0.51% 97.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1001355 0.90% 97.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 504765 0.45% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1818918 1.63% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 112776764 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38866915 # Number of instructions committed -system.cpu1.commit.committedOps 49203034 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111567737 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38062248 # Number of instructions committed +system.cpu1.commit.committedOps 48149803 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16980254 # Number of memory references committed -system.cpu1.commit.loads 9978385 # Number of loads committed -system.cpu1.commit.membars 195514 # Number of memory barriers committed -system.cpu1.commit.branches 6118836 # Number of branches committed +system.cpu1.commit.refs 16592498 # Number of memory references committed +system.cpu1.commit.loads 9753563 # Number of loads committed +system.cpu1.commit.membars 190132 # Number of memory barriers committed +system.cpu1.commit.branches 5967184 # Number of branches committed system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43616937 # Number of committed integer instructions. -system.cpu1.commit.function_calls 553185 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1856919 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42685255 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534609 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1818918 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 175333256 # The number of ROB reads -system.cpu1.rob.rob_writes 133679925 # The number of ROB writes -system.cpu1.timesIdled 1420320 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295172022 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4794342654 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38797276 # Number of Instructions Simulated -system.cpu1.committedOps 49133395 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38797276 # Number of Instructions Simulated -system.cpu1.cpi 10.582633 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.582633 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.094494 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.094494 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 393458890 # number of integer regfile reads -system.cpu1.int_regfile_writes 57301820 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4905 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2316 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18909839 # number of misc regfile reads -system.cpu1.misc_regfile_writes 419175 # number of misc regfile writes -system.cpu1.icache.replacements 613709 # number of replacements -system.cpu1.icache.tagsinuse 498.827741 # Cycle average of tags in use -system.cpu1.icache.total_refs 7879826 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 614221 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 12.828975 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74226336500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.827741 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974273 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974273 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7879826 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7879826 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7879826 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7879826 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7879826 # number of overall hits -system.cpu1.icache.overall_hits::total 7879826 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 660506 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 660506 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 660506 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 660506 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 660506 # number of overall misses -system.cpu1.icache.overall_misses::total 660506 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8908973494 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8908973494 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8908973494 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8908973494 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8908973494 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8908973494 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8540332 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8540332 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8540332 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8540332 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8540332 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8540332 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.077340 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.077340 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.077340 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.077340 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.077340 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.077340 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13488.103808 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13488.103808 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13488.103808 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13488.103808 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13488.103808 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13488.103808 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2847 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 1026 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 181 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.729282 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 1026 # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 172963873 # The number of ROB reads +system.cpu1.rob.rob_writes 131212452 # The number of ROB writes +system.cpu1.timesIdled 1408163 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 294610512 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1796500385 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37992609 # Number of Instructions Simulated +system.cpu1.committedOps 48080164 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37992609 # Number of Instructions Simulated +system.cpu1.cpi 10.759460 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.759460 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092941 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092941 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 387855246 # number of integer regfile reads +system.cpu1.int_regfile_writes 56190036 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4937 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2324 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18474333 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405457 # number of misc regfile writes +system.cpu1.icache.replacements 595836 # number of replacements +system.cpu1.icache.tagsinuse 480.940966 # Cycle average of tags in use +system.cpu1.icache.total_refs 7749865 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 596348 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 12.995541 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74230255500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 480.940966 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.939338 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.939338 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7749865 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7749865 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7749865 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7749865 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7749865 # number of overall hits +system.cpu1.icache.overall_hits::total 7749865 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 641285 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 641285 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 641285 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 641285 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 641285 # number of overall misses +system.cpu1.icache.overall_misses::total 641285 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8628357996 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8628357996 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8628357996 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8628357996 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8628357996 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8628357996 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8391150 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8391150 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8391150 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8391150 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8391150 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8391150 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076424 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.076424 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076424 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.076424 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076424 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.076424 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13454.794664 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13454.794664 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13454.794664 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13454.794664 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13454.794664 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13454.794664 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3208 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 172 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.651163 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46258 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 46258 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 46258 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 46258 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 46258 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 46258 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 614248 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 614248 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 614248 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 614248 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 614248 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 614248 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7279881995 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7279881995 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7279881995 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7279881995 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7279881995 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7279881995 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44912 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44912 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44912 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44912 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44912 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44912 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596373 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 596373 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 596373 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 596373 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 596373 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 596373 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7067932496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7067932496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7067932496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7067932496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7067932496 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7067932496 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2836500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2836500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2836500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 2836500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071923 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071923 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071923 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071923 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071923 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071923 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11851.698329 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11851.698329 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11851.698329 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11851.698329 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11851.698329 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11851.698329 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071072 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071072 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071072 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071072 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071072 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071072 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11851.529992 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11851.529992 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11851.529992 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11851.529992 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11851.529992 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11851.529992 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # 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miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133406 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.133406 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15278.371871 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15278.371871 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39392.953453 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 39392.953453 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9307.149908 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9307.149908 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5388.527742 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5388.527742 # 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number of replacements +system.cpu1.dcache.tagsinuse 474.680181 # Cycle average of tags in use +system.cpu1.dcache.total_refs 12675453 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 360873 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.124415 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70362031000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 474.680181 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.927110 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.927110 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8307994 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8307994 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4138933 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4138933 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97647 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 97647 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94867 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 94867 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12446927 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12446927 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12446927 # number of overall hits +system.cpu1.dcache.overall_hits::total 12446927 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 399316 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 399316 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1556536 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1556536 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13951 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13951 # 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number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53940000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53940000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 67495693493 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 67495693493 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 67495693493 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 67495693493 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8707310 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8707310 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5695469 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5695469 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111598 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111598 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105484 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105484 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14402779 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14402779 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14402779 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14402779 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045860 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045860 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273294 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273294 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125011 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125011 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100650 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100650 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135797 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135797 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135797 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135797 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15267.056667 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15267.056667 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39446.124916 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39446.124916 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9271.772633 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9271.772633 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5080.531224 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5080.531224 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34509.611920 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34509.611920 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34509.611920 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34509.611920 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 27560 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 11546 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3309 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 159 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.328800 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 72.616352 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 327755 # number of writebacks -system.cpu1.dcache.writebacks::total 327755 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 173193 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 173193 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1400907 # 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number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35738645182 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35738645182 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 205036718182 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 205036718182 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025935 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025935 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027943 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027943 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111484 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111484 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101096 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101096 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026729 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026729 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026729 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026729 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12546.063239 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12546.063239 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31562.085029 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31562.085029 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7107.572068 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7107.572068 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3390.995695 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3390.995695 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20407.968695 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20407.968695 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20407.968695 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20407.968695 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324541 # number of writebacks +system.cpu1.dcache.writebacks::total 324541 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171136 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 171136 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1394941 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1394941 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1433 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1433 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566077 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1566077 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566077 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1566077 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228180 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228180 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161595 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161595 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12518 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12518 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10611 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10611 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389775 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389775 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389775 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389775 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2858069500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2858069500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5115737712 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5115737712 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88636500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88636500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32718000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32718000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7973807212 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7973807212 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7973807212 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7973807212 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990097000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990097000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35704290190 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35704290190 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204694387190 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204694387190 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026206 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026206 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028373 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028373 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112170 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112170 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100593 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100593 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027062 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027062 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027062 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027062 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12525.503988 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12525.503988 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31657.772283 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31657.772283 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7080.723758 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7080.723758 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3083.404015 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3083.404015 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20457.461900 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20457.461900 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20457.461900 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20457.461900 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1838,18 +1804,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1245278858614 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1245278858614 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1245278858614 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1245278858614 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540179772418 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 540179772418 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540179772418 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 540179772418 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 42369 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41712 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 50346 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48858 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |