summaryrefslogtreecommitdiff
path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
diff options
context:
space:
mode:
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr')
-rwxr-xr-xtests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr2
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
index ab972f12d..7a0ceb162 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
@@ -8,6 +8,8 @@ warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
+warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
+warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0]
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented