diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 95f1cb47c..5c309f807 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.832863 # Nu sim_ticks 2832862976500 # Number of ticks simulated final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 159277 # Simulator instruction rate (inst/s) -host_op_rate 193189 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3989457396 # Simulator tick rate (ticks/s) -host_mem_usage 626716 # Number of bytes of host memory used -host_seconds 710.09 # Real time elapsed on the host +host_inst_rate 93807 # Simulator instruction rate (inst/s) +host_op_rate 113780 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2349621266 # Simulator tick rate (ticks/s) +host_mem_usage 586720 # Number of bytes of host memory used +host_seconds 1205.67 # Real time elapsed on the host sim_insts 113100501 # Number of instructions simulated sim_ops 137180951 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -444,7 +444,7 @@ system.cpu.dtb.flush_tlb 64 # Nu system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 4253 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 362 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -546,7 +546,7 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3089 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3025 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |