diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt | 2121 |
1 files changed, 1120 insertions, 1001 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index b41e9656d..8914a4f8a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.827042 # Number of seconds simulated -sim_ticks 2827042159500 # Number of ticks simulated -final_tick 2827042159500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.827025 # Number of seconds simulated +sim_ticks 2827025397500 # Number of ticks simulated +final_tick 2827025397500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100972 # Simulator instruction rate (inst/s) -host_op_rate 122474 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2522254422 # Simulator tick rate (ticks/s) -host_mem_usage 564960 # Number of bytes of host memory used -host_seconds 1120.84 # Real time elapsed on the host -sim_insts 113173742 # Number of instructions simulated -sim_ops 137273263 # Number of ops (including micro ops) simulated +host_inst_rate 96738 # Simulator instruction rate (inst/s) +host_op_rate 117339 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2415768223 # Simulator tick rate (ticks/s) +host_mem_usage 619580 # Number of bytes of host memory used +host_seconds 1170.24 # Real time elapsed on the host +sim_insts 113206948 # Number of instructions simulated +sim_ops 137314363 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1324048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9496932 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1324240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9499748 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10823604 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1324048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1324048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8116352 # Number of bytes written to this memory +system.physmem.bytes_read::total 10826676 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1324240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1324240 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8118016 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8133876 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8135540 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 20 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22933 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 148909 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 148953 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 171883 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126818 # Number of write requests responded to by this memory +system.physmem.num_reads::total 171931 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126844 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 131199 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 131225 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 453 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 468351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3359317 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 468422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3360333 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3828597 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 468351 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 468351 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2870970 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3829706 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 468422 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 468422 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2871575 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2877168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2870970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2877774 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2871575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 453 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 468351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3365516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 468422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3366532 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6705765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 171884 # Number of read requests accepted -system.physmem.writeReqs 167423 # Number of write requests accepted -system.physmem.readBursts 171884 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 167423 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10992576 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue -system.physmem.bytesWritten 10315392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10823668 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10452212 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6228 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4543 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10965 # Per bank write bursts -system.physmem.perBankRdBursts::1 10116 # Per bank write bursts -system.physmem.perBankRdBursts::2 11197 # Per bank write bursts -system.physmem.perBankRdBursts::3 11389 # Per bank write bursts -system.physmem.perBankRdBursts::4 13120 # Per bank write bursts -system.physmem.perBankRdBursts::5 10535 # Per bank write bursts -system.physmem.perBankRdBursts::6 11120 # Per bank write bursts -system.physmem.perBankRdBursts::7 11540 # Per bank write bursts -system.physmem.perBankRdBursts::8 10348 # Per bank write bursts -system.physmem.perBankRdBursts::9 11053 # Per bank write bursts -system.physmem.perBankRdBursts::10 10478 # Per bank write bursts -system.physmem.perBankRdBursts::11 9244 # Per bank write bursts -system.physmem.perBankRdBursts::12 10124 # Per bank write bursts -system.physmem.perBankRdBursts::13 10758 # Per bank write bursts -system.physmem.perBankRdBursts::14 10029 # Per bank write bursts -system.physmem.perBankRdBursts::15 9743 # Per bank write bursts -system.physmem.perBankWrBursts::0 10407 # Per bank write bursts -system.physmem.perBankWrBursts::1 9909 # Per bank write bursts -system.physmem.perBankWrBursts::2 10642 # Per bank write bursts -system.physmem.perBankWrBursts::3 10446 # Per bank write bursts -system.physmem.perBankWrBursts::4 9703 # Per bank write bursts -system.physmem.perBankWrBursts::5 10218 # Per bank write bursts -system.physmem.perBankWrBursts::6 10399 # Per bank write bursts -system.physmem.perBankWrBursts::7 10626 # Per bank write bursts -system.physmem.perBankWrBursts::8 10202 # Per bank write bursts -system.physmem.perBankWrBursts::9 10761 # Per bank write bursts -system.physmem.perBankWrBursts::10 9802 # Per bank write bursts -system.physmem.perBankWrBursts::11 9030 # Per bank write bursts -system.physmem.perBankWrBursts::12 9755 # Per bank write bursts -system.physmem.perBankWrBursts::13 10443 # Per bank write bursts -system.physmem.perBankWrBursts::14 9720 # Per bank write bursts -system.physmem.perBankWrBursts::15 9115 # Per bank write bursts +system.physmem.bw_total::total 6707480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 171932 # Number of read requests accepted +system.physmem.writeReqs 167449 # Number of write requests accepted +system.physmem.readBursts 171932 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 167449 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10995584 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue +system.physmem.bytesWritten 10340800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10826740 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10453876 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5856 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4542 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11320 # Per bank write bursts +system.physmem.perBankRdBursts::1 10283 # Per bank write bursts +system.physmem.perBankRdBursts::2 11137 # Per bank write bursts +system.physmem.perBankRdBursts::3 11363 # Per bank write bursts +system.physmem.perBankRdBursts::4 13028 # Per bank write bursts +system.physmem.perBankRdBursts::5 10237 # Per bank write bursts +system.physmem.perBankRdBursts::6 10954 # Per bank write bursts +system.physmem.perBankRdBursts::7 11381 # Per bank write bursts +system.physmem.perBankRdBursts::8 10407 # Per bank write bursts +system.physmem.perBankRdBursts::9 11232 # Per bank write bursts +system.physmem.perBankRdBursts::10 10729 # Per bank write bursts +system.physmem.perBankRdBursts::11 9386 # Per bank write bursts +system.physmem.perBankRdBursts::12 9853 # Per bank write bursts +system.physmem.perBankRdBursts::13 10909 # Per bank write bursts +system.physmem.perBankRdBursts::14 9951 # Per bank write bursts +system.physmem.perBankRdBursts::15 9636 # Per bank write bursts +system.physmem.perBankWrBursts::0 10810 # Per bank write bursts +system.physmem.perBankWrBursts::1 10132 # Per bank write bursts +system.physmem.perBankWrBursts::2 10502 # Per bank write bursts +system.physmem.perBankWrBursts::3 10558 # Per bank write bursts +system.physmem.perBankWrBursts::4 9654 # Per bank write bursts +system.physmem.perBankWrBursts::5 9978 # Per bank write bursts +system.physmem.perBankWrBursts::6 10358 # Per bank write bursts +system.physmem.perBankWrBursts::7 10535 # Per bank write bursts +system.physmem.perBankWrBursts::8 10309 # Per bank write bursts +system.physmem.perBankWrBursts::9 10935 # Per bank write bursts +system.physmem.perBankWrBursts::10 10009 # Per bank write bursts +system.physmem.perBankWrBursts::11 9154 # Per bank write bursts +system.physmem.perBankWrBursts::12 9556 # Per bank write bursts +system.physmem.perBankWrBursts::13 10555 # Per bank write bursts +system.physmem.perBankWrBursts::14 9521 # Per bank write bursts +system.physmem.perBankWrBursts::15 9009 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2827041948500 # Total gap between requests +system.physmem.totGap 2827025186500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 2993 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 168336 # Read request sizes (log2) +system.physmem.readPktSize::6 168384 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 163042 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151765 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 163068 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151696 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -159,137 +159,134 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64399 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 330.873212 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 190.977516 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.816153 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23539 36.55% 36.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14785 22.96% 59.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6319 9.81% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3687 5.73% 75.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2636 4.09% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1562 2.43% 81.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1140 1.77% 83.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1107 1.72% 85.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9624 14.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64399 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6814 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.206340 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 540.339482 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6812 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 64517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 330.708495 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 190.901316 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 347.828879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23555 36.51% 36.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14820 22.97% 59.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6443 9.99% 69.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3645 5.65% 75.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2568 3.98% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1574 2.44% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1131 1.75% 83.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1187 1.84% 85.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9594 14.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64517 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6820 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.190762 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 540.107379 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6818 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6814 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6814 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.653948 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.805353 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.459775 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5702 83.68% 83.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 39 0.57% 84.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 26 0.38% 84.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 231 3.39% 88.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 131 1.92% 89.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 61 0.90% 90.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 35 0.51% 91.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 27 0.40% 91.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 123 1.81% 93.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 13 0.19% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 19 0.28% 94.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 11 0.16% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 31 0.45% 94.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 13 0.19% 94.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 13 0.19% 95.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 26 0.38% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 61 0.90% 96.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 10 0.15% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 9 0.13% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 11 0.16% 96.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 89 1.31% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 7 0.10% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 18 0.26% 98.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 4 0.06% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 5 0.07% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.06% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 26 0.38% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 4 0.06% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 4 0.06% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.07% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 11 0.16% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 11 0.16% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.04% 99.60% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6820 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6820 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.691349 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.848646 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.179127 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5682 83.31% 83.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 64 0.94% 84.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 25 0.37% 84.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 208 3.05% 87.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 139 2.04% 89.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 55 0.81% 90.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 46 0.67% 91.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 37 0.54% 91.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 121 1.77% 93.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 14 0.21% 93.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 20 0.29% 94.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 15 0.22% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 20 0.29% 94.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 19 0.28% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 10 0.15% 94.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 21 0.31% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 67 0.98% 96.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 14 0.21% 96.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 7 0.10% 96.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 14 0.21% 96.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 85 1.25% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.04% 98.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 5 0.07% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 15 0.22% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.04% 98.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 16 0.23% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 5 0.07% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 25 0.37% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 8 0.12% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.03% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 7 0.10% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 12 0.18% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 5 0.07% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.60% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.04% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.04% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.04% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.03% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.04% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 3 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 9 0.13% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 4 0.06% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 2 0.03% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::232-235 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6814 # Writes before turning the bus around for reads -system.physmem.totQLat 2084525750 # Total ticks spent queuing -system.physmem.totMemAccLat 5305007000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 858795000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12136.34 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 6820 # Writes before turning the bus around for reads +system.physmem.totQLat 2011805750 # Total ticks spent queuing +system.physmem.totMemAccLat 5233168250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 859030000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11709.75 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30886.34 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30459.75 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.65 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 3.66 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.83 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.70 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s @@ -297,36 +294,41 @@ system.physmem.busUtil 0.06 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.50 # Average write queue length when enqueuing -system.physmem.readRowHits 141721 # Number of row buffer hits during reads -system.physmem.writeRowHits 126816 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.67 # Row buffer hit rate for writes -system.physmem.avgGap 8331811.45 # Average gap between requests -system.physmem.pageHitRate 80.65 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2694668588500 # Time in different power states -system.physmem.memoryStateTime::REF 94401060000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37972497000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 254499840 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 232356600 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 138864000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 126781875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 701859600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 637852800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 533628000 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 510805440 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 184648473360 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 184648473360 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 80377758270 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 79142156730 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1625717004000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1626800865000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1892372087070 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1892099291805 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.382923 # Core power per rank (mW) -system.physmem.averagePower::1 669.286428 # Core power per rank (mW) +system.physmem.avgWrQLen 27.20 # Average write queue length when enqueuing +system.physmem.readRowHits 141825 # Number of row buffer hits during reads +system.physmem.writeRowHits 127038 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.62 # Row buffer hit rate for writes +system.physmem.avgGap 8329945.36 # Average gap between requests +system.physmem.pageHitRate 80.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 254462040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 138843375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 699683400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 534774960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 80304363360 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625772042000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1892351625375 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.379373 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2704495478000 # Time in different power states +system.physmem_0.memoryStateTime::REF 94400540000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 28128105750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 233286480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 127289250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 640395600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 512231040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79168609575 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626768325500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1892097593685 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.289511 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2706163008250 # Time in different power states +system.physmem_1.memoryStateTime::REF 94400540000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 26461835250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory @@ -345,16 +347,24 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46933448 # Number of BP lookups -system.cpu.branchPred.condPredicted 24039449 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1232882 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29542848 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21360620 # Number of BTB hits +system.cpu.branchPred.lookups 46965884 # Number of BP lookups +system.cpu.branchPred.condPredicted 24051171 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1232760 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29570934 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21375571 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.303862 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11754095 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33720 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.285749 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11765533 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33715 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -376,27 +386,89 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 69937 # Table walker walks requested +system.cpu.dtb.walker.walksShort 69937 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29497 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22737 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 17703 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 52234 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 334.025730 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 1986.195905 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 50803 97.26% 97.26% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::4096-8191 591 1.13% 98.39% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 521 1.00% 99.39% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::12288-16383 84 0.16% 99.55% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-20479 102 0.20% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::20480-24575 114 0.22% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-28671 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::28672-32767 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-36863 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::36864-40959 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::45056-49151 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 52234 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 16206 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 9699.278169 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 7212.227669 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7791.284796 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 16044 99.00% 99.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 159 0.98% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-98303 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 16206 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 116899920224 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.624364 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.489854 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 116858057224 99.96% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 29153000 0.02% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 6015500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 4000000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 926000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 658000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 874000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 231500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 5000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 116899920224 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6318 82.14% 82.14% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1374 17.86% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7692 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 69937 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 69937 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7692 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7692 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 77629 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25465003 # DTB read hits -system.cpu.dtb.read_misses 60438 # DTB read misses -system.cpu.dtb.write_hits 19916425 # DTB write hits -system.cpu.dtb.write_misses 9382 # DTB write misses +system.cpu.dtb.read_hits 25472400 # DTB read hits +system.cpu.dtb.read_misses 60528 # DTB read misses +system.cpu.dtb.write_hits 19920178 # DTB write hits +system.cpu.dtb.write_misses 9409 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4324 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 344 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2309 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4326 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 345 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2281 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1303 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25525441 # DTB read accesses -system.cpu.dtb.write_accesses 19925807 # DTB write accesses +system.cpu.dtb.perms_faults 1305 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25532928 # DTB read accesses +system.cpu.dtb.write_accesses 19929587 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45381428 # DTB hits -system.cpu.dtb.misses 69820 # DTB misses -system.cpu.dtb.accesses 45451248 # DTB accesses +system.cpu.dtb.hits 45392578 # DTB hits +system.cpu.dtb.misses 69937 # DTB misses +system.cpu.dtb.accesses 45462515 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -418,8 +490,55 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 66294026 # ITB inst hits -system.cpu.itb.inst_misses 11939 # ITB inst misses +system.cpu.itb.walker.walks 11957 # Table walker walks requested +system.cpu.itb.walker.walksShort 11957 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 4035 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7756 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 166 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11791 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 476.931558 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2426.619854 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-8191 11573 98.15% 98.15% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-16383 164 1.39% 99.54% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-24575 47 0.40% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-32767 2 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 11791 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3494 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 10252.862049 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 7229.260491 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7922.738250 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1610 46.08% 46.08% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 989 28.31% 74.38% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 844 24.16% 98.54% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::24576-32767 31 0.89% 99.43% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-40959 18 0.52% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::73728-81919 2 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3494 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 22130705712 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.982067 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.132922 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 397376500 1.80% 1.80% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 21732921212 98.20% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 337000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 44500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 26500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 22130705712 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 3007 90.35% 90.35% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 321 9.65% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3328 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11957 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 11957 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3328 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3328 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 15285 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66242388 # ITB inst hits +system.cpu.itb.inst_misses 11957 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -435,91 +554,91 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66305965 # ITB inst accesses -system.cpu.itb.hits 66294026 # DTB hits -system.cpu.itb.misses 11939 # DTB misses -system.cpu.itb.accesses 66305965 # DTB accesses -system.cpu.numCycles 260580731 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66254345 # ITB inst accesses +system.cpu.itb.hits 66242388 # DTB hits +system.cpu.itb.misses 11957 # DTB misses +system.cpu.itb.accesses 66254345 # DTB accesses +system.cpu.numCycles 260505842 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104873538 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184739295 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46933448 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33114715 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 145635789 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6158762 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 168952 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8750 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 338958 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 503648 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.icacheStallCycles 104910536 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184564437 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46965884 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33141104 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 145523967 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6162316 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 169075 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 8609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 338609 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 504254 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 106 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66294321 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1128854 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4994 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 254609122 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.884999 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.237560 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 66242687 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1039458 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5021 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 254536314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.884658 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.237297 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 155317216 61.00% 61.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29235163 11.48% 72.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14076452 5.53% 78.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55980291 21.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 155286067 61.01% 61.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29244712 11.49% 72.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14083759 5.53% 78.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55921776 21.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 254609122 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.180111 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.708952 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78085586 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105431733 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64660886 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3829260 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2601657 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3422216 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 485978 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157447803 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3691485 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2601657 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83925210 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10033565 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74541150 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62655394 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 20852146 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146807646 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 950357 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 437123 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 62766 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 16447 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 18089237 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150492315 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678770164 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164434086 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 254536314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.180287 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.708485 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78110854 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105310937 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64681837 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3829276 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2603410 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3422230 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 485999 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157498066 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3692054 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2603410 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83952319 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10018441 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74493030 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62674544 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 20794570 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146849554 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 949739 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 436543 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 62719 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 16684 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 18031839 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150536032 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678970726 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164476932 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 10967 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141835122 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8657190 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2845976 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2649716 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13845319 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26411369 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21300781 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1686386 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2189128 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143541895 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2120957 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143337283 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 269192 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6251828 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14653372 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125306 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 254609122 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.562970 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.882443 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 141878160 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8657869 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2847901 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2651576 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13851577 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26418729 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21304216 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1685996 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2099557 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143583180 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2120928 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143378875 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 268933 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6250249 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14652310 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125244 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 254536314 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.563294 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.882192 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 166344309 65.33% 65.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45117660 17.72% 83.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32035421 12.58% 95.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10298180 4.04% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 813519 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 166156595 65.28% 65.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45308451 17.80% 83.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31957183 12.56% 95.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10300315 4.05% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 813737 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -527,9 +646,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 254609122 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 254536314 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7370311 32.63% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7371563 32.63% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available @@ -558,13 +677,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5632420 24.93% 57.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9586874 42.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5632608 24.93% 57.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9585974 42.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 96009315 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113982 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 96039761 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113980 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -592,96 +711,96 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 8594 0.01% 67.07% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26194290 18.27% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21008765 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26201849 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21012354 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143337283 # Type of FU issued -system.cpu.iq.rate 0.550069 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22589637 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157598 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 564106761 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 151919680 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140223084 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35756 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 143378875 # Type of FU issued +system.cpu.iq.rate 0.550386 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22590177 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157556 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 564117476 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 151959359 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140262857 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35698 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 13217 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165901147 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23436 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 324147 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 165943337 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23378 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 323934 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1490308 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1489912 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18251 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 701176 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18252 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 700651 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 88081 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6304 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 87937 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6369 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2601657 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 950737 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 291154 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145863821 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2603410 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 946501 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 282988 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145905073 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26411369 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21300781 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1096076 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17895 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 256263 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18251 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317548 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471732 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 789280 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142394540 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25793108 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 873030 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26418729 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21304216 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1096059 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17893 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 248042 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18252 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317390 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471834 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 789224 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142436087 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25800504 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 872964 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 200969 # number of nop insts executed -system.cpu.iew.exec_refs 46672402 # number of memory reference insts executed -system.cpu.iew.exec_branches 26533167 # Number of branches executed -system.cpu.iew.exec_stores 20879294 # Number of stores executed -system.cpu.iew.exec_rate 0.546451 # Inst execution rate -system.cpu.iew.wb_sent 142007306 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140234515 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63283849 # num instructions producing a value -system.cpu.iew.wb_consumers 95860591 # num instructions consuming a value +system.cpu.iew.exec_nop 200965 # number of nop insts executed +system.cpu.iew.exec_refs 46683536 # number of memory reference insts executed +system.cpu.iew.exec_branches 26544582 # Number of branches executed +system.cpu.iew.exec_stores 20883032 # Number of stores executed +system.cpu.iew.exec_rate 0.546767 # Inst execution rate +system.cpu.iew.wb_sent 142049013 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140274288 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63301991 # num instructions producing a value +system.cpu.iew.wb_consumers 95888204 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.538161 # insts written-back per cycle +system.cpu.iew.wb_rate 0.538469 # insts written-back per cycle system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7591533 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995651 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755158 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 251674404 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.546055 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.146686 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7591203 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995684 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755012 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 251600015 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.546380 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.145616 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 178222235 70.81% 70.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43294364 17.20% 88.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15476639 6.15% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4357303 1.73% 95.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6369018 2.53% 98.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1679088 0.67% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 777340 0.31% 99.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 414271 0.16% 99.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1084146 0.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 178032532 70.76% 70.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43398742 17.25% 88.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15483585 6.15% 94.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4358404 1.73% 95.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6462138 2.57% 98.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1589340 0.63% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 777430 0.31% 99.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 414440 0.16% 99.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1083404 0.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 251674404 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113328647 # Number of instructions committed -system.cpu.commit.committedOps 137428168 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 251600015 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113361853 # Number of instructions committed +system.cpu.commit.committedOps 137469268 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45520666 # Number of memory references committed -system.cpu.commit.loads 24921061 # Number of loads committed -system.cpu.commit.membars 814701 # Number of memory barriers committed -system.cpu.commit.branches 26049415 # Number of branches committed +system.cpu.commit.refs 45532382 # Number of memory references committed +system.cpu.commit.loads 24928817 # Number of loads committed +system.cpu.commit.membars 814713 # Number of memory barriers committed +system.cpu.commit.branches 26060941 # Number of branches committed system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120247607 # Number of committed integer instructions. -system.cpu.commit.function_calls 4892692 # Number of function calls committed. +system.cpu.commit.int_insts 120284813 # Number of committed integer instructions. +system.cpu.commit.function_calls 4896517 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91785919 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91815303 66.79% 66.79% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction @@ -710,210 +829,210 @@ system.cpu.commit.op_class_0::SimdFloatMisc 8593 0.01% 66.88% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24921061 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20599605 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24928817 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20603565 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137428168 # Class of committed instruction -system.cpu.commit.bw_lim_events 1084146 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 137469268 # Class of committed instruction +system.cpu.commit.bw_lim_events 1083404 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 373381031 # The number of ROB reads -system.cpu.rob.rob_writes 292971684 # The number of ROB writes -system.cpu.timesIdled 892930 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5971609 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5393503589 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113173742 # Number of Instructions Simulated -system.cpu.committedOps 137273263 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.302484 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.302484 # CPI: Total CPI of All Threads -system.cpu.ipc 0.434314 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.434314 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155831391 # number of integer regfile reads -system.cpu.int_regfile_writes 88636024 # number of integer regfile writes +system.cpu.rob.rob_reads 373323554 # The number of ROB reads +system.cpu.rob.rob_writes 293054802 # The number of ROB writes +system.cpu.timesIdled 892910 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5969528 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5393544954 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113206948 # Number of Instructions Simulated +system.cpu.committedOps 137314363 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.301147 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.301147 # CPI: Total CPI of All Threads +system.cpu.ipc 0.434566 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.434566 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155872747 # number of integer regfile reads +system.cpu.int_regfile_writes 88664446 # number of integer regfile writes system.cpu.fp_regfile_reads 9607 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 503020695 # number of cc regfile reads -system.cpu.cc_regfile_writes 53185327 # number of cc regfile writes -system.cpu.misc_regfile_reads 444130548 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521619 # number of misc regfile writes -system.cpu.dcache.tags.replacements 837995 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.958491 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40159583 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 838507 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.894154 # Average number of references to valid blocks. +system.cpu.cc_regfile_reads 503168366 # number of cc regfile reads +system.cpu.cc_regfile_writes 53197006 # number of cc regfile writes +system.cpu.misc_regfile_reads 443775049 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521649 # number of misc regfile writes +system.cpu.dcache.tags.replacements 837844 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.958421 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40169385 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 838356 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.914472 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.958491 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.958421 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179379502 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179379502 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23322864 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23322864 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15584894 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15584894 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 346636 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 346636 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 442009 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 442009 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460310 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460310 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38907758 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38907758 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39254394 # number of overall hits -system.cpu.dcache.overall_hits::total 39254394 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 700618 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 700618 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3574058 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3574058 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177109 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177109 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26740 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26740 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4274676 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4274676 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4451785 # number of overall misses -system.cpu.dcache.overall_misses::total 4451785 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9939142148 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9939142148 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 135148977049 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 135148977049 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 356483749 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 356483749 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 189500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 189500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 145088119197 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 145088119197 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 145088119197 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 145088119197 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24023482 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24023482 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19158952 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19158952 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523745 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523745 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468749 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 468749 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460315 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460315 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43182434 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43182434 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43706179 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43706179 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029164 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029164 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186548 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.186548 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338159 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.338159 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057045 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057045 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.098991 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.098991 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.101857 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.101857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14186.250065 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14186.250065 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37813.873488 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37813.873488 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13331.479020 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13331.479020 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 37900 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 37900 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33941.313727 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33941.313727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32590.998711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32590.998711 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 505021 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 179425849 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179425849 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23330547 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23330547 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15587007 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15587007 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 346674 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 346674 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441974 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441974 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460321 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460321 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38917554 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38917554 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39264228 # number of overall hits +system.cpu.dcache.overall_hits::total 39264228 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 700623 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 700623 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3575875 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3575875 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 177079 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 177079 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 26763 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 26763 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 4276498 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4276498 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4453577 # number of overall misses +system.cpu.dcache.overall_misses::total 4453577 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9909110648 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9909110648 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 134775393563 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 134775393563 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 355748499 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 355748499 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 176500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 176500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 144684504211 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 144684504211 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 144684504211 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 144684504211 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24031170 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24031170 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19162882 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19162882 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523753 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523753 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468737 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 468737 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460325 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460325 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43194052 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43194052 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43717805 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43717805 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029155 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029155 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186604 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.186604 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338096 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.338096 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057096 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057096 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.099007 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.099007 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.101871 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.101871 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14143.284831 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14143.284831 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37690.185916 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37690.185916 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13292.549378 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13292.549378 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 44125 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 44125 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33832.473255 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33832.473255 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32487.257818 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32487.257818 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 491325 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6926 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6982 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.916691 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 70.370238 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 695574 # number of writebacks -system.cpu.dcache.writebacks::total 695574 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286297 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 286297 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274736 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3274736 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18417 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 18417 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3561033 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3561033 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3561033 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3561033 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414321 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 414321 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299322 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299322 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119334 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 119334 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8323 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8323 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 713643 # 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number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110246000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 179500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 179500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17247532374 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17247532374 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18723992625 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18723992625 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792718250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792718250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440457453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440457453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233175703 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233175703 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017247 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017247 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015623 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015623 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227848 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227848 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017756 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017756 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016526 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016526 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019059 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019059 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12933.664152 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12933.664152 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39719.244523 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39719.244523 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12372.502816 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12372.502816 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.944972 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.944972 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 35900 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 35900 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24168.291953 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24168.291953 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22478.402915 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22478.402915 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 695426 # number of writebacks +system.cpu.dcache.writebacks::total 695426 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286545 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 286545 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3276416 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3276416 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18452 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18452 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3562961 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3562961 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3562961 # 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number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 109426500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17177248878 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17177248878 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18652683879 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18652683879 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792686500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792686500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440468453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440468453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233154953 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233154953 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017231 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017231 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015627 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227794 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227794 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017731 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017731 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016519 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016519 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019050 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019050 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12923.957358 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12923.957358 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39490.289031 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39490.289031 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.605768 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.605768 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13166.466129 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13166.466129 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42125 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42125 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24073.382148 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24073.382148 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22396.344913 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22396.344913 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -921,265 +1040,265 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1894210 # number of replacements -system.cpu.icache.tags.tagsinuse 511.373832 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64309690 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1894722 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.941491 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1894041 # number of replacements +system.cpu.icache.tags.tagsinuse 511.373863 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64258114 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1894553 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.917296 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.373832 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.373863 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998777 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 217 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68186062 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68186062 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64309690 # 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miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.029893 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.029893 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.029893 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.029893 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.029893 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13509.119197 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13509.119197 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13509.119197 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13509.119197 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13509.119197 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13509.119197 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1592 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 68134254 # Number of tag accesses +system.cpu.icache.tags.data_accesses 68134254 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 64258114 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64258114 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64258114 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64258114 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64258114 # number of overall hits +system.cpu.icache.overall_hits::total 64258114 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1981572 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1981572 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1981572 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1981572 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1981572 # number of overall misses +system.cpu.icache.overall_misses::total 1981572 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26765848354 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26765848354 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26765848354 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26765848354 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26765848354 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26765848354 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66239686 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66239686 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66239686 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13507.381187 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13507.381187 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13507.381187 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13507.381187 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2017 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 104 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 103 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.307692 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.582524 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157877000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494814250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652691250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000352 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000598 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024922 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013377 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987004 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987004 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461548 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461548 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000352 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000598 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179407 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060884 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000352 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000598 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179407 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060884 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1250973750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9058246549 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10311368299 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157876500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387443500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545320000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107345000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107345000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157876500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494788500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652665000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000372 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000597 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010528 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024905 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013376 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988468 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988468 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461519 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461519 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000372 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000597 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010528 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179479 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060908 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000372 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000597 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010528 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179479 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060908 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62768.277090 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67694.386848 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64757.304395 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10080.188003 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10080.188003 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62718.026171 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67384.953292 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64612.832850 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10097.791834 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10097.791834 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59987.377561 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59987.377561 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59491.315037 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59491.315037 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62768.277090 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60679.193814 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60924.332973 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62718.026171 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60198.884503 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60496.748505 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62768.277090 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60679.193814 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60924.332973 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62718.026171 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60198.884503 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60496.748505 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1300,54 +1419,54 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2565344 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2565278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2565017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2564966 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 695574 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 695426 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296684 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296684 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795456 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495832 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31236 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128794 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6451318 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121309456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98375777 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215684 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 219947773 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 65392 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3562462 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.010230 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.100625 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 2775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2779 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296811 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296811 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795114 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495409 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31281 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128693 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6450497 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121298704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98357729 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 219918257 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 65703 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3562118 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.010231 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.100630 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3526018 98.98% 98.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3525674 98.98% 98.98% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 36444 1.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3562462 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2503396529 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3562118 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2503082512 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 256500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2849706150 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2849465378 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1334755109 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1334578357 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19527240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19552240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74897454 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74992959 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30181 # Transaction distribution system.iobus.trans_dist::ReadResp 30181 # Transaction distribution @@ -1444,23 +1563,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347066130 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347066125 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36776516 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36776514 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.000725 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.000670 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 251942535000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.000725 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062545 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062545 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 251936772000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.000670 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062542 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062542 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1474,14 +1593,14 @@ system.iocache.demand_misses::realview.ide 220 # system.iocache.demand_misses::total 220 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 220 # number of overall misses system.iocache.overall_misses::total 220 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 26411377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 26411377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9622478237 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9622478237 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 26411377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 26411377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 26411377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 26411377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 26427377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 26427377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617153234 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9617153234 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 26427377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 26427377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 26427377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 26427377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1498,19 +1617,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 120051.713636 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120051.713636 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265638.202214 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265638.202214 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120051.713636 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120051.713636 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120051.713636 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120051.713636 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56749 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 120124.440909 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120124.440909 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265491.200144 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 265491.200144 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120124.440909 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120124.440909 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 56312 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7275 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7225 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.800550 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.794048 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1524,14 +1643,14 @@ system.iocache.demand_mshr_misses::realview.ide 220 system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 14970377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 14970377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7738798269 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7738798269 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 14970377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 14970377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 14970377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 14970377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 14986377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 14986377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7733477262 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7733477262 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 14986377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 14986377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 14986377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 14986377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1540,66 +1659,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68047.168182 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68047.168182 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213637.319705 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213637.319705 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68047.168182 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68047.168182 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68047.168182 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68047.168182 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68119.895455 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68119.895455 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213490.427948 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213490.427948 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 67832 # Transaction distribution -system.membus.trans_dist::ReadResp 67831 # Transaction distribution +system.membus.trans_dist::ReadReq 67820 # Transaction distribution +system.membus.trans_dist::ReadResp 67819 # Transaction distribution system.membus.trans_dist::WriteReq 27608 # Transaction distribution system.membus.trans_dist::WriteResp 27608 # Transaction distribution -system.membus.trans_dist::Writeback 126818 # Transaction distribution +system.membus.trans_dist::Writeback 126844 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4542 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution -system.membus.trans_dist::ReadExReq 135125 # Transaction distribution -system.membus.trans_dist::ReadExResp 135125 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4544 # Transaction distribution +system.membus.trans_dist::ReadExReq 135185 # Transaction distribution +system.membus.trans_dist::ReadExResp 135185 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452492 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560128 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452612 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560248 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108873 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108873 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 669001 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 669121 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16640360 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16803825 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16645096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16808561 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21439281 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21444017 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 484 # Total snoops (count) -system.membus.snoop_fanout::samples 336405 # Request fanout histogram +system.membus.snoop_fanout::samples 336478 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 336405 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 336478 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 336405 # Request fanout histogram -system.membus.reqLayer0.occupancy 94190000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 336478 # Request fanout histogram +system.membus.reqLayer0.occupancy 94194499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1698000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1701500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1683660499 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1683962999 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1677935457 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1678430208 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38220484 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38218486 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |