diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt | 745 |
1 files changed, 386 insertions, 359 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index b494abcbb..1df010cb5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.503581 # Nu sim_ticks 2503580880500 # Number of ticks simulated final_tick 2503580880500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56444 # Simulator instruction rate (inst/s) -host_tick_rate 1840259079 # Simulator tick rate (ticks/s) -host_mem_usage 413160 # Number of bytes of host memory used -host_seconds 1360.45 # Real time elapsed on the host -sim_insts 76789886 # Number of instructions simulated +host_inst_rate 80550 # Simulator instruction rate (inst/s) +host_op_rate 104045 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3392180683 # Simulator tick rate (ticks/s) +host_mem_usage 382816 # Number of bytes of host memory used +host_seconds 738.04 # Real time elapsed on the host +sim_insts 59449329 # Number of instructions simulated +sim_ops 76789886 # Number of ops (including micro ops) simulated system.nvmem.bytes_read 64 # Number of bytes read from this memory system.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -34,91 +36,132 @@ system.l2c.total_refs 1795685 # To system.l2c.sampled_refs 150314 # Sample count of references to valid blocks. system.l2c.avg_refs 11.946226 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11478.014025 # Average occupied blocks per context -system.l2c.occ_blocks::1 14356.915365 # Average occupied blocks per context -system.l2c.occ_percent::0 0.175141 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.219069 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1349535 # number of ReadReq hits -system.l2c.ReadReq_hits::1 153277 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 14304.535648 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 48.618373 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 3.761343 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 6047.704729 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 5430.309296 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.218270 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000742 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000057 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.092281 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.082860 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.394210 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 143695 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 9582 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 973305 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 376230 # number of ReadReq hits system.l2c.ReadReq_hits::total 1502812 # number of ReadReq hits -system.l2c.Writeback_hits::0 630148 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 630148 # number of Writeback hits system.l2c.Writeback_hits::total 630148 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 47 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu.data 47 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 47 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 17 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 17 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 17 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 105970 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu.data 105970 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 105970 # number of ReadExReq hits -system.l2c.demand_hits::0 1455505 # number of demand (read+write) hits -system.l2c.demand_hits::1 153277 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.dtb.walker 143695 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 9582 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 973305 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 482200 # number of demand (read+write) hits system.l2c.demand_hits::total 1608782 # number of demand (read+write) hits -system.l2c.overall_hits::0 1455505 # number of overall hits -system.l2c.overall_hits::1 153277 # number of overall hits +system.l2c.overall_hits::cpu.dtb.walker 143695 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 9582 # number of overall hits +system.l2c.overall_hits::cpu.inst 973305 # number of overall hits +system.l2c.overall_hits::cpu.data 482200 # number of overall hits system.l2c.overall_hits::total 1608782 # number of overall hits -system.l2c.ReadReq_misses::0 36088 # number of ReadReq misses -system.l2c.ReadReq_misses::1 150 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.dtb.walker 134 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 16 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 17088 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 19000 # number of ReadReq misses system.l2c.ReadReq_misses::total 36238 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3252 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu.data 3252 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 3252 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 4 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu.data 4 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 140397 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 140397 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 140397 # number of ReadExReq misses -system.l2c.demand_misses::0 176485 # number of demand (read+write) misses -system.l2c.demand_misses::1 150 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.dtb.walker 134 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 16 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 17088 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 159397 # number of demand (read+write) misses system.l2c.demand_misses::total 176635 # number of demand (read+write) misses -system.l2c.overall_misses::0 176485 # number of overall misses -system.l2c.overall_misses::1 150 # number of overall misses +system.l2c.overall_misses::cpu.dtb.walker 134 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 16 # number of overall misses +system.l2c.overall_misses::cpu.inst 17088 # number of overall misses +system.l2c.overall_misses::cpu.data 159397 # number of overall misses system.l2c.overall_misses::total 176635 # number of overall misses -system.l2c.ReadReq_miss_latency 1895542500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 1059500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7383005500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 9278548000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 9278548000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 1385623 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 153427 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 7004000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 843500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 894670500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 993024500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1895542500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 1059500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1059500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7383005500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7383005500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 7004000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 843500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 894670500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 8376030000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9278548000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 7004000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 843500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 894670500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 8376030000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9278548000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 143829 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 9598 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 990393 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 395230 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1539050 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 630148 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 630148 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 630148 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 3299 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 3299 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 3299 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 21 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 21 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 21 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 246367 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 246367 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 246367 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 1631990 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 153427 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.dtb.walker 143829 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 9598 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 990393 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 641597 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1785417 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 1631990 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 153427 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 143829 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 9598 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 990393 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 641597 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1785417 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.026045 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000978 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.027022 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.985753 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.190476 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.569869 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.108141 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000978 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.109119 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.108141 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000978 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.109119 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52525.562514 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 12636950 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 12689475.562514 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 325.799508 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52586.632905 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52574.145111 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 61856986.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 61909560.811778 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52574.145111 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 61856986.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 61909560.811778 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000932 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001667 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.017254 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.048073 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.985753 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.190476 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.569869 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000932 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.001667 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.017254 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.248438 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000932 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.001667 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.017254 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.248438 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52268.656716 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52718.750000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52356.653792 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52264.447368 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 325.799508 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52586.632905 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52268.656716 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 52718.750000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52356.653792 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52548.228637 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52268.656716 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 52718.750000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52356.653792 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52548.228637 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -127,55 +170,102 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 102643 # number of writebacks -system.l2c.ReadReq_mshr_hits 94 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 94 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 94 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 36144 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3252 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 4 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 140397 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 176541 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 176541 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1450468000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 131324500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 160000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5639183500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 7089651500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 7089651500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 131770082500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 32364127897 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 164134210397 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.026085 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.235578 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.261663 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.985753 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.190476 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.569869 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.108175 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.150651 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.258827 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.108175 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.150651 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.258827 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40130.256751 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40382.687577 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40165.982891 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40158.668525 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40158.668525 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.writebacks::writebacks 102643 # number of writebacks +system.l2c.writebacks::total 102643 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu.data 80 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu.data 80 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 94 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 134 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 16 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 17074 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 18920 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 36144 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 3252 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3252 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu.data 4 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 140397 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140397 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 134 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 16 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 17074 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 159317 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 176541 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 134 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 16 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 17074 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 159317 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 176541 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 5376000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 651000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 685402500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 759038500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1450468000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 131324500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 131324500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 160000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 160000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5639183500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5639183500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 5376000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 651000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 685402500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 6398222000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 7089651500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 5376000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 651000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 685402500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 6398222000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 7089651500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 4738500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131765344000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131770082500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32364127897 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32364127897 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 4738500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 164129471897 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164134210397 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000932 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017240 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.047871 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985753 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.190476 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569869 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000932 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.017240 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.248313 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000932 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.017240 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.248313 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40687.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40143.053766 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40118.313953 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40382.687577 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40165.982891 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40687.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40143.053766 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40160.321874 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40687.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40143.053766 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40160.321874 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -429,9 +519,9 @@ system.cpu.iew.iewDispNonSpecInsts 1227782 # Nu system.cpu.iew.iewIQFullEvents 84296 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 7341 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 32675 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 852505 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 852504 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 256815 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1109320 # Number of branch mispredicts detected at execute +system.cpu.iew.branchMispredicts 1109319 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 123469909 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 52917262 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 3434775 # Number of squashed instructions skipped in execute @@ -449,7 +539,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 0.209988 # insts written-back per cycle system.cpu.iew.wb_fanout 0.543006 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 76940267 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 59599710 # The number of committed instructions +system.cpu.commit.commitCommittedOps 76940267 # The number of committed instructions system.cpu.commit.commitSquashedInsts 27835988 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1499707 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 978113 # The number of times a branch was mispredicted @@ -470,7 +561,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 151014616 # Number of insts commited each cycle -system.cpu.commit.count 76940267 # Number of instructions committed +system.cpu.commit.committedInsts 59599710 # Number of instructions committed +system.cpu.commit.committedOps 76940267 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 27459843 # Number of memory references committed system.cpu.commit.loads 15680763 # Number of loads committed @@ -486,12 +578,13 @@ system.cpu.rob.rob_writes 214319630 # Th system.cpu.timesIdled 1877181 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 260374175 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.quiesceCycles 4591130340 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 76789886 # Number of Instructions Simulated -system.cpu.committedInsts_total 76789886 # Number of Instructions Simulated -system.cpu.cpi 5.416643 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.416643 # CPI: Total CPI of All Threads -system.cpu.ipc 0.184616 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.184616 # IPC: Total IPC of All Threads +system.cpu.committedInsts 59449329 # Number of Instructions Simulated +system.cpu.committedOps 76789886 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 59449329 # Number of Instructions Simulated +system.cpu.cpi 6.996604 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.996604 # CPI: Total CPI of All Threads +system.cpu.ipc 0.142926 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.142926 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 559798057 # number of integer regfile reads system.cpu.int_regfile_writes 89741069 # number of integer regfile writes system.cpu.fp_regfile_reads 8257 # number of floating regfile reads @@ -504,51 +597,39 @@ system.cpu.icache.total_refs 13035657 # To system.cpu.icache.sampled_refs 991689 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 13.144904 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6445921000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 511.615293 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.999249 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 13035657 # number of ReadReq hits +system.cpu.icache.occ_blocks::cpu.inst 511.615293 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13035657 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 13035657 # number of ReadReq hits -system.cpu.icache.demand_hits::0 13035657 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::cpu.inst 13035657 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 13035657 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 13035657 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::cpu.inst 13035657 # number of overall hits system.cpu.icache.overall_hits::total 13035657 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1079227 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::cpu.inst 1079227 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1079227 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1079227 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::cpu.inst 1079227 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1079227 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1079227 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::cpu.inst 1079227 # number of overall misses system.cpu.icache.overall_misses::total 1079227 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15906225491 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15906225491 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15906225491 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 14114884 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15906225491 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15906225491 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15906225491 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15906225491 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15906225491 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15906225491 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14114884 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 14114884 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 14114884 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::cpu.inst 14114884 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 14114884 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 14114884 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14114884 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 14114884 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.076460 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.076460 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.076460 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14738.535536 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14738.535536 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14738.535536 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.076460 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.076460 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.076460 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14738.535536 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14738.535536 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14738.535536 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 2390996 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 341 # number of cycles access was blocked @@ -557,35 +638,38 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7011.718475 system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 57255 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 87505 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 87505 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 87505 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 991722 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 991722 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 991722 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11850340996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11850340996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11850340996 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency 6359500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency 6359500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.070261 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.070261 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.070261 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11949.256945 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11949.256945 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11949.256945 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.writebacks::writebacks 57255 # number of writebacks +system.cpu.icache.writebacks::total 57255 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 87505 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 87505 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 87505 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 87505 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 87505 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 87505 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991722 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 991722 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 991722 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 991722 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 991722 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 991722 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11850340996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11850340996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11850340996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11850340996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11850340996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11850340996 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6359500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6359500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6359500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 6359500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.070261 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.070261 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.070261 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11949.256945 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11949.256945 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11949.256945 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 643728 # number of replacements system.cpu.dcache.tagsinuse 511.991681 # Cycle average of tags in use @@ -593,84 +677,69 @@ system.cpu.dcache.total_refs 22270301 # To system.cpu.dcache.sampled_refs 644240 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 34.568330 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 48663000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.991681 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 14416609 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 511.991681 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 14416609 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 14416609 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 7264899 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7264899 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 7264899 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 299899 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 299899 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 299899 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 285488 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285488 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 285488 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 21681508 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 21681508 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 21681508 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 21681508 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 21681508 # number of overall hits system.cpu.dcache.overall_hits::total 21681508 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 722544 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 722544 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 722544 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 2966373 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2966373 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2966373 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 13502 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13502 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 13502 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::0 21 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 21 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 21 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::0 3688917 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 3688917 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 3688917 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 3688917 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 3688917 # number of overall misses system.cpu.dcache.overall_misses::total 3688917 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 10864923000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 110367485740 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 219139000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency 467500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency 121232408740 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 121232408740 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 15139153 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10864923000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10864923000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 110367485740 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 110367485740 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 219139000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 219139000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 467500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 467500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 121232408740 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 121232408740 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 121232408740 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 121232408740 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 15139153 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 15139153 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 10231272 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10231272 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 10231272 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 313401 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 313401 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 313401 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 285509 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285509 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 285509 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 25370425 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 25370425 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 25370425 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 25370425 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 25370425 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 25370425 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.047727 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.289932 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.043082 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::0 0.000074 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.145402 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.145402 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15037.039959 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 37206.206280 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16230.114057 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 22261.904762 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 32863.956749 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 32863.956749 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047727 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289932 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.043082 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000074 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.145402 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.145402 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15037.039959 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37206.206280 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16230.114057 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 22261.904762 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32863.956749 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32863.956749 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 16658435 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 7526500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2975 # number of cycles access was blocked @@ -679,57 +748,63 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 5599.473950 system.cpu.dcache.avg_blocked_cycles::no_targets 27171.480144 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 572893 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 336628 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 2716799 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 1453 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 3053427 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 3053427 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 385916 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 249574 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 12049 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses 21 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 635490 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 635490 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5245615500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8926036935 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161663500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency 398500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 14171652435 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 14171652435 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147159299000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42287348315 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 189446647315 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025491 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038446 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000074 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.025048 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.025048 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13592.635444 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35765.091456 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13417.171550 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 18976.190476 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22300.354742 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22300.354742 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 572893 # number of writebacks +system.cpu.dcache.writebacks::total 572893 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 336628 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 336628 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716799 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2716799 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1453 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3053427 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3053427 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3053427 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3053427 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385916 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385916 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249574 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249574 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12049 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12049 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 21 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 21 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 635490 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 635490 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 635490 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 635490 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5245615500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5245615500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8926036935 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8926036935 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 161663500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 161663500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 398500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 398500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14171652435 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14171652435 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14171652435 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14171652435 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147159299000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147159299000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42287348315 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42287348315 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189446647315 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 189446647315 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025491 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.038446 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000074 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025048 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025048 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13592.635444 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35765.091456 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13417.171550 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 18976.190476 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22300.354742 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22300.354742 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -737,38 +812,6 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.avg_refs no_value # Average number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 0 # number of demand (read+write) misses -system.iocache.demand_misses::total 0 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 0 # number of overall misses -system.iocache.overall_misses::total 0 # number of overall misses -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -777,28 +820,12 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 0 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1307927966543 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1307927966543 # number of overall MSHR uncacheable cycles -system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307927966543 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1307927966543 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307927966543 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1307927966543 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 87993 # number of quiesce instructions executed |