diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt | 336 |
1 files changed, 168 insertions, 168 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 6a79df0e0..0468c1634 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.523500 # Nu sim_ticks 2523500318000 # Number of ticks simulated final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66325 # Simulator instruction rate (inst/s) -host_op_rate 85314 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2762063576 # Simulator tick rate (ticks/s) -host_mem_usage 400896 # Number of bytes of host memory used -host_seconds 913.63 # Real time elapsed on the host +host_inst_rate 76318 # Simulator instruction rate (inst/s) +host_op_rate 98167 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3178196363 # Simulator tick rate (ticks/s) +host_mem_usage 441472 # Number of bytes of host memory used +host_seconds 794.00 # Real time elapsed on the host sim_insts 60596849 # Number of instructions simulated sim_ops 77944928 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory @@ -539,7 +539,7 @@ system.cpu.int_regfile_reads 549353817 # nu system.cpu.int_regfile_writes 87979071 # number of integer regfile writes system.cpu.fp_regfile_reads 8318 # number of floating regfile reads system.cpu.fp_regfile_writes 2932 # number of floating regfile writes -system.cpu.misc_regfile_reads 122823412 # number of misc regfile reads +system.cpu.misc_regfile_reads 30426999 # number of misc regfile reads system.cpu.misc_regfile_writes 912865 # number of misc regfile writes system.cpu.icache.replacements 980837 # number of replacements system.cpu.icache.tagsinuse 511.007226 # Cycle average of tags in use @@ -633,6 +633,168 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 643459 # number of replacements +system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use +system.cpu.dcache.total_refs 21664123 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643971 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.641457 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13804735 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13804735 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7290056 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7290056 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 280491 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 280491 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21094791 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21094791 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21094791 # number of overall hits +system.cpu.dcache.overall_hits::total 21094791 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 731455 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 731455 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2960577 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2960577 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13626 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13626 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3692032 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3692032 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3692032 # number of overall misses +system.cpu.dcache.overall_misses::total 3692032 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9566755000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9566755000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 105515855226 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 115082610226 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 115082610226 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 115082610226 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24786823 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24786823 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24786823 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050320 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.288819 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000042 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.827733 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 53.870588 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks +system.cpu.dcache.writebacks::total 607749 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3057311 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385788 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385788 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248933 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248933 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634721 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634721 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025607 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025607 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12359.780501 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12359.780501 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33051.045538 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33051.045538 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11589.591352 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11589.591352 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 64388 # number of replacements system.cpu.l2cache.tagsinuse 51373.602635 # Cycle average of tags in use system.cpu.l2cache.total_refs 1911501 # Total number of references to valid blocks. @@ -896,168 +1058,6 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643459 # number of replacements -system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use -system.cpu.dcache.total_refs 21664123 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643971 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.641457 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13804735 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13804735 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7290056 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7290056 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 280491 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 280491 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21094791 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21094791 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21094791 # number of overall hits -system.cpu.dcache.overall_hits::total 21094791 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 731455 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 731455 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2960577 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2960577 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13626 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13626 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3692032 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3692032 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3692032 # number of overall misses -system.cpu.dcache.overall_misses::total 3692032 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9566755000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9566755000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 105515855226 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 115082610226 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 115082610226 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 115082610226 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24786823 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24786823 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24786823 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050320 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288819 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000042 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.827733 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 53.870588 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks -system.cpu.dcache.writebacks::total 607749 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3057311 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385788 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385788 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248933 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248933 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634721 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634721 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025607 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025607 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12359.780501 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12359.780501 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33051.045538 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33051.045538 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11589.591352 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11589.591352 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. |