diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini | 757 |
1 files changed, 666 insertions, 91 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index 13794ff0e..e73de7c57 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -10,27 +10,25 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain +children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm +boot_loader=/work/gem5/dist/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 flags_addr=469827632 gic_cpu_addr=738205696 -have_generic_timer=false have_large_asid_64=false have_lpae=false have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -44,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh +readfile=/work/gem5/outgoing/gem5_3/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -87,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img +image_file=/work/gem5/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -475,6 +473,583 @@ type=ExeTracer eventq_index=0 [system.cpu2] +type=MinorCPU +children=branchPred dstage2_mmu dtb executeFuncUnits isa istage2_mmu itb tracer +branchPred=system.cpu2.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu2.dstage2_mmu +dtb=system.cpu2.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu2.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=Null +isa=system.cpu2.isa +istage2_mmu=system.cpu2.istage2_mmu +itb=system.cpu2.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=true +system=system +tracer=system.cpu2.tracer +workload= + +[system.cpu2.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 + +[system.cpu2.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu2.dstage2_mmu.stage2_tlb +sys=system +tlb=system.cpu2.dtb + +[system.cpu2.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu2.dstage2_mmu.stage2_tlb.walker + +[system.cpu2.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu2.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu2.dtb.walker + +[system.cpu2.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu2.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu2.executeFuncUnits.funcUnits0 system.cpu2.executeFuncUnits.funcUnits1 system.cpu2.executeFuncUnits.funcUnits2 system.cpu2.executeFuncUnits.funcUnits3 system.cpu2.executeFuncUnits.funcUnits4 system.cpu2.executeFuncUnits.funcUnits5 system.cpu2.executeFuncUnits.funcUnits6 + +[system.cpu2.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu2.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu2.executeFuncUnits.funcUnits0.timings + +[system.cpu2.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu2.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu2.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu2.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu2.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu2.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu2.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu2.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu2.executeFuncUnits.funcUnits1.timings + +[system.cpu2.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu2.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu2.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu2.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu2.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu2.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu2.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu2.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu2.executeFuncUnits.funcUnits2.timings + +[system.cpu2.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu2.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu2.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu2.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu2.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu2.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu2.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu2.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu2.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu2.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu2.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu2.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu2.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu2.executeFuncUnits.funcUnits4.timings + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu2.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu2.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu2.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu2.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu2.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu2.executeFuncUnits.funcUnits5.timings + +[system.cpu2.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu2.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu2.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu2.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu2.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu2.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu2.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu2.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu2.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu2.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu2.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu2.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu2.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu2.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu2.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu2.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu2.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu2.istage2_mmu.stage2_tlb +sys=system +tlb=system.cpu2.itb + +[system.cpu2.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu2.istage2_mmu.stage2_tlb.walker + +[system.cpu2.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu2.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu2.itb.walker + +[system.cpu2.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu2.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu3] type=DerivO3CPU children=branchPred dstage2_mmu dtb fuPool isa istage2_mmu itb tracer LFSTSize=1024 @@ -485,7 +1060,7 @@ SQEntries=32 SSITSize=1024 activity=0 backComSize=5 -branchPred=system.cpu2.branchPred +branchPred=system.cpu3.branchPred cachePorts=200 checker=Null clk_domain=system.cpu_clk_domain @@ -502,8 +1077,8 @@ dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true -dstage2_mmu=system.cpu2.dstage2_mmu -dtb=system.cpu2.dtb +dstage2_mmu=system.cpu3.dstage2_mmu +dtb=system.cpu3.dtb eventq_index=0 fetchBufferSize=64 fetchQueueSize=32 @@ -511,7 +1086,7 @@ fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 forwardComSize=5 -fuPool=system.cpu2.fuPool +fuPool=system.cpu3.fuPool function_trace=false function_trace_start=0 iewToCommitDelay=1 @@ -519,11 +1094,11 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 interrupts=Null -isa=system.cpu2.isa +isa=system.cpu3.isa issueToExecuteDelay=1 issueWidth=8 -istage2_mmu=system.cpu2.istage2_mmu -itb=system.cpu2.itb +istage2_mmu=system.cpu3.istage2_mmu +itb=system.cpu3.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -558,12 +1133,12 @@ squashWidth=8 store_set_clear_period=250000 switched_out=true system=system -tracer=system.cpu2.tracer +tracer=system.cpu3.tracer trapLatency=13 wbWidth=8 workload= -[system.cpu2.branchPred] +[system.cpu3.branchPred] type=TournamentBP BTBEntries=4096 BTBTagSize=16 @@ -579,23 +1154,23 @@ localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 -[system.cpu2.dstage2_mmu] +[system.cpu3.dstage2_mmu] type=ArmStage2MMU children=stage2_tlb eventq_index=0 -stage2_tlb=system.cpu2.dstage2_mmu.stage2_tlb +stage2_tlb=system.cpu3.dstage2_mmu.stage2_tlb sys=system -tlb=system.cpu2.dtb +tlb=system.cpu3.dtb -[system.cpu2.dstage2_mmu.stage2_tlb] +[system.cpu3.dstage2_mmu.stage2_tlb] type=ArmTLB children=walker eventq_index=0 is_stage2=true size=32 -walker=system.cpu2.dstage2_mmu.stage2_tlb.walker +walker=system.cpu3.dstage2_mmu.stage2_tlb.walker -[system.cpu2.dstage2_mmu.stage2_tlb.walker] +[system.cpu3.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 @@ -603,15 +1178,15 @@ is_stage2=true num_squash_per_cycle=2 sys=system -[system.cpu2.dtb] +[system.cpu3.dtb] type=ArmTLB children=walker eventq_index=0 is_stage2=false size=64 -walker=system.cpu2.dtb.walker +walker=system.cpu3.dtb.walker -[system.cpu2.dtb.walker] +[system.cpu3.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 @@ -619,314 +1194,314 @@ is_stage2=false num_squash_per_cycle=2 sys=system -[system.cpu2.fuPool] +[system.cpu3.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 +FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 eventq_index=0 -[system.cpu2.fuPool.FUList0] +[system.cpu3.fuPool.FUList0] type=FUDesc children=opList count=6 eventq_index=0 -opList=system.cpu2.fuPool.FUList0.opList +opList=system.cpu3.fuPool.FUList0.opList -[system.cpu2.fuPool.FUList0.opList] +[system.cpu3.fuPool.FUList0.opList] type=OpDesc eventq_index=0 opClass=IntAlu opLat=1 pipelined=true -[system.cpu2.fuPool.FUList1] +[system.cpu3.fuPool.FUList1] type=FUDesc children=opList0 opList1 count=2 eventq_index=0 -opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 +opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 -[system.cpu2.fuPool.FUList1.opList0] +[system.cpu3.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 opClass=IntMult opLat=3 pipelined=true -[system.cpu2.fuPool.FUList1.opList1] +[system.cpu3.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 opClass=IntDiv opLat=20 pipelined=false -[system.cpu2.fuPool.FUList2] +[system.cpu3.fuPool.FUList2] type=FUDesc children=opList0 opList1 opList2 count=4 eventq_index=0 -opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 +opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 -[system.cpu2.fuPool.FUList2.opList0] +[system.cpu3.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 opClass=FloatAdd opLat=2 pipelined=true -[system.cpu2.fuPool.FUList2.opList1] +[system.cpu3.fuPool.FUList2.opList1] type=OpDesc eventq_index=0 opClass=FloatCmp opLat=2 pipelined=true -[system.cpu2.fuPool.FUList2.opList2] +[system.cpu3.fuPool.FUList2.opList2] type=OpDesc eventq_index=0 opClass=FloatCvt opLat=2 pipelined=true -[system.cpu2.fuPool.FUList3] +[system.cpu3.fuPool.FUList3] type=FUDesc children=opList0 opList1 opList2 count=2 eventq_index=0 -opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 +opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 -[system.cpu2.fuPool.FUList3.opList0] +[system.cpu3.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 opClass=FloatMult opLat=4 pipelined=true -[system.cpu2.fuPool.FUList3.opList1] +[system.cpu3.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu2.fuPool.FUList3.opList2] +[system.cpu3.fuPool.FUList3.opList2] type=OpDesc eventq_index=0 opClass=FloatSqrt opLat=24 pipelined=false -[system.cpu2.fuPool.FUList4] +[system.cpu3.fuPool.FUList4] type=FUDesc children=opList count=0 eventq_index=0 -opList=system.cpu2.fuPool.FUList4.opList +opList=system.cpu3.fuPool.FUList4.opList -[system.cpu2.fuPool.FUList4.opList] +[system.cpu3.fuPool.FUList4.opList] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5] +[system.cpu3.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 eventq_index=0 -opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 +opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 -[system.cpu2.fuPool.FUList5.opList00] +[system.cpu3.fuPool.FUList5.opList00] type=OpDesc eventq_index=0 opClass=SimdAdd opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5.opList01] +[system.cpu3.fuPool.FUList5.opList01] type=OpDesc eventq_index=0 opClass=SimdAddAcc opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5.opList02] +[system.cpu3.fuPool.FUList5.opList02] type=OpDesc eventq_index=0 opClass=SimdAlu opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5.opList03] +[system.cpu3.fuPool.FUList5.opList03] type=OpDesc eventq_index=0 opClass=SimdCmp opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5.opList04] +[system.cpu3.fuPool.FUList5.opList04] type=OpDesc eventq_index=0 opClass=SimdCvt opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5.opList05] +[system.cpu3.fuPool.FUList5.opList05] type=OpDesc eventq_index=0 opClass=SimdMisc opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5.opList06] +[system.cpu3.fuPool.FUList5.opList06] type=OpDesc eventq_index=0 opClass=SimdMult opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5.opList07] +[system.cpu3.fuPool.FUList5.opList07] type=OpDesc eventq_index=0 opClass=SimdMultAcc opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5.opList08] +[system.cpu3.fuPool.FUList5.opList08] type=OpDesc eventq_index=0 opClass=SimdShift opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5.opList09] +[system.cpu3.fuPool.FUList5.opList09] type=OpDesc eventq_index=0 opClass=SimdShiftAcc opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5.opList10] +[system.cpu3.fuPool.FUList5.opList10] type=OpDesc eventq_index=0 opClass=SimdSqrt opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5.opList11] +[system.cpu3.fuPool.FUList5.opList11] type=OpDesc eventq_index=0 opClass=SimdFloatAdd opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5.opList12] +[system.cpu3.fuPool.FUList5.opList12] type=OpDesc eventq_index=0 opClass=SimdFloatAlu opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5.opList13] +[system.cpu3.fuPool.FUList5.opList13] type=OpDesc eventq_index=0 opClass=SimdFloatCmp opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5.opList14] +[system.cpu3.fuPool.FUList5.opList14] type=OpDesc eventq_index=0 opClass=SimdFloatCvt opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5.opList15] +[system.cpu3.fuPool.FUList5.opList15] type=OpDesc eventq_index=0 opClass=SimdFloatDiv opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5.opList16] +[system.cpu3.fuPool.FUList5.opList16] type=OpDesc eventq_index=0 opClass=SimdFloatMisc opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5.opList17] +[system.cpu3.fuPool.FUList5.opList17] type=OpDesc eventq_index=0 opClass=SimdFloatMult opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5.opList18] +[system.cpu3.fuPool.FUList5.opList18] type=OpDesc eventq_index=0 opClass=SimdFloatMultAcc opLat=1 pipelined=true -[system.cpu2.fuPool.FUList5.opList19] +[system.cpu3.fuPool.FUList5.opList19] type=OpDesc eventq_index=0 opClass=SimdFloatSqrt opLat=1 pipelined=true -[system.cpu2.fuPool.FUList6] +[system.cpu3.fuPool.FUList6] type=FUDesc children=opList count=0 eventq_index=0 -opList=system.cpu2.fuPool.FUList6.opList +opList=system.cpu3.fuPool.FUList6.opList -[system.cpu2.fuPool.FUList6.opList] +[system.cpu3.fuPool.FUList6.opList] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true -[system.cpu2.fuPool.FUList7] +[system.cpu3.fuPool.FUList7] type=FUDesc children=opList0 opList1 count=4 eventq_index=0 -opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 +opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 -[system.cpu2.fuPool.FUList7.opList0] +[system.cpu3.fuPool.FUList7.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true -[system.cpu2.fuPool.FUList7.opList1] +[system.cpu3.fuPool.FUList7.opList1] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true -[system.cpu2.fuPool.FUList8] +[system.cpu3.fuPool.FUList8] type=FUDesc children=opList count=1 eventq_index=0 -opList=system.cpu2.fuPool.FUList8.opList +opList=system.cpu3.fuPool.FUList8.opList -[system.cpu2.fuPool.FUList8.opList] +[system.cpu3.fuPool.FUList8.opList] type=OpDesc eventq_index=0 opClass=IprAccess opLat=3 pipelined=false -[system.cpu2.isa] +[system.cpu3.isa] type=ArmISA eventq_index=0 fpsid=1090793632 @@ -956,23 +1531,23 @@ midr=1091551472 pmu=Null system=system -[system.cpu2.istage2_mmu] +[system.cpu3.istage2_mmu] type=ArmStage2MMU children=stage2_tlb eventq_index=0 -stage2_tlb=system.cpu2.istage2_mmu.stage2_tlb +stage2_tlb=system.cpu3.istage2_mmu.stage2_tlb sys=system -tlb=system.cpu2.itb +tlb=system.cpu3.itb -[system.cpu2.istage2_mmu.stage2_tlb] +[system.cpu3.istage2_mmu.stage2_tlb] type=ArmTLB children=walker eventq_index=0 is_stage2=true size=32 -walker=system.cpu2.istage2_mmu.stage2_tlb.walker +walker=system.cpu3.istage2_mmu.stage2_tlb.walker -[system.cpu2.istage2_mmu.stage2_tlb.walker] +[system.cpu3.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 @@ -980,15 +1555,15 @@ is_stage2=true num_squash_per_cycle=2 sys=system -[system.cpu2.itb] +[system.cpu3.itb] type=ArmTLB children=walker eventq_index=0 is_stage2=false size=64 -walker=system.cpu2.itb.walker +walker=system.cpu3.itb.walker -[system.cpu2.itb.walker] +[system.cpu3.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain eventq_index=0 @@ -996,7 +1571,7 @@ is_stage2=false num_squash_per_cycle=2 sys=system -[system.cpu2.tracer] +[system.cpu3.tracer] type=ExeTracer eventq_index=0 |