diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt | 1586 |
1 files changed, 781 insertions, 805 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index a5289b78c..53535ebf9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.824845 # Number of seconds simulated -sim_ticks 2824844934500 # Number of ticks simulated -final_tick 2824844934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2824844935500 # Number of ticks simulated +final_tick 2824844935500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 301884 # Simulator instruction rate (inst/s) -host_op_rate 366207 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6935241973 # Simulator tick rate (ticks/s) +host_inst_rate 301818 # Simulator instruction rate (inst/s) +host_op_rate 366127 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6933711439 # Simulator tick rate (ticks/s) host_mem_usage 588164 # Number of bytes of host memory used -host_seconds 407.32 # Real time elapsed on the host -sim_insts 122962642 # Number of instructions simulated -sim_ops 149162643 # Number of ops (including micro ops) simulated +host_seconds 407.41 # Real time elapsed on the host +sim_insts 122962678 # Number of instructions simulated +sim_ops 149162687 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory @@ -139,7 +139,7 @@ system.physmem.perBankWrBursts::14 4129 # Pe system.physmem.perBankWrBursts::15 3560 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 2823278666500 # Total gap between requests +system.physmem.totGap 2823278667500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -154,8 +154,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 68732 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 76464 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 20945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 76462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 20947 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 2008 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 532 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see @@ -202,13 +202,13 @@ system.physmem.wrQLenPdf::12 65 # Wh system.physmem.wrQLenPdf::13 66 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 65 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 1166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3816 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 3963 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 3852 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 4123 # What write queue length does an incoming req see @@ -232,38 +232,38 @@ system.physmem.wrQLenPdf::42 60 # Wh system.physmem.wrQLenPdf::43 41 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39182 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 275.494666 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 163.171776 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 307.907235 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16210 41.37% 41.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9497 24.24% 65.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3855 9.84% 75.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2019 5.15% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 39183 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 275.487635 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.171837 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.896605 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16209 41.37% 41.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9498 24.24% 65.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3856 9.84% 75.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2020 5.16% 80.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 1646 4.20% 84.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1042 2.66% 87.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1041 2.66% 87.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 570 1.45% 88.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 566 1.44% 90.36% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3777 9.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39182 # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39183 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 3537 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 28.251343 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 474.824507 # Reads before turning the bus around for writes @@ -301,12 +301,12 @@ system.physmem.wrPerTurnAround::112-115 1 0.03% 99.89% # Wr system.physmem.wrPerTurnAround::128-131 1 0.03% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-147 3 0.08% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 3537 # Writes before turning the bus around for reads -system.physmem.totQLat 1310108250 # Total ticks spent queuing -system.physmem.totMemAccLat 3184227000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1310437500 # Total ticks spent queuing +system.physmem.totMemAccLat 3184556250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 499765000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13107.24 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13110.54 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31857.24 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31860.54 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.26 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.27 # Average system read bandwidth in MiByte/s @@ -318,38 +318,38 @@ system.physmem.busUtilWrite 0.01 # Da system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 28.41 # Average write queue length when enqueuing system.physmem.readRowHits 80619 # Number of row buffer hits during reads -system.physmem.writeRowHits 48864 # Number of row buffer hits during writes +system.physmem.writeRowHits 48863 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.66 # Row buffer hit rate for reads system.physmem.writeRowHitRate 71.09 # Row buffer hit rate for writes system.physmem.avgGap 16727764.68 # Average gap between requests system.physmem.pageHitRate 76.76 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 156212280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 85094625 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 156219840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 85098750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 402051000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 227525760 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 179782062720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 73198076175 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1622869382250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1876720404810 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.445189 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2640467902750 # Time in different power states +system.physmem_0.actBackEnergy 73199813535 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1622867858250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1876720629855 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.445270 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2640465319000 # Time in different power states system.physmem_0.memoryStateTime::REF 91913120000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 20211500000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 20214084000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 140003640 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 76213500 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 377559000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 217734480 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 179782062720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 72424788525 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1619952843000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1872971204865 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.534203 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2641599878750 # Time in different power states +system.physmem_1.actBackEnergy 72425693970 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1619952048750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1872971316060 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.534243 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2641598541500 # Time in different power states system.physmem_1.memoryStateTime::REF 91913120000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 19067953250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 19069290500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -404,11 +404,11 @@ system.cpu0.dtb.walker.walksShort 4956 # Ta system.cpu0.dtb.walker.walkWaitTime::samples 4956 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::0 4956 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::total 4956 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 57378110626 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.254713 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -14614977624 -25.47% -25.47% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 71993088250 125.47% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 57378110626 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::samples 57378111376 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.254714 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -14615003624 -25.47% -25.47% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 71993115000 125.47% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 57378111376 # Table walker pending requests distribution system.cpu0.dtb.walker.walkPageSizes::4K 2714 66.86% 66.86% # Table walker page sizes translated system.cpu0.dtb.walker.walkPageSizes::1M 1345 33.14% 100.00% # Table walker page sizes translated system.cpu0.dtb.walker.walkPageSizes::total 4059 # Table walker page sizes translated @@ -421,9 +421,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4059 system.cpu0.dtb.walker.walkRequestOrigin::total 9015 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12035285 # DTB read hits +system.cpu0.dtb.read_hits 12035291 # DTB read hits system.cpu0.dtb.read_misses 4159 # DTB read misses -system.cpu0.dtb.write_hits 9387276 # DTB write hits +system.cpu0.dtb.write_hits 9387286 # DTB write hits system.cpu0.dtb.write_misses 797 # DTB write misses system.cpu0.dtb.flush_tlb 170 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 344 # Number of times TLB was flushed by MVA @@ -434,12 +434,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 725 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 165 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12039444 # DTB read accesses -system.cpu0.dtb.write_accesses 9388073 # DTB write accesses +system.cpu0.dtb.read_accesses 12039450 # DTB read accesses +system.cpu0.dtb.write_accesses 9388083 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21422561 # DTB hits +system.cpu0.dtb.hits 21422577 # DTB hits system.cpu0.dtb.misses 4956 # DTB misses -system.cpu0.dtb.accesses 21427517 # DTB accesses +system.cpu0.dtb.accesses 21427533 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -474,11 +474,11 @@ system.cpu0.itb.walker.walksShort 2296 # Ta system.cpu0.itb.walker.walkWaitTime::samples 2296 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::0 2296 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 2296 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 57378110626 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::samples 57378111376 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::mean 1.254717 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 -14615152624 -25.47% -25.47% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 71993263250 125.47% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 57378110626 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 71993264000 125.47% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 57378111376 # Table walker pending requests distribution system.cpu0.itb.walker.walkPageSizes::4K 1260 74.03% 74.03% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::1M 442 25.97% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 1702 # Table walker page sizes translated @@ -489,7 +489,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1702 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1702 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 3998 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 57357207 # ITB inst hits +system.cpu0.itb.inst_hits 57357196 # ITB inst hits system.cpu0.itb.inst_misses 2296 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -506,39 +506,39 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 57359503 # ITB inst accesses -system.cpu0.itb.hits 57357207 # DTB hits +system.cpu0.itb.inst_accesses 57359492 # ITB inst accesses +system.cpu0.itb.hits 57357196 # DTB hits system.cpu0.itb.misses 2296 # DTB misses -system.cpu0.itb.accesses 57359503 # DTB accesses -system.cpu0.numCycles 69413199 # number of cpu cycles simulated +system.cpu0.itb.accesses 57359492 # DTB accesses +system.cpu0.numCycles 69413201 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3088 # number of quiesce instructions executed -system.cpu0.committedInsts 55950811 # Number of instructions committed -system.cpu0.committedOps 67895775 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 59559074 # Number of integer alu accesses +system.cpu0.committedInsts 55950800 # Number of instructions committed +system.cpu0.committedOps 67895777 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 59559088 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4429 # Number of float alu accesses -system.cpu0.num_func_calls 5748533 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7418510 # number of instructions that are conditional controls -system.cpu0.num_int_insts 59559074 # number of integer instructions +system.cpu0.num_func_calls 5748539 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7418498 # number of instructions that are conditional controls +system.cpu0.num_int_insts 59559088 # number of integer instructions system.cpu0.num_fp_insts 4429 # number of float instructions -system.cpu0.num_int_register_reads 109971244 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41296090 # number of times the integer registers were written +system.cpu0.num_int_register_reads 109971177 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41296104 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3323 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1108 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 206667111 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 25287842 # number of times the CC registers were written -system.cpu0.num_mem_refs 21990124 # number of memory refs -system.cpu0.num_load_insts 12179885 # Number of load instructions -system.cpu0.num_store_insts 9810239 # Number of store instructions -system.cpu0.num_idle_cycles 65532351.821320 # Number of idle cycles -system.cpu0.num_busy_cycles 3880847.178680 # Number of busy cycles +system.cpu0.num_cc_register_reads 206667117 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 25287808 # number of times the CC registers were written +system.cpu0.num_mem_refs 21990141 # number of memory refs +system.cpu0.num_load_insts 12179891 # Number of load instructions +system.cpu0.num_store_insts 9810250 # Number of store instructions +system.cpu0.num_idle_cycles 65532353.686303 # Number of idle cycles +system.cpu0.num_busy_cycles 3880847.313697 # Number of busy cycles system.cpu0.not_idle_fraction 0.055909 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.944091 # Percentage of idle cycles -system.cpu0.Branches 13556627 # Number of branches fetched +system.cpu0.Branches 13556608 # Number of branches fetched system.cpu0.op_class::No_OpClass 2177 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46939683 68.04% 68.05% # Class of executed instruction +system.cpu0.op_class::IntAlu 46939668 68.04% 68.05% # Class of executed instruction system.cpu0.op_class::IntMult 49866 0.07% 68.12% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.12% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.12% # Class of executed instruction @@ -567,21 +567,21 @@ system.cpu0.op_class::SimdFloatMisc 3817 0.01% 68.12% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 68.12% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.12% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.12% # Class of executed instruction -system.cpu0.op_class::MemRead 12179885 17.66% 85.78% # Class of executed instruction -system.cpu0.op_class::MemWrite 9810239 14.22% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 12179891 17.66% 85.78% # Class of executed instruction +system.cpu0.op_class::MemWrite 9810250 14.22% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 68985667 # Class of executed instruction -system.cpu0.dcache.tags.replacements 833417 # number of replacements +system.cpu0.op_class::total 68985669 # Class of executed instruction +system.cpu0.dcache.tags.replacements 833415 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.996599 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 46053699 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 833929 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.224964 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 46053704 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 833927 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.225102 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.718134 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.522877 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.743087 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 15.012501 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.718128 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.522887 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.743086 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 15.012497 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.936949 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.022506 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu2.data 0.011217 # Average percentage of cache occupancy @@ -592,53 +592,53 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 91 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 193158098 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 193158098 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11428917 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 3665384 # number of ReadReq hits +system.cpu0.dcache.tags.tag_accesses 193158108 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 193158108 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11428921 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 3665380 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu2.data 4294725 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 6439390 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25828416 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9038916 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 2620667 # number of WriteReq hits +system.cpu0.dcache.ReadReq_hits::cpu3.data 6439389 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25828415 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 9038925 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 2620658 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu2.data 3331215 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 3935723 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18926521 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 169434 # number of SoftPFReq hits +system.cpu0.dcache.WriteReq_hits::cpu3.data 3935728 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18926526 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 169435 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::cpu1.data 54580 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::cpu2.data 74986 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::cpu3.data 86424 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 385424 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 210126 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 74902 # number of LoadLockedReq hits +system.cpu0.dcache.SoftPFReq_hits::total 385425 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 210127 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 74901 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 77543 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 87725 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 450296 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 211417 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 76882 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 211418 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 76881 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu2.data 80173 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu3.data 91598 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 460070 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20467833 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 6286051 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 20467846 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 6286038 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu2.data 7625940 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 10375113 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 44754937 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20637267 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 6340631 # number of overall hits +system.cpu0.dcache.demand_hits::cpu3.data 10375117 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 44754941 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 20637281 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 6340618 # number of overall hits system.cpu0.dcache.overall_hits::cpu2.data 7700926 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 10461537 # number of overall hits -system.cpu0.dcache.overall_hits::total 45140361 # number of overall hits +system.cpu0.dcache.overall_hits::cpu3.data 10461541 # number of overall hits +system.cpu0.dcache.overall_hits::total 45140366 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 163054 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu1.data 56550 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu2.data 94465 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 206058 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 520127 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu3.data 206057 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 520126 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 128070 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::cpu1.data 30037 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::cpu2.data 97212 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 1098175 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1353494 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu3.data 1098174 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1353493 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 50296 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::cpu1.data 17954 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::cpu2.data 32256 # number of SoftPFReq misses @@ -655,70 +655,70 @@ system.cpu0.dcache.StoreCondReq_misses::total 27 system.cpu0.dcache.demand_misses::cpu0.data 291124 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::cpu1.data 86587 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::cpu2.data 191677 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu3.data 1304233 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1873621 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu3.data 1304231 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1873619 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 341420 # number of overall misses system.cpu0.dcache.overall_misses::cpu1.data 104541 # number of overall misses system.cpu0.dcache.overall_misses::cpu2.data 223933 # number of overall misses -system.cpu0.dcache.overall_misses::cpu3.data 1342364 # number of overall misses -system.cpu0.dcache.overall_misses::total 2012258 # number of overall misses +system.cpu0.dcache.overall_misses::cpu3.data 1342362 # number of overall misses +system.cpu0.dcache.overall_misses::total 2012256 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 1025638000 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 1410367000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 3710226000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6146231000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1809303500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 6517751997 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 77696262478 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 86023317975 # number of WriteReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 3709040500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6145045500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1809360000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 6517744997 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 77695281478 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 86022386475 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 36347500 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 49512000 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 113107500 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 198967000 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 883000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 883000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 2834941500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 7928118997 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu3.data 81406488478 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 92169548975 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 2834941500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 7928118997 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu3.data 81406488478 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 92169548975 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 11591971 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 3721934 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu1.data 2834998000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 7928111997 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu3.data 81404321978 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 92167431975 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 2834998000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 7928111997 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu3.data 81404321978 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 92167431975 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 11591975 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 3721930 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu2.data 4389190 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu3.data 6645448 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26348543 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9166986 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 2650704 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu3.data 6645446 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 26348541 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9166995 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 2650695 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu2.data 3428427 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu3.data 5033898 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 20280015 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 219730 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu3.data 5033902 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 20280019 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 219731 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 72534 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 107242 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 124555 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 524061 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 214028 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 77519 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 524062 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 214029 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 77518 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 81128 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 95645 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 468320 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 211419 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 76882 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 211420 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 76881 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 80173 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 91623 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 460097 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 20758957 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 6372638 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 20758970 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 6372625 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu2.data 7817617 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu3.data 11679346 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 46628558 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 20978687 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 6445172 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu3.data 11679348 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 46628560 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 20978701 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 6445159 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu2.data 7924859 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu3.data 11803901 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 47152619 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu3.data 11803903 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 47152622 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.014066 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.015194 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.021522 # miss rate for ReadReq accesses @@ -729,13 +729,13 @@ system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.011332 system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.028355 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.218156 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.066740 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.228899 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.228898 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.247525 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.300778 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.306138 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.264544 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.264543 # miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018231 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.033759 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.033760 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.044189 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.082806 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.038487 # miss rate for LoadLockedReq accesses @@ -754,36 +754,34 @@ system.cpu0.dcache.overall_miss_rate::cpu3.data 0.113722 system.cpu0.dcache.overall_miss_rate::total 0.042675 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18136.834660 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14930.048166 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 18005.736249 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11816.788977 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 60235.825815 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 67046.784317 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 70750.347147 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 63556.482685 # average WriteReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 18000.070369 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 11814.532440 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 60237.706828 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 67046.712309 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 70749.518271 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 63555.841423 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13888.995032 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13810.878661 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14281.250000 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11039.003551 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 35320 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 32703.703704 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 32740.959959 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41361.869171 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 62417.135955 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 49193.272799 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27117.987201 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 35403.977962 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 60644.123709 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 45804.041517 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 501932 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 35431 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 12377 # number of cycles access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 32741.612482 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41361.832651 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 62415.570538 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 49192.195412 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27118.527659 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 35403.946703 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 60642.600117 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 45803.034989 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 501934 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 34859 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 12379 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 549 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.553607 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 64.537341 # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 692124 # number of writebacks -system.cpu0.dcache.writebacks::total 692124 # number of writebacks +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.547217 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 63.495446 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 692123 # number of writebacks +system.cpu0.dcache.writebacks::total 692123 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 75 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 15084 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 94480 # number of ReadReq MSHR hits @@ -805,12 +803,12 @@ system.cpu0.dcache.overall_mshr_hits::cpu3.data 1104529 system.cpu0.dcache.overall_mshr_hits::total 1163930 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 56475 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 79381 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 111578 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 247434 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 111577 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 247433 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 30037 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52970 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 88126 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 171133 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 88125 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 171132 # number of WriteReq MSHR misses system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 17691 # number of SoftPFReq MSHR misses system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 22463 # number of SoftPFReq MSHR misses system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 28075 # number of SoftPFReq MSHR misses @@ -823,12 +821,12 @@ system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 25 system.cpu0.dcache.StoreCondReq_mshr_misses::total 25 # number of StoreCondReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu1.data 86512 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu2.data 132351 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu3.data 199704 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 418567 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu3.data 199702 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 418565 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu1.data 104203 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu2.data 154814 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu3.data 227779 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 486796 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu3.data 227777 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 486794 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 3539 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 5604 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 8403 # number of ReadReq MSHR uncacheable @@ -843,12 +841,12 @@ system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 15034 system.cpu0.dcache.overall_mshr_uncacheable_misses::total 31407 # number of overall MSHR uncacheable misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 967480000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1154731000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1737713500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3859924500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1779266500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3530686500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 6386365938 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11696318938 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1737821000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3860032000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1779323000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3530687000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 6386469938 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11696479938 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 234355500 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 312434500 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 488593000 # number of SoftPFReq MSHR miss cycles @@ -859,34 +857,30 @@ system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 38674500 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76261000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 858000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 858000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2746746500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 4685417500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 8124079438 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15556243438 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2981102000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 4997852000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 8612672438 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16591626438 # number of overall MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2746803000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 4685418000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 8124290938 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15556511938 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2981158500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 4997852500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 8612883938 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16591894938 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 629109500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1118645000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1808845000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3556599500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 517115500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 860105000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1408279452 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2785499952 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1146225000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1978750000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 3217124452 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6342099452 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1808848000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3556602500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 629109500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1118645000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1808848000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3556602500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015174 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018086 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016790 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009391 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011332 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015450 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017507 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008439 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017506 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008438 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.243899 # mshr miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.209461 # mshr miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.225402 # mshr miss rate for SoftPFReq accesses @@ -907,12 +901,12 @@ system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019297 system.cpu0.dcache.overall_mshr_miss_rate::total 0.010324 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17131.119965 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14546.692533 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15573.979638 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15599.814496 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59235.825815 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 66654.455352 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72468.578376 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68346.367667 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15575.082678 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15600.312004 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59237.706828 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 66654.464791 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72470.580857 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68347.707840 # average WriteReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13247.159573 # average SoftPFReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13908.850109 # average SoftPFReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17403.134461 # average SoftPFReq mshr miss latency @@ -923,40 +917,35 @@ system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16001.034340 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16260.341151 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 34320 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 34320 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 31749.890189 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35401.451444 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40680.604485 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37165.479930 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28608.600520 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32282.945987 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37811.529763 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34083.325331 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 31750.543277 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35401.455221 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40682.070976 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37166.298993 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28609.142731 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32282.949216 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37812.790308 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34084.016931 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177764.764058 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 199615.453248 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215261.811258 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202701.441924 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179304.958391 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 197907.271054 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 212378.140854 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200959.523267 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 178456.328818 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 198869.346734 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 213989.919649 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 201932.672716 # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215262.168273 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202701.612903 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 97946.364627 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 112426.633166 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 120317.147798 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 113242.350431 # average overall mshr uncacheable latency system.cpu0.icache.tags.replacements 1977299 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.446080 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 94017526 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 511.446081 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 94017501 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 1977811 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 47.536153 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 47.536140 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 12783647500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 433.555546 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 10.959606 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 24.981249 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 41.949679 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 433.555541 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 10.959616 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 24.981248 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu3.inst 41.949675 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.846788 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.021405 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.048792 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.021406 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.048791 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu3.inst 0.081933 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998918 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -965,65 +954,65 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 220 system.cpu0.icache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 98016445 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 98016445 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 56629058 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 17886575 # number of ReadReq hits +system.cpu0.icache.tags.tag_accesses 98016418 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 98016418 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 56629047 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 17886534 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu2.inst 10324474 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu3.inst 9177419 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 94017526 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 56629058 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 17886575 # number of demand (read+write) hits +system.cpu0.icache.ReadReq_hits::cpu3.inst 9177446 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 94017501 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 56629047 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 17886534 # number of demand (read+write) hits system.cpu0.icache.demand_hits::cpu2.inst 10324474 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu3.inst 9177419 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 94017526 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 56629058 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 17886575 # number of overall hits +system.cpu0.icache.demand_hits::cpu3.inst 9177446 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 94017501 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 56629047 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 17886534 # number of overall hits system.cpu0.icache.overall_hits::cpu2.inst 10324474 # number of overall hits -system.cpu0.icache.overall_hits::cpu3.inst 9177419 # number of overall hits -system.cpu0.icache.overall_hits::total 94017526 # number of overall hits +system.cpu0.icache.overall_hits::cpu3.inst 9177446 # number of overall hits +system.cpu0.icache.overall_hits::total 94017501 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 729851 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::cpu1.inst 205937 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::cpu2.inst 497244 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu3.inst 588040 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2021072 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu3.inst 588038 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2021070 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 729851 # number of demand (read+write) misses system.cpu0.icache.demand_misses::cpu1.inst 205937 # number of demand (read+write) misses system.cpu0.icache.demand_misses::cpu2.inst 497244 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu3.inst 588040 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2021072 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu3.inst 588038 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 2021070 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 729851 # number of overall misses system.cpu0.icache.overall_misses::cpu1.inst 205937 # number of overall misses system.cpu0.icache.overall_misses::cpu2.inst 497244 # number of overall misses -system.cpu0.icache.overall_misses::cpu3.inst 588040 # number of overall misses -system.cpu0.icache.overall_misses::total 2021072 # number of overall misses +system.cpu0.icache.overall_misses::cpu3.inst 588038 # number of overall misses +system.cpu0.icache.overall_misses::total 2021070 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2906684000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 7063506500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 8485451487 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18455641987 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 7063507000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 8486116487 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18456307487 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu1.inst 2906684000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 7063506500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu3.inst 8485451487 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18455641987 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 7063507000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu3.inst 8486116487 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18456307487 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu1.inst 2906684000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 7063506500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu3.inst 8485451487 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18455641987 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 57358909 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 18092512 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.overall_miss_latency::cpu2.inst 7063507000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu3.inst 8486116487 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18456307487 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 57358898 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 18092471 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu2.inst 10821718 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu3.inst 9765459 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 96038598 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 57358909 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 18092512 # number of demand (read+write) accesses +system.cpu0.icache.ReadReq_accesses::cpu3.inst 9765484 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 96038571 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 57358898 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 18092471 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::cpu2.inst 10821718 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu3.inst 9765459 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 96038598 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 57358909 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 18092512 # number of overall (read+write) accesses +system.cpu0.icache.demand_accesses::cpu3.inst 9765484 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 96038571 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 57358898 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 18092471 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::cpu2.inst 10821718 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu3.inst 9765459 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 96038598 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu3.inst 9765484 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 96038571 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012724 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011382 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.045949 # miss rate for ReadReq accesses @@ -1040,33 +1029,31 @@ system.cpu0.icache.overall_miss_rate::cpu2.inst 0.045949 system.cpu0.icache.overall_miss_rate::cpu3.inst 0.060216 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.021044 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14114.433055 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14205.312684 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 14430.058307 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9131.610347 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14205.313689 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 14431.238265 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9131.948664 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14114.433055 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14205.312684 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 14430.058307 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9131.610347 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14205.313689 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 14431.238265 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9131.948664 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14114.433055 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14205.312684 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 14430.058307 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9131.610347 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14205.313689 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 14431.238265 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9131.948664 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 7577 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 331 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.891239 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 1977299 # number of writebacks system.cpu0.icache.writebacks::total 1977299 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 43224 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 43224 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu3.inst 43224 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 43224 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu3.inst 43224 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 43224 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 43222 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43222 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu3.inst 43222 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43222 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu3.inst 43222 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43222 # number of overall MSHR hits system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 205937 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 497244 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 544816 # number of ReadReq MSHR misses @@ -1080,17 +1067,17 @@ system.cpu0.icache.overall_mshr_misses::cpu2.inst 497244 system.cpu0.icache.overall_mshr_misses::cpu3.inst 544816 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 1247997 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2700747000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6566263500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 7404631489 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 16671641989 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6566264000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 7404656989 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 16671667989 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2700747000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6566263500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 7404631489 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 16671641989 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6566264000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 7404656989 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 16671667989 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2700747000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6566263500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 7404631489 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 16671641989 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6566264000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 7404656989 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 16671667989 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011382 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045949 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.055790 # mshr miss rate for ReadReq accesses @@ -1104,18 +1091,17 @@ system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045949 system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.055790 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.012995 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13114.433055 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13205.314695 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13591.068341 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13358.719603 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13205.315700 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13591.115145 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13358.740437 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13114.433055 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13205.314695 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 13591.068341 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13358.719603 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13205.315700 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 13591.115145 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13358.740437 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13114.433055 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13205.314695 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13591.068341 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13358.719603 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13205.315700 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13591.115145 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13358.740437 # average overall mshr miss latency system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1175,9 +1161,9 @@ system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1607 system.cpu1.dtb.walker.walkRequestOrigin::total 3505 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3875526 # DTB read hits +system.cpu1.dtb.read_hits 3875521 # DTB read hits system.cpu1.dtb.read_misses 1673 # DTB read misses -system.cpu1.dtb.write_hits 2730535 # DTB write hits +system.cpu1.dtb.write_hits 2730525 # DTB write hits system.cpu1.dtb.write_misses 225 # DTB write misses system.cpu1.dtb.flush_tlb 151 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 137 # Number of times TLB was flushed by MVA @@ -1185,15 +1171,15 @@ system.cpu1.dtb.flush_tlb_mva_asid 0 # Nu system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1104 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 239 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 238 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 65 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3877199 # DTB read accesses -system.cpu1.dtb.write_accesses 2730760 # DTB write accesses +system.cpu1.dtb.read_accesses 3877194 # DTB read accesses +system.cpu1.dtb.write_accesses 2730750 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6606061 # DTB hits +system.cpu1.dtb.hits 6606046 # DTB hits system.cpu1.dtb.misses 1898 # DTB misses -system.cpu1.dtb.accesses 6607959 # DTB accesses +system.cpu1.dtb.accesses 6607944 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1255,7 +1241,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 679 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 679 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 1616 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 18092512 # ITB inst hits +system.cpu1.itb.inst_hits 18092471 # ITB inst hits system.cpu1.itb.inst_misses 937 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1272,39 +1258,39 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 18093449 # ITB inst accesses -system.cpu1.itb.hits 18092512 # DTB hits +system.cpu1.itb.inst_accesses 18093408 # ITB inst accesses +system.cpu1.itb.hits 18092471 # DTB hits system.cpu1.itb.misses 937 # DTB misses -system.cpu1.itb.accesses 18093449 # DTB accesses +system.cpu1.itb.accesses 18093408 # DTB accesses system.cpu1.numCycles 144009903 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 17421496 # Number of instructions committed -system.cpu1.committedOps 20899704 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 18577797 # Number of integer alu accesses +system.cpu1.committedInsts 17421457 # Number of instructions committed +system.cpu1.committedOps 20899652 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 18577744 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1420 # Number of float alu accesses -system.cpu1.num_func_calls 1993621 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2230861 # number of instructions that are conditional controls -system.cpu1.num_int_insts 18577797 # number of integer instructions +system.cpu1.num_func_calls 1993615 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2230860 # number of instructions that are conditional controls +system.cpu1.num_int_insts 18577744 # number of integer instructions system.cpu1.num_fp_insts 1420 # number of float instructions -system.cpu1.num_int_register_reads 34369600 # number of times the integer registers were read -system.cpu1.num_int_register_writes 13035963 # number of times the integer registers were written +system.cpu1.num_int_register_reads 34369524 # number of times the integer registers were read +system.cpu1.num_int_register_writes 13035923 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1160 # number of times the floating registers were read system.cpu1.num_fp_register_writes 260 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 76091586 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 7577345 # number of times the CC registers were written -system.cpu1.num_mem_refs 6800182 # number of memory refs -system.cpu1.num_load_insts 3918123 # Number of load instructions -system.cpu1.num_store_insts 2882059 # Number of store instructions -system.cpu1.num_idle_cycles 136636530.852378 # Number of idle cycles -system.cpu1.num_busy_cycles 7373372.147622 # Number of busy cycles +system.cpu1.num_cc_register_reads 76091406 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 7577340 # number of times the CC registers were written +system.cpu1.num_mem_refs 6800165 # number of memory refs +system.cpu1.num_load_insts 3918117 # Number of load instructions +system.cpu1.num_store_insts 2882048 # Number of store instructions +system.cpu1.num_idle_cycles 136636530.804008 # Number of idle cycles +system.cpu1.num_busy_cycles 7373372.195992 # Number of busy cycles system.cpu1.not_idle_fraction 0.051200 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.948800 # Percentage of idle cycles -system.cpu1.Branches 4337148 # Number of branches fetched +system.cpu1.Branches 4337141 # Number of branches fetched system.cpu1.op_class::No_OpClass 23 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 14686036 68.30% 68.30% # Class of executed instruction +system.cpu1.op_class::IntAlu 14685999 68.30% 68.30% # Class of executed instruction system.cpu1.op_class::IntMult 16352 0.08% 68.37% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 68.37% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 68.37% # Class of executed instruction @@ -1333,11 +1319,11 @@ system.cpu1.op_class::SimdFloatMisc 955 0.00% 68.38% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 68.38% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.38% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.38% # Class of executed instruction -system.cpu1.op_class::MemRead 3918123 18.22% 86.60% # Class of executed instruction -system.cpu1.op_class::MemWrite 2882059 13.40% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 3918117 18.22% 86.60% # Class of executed instruction +system.cpu1.op_class::MemWrite 2882048 13.40% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21503548 # Class of executed instruction +system.cpu1.op_class::total 21503494 # Class of executed instruction system.cpu2.branchPred.lookups 5770264 # Number of BP lookups system.cpu2.branchPred.condPredicted 2970192 # Number of conditional branches predicted system.cpu2.branchPred.condIncorrect 504477 # Number of conditional branches incorrect @@ -1517,7 +1503,7 @@ system.cpu2.itb.inst_accesses 10824992 # IT system.cpu2.itb.hits 10823576 # DTB hits system.cpu2.itb.misses 1416 # DTB misses system.cpu2.itb.accesses 10824992 # DTB accesses -system.cpu2.numCycles 1395003779 # number of cpu cycles simulated +system.cpu2.numCycles 1395003781 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu2.committedInsts 20361751 # Number of instructions committed @@ -1564,20 +1550,20 @@ system.cpu2.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu2.op_class_0::total 24653563 # Class of committed instruction system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 42378112 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 1352625667 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 13251998 # Number of BP lookups -system.cpu3.branchPred.condPredicted 7208175 # Number of conditional branches predicted +system.cpu2.tickCycles 42378126 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 1352625655 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 13252062 # Number of BP lookups +system.cpu3.branchPred.condPredicted 7208218 # Number of conditional branches predicted system.cpu3.branchPred.condIncorrect 300007 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 8273745 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 4241517 # Number of BTB hits +system.cpu3.branchPred.BTBLookups 8273793 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 4241536 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 51.264778 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 3096619 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 51.264710 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 3096631 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 16788 # Number of incorrect RAS predictions. -system.cpu3.branchPred.indirectLookups 2038227 # Number of indirect predictor lookups. -system.cpu3.branchPred.indirectHits 1978271 # Number of indirect target hits. -system.cpu3.branchPred.indirectMisses 59956 # Number of indirect misses. +system.cpu3.branchPred.indirectLookups 2038250 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 1978281 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 59969 # Number of indirect misses. system.cpu3.branchPredindirectMispredicted 18256 # Number of mispredicted indirect branches. system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1608,15 +1594,15 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.walks 33988 # Table walker walks requested -system.cpu3.dtb.walker.walksShort 33988 # Table walker walks initiated with short descriptors -system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11189 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walks 33989 # Table walker walks requested +system.cpu3.dtb.walker.walksShort 33989 # Table walker walks initiated with short descriptors +system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11190 # Level at which table walker walks with short descriptors terminate system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 8109 # Level at which table walker walks with short descriptors terminate system.cpu3.dtb.walker.walksSquashedBefore 14690 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 19298 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 517.203855 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 3689.785170 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-16383 19110 99.03% 99.03% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::samples 19299 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 517.177056 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 3689.691447 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-16383 19111 99.03% 99.03% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::16384-32767 146 0.76% 99.78% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::32768-49151 30 0.16% 99.94% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::49152-65535 4 0.02% 99.96% # Table walker wait (enqueue to first request) latency @@ -1625,7 +1611,7 @@ system.cpu3.dtb.walker.walkWaitTime::81920-98303 2 0.01% 99. system.cpu3.dtb.walker.walkWaitTime::98304-114687 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::114688-131071 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::147456-163839 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 19298 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 19299 # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkCompletionTime::samples 6381 # Table walker service (enqueue to completion) latency system.cpu3.dtb.walker.walkCompletionTime::mean 13105.939508 # Table walker service (enqueue to completion) latency system.cpu3.dtb.walker.walkCompletionTime::gmean 10791.784480 # Table walker service (enqueue to completion) latency @@ -1636,9 +1622,9 @@ system.cpu3.dtb.walker.walkCompletionTime::65536-98303 1 0.02% system.cpu3.dtb.walker.walkCompletionTime::131072-163839 1 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu3.dtb.walker.walkCompletionTime::360448-393215 1 0.02% 100.00% # Table walker service (enqueue to completion) latency system.cpu3.dtb.walker.walkCompletionTime::total 6381 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -8047267064 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.135073 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-1 -8095966564 100.61% 100.61% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::samples -8047359064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.134723 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-1 -8096058564 100.61% 100.61% # Table walker pending requests distribution system.cpu3.dtb.walker.walksPending::2-3 33943000 -0.42% 100.18% # Table walker pending requests distribution system.cpu3.dtb.walker.walksPending::4-5 7702500 -0.10% 100.09% # Table walker pending requests distribution system.cpu3.dtb.walker.walksPending::6-7 2846000 -0.04% 100.05% # Table walker pending requests distribution @@ -1654,22 +1640,22 @@ system.cpu3.dtb.walker.walksPending::24-25 64500 -0.00% 100.00% # system.cpu3.dtb.walker.walksPending::26-27 35000 -0.00% 100.00% # Table walker pending requests distribution system.cpu3.dtb.walker.walksPending::28-29 17500 -0.00% 100.00% # Table walker pending requests distribution system.cpu3.dtb.walker.walksPending::30-31 59500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -8047267064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -8047359064 # Table walker pending requests distribution system.cpu3.dtb.walker.walkPageSizes::4K 1874 70.21% 70.21% # Table walker page sizes translated system.cpu3.dtb.walker.walkPageSizes::1M 795 29.79% 100.00% # Table walker page sizes translated system.cpu3.dtb.walker.walkPageSizes::total 2669 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 33988 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 33989 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 33988 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 33989 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2669 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2669 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 36657 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 36658 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 7187515 # DTB read hits -system.cpu3.dtb.read_misses 29422 # DTB read misses -system.cpu3.dtb.write_hits 5346412 # DTB write hits +system.cpu3.dtb.read_hits 7187448 # DTB read hits +system.cpu3.dtb.read_misses 29423 # DTB read misses +system.cpu3.dtb.write_hits 5346423 # DTB write hits system.cpu3.dtb.write_misses 4566 # DTB write misses system.cpu3.dtb.flush_tlb 162 # Number of times complete TLB was flushed system.cpu3.dtb.flush_tlb_mva 274 # Number of times TLB was flushed by MVA @@ -1680,12 +1666,12 @@ system.cpu3.dtb.align_faults 451 # Nu system.cpu3.dtb.prefetch_faults 735 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu3.dtb.perms_faults 408 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 7216937 # DTB read accesses -system.cpu3.dtb.write_accesses 5350978 # DTB write accesses +system.cpu3.dtb.read_accesses 7216871 # DTB read accesses +system.cpu3.dtb.write_accesses 5350989 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 12533927 # DTB hits -system.cpu3.dtb.misses 33988 # DTB misses -system.cpu3.dtb.accesses 12567915 # DTB accesses +system.cpu3.dtb.hits 12533871 # DTB hits +system.cpu3.dtb.misses 33989 # DTB misses +system.cpu3.dtb.accesses 12567860 # DTB accesses system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1755,16 +1741,16 @@ system.cpu3.itb.walker.walkCompletionTime::40960-45055 1 0.06% system.cpu3.itb.walker.walkCompletionTime::45056-49151 1 0.06% 99.89% # Table walker service (enqueue to completion) latency system.cpu3.itb.walker.walkCompletionTime::49152-53247 2 0.11% 100.00% # Table walker service (enqueue to completion) latency system.cpu3.itb.walker.walkCompletionTime::total 1793 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -8048536564 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.273748 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.444975 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::samples -8048628564 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.273756 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.444979 # Table walker pending requests distribution system.cpu3.itb.walker.walksPending::0 -5842963052 72.60% 72.60% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -2207207512 27.42% 100.02% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -2207299512 27.42% 100.02% # Table walker pending requests distribution system.cpu3.itb.walker.walksPending::2 1197000 -0.01% 100.01% # Table walker pending requests distribution system.cpu3.itb.walker.walksPending::3 240000 -0.00% 100.00% # Table walker pending requests distribution system.cpu3.itb.walker.walksPending::4 159500 -0.00% 100.00% # Table walker pending requests distribution system.cpu3.itb.walker.walksPending::5 37500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -8048536564 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -8048628564 # Table walker pending requests distribution system.cpu3.itb.walker.walkPageSizes::4K 959 73.04% 73.04% # Table walker page sizes translated system.cpu3.itb.walker.walkPageSizes::1M 354 26.96% 100.00% # Table walker page sizes translated system.cpu3.itb.walker.walkPageSizes::total 1313 # Table walker page sizes translated @@ -1775,7 +1761,7 @@ system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1313 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1313 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin::total 5899 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 9766961 # ITB inst hits +system.cpu3.itb.inst_hits 9766986 # ITB inst hits system.cpu3.itb.inst_misses 4586 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses @@ -1792,106 +1778,106 @@ system.cpu3.itb.domain_faults 0 # Nu system.cpu3.itb.perms_faults 793 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 9771547 # ITB inst accesses -system.cpu3.itb.hits 9766961 # DTB hits +system.cpu3.itb.inst_accesses 9771572 # ITB inst accesses +system.cpu3.itb.hits 9766986 # DTB hits system.cpu3.itb.misses 4586 # DTB misses -system.cpu3.itb.accesses 9771547 # DTB accesses -system.cpu3.numCycles 57688008 # number of cpu cycles simulated +system.cpu3.itb.accesses 9771572 # DTB accesses +system.cpu3.numCycles 57688006 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 20811667 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 52032939 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 13251998 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 9316407 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 33930226 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 1581195 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 20811649 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 52033022 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 13252062 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 9316448 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 33930227 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 1581201 # Number of cycles fetch has spent squashing system.cpu3.fetch.TlbCycles 68181 # Number of cycles fetch has spent waiting for tlb system.cpu3.fetch.MiscStallCycles 837 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.PendingDrainCycles 231 # Number of cycles fetch has spent waiting on pipes to drain system.cpu3.fetch.PendingTrapStallCycles 120341 # Number of stall cycles due to pending traps system.cpu3.fetch.PendingQuiesceStallCycles 80383 # Number of stall cycles due to pending quiesce instructions system.cpu3.fetch.IcacheWaitRetryStallCycles 479 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 9765461 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 207701 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.CacheLines 9765486 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 207700 # Number of outstanding Icache misses that were squashed system.cpu3.fetch.ItlbSquashes 2399 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 55802921 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.126478 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.271735 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::samples 55802907 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.126480 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.271736 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 41696635 74.72% 74.72% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 1836227 3.29% 78.01% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 1165179 2.09% 80.10% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3688200 6.61% 86.71% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 906119 1.62% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 549240 0.98% 89.32% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2914414 5.22% 94.54% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 602851 1.08% 95.62% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 2444056 4.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 41696580 74.72% 74.72% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 1836235 3.29% 78.01% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 1165184 2.09% 80.10% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3688211 6.61% 86.71% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 906128 1.62% 88.33% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 549241 0.98% 89.32% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 2914438 5.22% 94.54% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 602830 1.08% 95.62% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2444060 4.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 55802921 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.229718 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.901971 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 14568500 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 31866419 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 7772530 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 890722 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 704491 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 971896 # Number of times decode resolved a branch +system.cpu3.fetch.rateDist::total 55802907 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.229720 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.901973 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 14568551 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 31866325 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 7772560 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 890718 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 704494 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 971899 # Number of times decode resolved a branch system.cpu3.decode.BranchMispred 87220 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 44589995 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 289462 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 704491 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 15048240 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 3770694 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 21829138 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 8174722 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 6275353 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 42740341 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 1149 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 970338 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 89122 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 4852694 # Number of times rename has blocked due to SQ full -system.cpu3.rename.RenamedOperands 44469906 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 196241867 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 47658111 # Number of integer rename lookups +system.cpu3.decode.DecodedInsts 44590073 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 289455 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 704494 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 15048291 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 3770246 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 21829644 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 8174749 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 6275200 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 42740400 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 1148 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 970300 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 89126 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 4852570 # Number of times rename has blocked due to SQ full +system.cpu3.rename.RenamedOperands 44469975 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 196242063 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 47658053 # Number of integer rename lookups system.cpu3.rename.fp_rename_lookups 4195 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 37088315 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 7381591 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 715058 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 665415 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 5054904 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 7671721 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 5900836 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 1096117 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 1546300 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 41143792 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 502169 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 39136227 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 53751 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 5932360 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 13678384 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.rename.CommittedMaps 37088424 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 7381551 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 715073 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 665430 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 5054867 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 7671703 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 5900822 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 1096118 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 1546348 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 41143800 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 502182 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 39136171 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 53747 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 5932287 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 13678209 # Number of squashed operands that are examined and possibly removed from graph system.cpu3.iq.iqSquashedNonSpecRemoved 53132 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 55802921 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::samples 55802907 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::mean 0.701329 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.406591 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.406589 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 40242426 72.12% 72.12% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 5178735 9.28% 81.40% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 3976743 7.13% 88.52% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 3203415 5.74% 94.26% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 1255788 2.25% 96.51% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 764372 1.37% 97.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 832267 1.49% 99.37% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 238253 0.43% 99.80% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 110922 0.20% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 40242389 72.12% 72.12% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 5178782 9.28% 81.40% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 3976738 7.13% 88.52% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 3203416 5.74% 94.26% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 1255770 2.25% 96.51% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 764374 1.37% 97.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 832269 1.49% 99.37% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 238251 0.43% 99.80% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 110918 0.20% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 55802921 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 55802907 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 55579 9.37% 9.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 55578 9.37% 9.37% # attempts to use FU when none available system.cpu3.iq.fu_full::IntMult 0 0.00% 9.37% # attempts to use FU when none available system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.37% # attempts to use FU when none available system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.37% # attempts to use FU when none available @@ -1920,12 +1906,12 @@ system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.37% # at system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.37% # attempts to use FU when none available system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.37% # attempts to use FU when none available system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.37% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 279420 47.11% 56.48% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 258160 43.52% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 279414 47.11% 56.48% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 258161 43.52% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 84 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 26095739 66.68% 66.68% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 26095745 66.68% 66.68% # Type of FU issued system.cpu3.iq.FU_type_0::IntMult 29921 0.08% 66.76% # Type of FU issued system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.76% # Type of FU issued system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.76% # Type of FU issued @@ -1954,94 +1940,94 @@ system.cpu3.iq.FU_type_0::SimdFloatMisc 2385 0.01% 66.76% # Ty system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.76% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 66.76% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 7397588 18.90% 85.66% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 5610508 14.34% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 7397516 18.90% 85.66% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 5610518 14.34% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 39136227 # Type of FU issued -system.cpu3.iq.rate 0.678412 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 593159 # FU busy when requested +system.cpu3.iq.FU_type_0::total 39136171 # Type of FU issued +system.cpu3.iq.rate 0.678411 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 593153 # FU busy when requested system.cpu3.iq.fu_busy_rate 0.015156 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 134713506 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 47601839 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 37987745 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.int_inst_queue_reads 134713370 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 47601786 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 37987762 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 8779 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 5136 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 3873 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 39724596 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 39724534 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 4706 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 167565 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 167566 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1160512 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 1106 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 29283 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 565980 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 1160486 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 1105 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 29281 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 565962 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 108566 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 42617 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 108568 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 42515 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 704491 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 3164370 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 480380 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 41688366 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 67674 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 7671721 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 5900836 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 259515 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 22770 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 451545 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 29283 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 127479 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 130166 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 257645 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 38819065 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 7269277 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 283258 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 704494 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 3163832 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 480485 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 41688387 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 67679 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 7671703 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 5900822 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 259528 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 22774 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 451647 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 29281 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 127480 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 130164 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 257644 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 38819012 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 7269209 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 283254 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed system.cpu3.iew.exec_nop 42405 # number of nop insts executed -system.cpu3.iew.exec_refs 12824699 # number of memory reference insts executed -system.cpu3.iew.exec_branches 7229147 # Number of branches executed -system.cpu3.iew.exec_stores 5555422 # Number of stores executed -system.cpu3.iew.exec_rate 0.672914 # Inst execution rate -system.cpu3.iew.wb_sent 38534574 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 37991618 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 19895902 # num instructions producing a value -system.cpu3.iew.wb_consumers 34654427 # num instructions consuming a value -system.cpu3.iew.wb_rate 0.658570 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.574123 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 5941681 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 449037 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.iew.exec_refs 12824644 # number of memory reference insts executed +system.cpu3.iew.exec_branches 7229166 # Number of branches executed +system.cpu3.iew.exec_stores 5555435 # Number of stores executed +system.cpu3.iew.exec_rate 0.672913 # Inst execution rate +system.cpu3.iew.wb_sent 38534594 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 37991635 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 19895864 # num instructions producing a value +system.cpu3.iew.wb_consumers 34654258 # num instructions consuming a value +system.cpu3.iew.wb_rate 0.658571 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.574125 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 5941608 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 449050 # The number of times commit has been forced to stall to communicate backwards system.cpu3.commit.branchMispredicts 213879 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 54520381 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.655520 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::samples 54520380 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.655522 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::stdev 1.547792 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 40723522 74.69% 74.69% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 6130634 11.24% 85.94% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 3105134 5.70% 91.63% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 1318169 2.42% 94.05% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 725183 1.33% 95.38% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 499193 0.92% 96.30% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 937316 1.72% 98.02% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 226626 0.42% 98.43% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 854604 1.57% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 40723432 74.69% 74.69% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 6130706 11.24% 85.94% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 3105147 5.70% 91.63% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 1318175 2.42% 94.05% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 725189 1.33% 95.38% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 499185 0.92% 96.30% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 937323 1.72% 98.02% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 226618 0.42% 98.43% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 854605 1.57% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 54520381 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 29254199 # Number of instructions committed -system.cpu3.commit.committedOps 35739216 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 54520380 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 29254285 # Number of instructions committed +system.cpu3.commit.committedOps 35739310 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 11846065 # Number of memory references committed -system.cpu3.commit.loads 6511209 # Number of loads committed +system.cpu3.commit.refs 11846077 # Number of memory references committed +system.cpu3.commit.loads 6511217 # Number of loads committed system.cpu3.commit.membars 174051 # Number of memory barriers committed -system.cpu3.commit.branches 6823805 # Number of branches committed +system.cpu3.commit.branches 6823843 # Number of branches committed system.cpu3.commit.fp_insts 3728 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 31222090 # Number of committed integer instructions. -system.cpu3.commit.function_calls 1239495 # Number of function calls committed. +system.cpu3.commit.int_insts 31222167 # Number of committed integer instructions. +system.cpu3.commit.function_calls 1239499 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 23861802 66.77% 66.77% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 23861884 66.77% 66.77% # Class of committed instruction system.cpu3.commit.op_class_0::IntMult 28964 0.08% 66.85% # Class of committed instruction system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.85% # Class of committed instruction system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.85% # Class of committed instruction @@ -2070,31 +2056,31 @@ system.cpu3.commit.op_class_0::SimdFloatMisc 2385 0.01% 66.85% system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.85% # Class of committed instruction system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.85% # Class of committed instruction system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.85% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 6511209 18.22% 85.07% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 5334856 14.93% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 6511217 18.22% 85.07% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 5334860 14.93% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 35739216 # Class of committed instruction -system.cpu3.commit.bw_lim_events 854604 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 89694984 # The number of ROB reads -system.cpu3.rob.rob_writes 84644228 # The number of ROB writes -system.cpu3.timesIdled 227110 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1885087 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.commit.op_class_0::total 35739310 # Class of committed instruction +system.cpu3.commit.bw_lim_events 854605 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 89694977 # The number of ROB reads +system.cpu3.rob.rob_writes 84644260 # The number of ROB writes +system.cpu3.timesIdled 227108 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1885099 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu3.quiesceCycles 5160958859 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 29228584 # Number of Instructions Simulated -system.cpu3.committedOps 35713601 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.973685 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.973685 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.506667 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.506667 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 42269804 # number of integer regfile reads -system.cpu3.int_regfile_writes 24060507 # number of integer regfile writes +system.cpu3.committedInsts 29228670 # Number of Instructions Simulated +system.cpu3.committedOps 35713695 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.973679 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.973679 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.506668 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.506668 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 42269766 # number of integer regfile reads +system.cpu3.int_regfile_writes 24060528 # number of integer regfile writes system.cpu3.fp_regfile_reads 14520 # number of floating regfile reads system.cpu3.fp_regfile_writes 12259 # number of floating regfile writes -system.cpu3.cc_regfile_reads 137213750 # number of cc regfile reads -system.cpu3.cc_regfile_writes 14769664 # number of cc regfile writes -system.cpu3.misc_regfile_reads 75722045 # number of misc regfile reads -system.cpu3.misc_regfile_writes 336113 # number of misc regfile writes +system.cpu3.cc_regfile_reads 137213612 # number of cc regfile reads +system.cpu3.cc_regfile_writes 14769581 # number of cc regfile writes +system.cpu3.misc_regfile_reads 75722157 # number of misc regfile reads +system.cpu3.misc_regfile_writes 336126 # number of misc regfile writes system.iobus.trans_dist::ReadReq 30181 # Transaction distribution system.iobus.trans_dist::ReadResp 30181 # Transaction distribution system.iobus.trans_dist::WriteReq 59010 # Transaction distribution @@ -2163,7 +2149,7 @@ system.iobus.reqLayer19.occupancy 3000 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 3863000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 3864000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 22351500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2189,109 +2175,110 @@ system.iocache.tags.tag_accesses 328227 # Nu system.iocache.tags.data_accesses 328227 # Number of data accesses system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits +system.iocache.demand_hits::realview.ide 29 # number of demand (read+write) hits +system.iocache.demand_hits::total 29 # number of demand (read+write) hits +system.iocache.overall_hits::realview.ide 29 # number of overall hits +system.iocache.overall_hits::total 29 # number of overall hits system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses system.iocache.ReadReq_misses::total 249 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36195 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36195 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses -system.iocache.demand_misses::total 249 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 249 # number of overall misses -system.iocache.overall_misses::total 249 # number of overall misses +system.iocache.demand_misses::realview.ide 36444 # number of demand (read+write) misses +system.iocache.demand_misses::total 36444 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36444 # number of overall misses +system.iocache.overall_misses::total 36444 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 17512919 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 17512919 # number of ReadReq miss cycles system.iocache.WriteLineReq_miss_latency::realview.ide 1907451098 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 1907451098 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 17512919 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 17512919 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 17512919 # number of overall miss cycles -system.iocache.overall_miss_latency::total 17512919 # number of overall miss cycles +system.iocache.demand_miss_latency::realview.ide 1924964017 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1924964017 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 1924964017 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1924964017 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36473 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36473 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36473 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36473 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 0.999199 # miss rate for WriteLineReq accesses system.iocache.WriteLineReq_miss_rate::total 0.999199 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.demand_miss_rate::realview.ide 0.999205 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 0.999205 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ide 0.999205 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 0.999205 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 70333.008032 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 70333.008032 # average ReadReq miss latency system.iocache.WriteLineReq_avg_miss_latency::realview.ide 52699.298190 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 52699.298190 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 70333.008032 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 70333.008032 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 70333.008032 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 70333.008032 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 52819.778756 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 52819.778756 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 52819.778756 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 52819.778756 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36160 # number of writebacks system.iocache.writebacks::total 36160 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 148 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 148 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 15187 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 15187 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 148 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 148 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 148 # number of overall MSHR misses +system.iocache.demand_mshr_misses::realview.ide 15335 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 15335 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 15335 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 15335 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 10112919 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 10112919 # number of ReadReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 1147424968 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 1147424968 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 10112919 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10112919 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 10112919 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10112919 # number of overall MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1157537887 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1157537887 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1157537887 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1157537887 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.594378 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.419252 # mshr miss rate for WriteLineReq accesses system.iocache.WriteLineReq_mshr_miss_rate::total 0.419252 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.594378 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.594378 # mshr miss rate for overall accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.420448 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.420448 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.420448 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.420448 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68330.533784 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 68330.533784 # average ReadReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75553.102522 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75553.102522 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68330.533784 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68330.533784 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68330.533784 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68330.533784 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75483.396609 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75483.396609 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75483.396609 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75483.396609 # average overall mshr miss latency system.l2c.tags.replacements 103654 # number of replacements -system.l2c.tags.tagsinuse 65094.562586 # Cycle average of tags in use -system.l2c.tags.total_refs 5149242 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 65094.562604 # Cycle average of tags in use +system.l2c.tags.total_refs 5149240 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 168905 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 30.486025 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 30.486013 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 80133862000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 49018.245054 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 49018.245060 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.971846 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 4276.002230 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.data 2253.870491 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.966972 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 903.622290 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 882.214682 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 882.214681 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu2.dtb.walker 22.046662 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu2.inst 1923.753709 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu2.data 720.306234 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu3.dtb.walker 49.949258 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 3365.651455 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 1676.961608 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 3365.651463 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 1676.961612 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.747959 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy @@ -2317,19 +2304,19 @@ system.l2c.tags.age_task_id_blocks_1024::3 7607 # system.l2c.tags.age_task_id_blocks_1024::4 55305 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000977 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.994675 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45502420 # Number of tag accesses -system.l2c.tags.data_accesses 45502420 # Number of data accesses +system.l2c.tags.tag_accesses 45502395 # Number of tag accesses +system.l2c.tags.data_accesses 45502395 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 4144 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 2033 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 1722 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 868 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.dtb.walker 13393 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.itb.walker 1189 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 21090 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.dtb.walker 21091 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.itb.walker 4127 # number of ReadReq hits -system.l2c.ReadReq_hits::total 48566 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 692124 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 692124 # number of WritebackDirty hits +system.l2c.ReadReq_hits::total 48567 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 692123 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 692123 # number of WritebackDirty hits system.l2c.WritebackClean_hits::writebacks 1939703 # number of WritebackClean hits system.l2c.WritebackClean_hits::total 1939703 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits @@ -2343,8 +2330,8 @@ system.l2c.SCUpgradeReq_hits::total 19 # nu system.l2c.ReadExReq_hits::cpu0.data 66572 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 17866 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu2.data 28004 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3.data 44211 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 156653 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3.data 44210 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 156652 # number of ReadExReq hits system.l2c.ReadCleanReq_hits::cpu0.inst 721971 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::cpu1.inst 204101 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::cpu2.inst 492422 # number of ReadCleanReq hits @@ -2353,8 +2340,8 @@ system.l2c.ReadCleanReq_hits::total 1956655 # nu system.l2c.ReadSharedReq_hits::cpu0.data 211223 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 72596 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu2.data 101112 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 137862 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 522793 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3.data 137861 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 522792 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.dtb.walker 4144 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 2033 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 721971 # number of demand (read+write) hits @@ -2367,11 +2354,11 @@ system.l2c.demand_hits::cpu2.dtb.walker 13393 # nu system.l2c.demand_hits::cpu2.itb.walker 1189 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.inst 492422 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 129116 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.dtb.walker 21090 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.dtb.walker 21091 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.itb.walker 4127 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.inst 538161 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 182073 # number of demand (read+write) hits -system.l2c.demand_hits::total 2684667 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 182071 # number of demand (read+write) hits +system.l2c.demand_hits::total 2684666 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 4144 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 2033 # number of overall hits system.l2c.overall_hits::cpu0.inst 721971 # number of overall hits @@ -2384,11 +2371,11 @@ system.l2c.overall_hits::cpu2.dtb.walker 13393 # nu system.l2c.overall_hits::cpu2.itb.walker 1189 # number of overall hits system.l2c.overall_hits::cpu2.inst 492422 # number of overall hits system.l2c.overall_hits::cpu2.data 129116 # number of overall hits -system.l2c.overall_hits::cpu3.dtb.walker 21090 # number of overall hits +system.l2c.overall_hits::cpu3.dtb.walker 21091 # number of overall hits system.l2c.overall_hits::cpu3.itb.walker 4127 # number of overall hits system.l2c.overall_hits::cpu3.inst 538161 # number of overall hits -system.l2c.overall_hits::cpu3.data 182073 # number of overall hits -system.l2c.overall_hits::total 2684667 # number of overall hits +system.l2c.overall_hits::cpu3.data 182071 # number of overall hits +system.l2c.overall_hits::total 2684666 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses @@ -2455,49 +2442,49 @@ system.l2c.UpgradeReq_miss_latency::cpu3.data 1012500 system.l2c.UpgradeReq_miss_latency::total 1325500 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu3.data 317500 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 317500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1517069500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 3110086000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 5724333000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10351488500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1517126000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 3110079500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 5724450000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10351655500 # number of ReadExReq miss cycles system.l2c.ReadCleanReq_miss_latency::cpu1.inst 241264500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu2.inst 638292000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu3.inst 866799499 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1746355999 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 638292500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu3.inst 866843998 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1746400998 # number of ReadCleanReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.data 341211500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu2.data 263338500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3.data 578560500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 1183110500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3.data 578680000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 1183230000 # number of ReadSharedReq miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 132500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 241264500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1858281000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1858337500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.dtb.walker 3451000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 638292000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 3373424500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 638292500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 3373418000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu3.dtb.walker 9023500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 866799499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 6302893500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 13293561999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 866843998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 6303130000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 13293893498 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 132500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 241264500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1858281000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1858337500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.dtb.walker 3451000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 638292000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 3373424500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 638292500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 3373418000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu3.dtb.walker 9023500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 866799499 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 6302893500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 13293561999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 866843998 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 6303130000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 13293893498 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 4147 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 2034 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 1723 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 868 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.dtb.walker 13419 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.itb.walker 1189 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.dtb.walker 21156 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.dtb.walker 21157 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.itb.walker 4127 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 48663 # number of ReadReq accesses(hits+misses) -system.l2c.WritebackDirty_accesses::writebacks 692124 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 692124 # number of WritebackDirty accesses(hits+misses) +system.l2c.ReadReq_accesses::total 48664 # number of ReadReq accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 692123 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 692123 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackClean_accesses::writebacks 1939703 # number of WritebackClean accesses(hits+misses) system.l2c.WritebackClean_accesses::total 1939703 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1127 # number of UpgradeReq accesses(hits+misses) @@ -2511,8 +2498,8 @@ system.l2c.SCUpgradeReq_accesses::total 27 # nu system.l2c.ReadExReq_accesses::cpu0.data 126943 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 29662 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 52385 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 87366 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296356 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 87365 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296355 # number of ReadExReq accesses(hits+misses) system.l2c.ReadCleanReq_accesses::cpu0.inst 729845 # number of ReadCleanReq accesses(hits+misses) system.l2c.ReadCleanReq_accesses::cpu1.inst 205934 # number of ReadCleanReq accesses(hits+misses) system.l2c.ReadCleanReq_accesses::cpu2.inst 497236 # number of ReadCleanReq accesses(hits+misses) @@ -2521,8 +2508,8 @@ system.l2c.ReadCleanReq_accesses::total 1977715 # nu system.l2c.ReadSharedReq_accesses::cpu0.data 217252 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.data 75187 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu2.data 103095 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3.data 142064 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 537598 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3.data 142063 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 537597 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 4147 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 2034 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 729845 # number of demand (read+write) accesses @@ -2535,11 +2522,11 @@ system.l2c.demand_accesses::cpu2.dtb.walker 13419 # system.l2c.demand_accesses::cpu2.itb.walker 1189 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.inst 497236 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 155480 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.dtb.walker 21156 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.dtb.walker 21157 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.itb.walker 4127 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.inst 544700 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 229430 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2860332 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 229428 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2860331 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 4147 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 2034 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 729845 # number of overall (read+write) accesses @@ -2552,11 +2539,11 @@ system.l2c.overall_accesses::cpu2.dtb.walker 13419 system.l2c.overall_accesses::cpu2.itb.walker 1189 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.inst 497236 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.data 155480 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.dtb.walker 21156 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.dtb.walker 21157 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.itb.walker 4127 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.inst 544700 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 229430 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2860332 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 229428 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2860331 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000723 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000492 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000580 # miss rate for ReadReq accesses @@ -2573,8 +2560,8 @@ system.l2c.SCUpgradeReq_miss_rate::total 0.296296 # mi system.l2c.ReadExReq_miss_rate::cpu0.data 0.475576 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.397681 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 0.465419 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 0.493956 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.471403 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 0.493962 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.471404 # miss rate for ReadExReq accesses system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.010789 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.008901 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.009682 # miss rate for ReadCleanReq accesses @@ -2597,7 +2584,7 @@ system.l2c.demand_miss_rate::cpu2.inst 0.009682 # mi system.l2c.demand_miss_rate::cpu2.data 0.169565 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.dtb.walker 0.003120 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.inst 0.012005 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.206412 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.206413 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.061414 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000723 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000492 # miss rate for overall accesses @@ -2611,7 +2598,7 @@ system.l2c.overall_miss_rate::cpu2.inst 0.009682 # mi system.l2c.overall_miss_rate::cpu2.data 0.169565 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.dtb.walker 0.003120 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.inst 0.012005 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.206412 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.206413 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.061414 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 132500 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 132730.769231 # average ReadReq miss latency @@ -2623,46 +2610,44 @@ system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 1398.480663 system.l2c.UpgradeReq_avg_miss_latency::total 475.601005 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data 39687.500000 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 39687.500000 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 128608.808071 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 127561.871949 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 132645.881126 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 74096.393778 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 128613.597830 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 127561.605348 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 132648.592284 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 74097.589171 # average ReadExReq miss latency system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131622.749591 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 132590.776901 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 132558.418566 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 82922.886942 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 132590.880764 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 132565.223735 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 82925.023647 # average ReadCleanReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131691.045928 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 132798.033283 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 137686.934793 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 79912.901047 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 137715.373632 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 79920.972644 # average ReadSharedReq miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132500 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 131622.749591 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 129163.897963 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 129167.825120 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 132730.769231 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 132590.776901 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 127955.716128 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 132590.880764 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 127955.469580 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 136719.696970 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 132558.418566 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 133093.175243 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 75675.643976 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 132565.223735 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 133098.169225 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 75677.531085 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132500 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 131622.749591 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 129163.897963 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 129167.825120 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 132730.769231 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 132590.776901 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 127955.716128 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 132590.880764 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 127955.469580 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 136719.696970 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 132558.418566 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 133093.175243 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 75675.643976 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 132565.223735 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 133098.169225 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 75677.531085 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 94985 # number of writebacks system.l2c.writebacks::total 94985 # number of writebacks system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 3 # number of ReadCleanReq MSHR hits @@ -2740,55 +2725,51 @@ system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 3191000 system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker 8363500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 11677000 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 25361500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 39106500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 39113500 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 49225500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 113693500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 113700500 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data 550500 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 550500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1399109500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2866276000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 5292783000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 9558168500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1399166000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2866269500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 5292900000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 9558335500 # number of ReadExReq MSHR miss cycles system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 222934500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 590021500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 800941503 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1613897503 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 590022000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 800986002 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1613942502 # number of ReadCleanReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 315301500 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 241631500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 531706501 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 1088639501 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 531826001 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 1088759001 # number of ReadSharedReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 122500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 222934500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1714411000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1714467500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 3191000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 590021500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 3107907500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 590022000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 3107901000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker 8363500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 800941503 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 5824489501 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 12272382504 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 800986002 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 5824726001 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 12272714003 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 122500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 222934500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1714411000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1714467500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 3191000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 590021500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 3107907500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 590022000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 3107901000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 8363500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 800941503 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 5824489501 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 12272382504 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 800986002 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 5824726001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 12272714003 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 584851500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1048585500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 1703786000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3337223000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 483931000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 810126000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data 1331950000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2626007000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1068782500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 1858711500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3.data 3035736000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5963230000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 1703789000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3337226000 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 584851500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 1048585500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3.data 1703789000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3337226000 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000580 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.001938 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003120 # mshr miss rate for ReadReq accesses @@ -2801,7 +2782,7 @@ system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.320000 system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.296296 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.397681 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.465419 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.493956 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.493962 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.267692 # mshr miss rate for ReadExReq accesses system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.008901 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.009675 # mshr miss rate for ReadCleanReq accesses @@ -2819,7 +2800,7 @@ system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009675 # system.l2c.demand_mshr_miss_rate::cpu2.data 0.169449 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003120 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.inst 0.011996 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.206228 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.206230 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.035422 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000580 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008901 # mshr miss rate for overall accesses @@ -2829,63 +2810,58 @@ system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009675 system.l2c.overall_mshr_miss_rate::cpu2.data 0.169449 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003120 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.inst 0.011996 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.206228 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.206230 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.035422 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 122730.769231 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 126719.696970 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 125559.139785 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67993.297587 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68011.304348 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68023.478261 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 67991.022099 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67998.504785 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68002.691388 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 68812.500000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68812.500000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 118608.808071 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 117561.871949 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 122645.881126 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 120483.140473 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 118613.597830 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 117561.605348 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 122648.592284 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 120485.245550 # average ReadExReq mshr miss latency system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121622.749591 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 122640.095614 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 122580.578972 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122469.077478 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 122640.199543 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 122587.389348 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122472.492184 # average ReadCleanReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121691.045928 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 122967.684478 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 127814.062740 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 124901.273635 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 127842.788702 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 124914.984052 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121622.749591 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 119163.897963 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 119167.825120 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 122730.769231 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 122640.095614 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 117965.061110 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 122640.199543 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 117964.814393 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 126719.696970 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 122580.578972 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 123100.274775 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 121126.170847 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 122587.389348 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 123105.273190 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 121129.442681 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121622.749591 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 119163.897963 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 119167.825120 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 122730.769231 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 122640.095614 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 117965.061110 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 122640.199543 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 117964.814393 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 126719.696970 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 122580.578972 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 123100.274775 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 121126.170847 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 122587.389348 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 123105.273190 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 121129.442681 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165258.971461 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 187113.758030 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202759.252648 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 190198.506782 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167798.543689 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 186407.271054 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 200867.139195 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189452.925474 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 166399.268255 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 186805.175879 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 201924.704004 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 189869.455854 # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202759.609663 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 190198.677761 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91055.815040 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 105385.477387 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 113329.054144 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 106257.394848 # average overall mshr uncacheable latency system.membus.trans_dist::ReadReq 40114 # Transaction distribution system.membus.trans_dist::ReadResp 76256 # Transaction distribution system.membus.trans_dist::WriteReq 27565 # Transaction distribution @@ -2928,13 +2904,13 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 422579 # Request fanout histogram -system.membus.reqLayer0.occupancy 54357000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 54358000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 681000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 678498 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 480576517 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 480577516 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 576477250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 576478500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 796581 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) @@ -2979,60 +2955,60 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5652845 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2841067 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5652843 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2841066 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 44935 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 620 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 620 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 111946 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 111947 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2627538 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 760858 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 760857 # Transaction distribution system.toL2Bus.trans_dist::WritebackClean 1977299 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 146343 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 146342 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2855 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2881 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296356 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296356 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296355 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296355 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1977848 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 537746 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 537745 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 15186 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5950911 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2624548 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2624542 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 25489 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 101523 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8702471 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 101525 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8702467 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 253157304 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97861305 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97861113 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41336 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 179384 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 351239329 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 179388 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 351239141 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 193521 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4203870 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 4203916 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 0.021594 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.145354 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.145353 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4113091 97.84% 97.84% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4113137 97.84% 97.84% # Request fanout histogram system.toL2Bus.snoop_fanout::1 90779 2.16% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4203870 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3441050999 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4203916 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3441095952 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 260919 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 1872616750 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 760136706 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 760133706 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 11021467 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 48272206 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 48273206 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed |