diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt | 4616 |
1 files changed, 2305 insertions, 2311 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 317b8f2e9..b158166a6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.823751 # Number of seconds simulated -sim_ticks 2823750824500 # Number of ticks simulated -final_tick 2823750824500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.823713 # Number of seconds simulated +sim_ticks 2823712531500 # Number of ticks simulated +final_tick 2823712531500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 215412 # Simulator instruction rate (inst/s) -host_op_rate 261296 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4949093514 # Simulator tick rate (ticks/s) -host_mem_usage 585976 # Number of bytes of host memory used -host_seconds 570.56 # Real time elapsed on the host -sim_insts 122905142 # Number of instructions simulated -sim_ops 149084969 # Number of ops (including micro ops) simulated +host_inst_rate 235362 # Simulator instruction rate (inst/s) +host_op_rate 285496 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5406413351 # Simulator tick rate (ticks/s) +host_mem_usage 591960 # Number of bytes of host memory used +host_seconds 522.29 # Real time elapsed on the host +sim_insts 122926882 # Number of instructions simulated +sim_ops 149111695 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 542180 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3155236 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 537508 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3136100 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 122688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 900352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 121472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 903168 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.dtb.walker 1792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 341632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1990912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 4736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 343232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1991872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 4544 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 381248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 3510400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 387072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 3526656 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10952712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 542180 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 122688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 341632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 381248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1387748 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8236736 # Number of bytes written to this memory +system.physmem.bytes_read::total 10954952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 537508 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 121472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 343232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 387072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1389284 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8237952 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8254260 # Number of bytes written to this memory +system.physmem.bytes_written::total 8255476 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 16925 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 49820 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 16852 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 49521 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1917 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 14068 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 14112 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.dtb.walker 28 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5338 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 31108 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 74 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5363 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 31123 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 71 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 5957 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 54850 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 6048 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 55104 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180109 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 128699 # Number of write requests responded to by this memory +system.physmem.num_reads::total 180144 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 128718 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 133080 # Number of write requests responded to by this memory +system.physmem.num_writes::total 133099 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 113 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 192007 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1117392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 190355 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1110630 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 43449 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 318850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 43019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 319851 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.dtb.walker 635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 120985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 705059 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 121553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 705409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1609 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu3.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 135015 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 1243169 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 137079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 1248943 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3878781 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 192007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 43449 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 120985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 135015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 491456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2916949 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3879627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 190355 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 43019 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 121553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 137079 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 492006 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2917419 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6206 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2923155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2916949 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2923625 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2917419 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 192007 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1123598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 190355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1116836 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 43449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 318850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 43019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 319851 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.dtb.walker 635 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 120985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 705059 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 121553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 705409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1609 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 135015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 1243169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 137079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 1248943 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6801936 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 113342 # Number of read requests accepted -system.physmem.writeReqs 68762 # Number of write requests accepted -system.physmem.readBursts 113342 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 68762 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 7247168 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue -system.physmem.bytesWritten 4399872 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 7253888 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4400768 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6803252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 113749 # Number of read requests accepted +system.physmem.writeReqs 69024 # Number of write requests accepted +system.physmem.readBursts 113749 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 69024 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 7272896 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7040 # Total number of bytes read from write queue +system.physmem.bytesWritten 4416768 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 7279936 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4417536 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 110 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 7506 # Per bank write bursts -system.physmem.perBankRdBursts::1 6787 # Per bank write bursts -system.physmem.perBankRdBursts::2 7407 # Per bank write bursts -system.physmem.perBankRdBursts::3 7543 # Per bank write bursts -system.physmem.perBankRdBursts::4 7335 # Per bank write bursts -system.physmem.perBankRdBursts::5 7022 # Per bank write bursts -system.physmem.perBankRdBursts::6 7619 # Per bank write bursts -system.physmem.perBankRdBursts::7 7707 # Per bank write bursts -system.physmem.perBankRdBursts::8 6869 # Per bank write bursts -system.physmem.perBankRdBursts::9 7531 # Per bank write bursts -system.physmem.perBankRdBursts::10 6987 # Per bank write bursts -system.physmem.perBankRdBursts::11 6354 # Per bank write bursts -system.physmem.perBankRdBursts::12 6401 # Per bank write bursts -system.physmem.perBankRdBursts::13 7189 # Per bank write bursts -system.physmem.perBankRdBursts::14 6831 # Per bank write bursts -system.physmem.perBankRdBursts::15 6149 # Per bank write bursts -system.physmem.perBankWrBursts::0 4366 # Per bank write bursts -system.physmem.perBankWrBursts::1 3966 # Per bank write bursts -system.physmem.perBankWrBursts::2 4487 # Per bank write bursts -system.physmem.perBankWrBursts::3 4689 # Per bank write bursts -system.physmem.perBankWrBursts::4 4379 # Per bank write bursts -system.physmem.perBankWrBursts::5 4312 # Per bank write bursts -system.physmem.perBankWrBursts::6 4615 # Per bank write bursts -system.physmem.perBankWrBursts::7 4485 # Per bank write bursts -system.physmem.perBankWrBursts::8 4160 # Per bank write bursts -system.physmem.perBankWrBursts::9 4849 # Per bank write bursts -system.physmem.perBankWrBursts::10 4371 # Per bank write bursts -system.physmem.perBankWrBursts::11 3905 # Per bank write bursts -system.physmem.perBankWrBursts::12 3814 # Per bank write bursts -system.physmem.perBankWrBursts::13 4615 # Per bank write bursts -system.physmem.perBankWrBursts::14 4128 # Per bank write bursts -system.physmem.perBankWrBursts::15 3607 # Per bank write bursts +system.physmem.perBankRdBursts::0 7641 # Per bank write bursts +system.physmem.perBankRdBursts::1 6876 # Per bank write bursts +system.physmem.perBankRdBursts::2 7409 # Per bank write bursts +system.physmem.perBankRdBursts::3 7470 # Per bank write bursts +system.physmem.perBankRdBursts::4 7337 # Per bank write bursts +system.physmem.perBankRdBursts::5 7030 # Per bank write bursts +system.physmem.perBankRdBursts::6 7627 # Per bank write bursts +system.physmem.perBankRdBursts::7 7716 # Per bank write bursts +system.physmem.perBankRdBursts::8 6884 # Per bank write bursts +system.physmem.perBankRdBursts::9 7545 # Per bank write bursts +system.physmem.perBankRdBursts::10 7008 # Per bank write bursts +system.physmem.perBankRdBursts::11 6374 # Per bank write bursts +system.physmem.perBankRdBursts::12 6408 # Per bank write bursts +system.physmem.perBankRdBursts::13 7193 # Per bank write bursts +system.physmem.perBankRdBursts::14 6835 # Per bank write bursts +system.physmem.perBankRdBursts::15 6286 # Per bank write bursts +system.physmem.perBankWrBursts::0 4484 # Per bank write bursts +system.physmem.perBankWrBursts::1 4020 # Per bank write bursts +system.physmem.perBankWrBursts::2 4489 # Per bank write bursts +system.physmem.perBankWrBursts::3 4613 # Per bank write bursts +system.physmem.perBankWrBursts::4 4310 # Per bank write bursts +system.physmem.perBankWrBursts::5 4320 # Per bank write bursts +system.physmem.perBankWrBursts::6 4621 # Per bank write bursts +system.physmem.perBankWrBursts::7 4483 # Per bank write bursts +system.physmem.perBankWrBursts::8 4167 # Per bank write bursts +system.physmem.perBankWrBursts::9 4860 # Per bank write bursts +system.physmem.perBankWrBursts::10 4381 # Per bank write bursts +system.physmem.perBankWrBursts::11 3929 # Per bank write bursts +system.physmem.perBankWrBursts::12 3827 # Per bank write bursts +system.physmem.perBankWrBursts::13 4631 # Per bank write bursts +system.physmem.perBankWrBursts::14 4137 # Per bank write bursts +system.physmem.perBankWrBursts::15 3740 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 2822178697500 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 2822140482500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 113342 # Read request sizes (log2) +system.physmem.readPktSize::6 113749 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 68762 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 85611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 24487 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 69024 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 85840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 24773 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2446 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -191,176 +191,172 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 67 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 64 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 61 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 62 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39262 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.647547 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.649192 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.383393 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15575 39.67% 39.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9414 23.98% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3760 9.58% 73.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2064 5.26% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1515 3.86% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1018 2.59% 84.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 639 1.63% 86.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 658 1.68% 88.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4619 11.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39262 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3618 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 31.293256 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 632.321482 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 3616 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39259 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 297.757559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 173.671784 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.464821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15432 39.31% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9477 24.14% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3788 9.65% 73.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2095 5.34% 78.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1555 3.96% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1004 2.56% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 603 1.54% 86.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 654 1.67% 88.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4651 11.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39259 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3667 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.985274 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 628.070623 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 3665 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::36864-38911 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3618 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3618 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.001658 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.828073 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.498575 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 5 0.14% 0.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 2 0.06% 0.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 2 0.06% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 2 0.06% 0.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3234 89.39% 89.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 43 1.19% 90.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 55 1.52% 92.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 37 1.02% 93.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 88 2.43% 95.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 33 0.91% 96.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 11 0.30% 97.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 11 0.30% 97.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 5 0.14% 97.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.19% 97.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.06% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.14% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 54 1.49% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.08% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.03% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.11% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.06% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.03% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.06% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 3 0.08% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.06% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3618 # Writes before turning the bus around for reads -system.physmem.totQLat 1331922750 # Total ticks spent queuing -system.physmem.totMemAccLat 3455116500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 566185000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11762.26 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 3667 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3667 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.819744 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.710166 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 9.565148 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 9 0.25% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 3 0.08% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 3 0.08% 0.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 6 0.16% 0.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3283 89.53% 90.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 35 0.95% 91.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 47 1.28% 92.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 39 1.06% 93.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 88 2.40% 95.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 43 1.17% 96.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 6 0.16% 97.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.27% 97.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 7 0.19% 97.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 5 0.14% 97.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.11% 97.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.08% 97.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 62 1.69% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.03% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.03% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.11% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.11% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3667 # Writes before turning the bus around for reads +system.physmem.totQLat 1342938250 # Total ticks spent queuing +system.physmem.totMemAccLat 3473669500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 568195000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11817.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30512.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.57 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30567.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.57 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.94 # Average write queue length when enqueuing -system.physmem.readRowHits 93386 # Number of row buffer hits during reads -system.physmem.writeRowHits 49336 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.75 # Row buffer hit rate for writes -system.physmem.avgGap 15497620.58 # Average gap between requests -system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 157701600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 85878375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 459622800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 228737520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 179710355760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 72061196355 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1617839664000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1870543156410 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.633364 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2641056208250 # Time in different power states -system.physmem_0.memoryStateTime::REF 91876460000 # Time in different power states +system.physmem.avgWrQLen 27.55 # Average write queue length when enqueuing +system.physmem.readRowHits 93703 # Number of row buffer hits during reads +system.physmem.writeRowHits 49689 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.46 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.99 # Row buffer hit rate for writes +system.physmem.avgGap 15440685.89 # Average gap between requests +system.physmem.pageHitRate 78.50 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 158064480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 86055750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 461026800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 229003200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 179708321520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 72025489845 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1621445025000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1874112986595 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.488376 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2641083296250 # Time in different power states +system.physmem_0.memoryStateTime::REF 91875160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 18550863000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 18501220250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 139119120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 75726750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 423618000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 216749520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 179710355760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 71208324450 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1622163329250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1873937222850 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.425184 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2642291372250 # Time in different power states -system.physmem_1.memoryStateTime::REF 91876460000 # Time in different power states +system.physmem_1.actEnergy 138733560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 75508125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 425357400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 218194560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 179708321520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 71152837515 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1620392151000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1872111103680 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.495866 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2642358679500 # Time in different power states +system.physmem_1.memoryStateTime::REF 91875160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17320352000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17221255250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -373,9 +369,9 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -383,7 +379,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -413,49 +409,49 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 4996 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 4996 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 4996 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 4996 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 4996 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 56881650376 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.265666 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -15111501624 -26.57% -26.57% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 71993152000 126.57% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 56881650376 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 2808 68.21% 68.21% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1309 31.79% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4117 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4996 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 4966 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 4966 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 4966 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 4966 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 4966 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 56881367876 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.265672 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -15111782124 -26.57% -26.57% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 71993150000 126.57% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 56881367876 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 2795 68.22% 68.22% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1302 31.78% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4097 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4966 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4996 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4117 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4966 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4097 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4117 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 9113 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4097 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 9063 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12099084 # DTB read hits -system.cpu0.dtb.read_misses 4274 # DTB read misses -system.cpu0.dtb.write_hits 9151888 # DTB write hits -system.cpu0.dtb.write_misses 722 # DTB write misses +system.cpu0.dtb.read_hits 12103158 # DTB read hits +system.cpu0.dtb.read_misses 4250 # DTB read misses +system.cpu0.dtb.write_hits 9145748 # DTB write hits +system.cpu0.dtb.write_misses 716 # DTB write misses system.cpu0.dtb.flush_tlb 171 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 363 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 362 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2772 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2759 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 821 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 823 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 173 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12103358 # DTB read accesses -system.cpu0.dtb.write_accesses 9152610 # DTB write accesses +system.cpu0.dtb.perms_faults 174 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12107408 # DTB read accesses +system.cpu0.dtb.write_accesses 9146464 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21250972 # DTB hits -system.cpu0.dtb.misses 4996 # DTB misses -system.cpu0.dtb.accesses 21255968 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 21248906 # DTB hits +system.cpu0.dtb.misses 4966 # DTB misses +system.cpu0.dtb.accesses 21253872 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -485,93 +481,93 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 2442 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2442 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2442 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2442 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2442 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 56881650376 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.265668 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -15111616124 -26.57% -26.57% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 71993266500 126.57% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 56881650376 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1322 74.86% 74.86% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 444 25.14% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1766 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 2431 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2431 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2431 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2431 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2431 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 56881367876 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.265674 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -15111901124 -26.57% -26.57% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 71993269000 126.57% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 56881367876 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1314 74.83% 74.83% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 442 25.17% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1756 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2442 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2442 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2431 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2431 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1766 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1766 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4208 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 56923800 # ITB inst hits -system.cpu0.itb.inst_misses 2442 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1756 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1756 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4187 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 56926912 # ITB inst hits +system.cpu0.itb.inst_misses 2431 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 171 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 363 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 362 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1703 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1695 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 56926242 # ITB inst accesses -system.cpu0.itb.hits 56923800 # DTB hits -system.cpu0.itb.misses 2442 # DTB misses -system.cpu0.itb.accesses 56926242 # DTB accesses -system.cpu0.numPwrStateTransitions 2560 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1280 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 2127325768.303125 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 53245910996.367020 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1265 98.83% 98.83% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 56929343 # ITB inst accesses +system.cpu0.itb.hits 56926912 # DTB hits +system.cpu0.itb.misses 2431 # DTB misses +system.cpu0.itb.accesses 56929343 # DTB accesses +system.cpu0.numPwrStateTransitions 2564 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1282 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 2124006318.198128 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 53204391855.203163 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1267 98.83% 98.83% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1000-5e+10 11 0.86% 99.69% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.08% 99.77% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.08% 99.84% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.08% 99.92% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 1 0.08% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 1799911049001 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1280 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 100773841072 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2722976983428 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 68778258 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 1799910947501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1282 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 100736431570 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2722976099930 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 68779411 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3086 # number of quiesce instructions executed -system.cpu0.committedInsts 55461787 # Number of instructions committed -system.cpu0.committedOps 67232154 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 59006752 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4424 # Number of float alu accesses -system.cpu0.num_func_calls 5784619 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7357566 # number of instructions that are conditional controls -system.cpu0.num_int_insts 59006752 # number of integer instructions -system.cpu0.num_fp_insts 4424 # number of float instructions -system.cpu0.num_int_register_reads 108803726 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41133474 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3383 # number of times the floating registers were read +system.cpu0.kern.inst.quiesce 3087 # number of quiesce instructions executed +system.cpu0.committedInsts 55462034 # Number of instructions committed +system.cpu0.committedOps 67230601 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 59006165 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4380 # Number of float alu accesses +system.cpu0.num_func_calls 5788069 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7355854 # number of instructions that are conditional controls +system.cpu0.num_int_insts 59006165 # number of integer instructions +system.cpu0.num_fp_insts 4380 # number of float instructions +system.cpu0.num_int_register_reads 108801460 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41139310 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3339 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1042 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 204599031 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 24717436 # number of times the CC registers were written -system.cpu0.num_mem_refs 21838245 # number of memory refs -system.cpu0.num_load_insts 12248234 # Number of load instructions -system.cpu0.num_store_insts 9590011 # Number of store instructions -system.cpu0.num_idle_cycles 64958382.766609 # Number of idle cycles -system.cpu0.num_busy_cycles 3819875.233391 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055539 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944461 # Percentage of idle cycles -system.cpu0.Branches 13458694 # Number of branches fetched +system.cpu0.num_cc_register_reads 204596465 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 24709161 # number of times the CC registers were written +system.cpu0.num_mem_refs 21836532 # number of memory refs +system.cpu0.num_load_insts 12252554 # Number of load instructions +system.cpu0.num_store_insts 9583978 # Number of store instructions +system.cpu0.num_idle_cycles 64960338.337804 # Number of idle cycles +system.cpu0.num_busy_cycles 3819072.662196 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055526 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944474 # Percentage of idle cycles +system.cpu0.Branches 13460127 # Number of branches fetched system.cpu0.op_class::No_OpClass 2178 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46427379 67.95% 67.96% # Class of executed instruction -system.cpu0.op_class::IntMult 50783 0.07% 68.03% # Class of executed instruction +system.cpu0.op_class::IntAlu 46428516 67.96% 67.96% # Class of executed instruction +system.cpu0.op_class::IntMult 50840 0.07% 68.03% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.03% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.03% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.03% # Class of executed instruction @@ -595,550 +591,550 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.03% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.03% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.03% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3883 0.01% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3886 0.01% 68.04% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.04% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.04% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::MemRead 12248234 17.93% 85.96% # Class of executed instruction -system.cpu0.op_class::MemWrite 9590011 14.04% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 12252554 17.93% 85.97% # Class of executed instruction +system.cpu0.op_class::MemWrite 9583978 14.03% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 68322468 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 833257 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.996712 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 45925455 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 833769 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.081749 # Average number of references to valid blocks. +system.cpu0.op_class::total 68321952 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 833218 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.996713 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 45933242 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 833730 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.093666 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.041518 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.532588 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 4.805161 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 13.617445 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.941487 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.022525 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009385 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.026597 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.881738 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.691774 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 4.820044 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 13.603157 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.941175 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.022835 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009414 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.026569 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 193121109 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 193121109 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 11466282 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 3602501 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4049569 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 6704947 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25823299 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 8812878 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 2685246 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 3139889 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 4160679 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18798692 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 178656 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 57007 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 67385 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 85895 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 388943 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 216992 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 74973 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 70646 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 88358 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 450969 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 218031 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 76624 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73525 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 92476 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460656 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20279160 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 6287747 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7189458 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 10865626 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 44621991 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20457816 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 6344754 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7256843 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 10951521 # number of overall hits -system.cpu0.dcache.overall_hits::total 45010934 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 170890 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 52219 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 77937 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 220468 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 521514 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 112466 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 34991 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 102606 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 1224598 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1474661 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 53866 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 19687 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 19003 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu3.data 42601 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 135157 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 3704 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2351 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3769 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 8092 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 17916 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 193157378 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 193157378 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 11470530 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 3604905 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4052935 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu3.data 6701965 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25830335 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 8807060 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 2683880 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 3142868 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu3.data 4165696 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18799504 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 178529 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 56901 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 67360 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu3.data 86083 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 388873 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 216810 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 75069 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 70446 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 88639 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 450964 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 217842 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 76721 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73321 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu3.data 92790 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 460674 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 20277590 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 6288785 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 7195803 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu3.data 10867661 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 44629839 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 20456119 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 6345686 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 7263163 # number of overall hits +system.cpu0.dcache.overall_hits::cpu3.data 10953744 # number of overall hits +system.cpu0.dcache.overall_hits::total 45018712 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 170861 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 52117 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 78041 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu3.data 219706 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 520725 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 112296 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 34780 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 103289 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu3.data 1226440 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1476805 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 53971 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 19499 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 19151 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu3.data 42439 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 135060 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 3703 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2347 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3778 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 8109 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 17937 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu3.data 20 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 21 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 283356 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 87210 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 180543 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu3.data 1445066 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1996175 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 337222 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 106897 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 199546 # number of overall misses -system.cpu0.dcache.overall_misses::cpu3.data 1487667 # number of overall misses -system.cpu0.dcache.overall_misses::total 2131332 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 840626000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 1133704500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 3352508500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5326839000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1278551500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 5008629497 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 60718257320 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 67005438317 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28781500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 56444000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 111171000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 196396500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 450500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 450500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 2119177500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 6142333997 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu3.data 64070765820 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 72332277317 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 2119177500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 6142333997 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu3.data 64070765820 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 72332277317 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 11637172 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 3654720 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4127506 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu3.data 6925415 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26344813 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 8925344 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 2720237 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3242495 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu3.data 5385277 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 20273353 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 232522 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 76694 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 86388 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 128496 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 524100 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 220696 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 77324 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 74415 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 96450 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 468885 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 218032 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 76624 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73525 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 92496 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460677 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 20562516 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 6374957 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7370001 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu3.data 12310692 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 46618166 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 20795038 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 6451651 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7456389 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu3.data 12439188 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 47142266 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.014685 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.014288 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.018882 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.031835 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.019796 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012601 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.012863 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.031644 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.227397 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.072739 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.231660 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.256695 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.219973 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.331536 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.257884 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016783 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.030405 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050648 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.083898 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.038210 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_misses::cpu3.data 27 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 283157 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 86897 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 181330 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu3.data 1446146 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1997530 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 337128 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 106396 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 200481 # number of overall misses +system.cpu0.dcache.overall_misses::cpu3.data 1488585 # number of overall misses +system.cpu0.dcache.overall_misses::total 2132590 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 838773500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 1135742500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 3358270500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5332786500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1269362500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 5008758996 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 61128343835 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 67406465331 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28849500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 56408000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 111440000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 196697500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 509500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 509500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 2108136000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 6144501496 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu3.data 64486614335 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 72739251831 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 2108136000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 6144501496 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu3.data 64486614335 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 72739251831 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 11641391 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 3657022 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4130976 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu3.data 6921671 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 26351060 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 8919356 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 2718660 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 3246157 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu3.data 5392136 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 20276309 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 232500 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 76400 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 86511 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 128522 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 523933 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 220513 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 77416 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 74224 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 96748 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 468901 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 217843 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 76721 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73321 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 92817 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 460702 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 20560747 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 6375682 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7377133 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu3.data 12313807 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 46627369 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 20793247 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 6452082 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7463644 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu3.data 12442329 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 47151302 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.014677 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.014251 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.018892 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.031742 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.019761 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012590 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.012793 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.031819 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.227450 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.072834 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.232133 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.255223 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.221371 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.330208 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.257781 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016793 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.030317 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050900 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.083816 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.038253 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000005 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000216 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013780 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013680 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.024497 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu3.data 0.117383 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.042820 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.016216 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.016569 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.026762 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu3.data 0.119595 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.045211 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16098.086903 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14546.422110 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15206.326995 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10214.182170 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36539.438713 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48814.196996 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 49582.195398 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45437.858814 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12242.237346 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14975.855665 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13738.383589 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10962.073007 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 22525 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21452.380952 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24299.707602 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 34021.446398 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 44337.605217 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36235.438935 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19824.480575 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30781.544090 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 43067.948553 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33937.592696 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 336311 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 29493 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 12565 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 679 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.765698 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 43.435935 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 691735 # number of writebacks -system.cpu0.dcache.writebacks::total 691735 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 104 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 3034 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 108026 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 111164 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 47325 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 1128149 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1175474 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1653 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 2318 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 5313 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 9284 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 104 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 50359 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu3.data 1236175 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1286638 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 104 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 50359 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu3.data 1236175 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1286638 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 52115 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 74903 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 112442 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 239460 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 34991 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 55281 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 96449 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 186721 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 19358 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 15598 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 29608 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 64564 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 698 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 1451 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 2779 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4928 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 20 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 87106 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 130184 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu3.data 208891 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 426181 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 106464 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 145782 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu3.data 238499 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 490745 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 3449 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 7107 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 7761 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18317 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 2842 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 5190 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6229 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 14261 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 6291 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 12297 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 13990 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32578 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 786951500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1017548500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1612818000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3417318000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1243560500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2630255500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 4839784419 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8713600419 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 249854500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 223680000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 457627500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 931162000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9093000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 27428500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 39926500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76448000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 430500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 430500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2030512000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3647804000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 6452602419 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12130918419 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2280366500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3871484000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 6910229919 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13062080419 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 605119000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1489074500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1668784000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3762977500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 605119000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1489074500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1668784000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3762977500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014260 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018147 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016236 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009089 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012863 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017049 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017910 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009210 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.252406 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.180557 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.230420 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.123190 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.009027 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019499 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.028813 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010510 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000216 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000043 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013664 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017664 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.016968 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.009142 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016502 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019551 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019173 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.010410 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15100.287825 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13584.883115 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14343.554899 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14270.934603 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35539.438713 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 47579.738066 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50179.726270 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46666.418983 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12907.041017 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14340.300038 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15456.211159 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14422.309646 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13027.220630 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 18903.170227 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14367.218424 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15512.987013 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 21525 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21525 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23310.816706 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 28020.371167 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 30889.805779 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28464.240356 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21419.132289 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26556.666804 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 28973.831836 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26616.838519 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175447.665990 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 209522.231603 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215021.775544 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205436.343288 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 96188.046416 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 121092.502236 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 119284.060043 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115506.706980 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1969655 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.471697 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 93089501 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1970167 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 47.249548 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12499304500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 436.731895 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 12.926501 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 25.039106 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 36.774196 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.852992 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.025247 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.048905 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu3.inst 0.071825 # Average percentage of cache occupancy +system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000291 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000061 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013772 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013629 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.024580 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu3.data 0.117441 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.042840 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.016213 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.016490 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.026861 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu3.data 0.119639 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.045229 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16094.048007 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14553.151549 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15285.292618 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10241.080225 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36496.909143 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48492.666170 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 49842.098949 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45643.443333 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12292.074989 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14930.651138 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13742.754964 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10966.019959 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 18870.370370 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18196.428571 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24260.170086 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 33885.741444 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 44592.049720 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36414.597944 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19814.053160 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30648.797123 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 43320.747109 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34108.408945 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 335851 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 30410 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 12618 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 677 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.616817 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 44.918759 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 692039 # number of writebacks +system.cpu0.dcache.writebacks::total 692039 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 103 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 3007 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 107263 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 110373 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 47662 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 1129952 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1177614 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1644 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 2326 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 5317 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 9287 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 103 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 50669 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu3.data 1237215 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1287987 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 103 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 50669 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu3.data 1237215 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1287987 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 52014 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 75034 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 112443 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 239491 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 34780 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 55627 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 96488 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 186895 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 19172 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 15769 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 29454 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 64395 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 703 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 1452 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 2792 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4947 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 27 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 27 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 86794 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 130661 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu3.data 208931 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 426386 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 105966 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 146430 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu3.data 238385 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 490781 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 3424 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 7112 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 7739 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18275 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 2828 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 5192 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6207 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 14227 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 6252 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 12304 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 13946 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32502 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 785366000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1020201000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1616061500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3421628500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1234582500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2622763500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 4843611917 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8700957917 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 247389500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 224319000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 453567500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 925276000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9229000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 27290500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 39997500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76517000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 482500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 482500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2019948500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3642964500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 6459673417 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12122586417 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2267338000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3867283500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 6913240917 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13047862417 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 601508000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1489621000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1663692500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3754821500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 601508000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1489621000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1663692500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3754821500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014223 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018164 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016245 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009088 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012793 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017136 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017894 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009217 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.250942 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.182277 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.229175 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.122907 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.009081 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019562 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.028858 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010550 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000291 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000059 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013613 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017712 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.016967 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.009145 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016424 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019619 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019159 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.010409 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15099.127158 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13596.516246 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14372.273063 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14287.085945 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35496.909143 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 47149.109246 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50199.111983 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46555.327414 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12903.687670 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14225.315492 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15399.181775 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14368.755338 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13128.022760 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 18795.110193 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14325.752149 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15467.353952 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 17870.370370 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 17870.370370 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23272.904809 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27881.039484 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 30917.735602 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28431.014191 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21396.844271 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26410.458922 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29000.318464 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26585.915952 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175674.065421 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 209451.771654 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 214975.125985 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205462.188782 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 96210.492642 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 121068.026658 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 119295.317654 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115525.859947 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1969505 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.471624 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 93098332 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1970017 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 47.257629 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 12499756500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 436.760332 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 13.051317 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 24.695920 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu3.inst 36.964055 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.853048 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.025491 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.048234 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu3.inst 0.072195 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998968 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 260 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 97072276 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 97072276 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 56181878 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 17631013 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 9969832 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu3.inst 9306778 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 93089501 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 56181878 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 17631013 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 9969832 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu3.inst 9306778 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 93089501 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 56181878 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 17631013 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 9969832 # number of overall hits -system.cpu0.icache.overall_hits::cpu3.inst 9306778 # number of overall hits -system.cpu0.icache.overall_hits::total 93089501 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 743688 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 212939 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 469858 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu3.inst 586089 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2012574 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 743688 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 212939 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 469858 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu3.inst 586089 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2012574 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 743688 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 212939 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 469858 # number of overall misses -system.cpu0.icache.overall_misses::cpu3.inst 586089 # number of overall misses -system.cpu0.icache.overall_misses::total 2012574 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2915341500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6506958500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 7959529989 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 17381829989 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2915341500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 6506958500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu3.inst 7959529989 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 17381829989 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2915341500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 6506958500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu3.inst 7959529989 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 17381829989 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 56925566 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 17843952 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 10439690 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu3.inst 9892867 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 95102075 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 56925566 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 17843952 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 10439690 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu3.inst 9892867 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 95102075 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 56925566 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 17843952 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 10439690 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu3.inst 9892867 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 95102075 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013064 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011933 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.045007 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.059244 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.021162 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013064 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011933 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.045007 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu3.inst 0.059244 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.021162 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013064 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011933 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.045007 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu3.inst 0.059244 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.021162 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13690.970184 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13848.776652 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13580.753075 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8636.616586 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13690.970184 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13848.776652 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13580.753075 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8636.616586 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13690.970184 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13848.776652 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13580.753075 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8636.616586 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4059 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 97080848 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 97080848 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 56184409 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 17633594 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 9977155 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu3.inst 9303174 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 93098332 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 56184409 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 17633594 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 9977155 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu3.inst 9303174 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 93098332 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 56184409 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 17633594 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 9977155 # number of overall hits +system.cpu0.icache.overall_hits::cpu3.inst 9303174 # number of overall hits +system.cpu0.icache.overall_hits::total 93098332 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 744259 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 211927 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 469274 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu3.inst 586995 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2012455 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 744259 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 211927 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 469274 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu3.inst 586995 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 2012455 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 744259 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 211927 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 469274 # number of overall misses +system.cpu0.icache.overall_misses::cpu3.inst 586995 # number of overall misses +system.cpu0.icache.overall_misses::total 2012455 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2897125000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6498329500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 7981353488 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 17376807988 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2897125000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 6498329500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu3.inst 7981353488 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 17376807988 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2897125000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 6498329500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu3.inst 7981353488 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 17376807988 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 56928668 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 17845521 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 10446429 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu3.inst 9890169 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 95110787 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 56928668 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 17845521 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 10446429 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu3.inst 9890169 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 95110787 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 56928668 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 17845521 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 10446429 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu3.inst 9890169 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 95110787 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013074 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011876 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.044922 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.059351 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.021159 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013074 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011876 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.044922 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu3.inst 0.059351 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.021159 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013074 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011876 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.044922 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu3.inst 0.059351 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.021159 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13670.391220 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13847.623137 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13596.970141 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8634.631824 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13670.391220 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13847.623137 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13596.970141 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8634.631824 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13670.391220 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13847.623137 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13596.970141 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8634.631824 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4282 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 214 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 243 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.967290 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.621399 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1969655 # number of writebacks -system.cpu0.icache.writebacks::total 1969655 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 42373 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 42373 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu3.inst 42373 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 42373 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu3.inst 42373 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 42373 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 212939 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 469858 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 543716 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1226513 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 212939 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 469858 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu3.inst 543716 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1226513 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 212939 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 469858 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu3.inst 543716 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1226513 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2702402500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6037100500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 7028496990 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 15767999990 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2702402500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6037100500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 7028496990 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 15767999990 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2702402500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6037100500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 7028496990 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 15767999990 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011933 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045007 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.054960 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012897 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011933 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.045007 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.054960 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.012897 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011933 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045007 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.054960 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.012897 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12690.970184 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12848.776652 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12926.779771 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12855.958306 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12690.970184 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12848.776652 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12926.779771 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12855.958306 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12690.970184 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12848.776652 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12926.779771 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12855.958306 # average overall mshr miss latency -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.writebacks::writebacks 1969505 # number of writebacks +system.cpu0.icache.writebacks::total 1969505 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 42394 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 42394 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu3.inst 42394 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 42394 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu3.inst 42394 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 42394 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 211927 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 469274 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 544601 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1225802 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 211927 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 469274 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu3.inst 544601 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1225802 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 211927 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 469274 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu3.inst 544601 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1225802 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2685198000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6029055500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 7046769990 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 15761023490 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2685198000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6029055500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 7046769990 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 15761023490 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2685198000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6029055500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 7046769990 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 15761023490 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.044922 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.055065 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012888 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.044922 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.055065 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.012888 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.044922 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.055065 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.012888 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12670.391220 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12847.623137 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12939.326204 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12857.723751 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12670.391220 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12847.623137 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12939.326204 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12857.723751 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12670.391220 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12847.623137 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12939.326204 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12857.723751 # average overall mshr miss latency +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1168,63 +1164,61 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 2014 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 2014 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 554 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1460 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 2014 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 2014 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 2014 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1648 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12287.621359 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10419.476914 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6887.691629 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 0.91% 0.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-6143 458 27.79% 28.70% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::6144-8191 116 7.04% 35.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::10240-12287 507 30.76% 66.50% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-14335 107 6.49% 73.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::14336-16383 75 4.55% 77.55% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-18431 12 0.73% 78.28% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::22528-24575 336 20.39% 98.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-26623 22 1.33% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1648 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 2001 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 2001 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 565 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1436 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 2001 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 2001 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 2001 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1629 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 10353.898097 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9102.917994 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5277.363913 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 0.92% 0.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-6143 529 32.47% 33.39% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::6144-8191 134 8.23% 41.62% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::10240-12287 516 31.68% 73.30% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-14335 268 16.45% 89.75% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::14336-16383 35 2.15% 91.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::22528-24575 132 8.10% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1629 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1102 66.87% 66.87% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 546 33.13% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1648 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2014 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1072 65.81% 65.81% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 557 34.19% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1629 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2001 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2014 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1648 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2001 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1629 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1648 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 3662 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1629 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3630 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3812187 # DTB read hits -system.cpu1.dtb.read_misses 1742 # DTB read misses -system.cpu1.dtb.write_hits 2799792 # DTB write hits -system.cpu1.dtb.write_misses 272 # DTB write misses -system.cpu1.dtb.flush_tlb 153 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 180 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 3814262 # DTB read hits +system.cpu1.dtb.read_misses 1730 # DTB read misses +system.cpu1.dtb.write_hits 2798296 # DTB write hits +system.cpu1.dtb.write_misses 271 # DTB write misses +system.cpu1.dtb.flush_tlb 154 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 179 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1235 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1231 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 241 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 257 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 89 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3813929 # DTB read accesses -system.cpu1.dtb.write_accesses 2800064 # DTB write accesses +system.cpu1.dtb.perms_faults 87 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3815992 # DTB read accesses +system.cpu1.dtb.write_accesses 2798567 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6611979 # DTB hits -system.cpu1.dtb.misses 2014 # DTB misses -system.cpu1.dtb.accesses 6613993 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 6612558 # DTB hits +system.cpu1.dtb.misses 2001 # DTB misses +system.cpu1.dtb.accesses 6614559 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1254,148 +1248,147 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 1033 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1033 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 201 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 832 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1033 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1033 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1033 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 763 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12903.669725 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10877.320310 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7130.133618 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 252 33.03% 33.03% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 198 25.95% 58.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 53 6.95% 65.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 68 8.91% 74.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-18431 1 0.13% 74.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 185 24.25% 99.21% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-26623 6 0.79% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 763 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 1010 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1010 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 203 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 807 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1010 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1010 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1010 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 742 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 10898.247978 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9294.148205 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6181.528328 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 309 41.64% 41.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::6144-8191 2 0.27% 41.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 197 26.55% 68.46% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 117 15.77% 84.23% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 15 2.02% 86.25% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 102 13.75% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 742 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 562 73.66% 73.66% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 201 26.34% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 763 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 539 72.64% 72.64% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 203 27.36% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 742 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1033 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1033 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1010 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1010 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 763 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 763 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 1796 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 17843952 # ITB inst hits -system.cpu1.itb.inst_misses 1033 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 742 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 742 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1752 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 17845521 # ITB inst hits +system.cpu1.itb.inst_misses 1010 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 153 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 180 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 154 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 179 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 730 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 709 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 17844985 # ITB inst accesses -system.cpu1.itb.hits 17843952 # DTB hits -system.cpu1.itb.misses 1033 # DTB misses -system.cpu1.itb.accesses 17844985 # DTB accesses -system.cpu1.numPwrStateTransitions 704 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 352 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 882103975.423295 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 11685879500.755745 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 347 98.58% 98.58% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 17846531 # ITB inst accesses +system.cpu1.itb.hits 17845521 # DTB hits +system.cpu1.itb.misses 1010 # DTB misses +system.cpu1.itb.accesses 17846531 # DTB accesses +system.cpu1.numPwrStateTransitions 702 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 351 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 884610555.122507 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 11702380509.763947 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 346 98.58% 98.58% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1000-5e+10 3 0.85% 99.43% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.57% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 156798535501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 352 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 2513250225151 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 310500599349 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 143831015 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 156798063501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 351 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 2513214226652 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 310498304848 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 143755305 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 17251961 # Number of instructions committed -system.cpu1.committedOps 20817165 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 18580086 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1666 # Number of float alu accesses -system.cpu1.num_func_calls 1994134 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2173480 # number of instructions that are conditional controls -system.cpu1.num_int_insts 18580086 # number of integer instructions -system.cpu1.num_fp_insts 1666 # number of float instructions -system.cpu1.num_int_register_reads 34430067 # number of times the integer registers were read -system.cpu1.num_int_register_writes 13026660 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1213 # number of times the floating registers were read +system.cpu1.committedInsts 17251469 # Number of instructions committed +system.cpu1.committedOps 20813754 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 18573481 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1582 # Number of float alu accesses +system.cpu1.num_func_calls 1994080 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2178225 # number of instructions that are conditional controls +system.cpu1.num_int_insts 18573481 # number of integer instructions +system.cpu1.num_fp_insts 1582 # number of float instructions +system.cpu1.num_int_register_reads 34424804 # number of times the integer registers were read +system.cpu1.num_int_register_writes 13020587 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1129 # number of times the floating registers were read system.cpu1.num_fp_register_writes 454 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 75796626 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 7400275 # number of times the CC registers were written -system.cpu1.num_mem_refs 6814833 # number of memory refs -system.cpu1.num_load_insts 3855659 # Number of load instructions -system.cpu1.num_store_insts 2959174 # Number of store instructions -system.cpu1.num_idle_cycles 136834040.067403 # Number of idle cycles -system.cpu1.num_busy_cycles 6996974.932597 # Number of busy cycles -system.cpu1.not_idle_fraction 0.048647 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.951353 # Percentage of idle cycles -system.cpu1.Branches 4280023 # Number of branches fetched -system.cpu1.op_class::No_OpClass 48 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 14598901 68.12% 68.12% # Class of executed instruction -system.cpu1.op_class::IntMult 16055 0.07% 68.20% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 990 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::MemRead 3855659 17.99% 86.19% # Class of executed instruction -system.cpu1.op_class::MemWrite 2959174 13.81% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 75792524 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 7403118 # number of times the CC registers were written +system.cpu1.num_mem_refs 6816030 # number of memory refs +system.cpu1.num_load_insts 3857938 # Number of load instructions +system.cpu1.num_store_insts 2958092 # Number of store instructions +system.cpu1.num_idle_cycles 136763817.825679 # Number of idle cycles +system.cpu1.num_busy_cycles 6991487.174321 # Number of busy cycles +system.cpu1.not_idle_fraction 0.048635 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.951365 # Percentage of idle cycles +system.cpu1.Branches 4283308 # Number of branches fetched +system.cpu1.op_class::No_OpClass 49 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 14594706 68.11% 68.11% # Class of executed instruction +system.cpu1.op_class::IntMult 16119 0.08% 68.19% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 983 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::MemRead 3857938 18.00% 86.20% # Class of executed instruction +system.cpu1.op_class::MemWrite 2958092 13.80% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21430827 # Class of executed instruction -system.cpu2.branchPred.lookups 5563915 # Number of BP lookups -system.cpu2.branchPred.condPredicted 2829451 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 493242 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3244476 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 1661186 # Number of BTB hits +system.cpu1.op_class::total 21427887 # Class of executed instruction +system.cpu2.branchPred.lookups 5563559 # Number of BP lookups +system.cpu2.branchPred.condPredicted 2831152 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 495188 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3274111 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 1663178 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 51.200440 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 1571960 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 328162 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 674670 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 641704 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 32966 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 22004 # Number of mispredicted indirect branches. -system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu2.branchPred.BTBHitPct 50.797850 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 1571133 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 329841 # Number of incorrect RAS predictions. +system.cpu2.branchPred.indirectLookups 676012 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 643238 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 32774 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 22078 # Number of mispredicted indirect branches. +system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1425,59 +1418,58 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu2.dtb.walker.walks 11911 # Table walker walks requested -system.cpu2.dtb.walker.walksShort 11911 # Table walker walks initiated with short descriptors -system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7385 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4526 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 11911 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 11911 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 11911 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 2027 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 12784.410459 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 11026.371953 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 6894.594481 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-8191 547 26.99% 26.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1059 52.24% 79.23% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::16384-24575 401 19.78% 99.01% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::24576-32767 18 0.89% 99.90% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::81920-90111 2 0.10% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 2027 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu2.dtb.walker.walks 12042 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 12042 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7406 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4636 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 12042 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 12042 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 12042 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 2043 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 11062.897699 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 9694.627890 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 6045.581336 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-8191 687 33.63% 33.63% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1153 56.44% 90.06% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::16384-24575 200 9.79% 99.85% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::81920-90111 3 0.15% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 2043 # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walksPending::samples 2000042500 # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::0 2000042500 100.00% 100.00% # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::total 2000042500 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 1245 61.42% 61.42% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::1M 782 38.58% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 2027 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 11911 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkPageSizes::4K 1264 61.87% 61.87% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 779 38.13% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 2043 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12042 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 11911 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2027 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12042 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2043 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2027 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 13938 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2043 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 14085 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 4327855 # DTB read hits -system.cpu2.dtb.read_misses 10705 # DTB read misses -system.cpu2.dtb.write_hits 3342614 # DTB write hits -system.cpu2.dtb.write_misses 1206 # DTB write misses -system.cpu2.dtb.flush_tlb 153 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 143 # Number of times TLB was flushed by MVA +system.cpu2.dtb.read_hits 4331167 # DTB read hits +system.cpu2.dtb.read_misses 10867 # DTB read misses +system.cpu2.dtb.write_hits 3346265 # DTB write hits +system.cpu2.dtb.write_misses 1175 # DTB write misses +system.cpu2.dtb.flush_tlb 152 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 1399 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 245 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 301 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 1411 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 255 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 303 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 123 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 4338560 # DTB read accesses -system.cpu2.dtb.write_accesses 3343820 # DTB write accesses +system.cpu2.dtb.perms_faults 127 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 4342034 # DTB read accesses +system.cpu2.dtb.write_accesses 3347440 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 7670469 # DTB hits -system.cpu2.dtb.misses 11911 # DTB misses -system.cpu2.dtb.accesses 7682380 # DTB accesses -system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu2.dtb.hits 7677432 # DTB hits +system.cpu2.dtb.misses 12042 # DTB misses +system.cpu2.dtb.accesses 7689474 # DTB accesses +system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1507,66 +1499,66 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu2.itb.walker.walks 1348 # Table walker walks requested -system.cpu2.itb.walker.walksShort 1348 # Table walker walks initiated with short descriptors -system.cpu2.itb.walker.walksShortTerminationLevel::Level1 252 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1096 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 1348 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 1348 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 1348 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 848 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 13074.292453 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 11434.302344 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 6448.856060 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::4096-6143 240 28.30% 28.30% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::6144-8191 2 0.24% 28.54% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::10240-12287 241 28.42% 56.96% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::12288-14335 61 7.19% 64.15% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::14336-16383 126 14.86% 79.01% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::22528-24575 176 20.75% 99.76% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::24576-26623 2 0.24% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 848 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu2.itb.walker.walks 1330 # Table walker walks requested +system.cpu2.itb.walker.walksShort 1330 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walksShortTerminationLevel::Level1 245 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1085 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 1330 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 1330 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 1330 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 845 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 11181.065089 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 9687.789458 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 6060.643085 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::4096-6143 346 40.95% 40.95% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::6144-8191 3 0.36% 41.30% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::10240-12287 226 26.75% 68.05% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::12288-14335 99 11.72% 79.76% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::14336-16383 48 5.68% 85.44% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::22528-24575 122 14.44% 99.88% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::24576-26623 1 0.12% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 845 # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walksPending::samples 2000028000 # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::0 2000028000 100.00% 100.00% # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::total 2000028000 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 600 70.75% 70.75% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::1M 248 29.25% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 848 # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::4K 603 71.36% 71.36% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 242 28.64% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 845 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1348 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1348 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1330 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1330 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 848 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 848 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 2196 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 10441487 # ITB inst hits -system.cpu2.itb.inst_misses 1348 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 845 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 845 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 2175 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 10448237 # ITB inst hits +system.cpu2.itb.inst_misses 1330 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 153 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 143 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb 152 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 821 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 823 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1710 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1725 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 10442835 # ITB inst accesses -system.cpu2.itb.hits 10441487 # DTB hits -system.cpu2.itb.misses 1348 # DTB misses -system.cpu2.itb.accesses 10442835 # DTB accesses -system.cpu2.numPwrStateTransitions 1074 # Number of power state transitions -system.cpu2.pwrStateClkGateDist::samples 537 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::mean 5095328839.376163 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::stdev 41281959005.190056 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::underflows 492 91.62% 91.62% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::1000-5e+10 38 7.08% 98.70% # Distribution of time spent in the clock gated state +system.cpu2.itb.inst_accesses 10449567 # ITB inst accesses +system.cpu2.itb.hits 10448237 # DTB hits +system.cpu2.itb.misses 1330 # DTB misses +system.cpu2.itb.accesses 10449567 # DTB accesses +system.cpu2.numPwrStateTransitions 1076 # Number of power state transitions +system.cpu2.pwrStateClkGateDist::samples 538 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::mean 5085855532.985130 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::stdev 41244061935.633728 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::underflows 493 91.64% 91.64% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1000-5e+10 38 7.06% 98.70% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::5e+10-1e+11 1 0.19% 98.88% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11 1 0.19% 99.07% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11 1 0.19% 99.26% # Distribution of time spent in the clock gated state @@ -1574,73 +1566,73 @@ system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11 1 0.19% 99.44 system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11 2 0.37% 99.81% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11 1 0.19% 100.00% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::max_value 500052269001 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::total 537 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateResidencyTicks::ON 87559237755 # Cumulative time (in ticks) in various power states -system.cpu2.pwrStateResidencyTicks::CLK_GATED 2736191586745 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 141974504 # number of cpu cycles simulated +system.cpu2.pwrStateClkGateDist::max_value 500051113501 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::total 538 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateResidencyTicks::ON 87522254754 # Cumulative time (in ticks) in various power states +system.cpu2.pwrStateResidencyTicks::CLK_GATED 2736190276746 # Cumulative time (in ticks) in various power states +system.cpu2.numCycles 141975261 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 19185413 # Number of instructions committed -system.cpu2.committedOps 23254826 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 1388377 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 540 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 36744 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 7.400128 # CPI: cycles per instruction -system.cpu2.ipc 0.135133 # IPC: instructions per cycle -system.cpu2.op_class_0::No_OpClass 50 0.00% 0.00% # Class of committed instruction -system.cpu2.op_class_0::IntAlu 15529839 66.78% 66.78% # Class of committed instruction -system.cpu2.op_class_0::IntMult 18571 0.08% 66.86% # Class of committed instruction -system.cpu2.op_class_0::IntDiv 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::FloatAdd 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::FloatCmp 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::FloatCvt 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::FloatMult 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::FloatDiv 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::FloatSqrt 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdAdd 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdAddAcc 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdAlu 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdCmp 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdCvt 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdMisc 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdMult 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdMultAcc 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdShift 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdSqrt 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMisc 1326 0.01% 66.87% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction -system.cpu2.op_class_0::MemRead 4244552 18.25% 85.12% # Class of committed instruction -system.cpu2.op_class_0::MemWrite 3460488 14.88% 100.00% # Class of committed instruction +system.cpu2.committedInsts 19207075 # Number of instructions committed +system.cpu2.committedOps 23282264 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 1390064 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 541 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 36123 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 7.391821 # CPI: cycles per instruction +system.cpu2.ipc 0.135285 # IPC: instructions per cycle +system.cpu2.op_class_0::No_OpClass 48 0.00% 0.00% # Class of committed instruction +system.cpu2.op_class_0::IntAlu 15551874 66.80% 66.80% # Class of committed instruction +system.cpu2.op_class_0::IntMult 18578 0.08% 66.88% # Class of committed instruction +system.cpu2.op_class_0::IntDiv 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::FloatAdd 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::FloatCmp 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::FloatCvt 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::FloatMult 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::FloatDiv 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::FloatSqrt 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdAdd 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdAddAcc 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdAlu 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdCmp 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdCvt 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdMisc 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdMult 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdMultAcc 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdShift 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdSqrt 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMisc 1338 0.01% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::MemRead 4246805 18.24% 85.12% # Class of committed instruction +system.cpu2.op_class_0::MemWrite 3463621 14.88% 100.00% # Class of committed instruction system.cpu2.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.op_class_0::total 23254826 # Class of committed instruction +system.cpu2.op_class_0::total 23282264 # Class of committed instruction system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 38692637 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 103281867 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 13574263 # Number of BP lookups -system.cpu3.branchPred.condPredicted 7472946 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 296816 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 8409244 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 4443267 # Number of BTB hits +system.cpu2.tickCycles 38700481 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 103274780 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 13558463 # Number of BP lookups +system.cpu3.branchPred.condPredicted 7461726 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 297292 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 8389979 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 4437676 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 52.837889 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 3091382 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 16244 # Number of incorrect RAS predictions. -system.cpu3.branchPred.indirectLookups 2018293 # Number of indirect predictor lookups. -system.cpu3.branchPred.indirectHits 1956673 # Number of indirect target hits. -system.cpu3.branchPred.indirectMisses 61620 # Number of indirect misses. -system.cpu3.branchPredindirectMispredicted 18086 # Number of mispredicted indirect branches. -system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu3.branchPred.BTBHitPct 52.892576 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 3087767 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 16069 # Number of incorrect RAS predictions. +system.cpu3.branchPred.indirectLookups 2015433 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 1953316 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 62117 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 18167 # Number of mispredicted indirect branches. +system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1670,92 +1662,93 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu3.dtb.walker.walks 34289 # Table walker walks requested -system.cpu3.dtb.walker.walksShort 34289 # Table walker walks initiated with short descriptors -system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 10988 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 8074 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 15227 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 19062 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 480.983108 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 2977.429006 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-8191 18630 97.73% 97.73% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::8192-16383 285 1.50% 99.23% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::16384-24575 92 0.48% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::24576-32767 31 0.16% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::32768-40959 6 0.03% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::40960-49151 14 0.07% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::49152-57343 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::57344-65535 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-73727 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 19062 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 6433 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 11737.913882 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 9614.193609 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 7621.962559 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-8191 2432 37.81% 37.81% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::8192-16383 2842 44.18% 81.98% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::16384-24575 955 14.85% 96.83% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::24576-32767 108 1.68% 98.51% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::32768-40959 45 0.70% 99.21% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::40960-49151 39 0.61% 99.81% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::49152-57343 6 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-73727 2 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 6433 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -8544248564 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.589102 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::stdev 0.347038 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-1 -8589968064 100.54% 100.54% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::2-3 32103000 -0.38% 100.16% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-5 6761500 -0.08% 100.08% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::6-7 2522000 -0.03% 100.05% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-9 1641500 -0.02% 100.03% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::10-11 647000 -0.01% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-13 437000 -0.01% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::14-15 926500 -0.01% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-17 267500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::18-19 118000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-21 41000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::22-23 32500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-25 26000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::26-27 29500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-29 9000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::30-31 157500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -8544248564 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 1826 71.78% 71.78% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::1M 718 28.22% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 2544 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 34289 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu3.dtb.walker.walks 34483 # Table walker walks requested +system.cpu3.dtb.walker.walksShort 34483 # Table walker walks initiated with short descriptors +system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 10978 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 8165 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 15340 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 19143 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 456.015254 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 2830.743841 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-8191 18720 97.79% 97.79% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::8192-16383 307 1.60% 99.39% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::16384-24575 66 0.34% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::24576-32767 32 0.17% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::32768-40959 6 0.03% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::40960-49151 8 0.04% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::73728-81919 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::81920-90111 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 19143 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 6521 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 10311.301948 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 8555.831863 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 6751.449027 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-8191 2865 43.93% 43.93% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::8192-16383 2966 45.48% 89.42% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::16384-24575 551 8.45% 97.87% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::24576-32767 84 1.29% 99.16% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::32768-40959 31 0.48% 99.63% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::40960-49151 17 0.26% 99.89% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::90112-98303 2 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 6521 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -8545598564 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.743431 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::stdev 0.275134 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-1 -8589277064 100.51% 100.51% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::2-3 31465000 -0.37% 100.14% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-5 6055500 -0.07% 100.07% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::6-7 2113000 -0.02% 100.05% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-9 1651500 -0.02% 100.03% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::10-11 591000 -0.01% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-13 384000 -0.00% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::14-15 739000 -0.01% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-17 231000 -0.00% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::18-19 112500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-21 46500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::22-23 31000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-25 29500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::26-27 22000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-29 12000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::30-31 195000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -8545598564 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 1839 71.81% 71.81% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::1M 722 28.19% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 2561 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 34483 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 34289 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2544 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 34483 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2561 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2544 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 36833 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2561 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 37044 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 7476077 # DTB read hits -system.cpu3.dtb.read_misses 28705 # DTB read misses -system.cpu3.dtb.write_hits 5707301 # DTB write hits -system.cpu3.dtb.write_misses 5584 # DTB write misses +system.cpu3.dtb.read_hits 7471341 # DTB read hits +system.cpu3.dtb.read_misses 28725 # DTB read misses +system.cpu3.dtb.write_hits 5714088 # DTB write hits +system.cpu3.dtb.write_misses 5758 # DTB write misses system.cpu3.dtb.flush_tlb 157 # Number of times complete TLB was flushed -system.cpu3.dtb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA +system.cpu3.dtb.flush_tlb_mva 225 # Number of times TLB was flushed by MVA system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 1654 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 379 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 711 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_entries 1650 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 393 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 706 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 337 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 7504782 # DTB read accesses -system.cpu3.dtb.write_accesses 5712885 # DTB write accesses +system.cpu3.dtb.perms_faults 319 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 7500066 # DTB read accesses +system.cpu3.dtb.write_accesses 5719846 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 13183378 # DTB hits -system.cpu3.dtb.misses 34289 # DTB misses -system.cpu3.dtb.accesses 13217667 # DTB accesses -system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu3.dtb.hits 13185429 # DTB hits +system.cpu3.dtb.misses 34483 # DTB misses +system.cpu3.dtb.accesses 13219912 # DTB accesses +system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1785,220 +1778,221 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu3.itb.walker.walks 4253 # Table walker walks requested -system.cpu3.itb.walker.walksShort 4253 # Table walker walks initiated with short descriptors -system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1354 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu3.itb.walker.walks 4240 # Table walker walks requested +system.cpu3.itb.walker.walksShort 4240 # Table walker walks initiated with short descriptors +system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1366 # Level at which table walker walks with short descriptors terminate system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2463 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 436 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 3817 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1262.509824 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 4945.350323 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-8191 3591 94.08% 94.08% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::8192-16383 162 4.24% 98.32% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::16384-24575 27 0.71% 99.03% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::24576-32767 17 0.45% 99.48% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-40959 8 0.21% 99.69% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::40960-49151 6 0.16% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::49152-57343 1 0.03% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::57344-65535 4 0.10% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::73728-81919 1 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 3817 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 1618 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 11355.377009 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 9318.464391 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 7299.331906 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-8191 704 43.51% 43.51% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::8192-16383 629 38.88% 82.39% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::16384-24575 254 15.70% 98.08% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::24576-32767 19 1.17% 99.26% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::32768-40959 8 0.49% 99.75% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::40960-49151 2 0.12% 99.88% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::49152-57343 1 0.06% 99.94% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksSquashedBefore 411 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 3829 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1196.395926 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 4662.983981 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-8191 3612 94.33% 94.33% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::8192-16383 152 3.97% 98.30% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::16384-24575 35 0.91% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::24576-32767 19 0.50% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-40959 3 0.08% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::40960-49151 2 0.05% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::49152-57343 2 0.05% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::57344-65535 1 0.03% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-73727 2 0.05% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::81920-90111 1 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 3829 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 1597 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 10150.594865 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 8236.395815 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 7276.129645 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-8191 852 53.35% 53.35% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::8192-16383 514 32.19% 85.54% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::16384-24575 201 12.59% 98.12% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::24576-32767 13 0.81% 98.94% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-40959 11 0.69% 99.62% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::40960-49151 3 0.19% 99.81% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::49152-57343 2 0.13% 99.94% # Table walker service (enqueue to completion) latency system.cpu3.itb.walker.walkCompletionTime::81920-90111 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 1618 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -4448372768 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.737414 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.439006 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -1166371868 26.22% 26.22% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -3283428900 73.81% 100.03% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 1175000 -0.03% 100.01% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 224000 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 29000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -4448372768 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 844 71.40% 71.40% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::1M 338 28.60% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 1182 # Table walker page sizes translated +system.cpu3.itb.walker.walkCompletionTime::total 1597 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -8763056564 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.696085 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.459515 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -2661759664 30.37% 30.37% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -6102526900 69.64% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 1039000 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 149500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 41500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -8763056564 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 846 71.33% 71.33% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::1M 340 28.67% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 1186 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4253 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4253 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4240 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4240 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1182 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1182 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 5435 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 9894210 # ITB inst hits -system.cpu3.itb.inst_misses 4253 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1186 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1186 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 5426 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 9891489 # ITB inst hits +system.cpu3.itb.inst_misses 4240 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses system.cpu3.itb.flush_tlb 157 # Number of times complete TLB was flushed -system.cpu3.itb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA +system.cpu3.itb.flush_tlb_mva 225 # Number of times TLB was flushed by MVA system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 1133 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_entries 1134 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 703 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 708 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 9898463 # ITB inst accesses -system.cpu3.itb.hits 9894210 # DTB hits -system.cpu3.itb.misses 4253 # DTB misses -system.cpu3.itb.accesses 9898463 # DTB accesses -system.cpu3.numPwrStateTransitions 1744 # Number of power state transitions -system.cpu3.pwrStateClkGateDist::samples 872 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::mean 24195228.891055 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::stdev 644254106.585039 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::underflows 857 98.28% 98.28% # Distribution of time spent in the clock gated state +system.cpu3.itb.inst_accesses 9895729 # ITB inst accesses +system.cpu3.itb.hits 9891489 # DTB hits +system.cpu3.itb.misses 4240 # DTB misses +system.cpu3.itb.accesses 9895729 # DTB accesses +system.cpu3.numPwrStateTransitions 1742 # Number of power state transitions +system.cpu3.pwrStateClkGateDist::samples 871 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::mean 24222914.443169 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::stdev 644616845.496373 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::underflows 856 98.28% 98.28% # Distribution of time spent in the clock gated state system.cpu3.pwrStateClkGateDist::1000-5e+10 15 1.72% 100.00% # Distribution of time spent in the clock gated state system.cpu3.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::max_value 18906661340 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::total 872 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateResidencyTicks::ON 2802652584907 # Cumulative time (in ticks) in various power states -system.cpu3.pwrStateResidencyTicks::CLK_GATED 21098239593 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 55802582 # number of cpu cycles simulated +system.cpu3.pwrStateClkGateDist::max_value 18906422924 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::total 871 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateResidencyTicks::ON 2802614373020 # Cumulative time (in ticks) in various power states +system.cpu3.pwrStateResidencyTicks::CLK_GATED 21098158480 # Cumulative time (in ticks) in various power states +system.cpu3.numCycles 55804206 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 20935031 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 53976458 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 13574263 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 9491322 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 32368112 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 1569845 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 63704 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 1342 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 208 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 113598 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 71390 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 9892868 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 204224 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 2239 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 54338522 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.198008 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.332788 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 20943122 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 53945813 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 13558463 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 9478759 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 32366624 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 1570295 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 59981 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 769 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 238 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 103755 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 71551 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 320 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 9890169 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 205274 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 2246 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 54331487 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.197628 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.332891 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 39853023 73.34% 73.34% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 1853402 3.41% 76.75% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 1194631 2.20% 78.95% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3690685 6.79% 85.74% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 942938 1.74% 87.48% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 608116 1.12% 88.60% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2975810 5.48% 94.07% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 643271 1.18% 95.26% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 2576646 4.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 39855672 73.36% 73.36% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 1851434 3.41% 76.76% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 1194487 2.20% 78.96% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3686492 6.79% 85.75% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 943670 1.74% 87.48% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 608106 1.12% 88.60% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 2967627 5.46% 94.07% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 643917 1.19% 95.25% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2580082 4.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 54338522 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.243255 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.967275 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 14662616 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 29996417 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 7962115 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 1015455 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 701676 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 1056216 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 84320 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 46882791 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 277439 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 701676 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 15188976 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 3032843 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 21357872 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 8442903 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 5613994 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 45010257 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 711 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 1193798 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 109598 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 3924436 # Number of times rename has blocked due to SQ full -system.cpu3.rename.RenamedOperands 46943427 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 206658226 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 50584429 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 3918 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 39299455 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 7643972 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 719812 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 667882 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 5739952 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 7978184 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 6284983 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 1159177 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 1675680 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 43355264 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 518308 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 41274077 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 55092 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 6092748 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 14109869 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 54644 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 54338522 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.759573 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.457624 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 54331487 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.242965 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.966698 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 14668908 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 29986640 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 7957627 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 1016633 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 701473 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 1058313 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 84773 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 46874682 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 279635 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 701473 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 15195365 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 3032088 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 21321904 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 8439674 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 5640768 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 45002197 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 690 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 1195883 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 108366 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 3949949 # Number of times rename has blocked due to SQ full +system.cpu3.rename.RenamedOperands 46926978 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 206658489 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 50587166 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 3902 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 39299186 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 7627792 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 720809 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 668593 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 5741274 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 7971579 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 6293429 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 1156869 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 1562249 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 43347954 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 520206 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 41277545 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 55280 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 6083084 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 14076683 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 54734 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 54331487 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.759735 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.457545 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 38089201 70.10% 70.10% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 5343903 9.83% 79.93% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 4107112 7.56% 87.49% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 3342238 6.15% 93.64% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 1372760 2.53% 96.17% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 822455 1.51% 97.68% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 871489 1.60% 99.28% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 257925 0.47% 99.76% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 131439 0.24% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 38079008 70.09% 70.09% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 5345699 9.84% 79.93% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 4107348 7.56% 87.49% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 3341746 6.15% 93.64% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 1375872 2.53% 96.17% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 821998 1.51% 97.68% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 871189 1.60% 99.28% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 257716 0.47% 99.76% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 130911 0.24% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 54338522 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 54331487 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 64295 10.27% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 1 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 288567 46.11% 56.39% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 272927 43.61% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 64496 10.30% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 288888 46.14% 56.45% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 272662 43.55% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 61 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 27558257 66.77% 66.77% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 31168 0.08% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 62 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 27558666 66.76% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 30979 0.08% 66.84% # Type of FU issued system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.84% # Type of FU issued system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.84% # Type of FU issued system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.84% # Type of FU issued @@ -2022,99 +2016,99 @@ system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.84% # Ty system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.84% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.84% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 2328 0.01% 66.85% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 2332 0.01% 66.85% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.85% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 66.85% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 66.85% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.85% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 7689945 18.63% 85.48% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 5992314 14.52% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 7685963 18.62% 85.47% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 5999538 14.53% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 41274077 # Type of FU issued -system.cpu3.iq.rate 0.739645 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 625790 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.015162 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 137559378 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 49989246 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 40120759 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 8180 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 4843 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 3492 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 41895381 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 4425 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 174238 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 41277545 # Type of FU issued +system.cpu3.iq.rate 0.739685 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 626046 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.015167 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 137559508 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 49974445 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 40123728 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 8395 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 4805 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 3602 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 41898968 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 4561 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 173439 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1195264 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 1195 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 28361 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 579365 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 1192109 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 1191 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 28578 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 580828 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 104459 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 43794 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 104405 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 43387 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 701676 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 2636383 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 282446 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 43936154 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 66826 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 7978184 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 6284983 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 267113 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 25993 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 250282 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 28361 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 127792 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 130048 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 257840 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 40954158 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 7560730 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 285711 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 701473 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 2634873 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 283425 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 43928502 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 66531 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 7971579 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 6293429 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 268536 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 25934 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 251471 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 28578 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 127058 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 130735 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 257793 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 40956248 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 7556430 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 286903 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 62582 # number of nop insts executed -system.cpu3.iew.exec_refs 13496719 # number of memory reference insts executed -system.cpu3.iew.exec_branches 7548230 # Number of branches executed -system.cpu3.iew.exec_stores 5935989 # Number of stores executed -system.cpu3.iew.exec_rate 0.733912 # Inst execution rate -system.cpu3.iew.wb_sent 40661575 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 40124251 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 21126058 # num instructions producing a value -system.cpu3.iew.wb_consumers 37308798 # num instructions consuming a value -system.cpu3.iew.wb_rate 0.719039 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.566249 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 6107928 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 463664 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 213549 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 53039462 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.713065 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.610172 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 60342 # number of nop insts executed +system.cpu3.iew.exec_refs 13498971 # number of memory reference insts executed +system.cpu3.iew.exec_branches 7544495 # Number of branches executed +system.cpu3.iew.exec_stores 5942541 # Number of stores executed +system.cpu3.iew.exec_rate 0.733928 # Inst execution rate +system.cpu3.iew.wb_sent 40664526 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 40127330 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 21123316 # num instructions producing a value +system.cpu3.iew.wb_consumers 37320445 # num instructions consuming a value +system.cpu3.iew.wb_rate 0.719074 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.565999 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 6097313 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 465472 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 213597 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 53033650 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.713199 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.610019 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 38622110 72.82% 72.82% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 6314877 11.91% 84.72% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 3213776 6.06% 90.78% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 1409463 2.66% 93.44% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 790260 1.49% 94.93% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 551904 1.04% 95.97% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 961415 1.81% 97.78% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 244563 0.46% 98.24% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 931094 1.76% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 38610990 72.80% 72.80% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 6319361 11.92% 84.72% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 3213493 6.06% 90.78% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 1410131 2.66% 93.44% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 792140 1.49% 94.93% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 553402 1.04% 95.98% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 958153 1.81% 97.78% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 245496 0.46% 98.25% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 930484 1.75% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 53039462 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 31045718 # Number of instructions committed -system.cpu3.commit.committedOps 37820561 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 53033650 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 31044800 # Number of instructions committed +system.cpu3.commit.committedOps 37823572 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 12488538 # Number of memory references committed -system.cpu3.commit.loads 6782920 # Number of loads committed -system.cpu3.commit.membars 181312 # Number of memory barriers committed -system.cpu3.commit.branches 7134012 # Number of branches committed -system.cpu3.commit.fp_insts 3283 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 32975843 # Number of committed integer instructions. -system.cpu3.commit.function_calls 1245781 # Number of function calls committed. +system.cpu3.commit.refs 12492071 # Number of memory references committed +system.cpu3.commit.loads 6779470 # Number of loads committed +system.cpu3.commit.membars 181779 # Number of memory barriers committed +system.cpu3.commit.branches 7130164 # Number of branches committed +system.cpu3.commit.fp_insts 3347 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 32983556 # Number of committed integer instructions. +system.cpu3.commit.function_calls 1245135 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 25299473 66.89% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 30222 0.08% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 25299125 66.89% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 30044 0.08% 66.97% # Class of committed instruction system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.97% # Class of committed instruction system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.97% # Class of committed instruction system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.97% # Class of committed instruction @@ -2138,36 +2132,36 @@ system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.97% # system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.97% # Class of committed instruction system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.97% # Class of committed instruction system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 2328 0.01% 66.98% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.98% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.98% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.98% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 6782920 17.93% 84.91% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 5705618 15.09% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 2332 0.01% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 6779470 17.92% 84.90% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 5712601 15.10% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 37820561 # Class of committed instruction -system.cpu3.commit.bw_lim_events 931094 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 90431014 # The number of ROB reads -system.cpu3.rob.rob_writes 89155949 # The number of ROB writes -system.cpu3.timesIdled 227288 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1464060 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 5161848397 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 31005981 # Number of Instructions Simulated -system.cpu3.committedOps 37780824 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.799736 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.799736 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.555637 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.555637 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 44884059 # number of integer regfile reads -system.cpu3.int_regfile_writes 25155589 # number of integer regfile writes -system.cpu3.fp_regfile_reads 14375 # number of floating regfile reads -system.cpu3.fp_regfile_writes 12072 # number of floating regfile writes -system.cpu3.cc_regfile_reads 144434496 # number of cc regfile reads -system.cpu3.cc_regfile_writes 15958517 # number of cc regfile writes -system.cpu3.misc_regfile_reads 98379107 # number of misc regfile reads -system.cpu3.misc_regfile_writes 343145 # number of misc regfile writes -system.iobus.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu3.commit.op_class_0::total 37823572 # Class of committed instruction +system.cpu3.commit.bw_lim_events 930484 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 90425378 # The number of ROB reads +system.cpu3.rob.rob_writes 89139493 # The number of ROB writes +system.cpu3.timesIdled 227716 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1472719 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 5161848513 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 31006304 # Number of Instructions Simulated +system.cpu3.committedOps 37785076 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.799770 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.799770 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.555627 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.555627 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 44890181 # number of integer regfile reads +system.cpu3.int_regfile_writes 25156907 # number of integer regfile writes +system.cpu3.fp_regfile_reads 14457 # number of floating regfile reads +system.cpu3.fp_regfile_writes 12074 # number of floating regfile writes +system.cpu3.cc_regfile_reads 144431120 # number of cc regfile reads +system.cpu3.cc_regfile_writes 15956854 # number of cc regfile writes +system.cpu3.misc_regfile_reads 98347677 # number of misc regfile reads +system.cpu3.misc_regfile_writes 344757 # number of misc regfile writes +system.iobus.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30152 # Transaction distribution system.iobus.trans_dist::ReadResp 30152 # Transaction distribution system.iobus.trans_dist::WriteReq 59010 # Transaction distribution @@ -2218,15 +2212,15 @@ system.iobus.pkt_size_system.bridge.master::total 159093 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480085 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 29851500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 29764500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 228500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 229000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 19500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 20500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 4500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2236,32 +2230,32 @@ system.iobus.reqLayer19.occupancy 3000 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 4026500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 3967500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 23286500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 23290000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 72958030 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 72552043 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 50254000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 50146000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 14338000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 14254000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.002565 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.002362 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 248718527509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.002565 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062660 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062660 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 248718607009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.002362 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062648 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062648 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 327996 # Number of tag accesses system.iocache.tags.data_accesses 327996 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses system.iocache.ReadReq_misses::total 220 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2270,14 +2264,14 @@ system.iocache.demand_misses::realview.ide 36444 # system.iocache.demand_misses::total 36444 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36444 # number of overall misses system.iocache.overall_misses::total 36444 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 16295912 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 16295912 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 1689414118 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 1689414118 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 1705710030 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1705710030 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 1705710030 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1705710030 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 16061914 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 16061914 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 1680216129 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 1680216129 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 1696278043 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1696278043 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 1696278043 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1696278043 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2294,14 +2288,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 74072.327273 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 74072.327273 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 46637.978081 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 46637.978081 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 46803.589891 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 46803.589891 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 46803.589891 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 46803.589891 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 73008.700000 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 73008.700000 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 46384.058331 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 46384.058331 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 46544.782214 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 46544.782214 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 46544.782214 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 46544.782214 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2310,744 +2304,744 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 137 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 137 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 14064 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 14064 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 14201 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 14201 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 14201 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 14201 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 9445912 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 9445912 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 985358547 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 985358547 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 994804459 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 994804459 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 994804459 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 994804459 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.622727 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.622727 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.388251 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.388251 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.389666 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.389666 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.389666 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.389666 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68948.262774 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68948.262774 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70062.467790 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70062.467790 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70051.718823 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70051.718823 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70051.718823 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70051.718823 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 100866 # number of replacements -system.l2c.tags.tagsinuse 65104.734410 # Cycle average of tags in use -system.l2c.tags.total_refs 5134220 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 166034 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 30.922703 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 79359149000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 49022.002356 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.902695 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.002960 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4655.957926 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1835.969861 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000002 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 774.839390 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 858.475569 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 20.852845 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2233.809872 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 830.848364 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 56.245543 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.itb.walker 0.001828 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2978.546484 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 1834.278716 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.748016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.071044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.028015 # Average percentage of cache occupancy +system.iocache.ReadReq_mshr_misses::realview.ide 135 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 135 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 13984 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 13984 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 14119 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 14119 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 14119 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 14119 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 9311914 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 9311914 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 980165529 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 980165529 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 989477443 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 989477443 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 989477443 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 989477443 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.613636 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.613636 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.386042 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.386042 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.387416 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.387416 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.387416 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.387416 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68977.140741 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68977.140741 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70091.928561 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70091.928561 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70081.269424 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70081.269424 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70081.269424 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70081.269424 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 100900 # number of replacements +system.l2c.tags.tagsinuse 65188.817028 # Cycle average of tags in use +system.l2c.tags.total_refs 5432391 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 166232 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 32.679574 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 76153677500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.990870 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.930107 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.003315 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4645.223340 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 20148.450289 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.003029 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 771.166553 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6124.303836 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 20.124161 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2252.228504 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 10091.945751 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 55.278842 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.itb.walker 0.002282 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2987.422614 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 18086.743533 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.070880 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.307441 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011823 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013099 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000318 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034085 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.012678 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000858 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.011767 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.093449 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000307 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.034366 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.153991 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000843 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.045449 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.027989 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993419 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 60 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65108 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 60 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2141 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8201 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54725 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000916 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.993469 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45365928 # Number of tag accesses -system.l2c.tags.data_accesses 45365928 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 4277 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2153 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 1575 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 876 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 12818 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 1200 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 20699 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 3759 # number of ReadReq hits -system.l2c.ReadReq_hits::total 47357 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 691735 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 691735 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1932411 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1932411 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 9 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3.data 31 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 56 # number of UpgradeReq hits +system.l2c.tags.occ_percent::cpu3.inst 0.045584 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.275982 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994702 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 65 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65267 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 59 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5926 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 59314 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000992 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.995895 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 45033905 # Number of tag accesses +system.l2c.tags.data_accesses 45033905 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.l2c.ReadReq_hits::cpu0.dtb.walker 3242 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1702 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 1228 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 661 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 12254 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 909 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.dtb.walker 19814 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.itb.walker 3415 # number of ReadReq hits +system.l2c.ReadReq_hits::total 43225 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 692039 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 692039 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1932297 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1932297 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 1108 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 480 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 437 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3.data 765 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2790 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu3.data 16 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 17 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 66409 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 22548 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 25529 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3.data 44640 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 159126 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 735776 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 211019 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 464507 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 537647 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1948949 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 223325 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 69756 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 89766 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 140401 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 523248 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4277 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2153 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 735776 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 289734 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 1575 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 876 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 211019 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 92304 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 12818 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 1200 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 464507 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 115295 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.dtb.walker 20699 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.itb.walker 3759 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 537647 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 185041 # number of demand (read+write) hits -system.l2c.demand_hits::total 2678680 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4277 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2153 # number of overall hits -system.l2c.overall_hits::cpu0.inst 735776 # number of overall hits -system.l2c.overall_hits::cpu0.data 289734 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 1575 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 876 # number of overall hits -system.l2c.overall_hits::cpu1.inst 211019 # number of overall hits -system.l2c.overall_hits::cpu1.data 92304 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 12818 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 1200 # number of overall hits -system.l2c.overall_hits::cpu2.inst 464507 # number of overall hits -system.l2c.overall_hits::cpu2.data 115295 # number of overall hits -system.l2c.overall_hits::cpu3.dtb.walker 20699 # number of overall hits -system.l2c.overall_hits::cpu3.itb.walker 3759 # number of overall hits -system.l2c.overall_hits::cpu3.inst 537647 # number of overall hits -system.l2c.overall_hits::cpu3.data 185041 # number of overall hits -system.l2c.overall_hits::total 2678680 # number of overall hits +system.l2c.SCUpgradeReq_hits::cpu3.data 25 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 26 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 67205 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 22539 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 26172 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3.data 44897 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 160813 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 736420 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 210026 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 463898 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 538419 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1948763 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 223430 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 69477 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 90045 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3.data 140227 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 523179 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 3242 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1702 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 736420 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 290635 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 1228 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 661 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 210026 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 92016 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 12254 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 909 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 463898 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 116217 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.dtb.walker 19814 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.itb.walker 3415 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 538419 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 185124 # number of demand (read+write) hits +system.l2c.demand_hits::total 2675980 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 3242 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1702 # number of overall hits +system.l2c.overall_hits::cpu0.inst 736420 # number of overall hits +system.l2c.overall_hits::cpu0.data 290635 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 1228 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 661 # number of overall hits +system.l2c.overall_hits::cpu1.inst 210026 # number of overall hits +system.l2c.overall_hits::cpu1.data 92016 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 12254 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 909 # number of overall hits +system.l2c.overall_hits::cpu2.inst 463898 # number of overall hits +system.l2c.overall_hits::cpu2.data 116217 # number of overall hits +system.l2c.overall_hits::cpu3.dtb.walker 19814 # number of overall hits +system.l2c.overall_hits::cpu3.itb.walker 3415 # number of overall hits +system.l2c.overall_hits::cpu3.inst 538419 # number of overall hits +system.l2c.overall_hits::cpu3.data 185124 # number of overall hits +system.l2c.overall_hits::total 2675980 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.dtb.walker 28 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.dtb.walker 74 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.dtb.walker 71 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 111 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1108 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 471 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 437 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 730 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2746 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu3.data 4 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 44938 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 11967 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 29307 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 51051 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 137263 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 7908 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1917 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 5345 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu3.inst 5962 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 21132 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 5135 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 2415 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 2185 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3.data 4425 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 14160 # number of ReadSharedReq misses +system.l2c.ReadReq_misses::total 108 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 3 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 1 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu3.data 2 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 43978 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 11759 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 29016 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 50830 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 135583 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 7835 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 1898 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 5370 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 6053 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 21156 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 5105 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 2412 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 2209 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3.data 4457 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 14183 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7908 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 50073 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7835 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 49083 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1917 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 14382 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1898 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 14171 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.dtb.walker 28 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 5345 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 31492 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.dtb.walker 74 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 5370 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 31225 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.dtb.walker 71 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 5962 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 55476 # number of demand (read+write) misses -system.l2c.demand_misses::total 172666 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 6053 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 55287 # number of demand (read+write) misses +system.l2c.demand_misses::total 171030 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7908 # number of overall misses -system.l2c.overall_misses::cpu0.data 50073 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7835 # number of overall misses +system.l2c.overall_misses::cpu0.data 49083 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1917 # number of overall misses -system.l2c.overall_misses::cpu1.data 14382 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1898 # number of overall misses +system.l2c.overall_misses::cpu1.data 14171 # number of overall misses system.l2c.overall_misses::cpu2.dtb.walker 28 # number of overall misses -system.l2c.overall_misses::cpu2.inst 5345 # number of overall misses -system.l2c.overall_misses::cpu2.data 31492 # number of overall misses -system.l2c.overall_misses::cpu3.dtb.walker 74 # number of overall misses +system.l2c.overall_misses::cpu2.inst 5370 # number of overall misses +system.l2c.overall_misses::cpu2.data 31225 # number of overall misses +system.l2c.overall_misses::cpu3.dtb.walker 71 # number of overall misses system.l2c.overall_misses::cpu3.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu3.inst 5962 # number of overall misses -system.l2c.overall_misses::cpu3.data 55476 # number of overall misses -system.l2c.overall_misses::total 172666 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 97500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2372000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.dtb.walker 6843500 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu3.inst 6053 # number of overall misses +system.l2c.overall_misses::cpu3.data 55287 # number of overall misses +system.l2c.overall_misses::total 171030 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 83500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2403500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.dtb.walker 6664000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.itb.walker 84000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 9397000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 29500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 173000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3.data 234000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 436500 # number of UpgradeReq miss cycles +system.l2c.ReadReq_miss_latency::total 9235000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 59000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 86500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3.data 29500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 175000 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu3.data 162500 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 162500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 940191500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 2264857500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 4197518500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7402567500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 159894500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu2.inst 444350000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu3.inst 496961999 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1101206499 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 202988000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2.data 181452000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3.data 393224500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 777664500 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 97500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 159894500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1143179500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 2372000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 444350000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 2446309500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.dtb.walker 6843500 # number of demand (read+write) miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 940228500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 2258171500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 4211938000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7410338000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 154678500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 443554000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu3.inst 505532999 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1103765499 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 202470000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 181243500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3.data 394790500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 778504000 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 83500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 154678500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1142698500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 2403500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 443554000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 2439415000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.dtb.walker 6664000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu3.itb.walker 84000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 496961999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 4590743000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9290835499 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 97500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 159894500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1143179500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 2372000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 444350000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 2446309500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.dtb.walker 6843500 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu3.inst 505532999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 4606728500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9301842499 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 83500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 154678500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1142698500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 2403500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 443554000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 2439415000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.dtb.walker 6664000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu3.itb.walker 84000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 496961999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 4590743000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9290835499 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4282 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2155 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 1576 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 876 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 12846 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 1200 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.dtb.walker 20773 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.itb.walker 3760 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 47468 # number of ReadReq accesses(hits+misses) -system.l2c.WritebackDirty_accesses::writebacks 691735 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 691735 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 1932411 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 1932411 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1119 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 476 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 446 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 761 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2802 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu3.inst 505532999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 4606728500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9301842499 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 3247 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1704 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 1229 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 661 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 12282 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 909 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.dtb.walker 19885 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.itb.walker 3416 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 43333 # number of ReadReq accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 692039 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 692039 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 1932297 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 1932297 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1113 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 482 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 440 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 766 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2801 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu3.data 20 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 21 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111347 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 34515 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 54836 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 95691 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296389 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 743684 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 212936 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu2.inst 469852 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu3.inst 543609 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1970081 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 228460 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 72171 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2.data 91951 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3.data 144826 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 537408 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4282 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2155 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 743684 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 339807 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 1576 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 876 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 212936 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 106686 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 12846 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 1200 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 469852 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 146787 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.dtb.walker 20773 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.itb.walker 3760 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 543609 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 240517 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2851346 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4282 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 2155 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 743684 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 339807 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 1576 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 876 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 212936 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 106686 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 12846 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 1200 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 469852 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 146787 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.dtb.walker 20773 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.itb.walker 3760 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 543609 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 240517 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2851346 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001168 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000928 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000635 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.002180 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.dtb.walker 0.003562 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.itb.walker 0.000266 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.002338 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990170 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989496 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.979821 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3.data 0.959264 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.980014 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu3.data 0.200000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.190476 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.403585 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.346719 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.534448 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 0.533498 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.463118 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.010634 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.009003 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.011376 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.010967 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.010726 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.022477 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.033462 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.023763 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.030554 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.026349 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001168 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000928 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.010634 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.147357 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000635 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009003 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.134807 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.002180 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.011376 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.214542 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.dtb.walker 0.003562 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.itb.walker 0.000266 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.010967 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.230653 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.060556 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001168 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000928 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.010634 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.147357 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000635 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009003 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.134807 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.002180 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.011376 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.214542 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.dtb.walker 0.003562 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.itb.walker 0.000266 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.010967 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.230653 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.060556 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 97500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 84714.285714 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 92479.729730 # average ReadReq miss latency +system.l2c.SCUpgradeReq_accesses::cpu3.data 27 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111183 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 34298 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 55188 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 95727 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296396 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 744255 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 211924 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 469268 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu3.inst 544472 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1969919 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 228535 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 71889 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 92254 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3.data 144684 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 537362 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 3247 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1704 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 744255 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 339718 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 1229 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 661 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 211924 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 106187 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 12282 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 909 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 469268 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 147442 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.dtb.walker 19885 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.itb.walker 3416 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 544472 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 240411 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2847010 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 3247 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1704 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 744255 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 339718 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 1229 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 661 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 211924 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 106187 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 12282 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 909 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 469268 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 147442 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.dtb.walker 19885 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.itb.walker 3416 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 544472 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 240411 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2847010 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001540 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001174 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000814 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.002280 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.dtb.walker 0.003571 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.itb.walker 0.000293 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.002492 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.004492 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.004149 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.006818 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 0.001305 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.003927 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu3.data 0.074074 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.071429 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.395546 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.342848 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.525766 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 0.530989 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.457439 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.010527 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.008956 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.011443 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.011117 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.010740 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.022338 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.033552 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.023945 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.030805 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.026394 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001540 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.001174 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.010527 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.144482 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000814 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.008956 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.133453 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.002280 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.011443 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.211778 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.dtb.walker 0.003571 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.itb.walker 0.000293 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.011117 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.229969 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.060074 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001540 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.001174 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.010527 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.144482 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000814 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.008956 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.133453 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.002280 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.011443 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.211778 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.dtb.walker 0.003571 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.itb.walker 0.000293 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.011117 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.229969 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.060074 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 85839.285714 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 93859.154930 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 84000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 84657.657658 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 62.632696 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 395.881007 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 320.547945 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 158.958485 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data 40625 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 40625 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 78565.346369 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 77280.427884 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 82222.062251 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53929.809927 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 83408.711528 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 83133.769878 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 83354.914291 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 52110.850795 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 84053.002070 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 83044.393593 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 88864.293785 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 54919.809322 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 97500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 83408.711528 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 79486.823808 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 84714.285714 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 83133.769878 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 77680.347390 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 92479.729730 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::total 85509.259259 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 29500 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 28833.333333 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 29500 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 15909.090909 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data 81250 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 81250 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 79958.202228 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 77825.044803 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 82863.230376 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 54655.362398 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81495.521602 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 82598.510242 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 83517.759623 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 52172.693279 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83942.786070 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 82047.759167 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 88577.630693 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 54889.938659 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 81495.521602 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 80636.405335 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 85839.285714 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 82598.510242 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 78123.779023 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 93859.154930 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.itb.walker 84000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 83354.914291 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 82751.874685 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 53808.135354 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 97500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 83408.711528 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 79486.823808 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 84714.285714 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 83133.769878 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 77680.347390 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 92479.729730 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 83517.759623 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 83323.900736 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 54387.198147 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 81495.521602 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 80636.405335 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 85839.285714 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 82598.510242 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 78123.779023 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 93859.154930 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.itb.walker 84000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 83354.914291 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 82751.874685 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 53808.135354 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 83517.759623 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 83323.900736 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 54387.198147 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 92509 # number of writebacks -system.l2c.writebacks::total 92509 # number of writebacks +system.l2c.writebacks::writebacks 92528 # number of writebacks +system.l2c.writebacks::total 92528 # number of writebacks system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 4 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 5 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2.data 18 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3.data 45 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 63 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2.data 20 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu3.data 46 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 66 # number of ReadSharedReq MSHR hits system.l2c.demand_mshr_hits::cpu2.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.data 18 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.data 20 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu3.inst 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3.data 45 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.data 46 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu2.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.data 18 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.data 20 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu3.inst 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3.data 45 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 72 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.data 46 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 28 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker 74 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker 71 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu3.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 471 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 437 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 730 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1638 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu3.data 4 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 11967 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 29307 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3.data 51051 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 92325 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1917 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 5341 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 5957 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 13215 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2415 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2.data 2167 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu3.data 4380 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 8962 # number of ReadSharedReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 2 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 3 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 1 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu3.data 2 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 11759 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 29016 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3.data 50830 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 91605 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1898 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 5366 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 6048 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 13312 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2412 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 2189 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu3.data 4411 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 9012 # number of ReadSharedReq MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1917 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 14382 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1898 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 14171 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.dtb.walker 28 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 5341 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 31474 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.dtb.walker 74 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 5366 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 31205 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.dtb.walker 71 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu3.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.inst 5957 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.data 55431 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 114606 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 6048 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.data 55241 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 114030 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1917 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 14382 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1898 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 14171 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.dtb.walker 28 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 5341 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 31474 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.dtb.walker 74 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 5366 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 31205 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.dtb.walker 71 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.inst 5957 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.data 55431 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 114606 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3449 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2.data 7107 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu3.data 7761 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 18317 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2842 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2.data 5190 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu3.data 6229 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 14261 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 6291 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2.data 12297 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu3.data 13990 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 32578 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 87500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2092000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker 6103500 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu3.inst 6048 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.data 55241 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 114030 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3424 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2.data 7112 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu3.data 7739 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 18275 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2828 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2.data 5192 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu3.data 6207 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 14227 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 6252 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2.data 12304 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu3.data 13946 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 32502 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 73500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2123500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker 5954000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker 74000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 8357000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 8934500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 8316500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 13861000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 31112000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data 180500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 180500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 820521500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1971787500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 3687008500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 6479317500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 140724500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 390804500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 437012499 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 968541499 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 178838000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 158632000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 346274500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 683744500 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 87500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 140724500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 999359500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2092000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 390804500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2130419500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker 6103500 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 8225000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 39000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 56500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 19500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 115000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data 142500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 142500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 822638500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1968011500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 3703638000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 6494288000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 135698500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 389778500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 444784999 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 970261999 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 178350000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 157962500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 346988500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 683301000 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 73500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 135698500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1000988500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2123500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 389778500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2125974000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker 5954000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.itb.walker 74000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 437012499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 4033283000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8139960499 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 87500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 140724500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 999359500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2092000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 390804500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2130419500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 6103500 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 444784999 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 4050626500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 8156075999 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 73500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 135698500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1000988500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2123500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 389778500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2125974000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 5954000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.itb.walker 74000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 437012499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 4033283000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8139960499 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 561987500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1400221000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 1571751000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3533959500 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 561987500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 1400221000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3.data 1571751000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 3533959500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000635 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.002180 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003562 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.000266 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.002191 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989496 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.979821 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.959264 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.584582 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.200000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.190476 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.346719 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.534448 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.533498 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.311499 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.009003 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.011367 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010958 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006708 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.033462 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.023567 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.030243 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.016676 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000635 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009003 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.134807 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002180 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011367 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.214420 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003562 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.000266 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010958 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.230466 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.040194 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000635 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009003 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.134807 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002180 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011367 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.214420 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003562 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.000266 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010958 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.230466 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.040194 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 87500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74714.285714 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 82479.729730 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_latency::cpu3.inst 444784999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 4050626500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 8156075999 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 558689000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1400703000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 1566927500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3526319500 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 558689000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 1400703000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3.data 1566927500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3526319500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000814 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.002280 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003571 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.000293 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.002331 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.004149 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.006818 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.001305 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.002142 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.074074 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.071429 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.342848 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.525766 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.530989 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.309063 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.008956 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.011435 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.011108 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006758 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.033552 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.023728 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.030487 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.016771 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000814 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008956 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.133453 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002280 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011435 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.211643 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003571 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.000293 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.011108 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.229777 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.040053 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000814 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008956 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.133453 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002280 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011435 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.211643 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003571 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.000293 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.011108 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.229777 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.040053 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 75839.285714 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 83859.154930 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 80355.769231 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18969.214437 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19030.892449 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18987.671233 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18993.894994 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 45125 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 45125 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68565.346369 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 67280.427884 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 72222.062251 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 70179.447604 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 73408.711528 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73170.660925 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73361.171563 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73291.070677 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74053.002070 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73203.507153 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 79058.105023 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76293.740237 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 87500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73408.711528 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69486.823808 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74714.285714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73170.660925 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67688.234733 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 82479.729730 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 81435.643564 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 18833.333333 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 19500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19166.666667 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 71250 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71250 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69958.202228 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 67825.044803 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 72863.230376 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70894.470826 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71495.521602 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72638.557585 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73542.493221 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72886.267954 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73942.786070 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72161.946094 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 78664.361823 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75821.238349 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71495.521602 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70636.405335 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 75839.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72638.557585 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 68129.274155 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 83859.154930 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73361.171563 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 72762.226913 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 71025.605108 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 87500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73408.711528 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69486.823808 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74714.285714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73170.660925 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67688.234733 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 82479.729730 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73542.493221 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 73326.451368 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 71525.703753 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71495.521602 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70636.405335 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75839.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72638.557585 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 68129.274155 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 83859.154930 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73361.171563 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 72762.226913 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 71025.605108 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162942.157147 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 197019.980301 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202519.134132 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 192933.313315 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 89331.982197 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 113866.878100 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 112348.177269 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 108476.870894 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 349065 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 146440 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73542.493221 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 73326.451368 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 71525.703753 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163168.516355 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 196949.240720 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202471.572555 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 192958.659371 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 89361.644274 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 113841.271131 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 112356.768966 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 108495.461818 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 344722 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 142063 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 40114 # Transaction distribution -system.membus.trans_dist::ReadResp 75665 # Transaction distribution +system.membus.trans_dist::ReadResp 75706 # Transaction distribution system.membus.trans_dist::WriteReq 27565 # Transaction distribution system.membus.trans_dist::WriteResp 27565 # Transaction distribution -system.membus.trans_dist::WritebackDirty 128699 # Transaction distribution -system.membus.trans_dist::CleanEvict 8576 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4535 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1836 # Transaction distribution -system.membus.trans_dist::ReadExReq 135474 # Transaction distribution -system.membus.trans_dist::ReadExResp 135474 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 35551 # Transaction distribution +system.membus.trans_dist::WritebackDirty 128718 # Transaction distribution +system.membus.trans_dist::CleanEvict 8591 # Transaction distribution +system.membus.trans_dist::UpgradeReq 126 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 40 # Transaction distribution +system.membus.trans_dist::ReadExReq 135468 # Transaction distribution +system.membus.trans_dist::ReadExResp 135468 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 35592 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 22160 # Transaction distribution +system.membus.trans_dist::InvalidateResp 22240 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 476553 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 584005 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95097 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 95097 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 470452 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 577904 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95179 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 95179 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 673083 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16895100 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17058225 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2321472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2321472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19379697 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 340 # Total snoops (count) -system.membus.snoopTraffic 21632 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 342782 # Request fanout histogram -system.membus.snoop_fanout::mean 0.015424 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.123231 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16898684 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17061809 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2321600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2321600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19383409 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 336 # Total snoops (count) +system.membus.snoopTraffic 21376 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 338143 # Request fanout histogram +system.membus.snoop_fanout::mean 0.015650 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.124118 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 337495 98.46% 98.46% # Request fanout histogram -system.membus.snoop_fanout::1 5287 1.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 332851 98.43% 98.43% # Request fanout histogram +system.membus.snoop_fanout::1 5292 1.57% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 342782 # Request fanout histogram -system.membus.reqLayer0.occupancy 57572000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 338143 # Request fanout histogram +system.membus.reqLayer0.occupancy 57431500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 694499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 684999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 502472051 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 500677543 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 647767750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 649758250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 729588 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 720586 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3079,85 +3073,85 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5637070 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2833088 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 44773 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 304 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 304 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 5637023 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2833220 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 44733 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 306 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 306 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 110855 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2618591 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 111093 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2618641 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 746435 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1969655 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 146584 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2802 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 21 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2823 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296389 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296389 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1970201 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 537545 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4503 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5927985 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2623938 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 25305 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 99572 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8676800 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 252179448 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97825081 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41104 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 175440 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 350221073 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 122763 # Total snoops (count) -system.toL2Bus.snoopTraffic 6010036 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 4133801 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021872 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.146266 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 747081 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1969505 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 146278 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2801 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2829 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296396 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296396 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1970061 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 537497 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4488 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5927533 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2623831 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24350 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 98043 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8673757 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 252159480 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97841913 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37624 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 168032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 350207049 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 125784 # Total snoops (count) +system.toL2Bus.snoopTraffic 6024500 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 4134386 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021942 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.146494 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4043386 97.81% 97.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 90415 2.19% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4043670 97.81% 97.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 90716 2.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4133801 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3409727455 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4134386 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3408827455 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 234412 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 230414 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1840405228 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1839308788 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 767451664 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 767442228 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10602473 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10535976 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 47179732 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 47560224 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed |