diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt | 4525 |
1 files changed, 2258 insertions, 2267 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 8cd4c8c91..c1cc0c7a4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,160 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.824799 # Number of seconds simulated -sim_ticks 2824799320500 # Number of ticks simulated -final_tick 2824799320500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.824861 # Number of seconds simulated +sim_ticks 2824861157500 # Number of ticks simulated +final_tick 2824861157500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 252554 # Simulator instruction rate (inst/s) -host_op_rate 306369 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5799873287 # Simulator tick rate (ticks/s) -host_mem_usage 587696 # Number of bytes of host memory used -host_seconds 487.05 # Real time elapsed on the host -sim_insts 123005008 # Number of instructions simulated -sim_ops 149215388 # Number of ops (including micro ops) simulated +host_inst_rate 318305 # Simulator instruction rate (inst/s) +host_op_rate 386131 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7310787662 # Simulator tick rate (ticks/s) +host_mem_usage 588068 # Number of bytes of host memory used +host_seconds 386.40 # Real time elapsed on the host +sim_insts 122991731 # Number of instructions simulated +sim_ops 149199638 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 540900 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4166756 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 103808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 925440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 328256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1677824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 4416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 415296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 3014912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 541668 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4133796 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 101440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 929920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 334208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1678016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 4352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 417280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 3020416 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11180680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 540900 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 103808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 328256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 415296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1388260 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8418624 # Number of bytes written to this memory +system.physmem.bytes_read::total 11164360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 541668 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 101440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 334208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 417280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1394596 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8401024 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8436148 # Number of bytes written to this memory +system.physmem.bytes_written::total 8418548 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 16905 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 65625 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1622 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 14460 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 29 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5129 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 26216 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 69 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 6489 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 47108 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 16917 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 65110 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 14530 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 32 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5222 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 26219 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 68 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 6520 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 47194 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 183671 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131541 # Number of write requests responded to by this memory +system.physmem.num_reads::total 183416 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131266 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135922 # Number of write requests responded to by this memory +system.physmem.num_writes::total 135647 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 68 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 191483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1475063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 36749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 327613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 116205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 593962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 147018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 1067301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 191750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1463363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35910 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 329191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 118310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 594017 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1541 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 147717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 1069226 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3958044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 191483 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 36749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 116205 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 147018 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 491454 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2980256 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6204 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2986459 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2980256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3952180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 191750 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35910 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 118310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 147717 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 493687 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2973960 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6203 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2980163 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2973960 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 68 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 191483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1481266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 36749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 327613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 116205 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 593962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 147018 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 1067301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 191750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1469566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 35910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 329191 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 118310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 594017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 147717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 1069226 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6944503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 101122 # Number of read requests accepted -system.physmem.writeReqs 69399 # Number of write requests accepted -system.physmem.readBursts 101122 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 69399 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6464000 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue -system.physmem.bytesWritten 4440192 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6471808 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4441536 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6932344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 101370 # Number of read requests accepted +system.physmem.writeReqs 69810 # Number of write requests accepted +system.physmem.readBursts 101370 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 69810 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6481472 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue +system.physmem.bytesWritten 4467008 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6487680 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4467840 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 22992 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 7206 # Per bank write bursts -system.physmem.perBankRdBursts::1 6389 # Per bank write bursts -system.physmem.perBankRdBursts::2 6982 # Per bank write bursts -system.physmem.perBankRdBursts::3 6703 # Per bank write bursts -system.physmem.perBankRdBursts::4 6109 # Per bank write bursts -system.physmem.perBankRdBursts::5 6146 # Per bank write bursts -system.physmem.perBankRdBursts::6 6610 # Per bank write bursts -system.physmem.perBankRdBursts::7 6743 # Per bank write bursts -system.physmem.perBankRdBursts::8 6516 # Per bank write bursts -system.physmem.perBankRdBursts::9 6576 # Per bank write bursts -system.physmem.perBankRdBursts::10 6052 # Per bank write bursts -system.physmem.perBankRdBursts::11 5500 # Per bank write bursts -system.physmem.perBankRdBursts::12 5540 # Per bank write bursts -system.physmem.perBankRdBursts::13 6495 # Per bank write bursts -system.physmem.perBankRdBursts::14 6075 # Per bank write bursts -system.physmem.perBankRdBursts::15 5358 # Per bank write bursts -system.physmem.perBankWrBursts::0 4814 # Per bank write bursts -system.physmem.perBankWrBursts::1 4268 # Per bank write bursts -system.physmem.perBankWrBursts::2 4976 # Per bank write bursts -system.physmem.perBankWrBursts::3 4599 # Per bank write bursts -system.physmem.perBankWrBursts::4 4151 # Per bank write bursts -system.physmem.perBankWrBursts::5 4285 # Per bank write bursts -system.physmem.perBankWrBursts::6 4619 # Per bank write bursts -system.physmem.perBankWrBursts::7 4309 # Per bank write bursts -system.physmem.perBankWrBursts::8 4473 # Per bank write bursts -system.physmem.perBankWrBursts::9 4780 # Per bank write bursts -system.physmem.perBankWrBursts::10 4110 # Per bank write bursts -system.physmem.perBankWrBursts::11 3894 # Per bank write bursts -system.physmem.perBankWrBursts::12 3790 # Per bank write bursts -system.physmem.perBankWrBursts::13 4672 # Per bank write bursts -system.physmem.perBankWrBursts::14 4032 # Per bank write bursts -system.physmem.perBankWrBursts::15 3606 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6935 # Per bank write bursts +system.physmem.perBankRdBursts::1 6436 # Per bank write bursts +system.physmem.perBankRdBursts::2 6583 # Per bank write bursts +system.physmem.perBankRdBursts::3 6249 # Per bank write bursts +system.physmem.perBankRdBursts::4 6342 # Per bank write bursts +system.physmem.perBankRdBursts::5 6194 # Per bank write bursts +system.physmem.perBankRdBursts::6 6523 # Per bank write bursts +system.physmem.perBankRdBursts::7 6688 # Per bank write bursts +system.physmem.perBankRdBursts::8 6445 # Per bank write bursts +system.physmem.perBankRdBursts::9 6967 # Per bank write bursts +system.physmem.perBankRdBursts::10 6205 # Per bank write bursts +system.physmem.perBankRdBursts::11 5540 # Per bank write bursts +system.physmem.perBankRdBursts::12 5538 # Per bank write bursts +system.physmem.perBankRdBursts::13 6823 # Per bank write bursts +system.physmem.perBankRdBursts::14 6219 # Per bank write bursts +system.physmem.perBankRdBursts::15 5586 # Per bank write bursts +system.physmem.perBankWrBursts::0 4692 # Per bank write bursts +system.physmem.perBankWrBursts::1 4257 # Per bank write bursts +system.physmem.perBankWrBursts::2 4659 # Per bank write bursts +system.physmem.perBankWrBursts::3 4198 # Per bank write bursts +system.physmem.perBankWrBursts::4 4374 # Per bank write bursts +system.physmem.perBankWrBursts::5 4446 # Per bank write bursts +system.physmem.perBankWrBursts::6 4601 # Per bank write bursts +system.physmem.perBankWrBursts::7 4285 # Per bank write bursts +system.physmem.perBankWrBursts::8 4489 # Per bank write bursts +system.physmem.perBankWrBursts::9 5118 # Per bank write bursts +system.physmem.perBankWrBursts::10 4303 # Per bank write bursts +system.physmem.perBankWrBursts::11 3737 # Per bank write bursts +system.physmem.perBankWrBursts::12 3765 # Per bank write bursts +system.physmem.perBankWrBursts::13 4849 # Per bank write bursts +system.physmem.perBankWrBursts::14 4212 # Per bank write bursts +system.physmem.perBankWrBursts::15 3812 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2823233051500 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 2823294888500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 101122 # Read request sizes (log2) +system.physmem.readPktSize::6 101370 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 69399 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 77320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 20991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 69810 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 77482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21030 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -183,169 +183,168 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 67 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 67 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 68 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 67 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 67 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 64 # 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Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 275.792296 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 163.681718 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 307.680924 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16252 41.11% 41.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9627 24.35% 65.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3980 10.07% 75.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2061 5.21% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1623 4.11% 84.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1029 2.60% 87.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 580 1.47% 88.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 548 1.39% 90.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3837 9.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39537 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3613 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.947135 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 470.013093 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 3611 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39513 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 277.080657 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.075754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 309.106343 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16212 41.03% 41.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9667 24.47% 65.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3869 9.79% 75.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2066 5.23% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1631 4.13% 84.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 996 2.52% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 644 1.63% 88.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 576 1.46% 90.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3852 9.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39513 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3600 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.123611 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 470.848490 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 3598 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3613 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3613 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.202325 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.997759 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.552053 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 4 0.11% 0.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 2 0.06% 0.17% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 3600 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3600 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.388056 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.044932 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 10.866321 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 5 0.14% 0.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 1 0.03% 0.17% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::8-11 2 0.06% 0.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 5 0.14% 0.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3178 87.96% 88.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 101 2.80% 91.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 43 1.19% 92.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 66 1.83% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 15 0.42% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 55 1.52% 96.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 32 0.89% 96.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.17% 97.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 5 0.14% 97.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 12 0.33% 97.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.06% 97.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.08% 97.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 56 1.55% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.06% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.03% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 11 0.30% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.03% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.22% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3613 # Writes before turning the bus around for reads -system.physmem.totQLat 1315778000 # Total ticks spent queuing -system.physmem.totMemAccLat 3209528000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 505000000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13027.50 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::12-15 4 0.11% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3199 88.86% 89.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 88 2.44% 91.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 45 1.25% 92.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 29 0.81% 93.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 26 0.72% 94.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 9 0.25% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 30 0.83% 95.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 4 0.11% 95.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 51 1.42% 97.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.22% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.17% 97.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.22% 97.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 35 0.97% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.06% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 15 0.42% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 27 0.75% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.06% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 1 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3600 # Writes before turning the bus around for reads +system.physmem.totQLat 1317228500 # Total ticks spent queuing +system.physmem.totMemAccLat 3216097250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 506365000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13006.71 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31777.50 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31756.71 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.30 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 30.16 # Average write queue length when enqueuing -system.physmem.readRowHits 81477 # Number of row buffer hits during reads -system.physmem.writeRowHits 49363 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.13 # Row buffer hit rate for writes -system.physmem.avgGap 16556512.40 # Average gap between requests -system.physmem.pageHitRate 76.78 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 159508440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 86917875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 412503000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 233416080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 179779011360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 73304297100 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1624538062500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1878513716355 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.386003 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2640260933000 # Time in different power states -system.physmem_0.memoryStateTime::REF 91911560000 # Time in different power states +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.92 # Average write queue length when enqueuing +system.physmem.readRowHits 81828 # Number of row buffer hits during reads +system.physmem.writeRowHits 49728 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.80 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.23 # Row buffer hit rate for writes +system.physmem.avgGap 16493135.23 # Average gap between requests +system.physmem.pageHitRate 76.90 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 156575160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 85288500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 405210000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 230117760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 179783588400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 73297208295 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1624589512500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1878547500615 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.380132 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2640349085250 # Time in different power states +system.physmem_0.memoryStateTime::REF 91913900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 20369491500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 20348745750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 139391280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 75900000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 375273600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 216153360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 179779011360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 72455887440 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1616321661750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1869363278790 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.677649 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2641542244250 # Time in different power states -system.physmem_1.memoryStateTime::REF 91911560000 # Time in different power states +system.physmem_1.actEnergy 142143120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 77405625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 384696000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 222166800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 179783588400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 72817182225 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1617846694500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1871273876670 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.628012 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2641092160250 # Time in different power states +system.physmem_1.memoryStateTime::REF 91913900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 19077733750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 19603403000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -395,47 +394,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 4963 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 4963 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 4963 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 4963 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 4963 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 53087691330 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.356118 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -18905470420 -35.61% -35.61% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 71993161750 135.61% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 53087691330 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 2701 66.40% 66.40% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1367 33.60% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4068 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4963 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 4961 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 4961 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 4961 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 4961 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 4961 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 53085056580 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.356184 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -18908069420 -35.62% -35.62% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 71993126000 135.62% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 53085056580 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 2703 66.58% 66.58% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1357 33.42% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4060 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4961 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4963 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4068 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4961 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4060 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4068 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 9031 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4060 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 9021 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 11938297 # DTB read hits -system.cpu0.dtb.read_misses 4171 # DTB read misses -system.cpu0.dtb.write_hits 9295240 # DTB write hits -system.cpu0.dtb.write_misses 792 # DTB write misses +system.cpu0.dtb.read_hits 11954071 # DTB read hits +system.cpu0.dtb.read_misses 4163 # DTB read misses +system.cpu0.dtb.write_hits 9292740 # DTB write hits +system.cpu0.dtb.write_misses 798 # DTB write misses system.cpu0.dtb.flush_tlb 171 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 345 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 343 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2875 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2861 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 692 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 729 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 167 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 11942468 # DTB read accesses -system.cpu0.dtb.write_accesses 9296032 # DTB write accesses +system.cpu0.dtb.perms_faults 164 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 11958234 # DTB read accesses +system.cpu0.dtb.write_accesses 9293538 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21233537 # DTB hits -system.cpu0.dtb.misses 4963 # DTB misses -system.cpu0.dtb.accesses 21238500 # DTB accesses +system.cpu0.dtb.hits 21246811 # DTB hits +system.cpu0.dtb.misses 4961 # DTB misses +system.cpu0.dtb.accesses 21251772 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -465,650 +464,649 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 2305 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2305 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2305 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2305 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2305 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 53087691330 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.356120 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -18905570920 -35.61% -35.61% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 71993262250 135.61% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 53087691330 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1266 73.91% 73.91% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 447 26.09% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1713 # Table walker page sizes translated +system.cpu0.itb.walker.walks 2298 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2298 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2298 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2298 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2298 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 53085056580 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.356187 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -18908211420 -35.62% -35.62% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 71993268000 135.62% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 53085056580 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1259 73.88% 73.88% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 445 26.12% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1704 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2305 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2305 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2298 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2298 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1713 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1713 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4018 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 57022290 # ITB inst hits -system.cpu0.itb.inst_misses 2305 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1704 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1704 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4002 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 57099385 # ITB inst hits +system.cpu0.itb.inst_misses 2298 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 171 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 345 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 343 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1719 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1710 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 57024595 # ITB inst accesses -system.cpu0.itb.hits 57022290 # DTB hits -system.cpu0.itb.misses 2305 # DTB misses -system.cpu0.itb.accesses 57024595 # DTB accesses -system.cpu0.numCycles 68977361 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 57101683 # ITB inst accesses +system.cpu0.itb.hits 57099385 # DTB hits +system.cpu0.itb.misses 2298 # DTB misses +system.cpu0.itb.accesses 57101683 # DTB accesses +system.cpu0.numCycles 69056574 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3088 # number of quiesce instructions executed -system.cpu0.committedInsts 55612915 # Number of instructions committed -system.cpu0.committedOps 67456889 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 59167201 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4525 # Number of float alu accesses -system.cpu0.num_func_calls 5730859 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7383240 # number of instructions that are conditional controls -system.cpu0.num_int_insts 59167201 # number of integer instructions -system.cpu0.num_fp_insts 4525 # number of float instructions -system.cpu0.num_int_register_reads 109233677 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41018104 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3419 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1108 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 205348706 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 25186036 # number of times the CC registers were written -system.cpu0.num_mem_refs 21795373 # number of memory refs -system.cpu0.num_load_insts 12079832 # Number of load instructions -system.cpu0.num_store_insts 9715541 # Number of store instructions -system.cpu0.num_idle_cycles 65194671.854537 # Number of idle cycles -system.cpu0.num_busy_cycles 3782689.145463 # Number of busy cycles -system.cpu0.not_idle_fraction 0.054840 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.945160 # Percentage of idle cycles -system.cpu0.Branches 13504260 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2176 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46697221 68.12% 68.13% # Class of executed instruction -system.cpu0.op_class::IntMult 49891 0.07% 68.20% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3798 0.01% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::MemRead 12079832 17.62% 85.83% # Class of executed instruction -system.cpu0.op_class::MemWrite 9715541 14.17% 100.00% # Class of executed instruction +system.cpu0.kern.inst.quiesce 3089 # number of quiesce instructions executed +system.cpu0.committedInsts 55687288 # Number of instructions committed +system.cpu0.committedOps 67533449 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 59242376 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4494 # Number of float alu accesses +system.cpu0.num_func_calls 5745250 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7381553 # number of instructions that are conditional controls +system.cpu0.num_int_insts 59242376 # number of integer instructions +system.cpu0.num_fp_insts 4494 # number of float instructions +system.cpu0.num_int_register_reads 109364811 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41080412 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3324 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1172 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 205588674 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 25205684 # number of times the CC registers were written +system.cpu0.num_mem_refs 21809022 # number of memory refs +system.cpu0.num_load_insts 12095983 # Number of load instructions +system.cpu0.num_store_insts 9713039 # Number of store instructions +system.cpu0.num_idle_cycles 65267085.823243 # Number of idle cycles +system.cpu0.num_busy_cycles 3789488.176757 # Number of busy cycles +system.cpu0.not_idle_fraction 0.054875 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.945125 # Percentage of idle cycles +system.cpu0.Branches 13519145 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2178 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 46763414 68.14% 68.14% # Class of executed instruction +system.cpu0.op_class::IntMult 50008 0.07% 68.22% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3788 0.01% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::MemRead 12095983 17.63% 85.85% # Class of executed instruction +system.cpu0.op_class::MemWrite 9713039 14.15% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 68548459 # Class of executed instruction -system.cpu0.dcache.tags.replacements 833427 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.996688 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 46067752 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 833939 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.241153 # Average number of references to valid blocks. +system.cpu0.op_class::total 68628410 # Class of executed instruction +system.cpu0.dcache.tags.replacements 834050 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.996936 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 46064647 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 834562 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.196195 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 476.386497 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.984373 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.249015 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 17.376803 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.930442 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.023407 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012205 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.033939 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 476.071339 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 12.092828 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.251514 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 17.581255 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929827 # 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average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16637.205712 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 37224.137931 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 37224.137931 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 31994.177310 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35471.939868 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40542.790998 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37169.316238 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28844.006133 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32340.923393 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37660.970262 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34084.093609 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177105.361239 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 198224.875988 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215905.993432 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202640.545340 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178532.451499 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196258.271840 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 213093.752149 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200852.630387 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 177745.215879 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 197368.208212 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 214663.760608 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 201851.754282 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013739 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.016991 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.017125 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.009080 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016327 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019626 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019366 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.010452 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16890.339748 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14528.801342 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15530.343603 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15516.715462 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 60124.379964 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 66680.693855 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72337.063934 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68414.351230 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13133.129736 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13900.349498 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17626.708418 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15255.257438 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15024.366472 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 17139.810427 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 15682.266910 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15964.394807 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 38310.344828 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 38310.344828 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 32114.775153 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35362.391038 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40515.108883 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37148.023481 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28926.616006 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32230.953838 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37650.205217 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34063.257643 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176222.432354 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 198567.958515 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 216137.290733 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202715.044502 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177386.437029 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196838.390967 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 213367.499553 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200958.851281 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176743.653599 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 197813.634965 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 214914.337108 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 201940.400911 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1980846 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.437171 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 93844389 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1981358 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 47.363671 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1988229 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.436135 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 93879079 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1988741 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 47.205282 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 12780860000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 431.192789 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 10.885225 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 29.403855 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 39.955303 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.842173 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.021260 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.057429 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu3.inst 0.078038 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998901 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 432.331889 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 10.896673 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 29.513324 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu3.inst 38.694249 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.844398 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.021283 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.057643 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu3.inst 0.075575 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998899 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 97851139 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 97851139 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 56302251 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 17886257 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 10425215 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu3.inst 9230666 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 93844389 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 56302251 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 17886257 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 10425215 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu3.inst 9230666 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 93844389 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 56302251 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 17886257 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 10425215 # number of overall hits -system.cpu0.icache.overall_hits::cpu3.inst 9230666 # number of overall hits -system.cpu0.icache.overall_hits::total 93844389 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 721752 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 203984 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 502026 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu3.inst 597588 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2025350 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 721752 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 203984 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 502026 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu3.inst 597588 # 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number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 57024003 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 18090241 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 10927241 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu3.inst 9828254 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 95869739 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 57024003 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 18090241 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 10927241 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu3.inst 9828254 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 95869739 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012657 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011276 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.045943 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.060803 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.021126 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012657 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011276 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.045943 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu3.inst 0.060803 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.021126 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012657 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011276 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.045943 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu3.inst 0.060803 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.021126 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13990.160993 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14265.770100 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 14385.142421 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9189.495637 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13990.160993 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14265.770100 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 14385.142421 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9189.495637 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13990.160993 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14265.770100 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 14385.142421 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9189.495637 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6745 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 97900719 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 97900719 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 56377741 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 17889109 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 10408050 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu3.inst 9204179 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 93879079 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 56377741 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 17889109 # 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average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13565.294373 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13357.950410 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1139,60 +1137,60 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 1928 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 1928 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 500 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1428 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 1928 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 1928 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 1928 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1628 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 13253.992629 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11553.834233 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6560.213470 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-6143 361 22.17% 22.17% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::6144-8191 74 4.55% 26.72% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::10240-12287 476 29.24% 55.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-14335 145 8.91% 64.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::14336-16383 172 10.57% 75.43% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-18431 41 2.52% 77.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::22528-24575 347 21.31% 99.26% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-26623 12 0.74% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1628 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 1881 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 1881 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 484 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1397 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 1881 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 1881 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 1881 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1593 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 14363.151287 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 12650.519591 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6659.719490 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-6143 280 17.58% 17.58% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::6144-8191 51 3.20% 20.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::10240-12287 461 28.94% 49.72% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-14335 64 4.02% 53.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::14336-16383 240 15.07% 68.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-18431 70 4.39% 73.20% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::22528-24575 406 25.49% 98.68% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-26623 21 1.32% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1593 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1130 69.41% 69.41% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 498 30.59% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1628 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1928 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1111 69.74% 69.74% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 482 30.26% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1593 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1881 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1928 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1628 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1881 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1593 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1628 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 3556 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1593 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3474 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3876436 # DTB read hits -system.cpu1.dtb.read_misses 1705 # DTB read misses -system.cpu1.dtb.write_hits 2738772 # DTB write hits -system.cpu1.dtb.write_misses 223 # DTB write misses +system.cpu1.dtb.read_hits 3874640 # DTB read hits +system.cpu1.dtb.read_misses 1654 # DTB read misses +system.cpu1.dtb.write_hits 2733455 # DTB write hits +system.cpu1.dtb.write_misses 227 # DTB write misses system.cpu1.dtb.flush_tlb 150 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 142 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 133 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1110 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1091 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 221 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 239 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 64 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3878141 # DTB read accesses -system.cpu1.dtb.write_accesses 2738995 # DTB write accesses +system.cpu1.dtb.read_accesses 3876294 # DTB read accesses +system.cpu1.dtb.write_accesses 2733682 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6615208 # DTB hits -system.cpu1.dtb.misses 1928 # DTB misses -system.cpu1.dtb.accesses 6617136 # DTB accesses +system.cpu1.dtb.hits 6608095 # DTB hits +system.cpu1.dtb.misses 1881 # DTB misses +system.cpu1.dtb.accesses 6609976 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1222,130 +1220,130 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 970 # Table walker walks requested -system.cpu1.itb.walker.walksShort 970 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 180 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 790 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 970 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 970 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 970 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 698 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12663.323782 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10953.370627 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6428.547911 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 206 29.51% 29.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::6144-8191 1 0.14% 29.66% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 176 25.21% 54.87% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 64 9.17% 64.04% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 123 17.62% 81.66% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 124 17.77% 99.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-26623 4 0.57% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 698 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 931 # Table walker walks requested +system.cpu1.itb.walker.walksShort 931 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 177 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 754 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 931 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 931 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 931 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 674 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 13750.741840 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 12141.602155 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6305.334498 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 145 21.51% 21.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::6144-8191 1 0.15% 21.66% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 171 25.37% 47.03% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 42 6.23% 53.26% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 173 25.67% 78.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 137 20.33% 99.26% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-26623 5 0.74% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 674 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 518 74.21% 74.21% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 180 25.79% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 698 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 497 73.74% 73.74% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 177 26.26% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 674 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 970 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 970 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 931 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 931 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 698 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 698 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 1668 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 18090241 # ITB inst hits -system.cpu1.itb.inst_misses 970 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 674 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 674 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1605 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 18095406 # ITB inst hits +system.cpu1.itb.inst_misses 931 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 150 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 142 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 133 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 729 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 705 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 18091211 # ITB inst accesses -system.cpu1.itb.hits 18090241 # DTB hits -system.cpu1.itb.misses 970 # DTB misses -system.cpu1.itb.accesses 18091211 # DTB accesses -system.cpu1.numCycles 144011692 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 18096337 # ITB inst accesses +system.cpu1.itb.hits 18095406 # DTB hits +system.cpu1.itb.misses 931 # DTB misses +system.cpu1.itb.accesses 18096337 # DTB accesses +system.cpu1.numCycles 144011073 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 17421387 # Number of instructions committed -system.cpu1.committedOps 20908811 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 18586966 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1243 # Number of float alu accesses -system.cpu1.num_func_calls 1994388 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2228706 # number of instructions that are conditional controls -system.cpu1.num_int_insts 18586966 # number of integer instructions -system.cpu1.num_fp_insts 1243 # number of float instructions -system.cpu1.num_int_register_reads 34395717 # number of times the integer registers were read -system.cpu1.num_int_register_writes 13039867 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1047 # number of times the floating registers were read +system.cpu1.committedInsts 17425922 # Number of instructions committed +system.cpu1.committedOps 20908303 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 18576861 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1355 # Number of float alu accesses +system.cpu1.num_func_calls 1992339 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2240244 # number of instructions that are conditional controls +system.cpu1.num_int_insts 18576861 # number of integer instructions +system.cpu1.num_fp_insts 1355 # number of float instructions +system.cpu1.num_int_register_reads 34373942 # number of times the integer registers were read +system.cpu1.num_int_register_writes 13031779 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1159 # number of times the floating registers were read system.cpu1.num_fp_register_writes 196 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 76120282 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 7571334 # number of times the CC registers were written -system.cpu1.num_mem_refs 6808450 # number of memory refs -system.cpu1.num_load_insts 3918979 # Number of load instructions -system.cpu1.num_store_insts 2889471 # Number of store instructions -system.cpu1.num_idle_cycles 136781206.784887 # Number of idle cycles -system.cpu1.num_busy_cycles 7230485.215113 # Number of busy cycles -system.cpu1.not_idle_fraction 0.050208 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.949792 # Percentage of idle cycles -system.cpu1.Branches 4335876 # Number of branches fetched -system.cpu1.op_class::No_OpClass 24 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 14685914 68.27% 68.27% # Class of executed instruction -system.cpu1.op_class::IntMult 16370 0.08% 68.35% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 946 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::MemRead 3918979 18.22% 86.57% # Class of executed instruction -system.cpu1.op_class::MemWrite 2889471 13.43% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 76108520 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 7595432 # number of times the CC registers were written +system.cpu1.num_mem_refs 6800589 # number of memory refs +system.cpu1.num_load_insts 3916596 # Number of load instructions +system.cpu1.num_store_insts 2883993 # Number of store instructions +system.cpu1.num_idle_cycles 136777457.840207 # Number of idle cycles +system.cpu1.num_busy_cycles 7233615.159793 # Number of busy cycles +system.cpu1.not_idle_fraction 0.050230 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.949770 # Percentage of idle cycles +system.cpu1.Branches 4344988 # Number of branches fetched +system.cpu1.op_class::No_OpClass 22 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 14692274 68.30% 68.30% # Class of executed instruction +system.cpu1.op_class::IntMult 16424 0.08% 68.38% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 958 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::MemRead 3916596 18.21% 86.59% # Class of executed instruction +system.cpu1.op_class::MemWrite 2883993 13.41% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21511704 # Class of executed instruction -system.cpu2.branchPred.lookups 5805237 # Number of BP lookups -system.cpu2.branchPred.condPredicted 2994100 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 512421 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3358874 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2415611 # Number of BTB hits +system.cpu1.op_class::total 21510267 # Class of executed instruction +system.cpu2.branchPred.lookups 5796775 # Number of BP lookups +system.cpu2.branchPred.condPredicted 2983658 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 509824 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3342660 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2404944 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 71.917285 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 1615920 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 333124 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 71.947012 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 1622496 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 331360 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1375,55 +1373,54 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 12664 # Table walker walks requested -system.cpu2.dtb.walker.walksShort 12664 # Table walker walks initiated with short descriptors -system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 8020 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4644 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 12664 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 12664 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 12664 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 2157 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 12096.893834 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 10423.094509 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 6904.169413 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-16383 1795 83.22% 83.22% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::16384-32767 361 16.74% 99.95% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::131072-147455 1 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 2157 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walks 13089 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 13089 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 8217 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4872 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 13089 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 13089 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 13089 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 2190 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 13303.881279 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 11625.278622 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 8511.286061 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-32767 2189 99.95% 99.95% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::262144-294911 1 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 2190 # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walksPending::samples 2000052000 # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::0 2000052000 100.00% 100.00% # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::total 2000052000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 1306 60.55% 60.55% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::1M 851 39.45% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 2157 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12664 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkPageSizes::4K 1357 61.96% 61.96% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 833 38.04% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 2190 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 13089 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12664 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2157 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 13089 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2190 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2157 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 14821 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2190 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 15279 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 4677262 # DTB read hits -system.cpu2.dtb.read_misses 11320 # DTB read misses -system.cpu2.dtb.write_hits 3564595 # DTB write hits -system.cpu2.dtb.write_misses 1344 # DTB write misses -system.cpu2.dtb.flush_tlb 154 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 157 # Number of times TLB was flushed by MVA +system.cpu2.dtb.read_hits 4658776 # DTB read hits +system.cpu2.dtb.read_misses 11701 # DTB read misses +system.cpu2.dtb.write_hits 3572503 # DTB write hits +system.cpu2.dtb.write_misses 1388 # DTB write misses +system.cpu2.dtb.flush_tlb 153 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 167 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 1473 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 212 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 332 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 1490 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 207 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 330 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 121 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 4688582 # DTB read accesses -system.cpu2.dtb.write_accesses 3565939 # DTB write accesses +system.cpu2.dtb.perms_faults 125 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 4670477 # DTB read accesses +system.cpu2.dtb.write_accesses 3573891 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 8241857 # DTB hits -system.cpu2.dtb.misses 12664 # DTB misses -system.cpu2.dtb.accesses 8254521 # DTB accesses +system.cpu2.dtb.hits 8231279 # DTB hits +system.cpu2.dtb.misses 13089 # DTB misses +system.cpu2.dtb.accesses 8244368 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1453,81 +1450,82 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 1329 # Table walker walks requested -system.cpu2.itb.walker.walksShort 1329 # Table walker walks initiated with short descriptors -system.cpu2.itb.walker.walksShortTerminationLevel::Level1 263 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1066 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 1329 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 1329 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 1329 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 852 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 12299.295775 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 10742.634902 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 6145.721581 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::4096-6143 262 30.75% 30.75% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::10240-12287 255 29.93% 60.68% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::12288-14335 38 4.46% 65.14% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::14336-16383 163 19.13% 84.27% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::22528-24575 131 15.38% 99.65% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walks 1368 # Table walker walks requested +system.cpu2.itb.walker.walksShort 1368 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walksShortTerminationLevel::Level1 248 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1120 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 1368 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 1368 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 1368 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 861 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 13222.996516 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 11667.249033 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 6172.725517 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::4096-6143 213 24.74% 24.74% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::6144-8191 1 0.12% 24.85% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::10240-12287 235 27.29% 52.15% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::12288-14335 37 4.30% 56.45% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::14336-16383 216 25.09% 81.53% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::22528-24575 156 18.12% 99.65% # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walkCompletionTime::24576-26623 3 0.35% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 852 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 861 # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walksPending::samples 2000037500 # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::0 2000037500 100.00% 100.00% # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::total 2000037500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 589 69.13% 69.13% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::1M 263 30.87% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 852 # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::4K 613 71.20% 71.20% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 248 28.80% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 861 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1329 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1329 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1368 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1368 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 852 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 852 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 2181 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 10929097 # ITB inst hits -system.cpu2.itb.inst_misses 1329 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 861 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 861 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 2229 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 10912675 # ITB inst hits +system.cpu2.itb.inst_misses 1368 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 154 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 157 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb 153 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 167 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 862 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 871 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1732 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1750 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 10930426 # ITB inst accesses -system.cpu2.itb.hits 10929097 # DTB hits -system.cpu2.itb.misses 1329 # DTB misses -system.cpu2.itb.accesses 10930426 # DTB accesses -system.cpu2.numCycles 1393382531 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 10914043 # ITB inst accesses +system.cpu2.itb.hits 10912675 # DTB hits +system.cpu2.itb.misses 1368 # DTB misses +system.cpu2.itb.accesses 10914043 # DTB accesses +system.cpu2.numCycles 1393518293 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 20580093 # Number of instructions committed -system.cpu2.committedOps 24901206 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 1467300 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 567 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 4256226860 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 67.705356 # CPI: cycles per instruction -system.cpu2.ipc 0.014770 # IPC: instructions per cycle +system.cpu2.committedInsts 20499509 # Number of instructions committed +system.cpu2.committedOps 24824986 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 1466668 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 563 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 4256214875 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 67.978130 # CPI: cycles per instruction +system.cpu2.ipc 0.014711 # IPC: instructions per cycle system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 42624758 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 1350757773 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 13301320 # Number of BP lookups -system.cpu3.branchPred.condPredicted 7249235 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 312069 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 8284814 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 6256612 # Number of BTB hits +system.cpu2.tickCycles 42617577 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 1350900716 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 13279535 # Number of BP lookups +system.cpu3.branchPred.condPredicted 7247058 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 312507 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 8265977 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 6247053 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 75.519040 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 3109270 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 16225 # Number of incorrect RAS predictions. +system.cpu3.branchPred.BTBHitPct 75.575495 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 3099050 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 16324 # Number of incorrect RAS predictions. system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1557,88 +1555,86 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.walks 33037 # Table walker walks requested -system.cpu3.dtb.walker.walksShort 33037 # Table walker walks initiated with short descriptors -system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11464 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7705 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 13868 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 19169 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 496.400438 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 3535.731274 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-16383 19002 99.13% 99.13% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::16384-32767 134 0.70% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::32768-49151 21 0.11% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::49152-65535 6 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-81919 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::81920-98303 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::98304-114687 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::114688-131071 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::147456-163839 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 19169 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 6102 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 13023.926581 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 10629.521640 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 8508.049417 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-16383 4638 76.01% 76.01% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::16384-32767 1335 21.88% 97.89% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::32768-49151 115 1.88% 99.77% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::49152-65535 9 0.15% 99.92% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-81919 1 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::131072-147455 2 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walks 33115 # Table walker walks requested +system.cpu3.dtb.walker.walksShort 33115 # Table walker walks initiated with short descriptors +system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11558 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7619 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 13938 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 19177 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 468.973249 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 3138.682305 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-8191 18760 97.83% 97.83% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::8192-16383 261 1.36% 99.19% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::16384-24575 95 0.50% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::24576-32767 29 0.15% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::32768-40959 11 0.06% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::40960-49151 11 0.06% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::49152-57343 5 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-73727 4 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 19177 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 6222 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 13175.506268 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 10775.791198 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 8313.068780 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-16383 4548 73.10% 73.10% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::16384-32767 1554 24.98% 98.07% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::32768-49151 108 1.74% 99.81% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::49152-65535 9 0.14% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu3.dtb.walker.walkCompletionTime::147456-163839 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 6102 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -8042044064 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.800774 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::stdev 0.238438 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-1 -8088297564 100.58% 100.58% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::2-3 32871500 -0.41% 100.17% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-5 7478500 -0.09% 100.07% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::6-7 2286500 -0.03% 100.04% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-9 1244500 -0.02% 100.03% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::10-11 730000 -0.01% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-13 408500 -0.01% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::14-15 765000 -0.01% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-17 196000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::18-19 177000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-21 43000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::22-23 10500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-25 11000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::26-27 4500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walkCompletionTime::total 6222 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -8045387064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 1.137184 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-1 -8091405064 100.57% 100.57% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::2-3 33349500 -0.41% 100.16% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-5 6720000 -0.08% 100.07% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::6-7 2348000 -0.03% 100.04% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-9 1216500 -0.02% 100.03% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::10-11 680000 -0.01% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-13 415500 -0.01% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::14-15 841500 -0.01% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-17 133000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::18-19 159500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-21 77000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::22-23 11000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-25 34000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::26-27 10000 -0.00% 100.00% # Table walker pending requests distribution system.cpu3.dtb.walker.walksPending::28-29 3500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::30-31 23500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -8042044064 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 1824 68.91% 68.91% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::1M 823 31.09% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 2647 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 33037 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walksPending::30-31 19000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -8045387064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 1814 68.95% 68.95% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::1M 817 31.05% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 2631 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 33115 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 33037 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2647 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 33115 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2631 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2647 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 35684 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2631 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 35746 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 7253561 # DTB read hits -system.cpu3.dtb.read_misses 28594 # DTB read misses -system.cpu3.dtb.write_hits 5432397 # DTB write hits -system.cpu3.dtb.write_misses 4443 # DTB write misses -system.cpu3.dtb.flush_tlb 161 # Number of times complete TLB was flushed -system.cpu3.dtb.flush_tlb_mva 273 # Number of times TLB was flushed by MVA +system.cpu3.dtb.read_hits 7259419 # DTB read hits +system.cpu3.dtb.read_misses 28704 # DTB read misses +system.cpu3.dtb.write_hits 5430970 # DTB write hits +system.cpu3.dtb.write_misses 4411 # DTB write misses +system.cpu3.dtb.flush_tlb 162 # Number of times complete TLB was flushed +system.cpu3.dtb.flush_tlb_mva 274 # Number of times TLB was flushed by MVA system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 1945 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 458 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 789 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_entries 1937 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 485 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 827 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 336 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 7282155 # DTB read accesses -system.cpu3.dtb.write_accesses 5436840 # DTB write accesses +system.cpu3.dtb.perms_faults 313 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 7288123 # DTB read accesses +system.cpu3.dtb.write_accesses 5435381 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 12685958 # DTB hits -system.cpu3.dtb.misses 33037 # DTB misses -system.cpu3.dtb.accesses 12718995 # DTB accesses +system.cpu3.dtb.hits 12690389 # DTB hits +system.cpu3.dtb.misses 33115 # DTB misses +system.cpu3.dtb.accesses 12723504 # DTB accesses system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1668,389 +1664,386 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.walks 4585 # Table walker walks requested -system.cpu3.itb.walker.walksShort 4585 # Table walker walks initiated with short descriptors -system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1570 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2921 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 94 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 4491 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1433.533734 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 6108.583355 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-8191 4220 93.97% 93.97% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::8192-16383 132 2.94% 96.90% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::16384-24575 81 1.80% 98.71% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::24576-32767 32 0.71% 99.42% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-40959 7 0.16% 99.58% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::40960-49151 7 0.16% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::49152-57343 2 0.04% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::57344-65535 2 0.04% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-73727 2 0.04% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::73728-81919 2 0.04% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::81920-90111 1 0.02% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::90112-98303 2 0.04% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::98304-106495 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 4491 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 1402 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 13658.345221 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 11345.191727 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 7983.067706 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-4095 20 1.43% 1.43% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::4096-8191 403 28.74% 30.17% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::8192-12287 331 23.61% 53.78% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::12288-16383 266 18.97% 72.75% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::16384-20479 21 1.50% 74.25% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::20480-24575 301 21.47% 95.72% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::24576-28671 32 2.28% 98.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::28672-32767 5 0.36% 98.36% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::32768-36863 3 0.21% 98.57% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::36864-40959 5 0.36% 98.93% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::40960-45055 11 0.78% 99.71% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::45056-49151 2 0.14% 99.86% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::53248-57343 1 0.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::57344-61439 1 0.07% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 1402 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -8073456064 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.704569 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.455286 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -2382514092 29.51% 29.51% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -5692999972 70.52% 100.03% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 1707500 -0.02% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 179000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 115500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::5 56000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -8073456064 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 964 73.70% 73.70% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::1M 344 26.30% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 1308 # Table walker page sizes translated +system.cpu3.itb.walker.walks 4611 # Table walker walks requested +system.cpu3.itb.walker.walksShort 4611 # Table walker walks initiated with short descriptors +system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1576 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2936 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 99 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 4512 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1190.824468 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 4827.188758 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-8191 4272 94.68% 94.68% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::8192-16383 112 2.48% 97.16% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::16384-24575 85 1.88% 99.05% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::24576-32767 29 0.64% 99.69% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-40959 6 0.13% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::40960-49151 4 0.09% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::49152-57343 1 0.02% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::57344-65535 1 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-73727 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::73728-81919 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 4512 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 1416 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 13825.918079 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 11456.247028 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 8136.352957 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-4095 24 1.69% 1.69% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::4096-8191 390 27.54% 29.24% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::8192-12287 346 24.44% 53.67% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::12288-16383 256 18.08% 71.75% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::16384-20479 18 1.27% 73.02% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::20480-24575 314 22.18% 95.20% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::24576-28671 43 3.04% 98.23% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::28672-32767 4 0.28% 98.52% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-36863 3 0.21% 98.73% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::36864-40959 3 0.21% 98.94% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::40960-45055 8 0.56% 99.51% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::45056-49151 3 0.21% 99.72% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::53248-57343 1 0.07% 99.79% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::57344-61439 2 0.14% 99.93% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::61440-65535 1 0.07% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::total 1416 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -3903952768 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.701862 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.456296 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -1162140296 29.77% 29.77% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -2743359472 70.27% 100.04% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 1351500 -0.03% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 161000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 34500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -3903952768 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 967 73.42% 73.42% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::1M 350 26.58% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 1317 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4585 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4585 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4611 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4611 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1308 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1308 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 5893 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 9829313 # ITB inst hits -system.cpu3.itb.inst_misses 4585 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1317 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1317 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 5928 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 9805675 # ITB inst hits +system.cpu3.itb.inst_misses 4611 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.flush_tlb 161 # Number of times complete TLB was flushed -system.cpu3.itb.flush_tlb_mva 273 # Number of times TLB was flushed by MVA +system.cpu3.itb.flush_tlb 162 # Number of times complete TLB was flushed +system.cpu3.itb.flush_tlb_mva 274 # Number of times TLB was flushed by MVA system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 1305 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_entries 1315 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 736 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 717 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 9833898 # ITB inst accesses -system.cpu3.itb.hits 9829313 # DTB hits -system.cpu3.itb.misses 4585 # DTB misses -system.cpu3.itb.accesses 9833898 # DTB accesses -system.cpu3.numCycles 58255672 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 9810286 # ITB inst accesses +system.cpu3.itb.hits 9805675 # DTB hits +system.cpu3.itb.misses 4611 # DTB misses +system.cpu3.itb.accesses 9810286 # DTB accesses +system.cpu3.numCycles 58198080 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 20975785 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 52339111 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 13301320 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 9365882 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 34230578 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 1600984 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 75110 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 679 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 249 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 165248 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 76892 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 429 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 9828258 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 213311 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 2192 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 56325440 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.124081 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.271401 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 21004644 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 52275874 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 13279535 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 9346103 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 34135840 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 1598180 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 75752 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 771 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 231 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 170446 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 76408 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 496 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 9804624 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 214264 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 2206 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 56263657 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.123824 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.271758 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 42135738 74.81% 74.81% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 1842427 3.27% 78.08% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 1174880 2.09% 80.16% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3692209 6.56% 86.72% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 916764 1.63% 88.35% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 558692 0.99% 89.34% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2925255 5.19% 94.53% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 602319 1.07% 95.60% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 2477156 4.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 42100278 74.83% 74.83% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 1838046 3.27% 78.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 1170997 2.08% 80.17% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3679420 6.54% 86.71% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 917674 1.63% 88.35% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 559385 0.99% 89.34% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 2919080 5.19% 94.53% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 600185 1.07% 95.59% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2478592 4.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 56325440 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.228327 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.898438 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 14665639 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 32213939 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 7840695 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 894660 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 710284 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 980840 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 91372 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 45017968 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 299154 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 710284 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 15152191 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 3825257 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 22150592 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 8241060 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 6245828 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 43133854 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 881 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 923199 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 93585 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 4851932 # Number of times rename has blocked due to SQ full -system.cpu3.rename.RenamedOperands 44760576 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 198184537 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 48159961 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 3993 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 37280661 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 7479915 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 724518 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 673070 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 5055817 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 7747142 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 6009339 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 1097938 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 1536830 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 41471519 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 515844 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 39457989 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 52603 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 6038881 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 13851448 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 54585 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 56325440 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.700536 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.407802 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 56263657 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.228178 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.898241 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 14695652 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 32129586 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 7839305 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 889993 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 708923 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 981902 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 91350 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 45004399 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 298008 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 708923 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 15180574 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 3814501 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 22072917 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 8236779 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 6249745 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 43123968 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 829 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 908553 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 90362 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 4872933 # Number of times rename has blocked due to SQ full +system.cpu3.rename.RenamedOperands 44747932 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 198117330 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 48138419 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 3926 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 37260005 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 7487927 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 723224 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 671648 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 5026285 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 7752515 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 6007333 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 1093193 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 1517567 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 41462674 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 517140 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 39449683 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 52518 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 6046914 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 13857480 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 54926 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 56263657 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.701157 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.409344 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 40673603 72.21% 72.21% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 5189038 9.21% 81.42% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 3994905 7.09% 88.52% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 3229029 5.73% 94.25% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 1266179 2.25% 96.50% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 777932 1.38% 97.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 838695 1.49% 99.37% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 242964 0.43% 99.80% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 113095 0.20% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 40631196 72.22% 72.22% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 5180458 9.21% 81.42% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 3984831 7.08% 88.51% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 3217649 5.72% 94.22% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 1270759 2.26% 96.48% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 778914 1.38% 97.87% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 843481 1.50% 99.37% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 242828 0.43% 99.80% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 113541 0.20% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 56325440 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 56263657 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 56406 9.38% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 283401 47.13% 56.51% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 261530 43.49% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 56843 9.40% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 285724 47.25% 56.65% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 262185 43.35% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 83 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 26250639 66.53% 66.53% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 29940 0.08% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 2415 0.01% 66.61% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.61% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 66.61% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.61% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 7470638 18.93% 85.54% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 5704269 14.46% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 84 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 26236947 66.51% 66.51% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 29772 0.08% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 2427 0.01% 66.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 66.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.59% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 7477838 18.96% 85.54% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 5702609 14.46% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 39457989 # Type of FU issued -system.cpu3.iq.rate 0.677324 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 601337 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.015240 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 135886575 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 48050717 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 38292520 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 8783 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 4710 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 3829 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 40054524 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 4719 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 171660 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 39449683 # Type of FU issued +system.cpu3.iq.rate 0.677852 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 604752 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.015330 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 135811723 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 48051371 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 38283859 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 8570 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 4586 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 3750 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 40049753 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 4598 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 172364 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1179297 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 1335 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 29850 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 609995 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 1182055 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 1378 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 29890 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 609761 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 109451 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 43922 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 109360 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 44921 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 710284 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 3184032 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 520990 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 42035728 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 77277 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 7747142 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 6009339 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 266862 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 22482 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 492410 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 29850 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 141082 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 125238 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 266320 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 39125976 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 7338106 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 299066 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 708923 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 3187363 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 509464 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 42027375 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 77349 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 7752515 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 6007333 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 267430 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 22605 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 480734 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 29890 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 141333 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 125701 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 267034 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 39117599 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 7344612 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 299061 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 48365 # number of nop insts executed -system.cpu3.iew.exec_refs 12982427 # number of memory reference insts executed -system.cpu3.iew.exec_branches 7264644 # Number of branches executed -system.cpu3.iew.exec_stores 5644321 # Number of stores executed -system.cpu3.iew.exec_rate 0.671625 # Inst execution rate -system.cpu3.iew.wb_sent 38838436 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 38296349 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 20014644 # num instructions producing a value -system.cpu3.iew.wb_consumers 34860024 # num instructions consuming a value -system.cpu3.iew.wb_rate 0.657384 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.574143 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 6055415 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 461259 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 221839 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 55029535 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.653724 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.548863 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 47561 # number of nop insts executed +system.cpu3.iew.exec_refs 12987668 # number of memory reference insts executed +system.cpu3.iew.exec_branches 7261479 # Number of branches executed +system.cpu3.iew.exec_stores 5643056 # Number of stores executed +system.cpu3.iew.exec_rate 0.672146 # Inst execution rate +system.cpu3.iew.wb_sent 38828070 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 38287609 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 20013510 # num instructions producing a value +system.cpu3.iew.wb_consumers 34846989 # num instructions consuming a value +system.cpu3.iew.wb_rate 0.657884 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.574325 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 6062120 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 462214 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 222319 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 54968801 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.654162 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.550259 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 41164710 74.80% 74.80% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 6174910 11.22% 86.03% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 3105944 5.64% 91.67% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 1319292 2.40% 94.07% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 711711 1.29% 95.36% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 496248 0.90% 96.26% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 960829 1.75% 98.01% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 230731 0.42% 98.43% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 865160 1.57% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 41122825 74.81% 74.81% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 6168562 11.22% 86.03% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 3091321 5.62% 91.66% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 1317611 2.40% 94.05% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 712190 1.30% 95.35% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 498110 0.91% 96.26% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 959967 1.75% 98.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 230353 0.42% 98.42% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 867862 1.58% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 55029535 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 29416260 # Number of instructions committed -system.cpu3.commit.committedOps 35974129 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 54968801 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 29404628 # Number of instructions committed +system.cpu3.commit.committedOps 35958516 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 11967189 # Number of memory references committed -system.cpu3.commit.loads 6567845 # Number of loads committed -system.cpu3.commit.membars 179077 # Number of memory barriers committed -system.cpu3.commit.branches 6853829 # Number of branches committed -system.cpu3.commit.fp_insts 3808 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 31432423 # Number of committed integer instructions. -system.cpu3.commit.function_calls 1245286 # Number of function calls committed. +system.cpu3.commit.refs 11968032 # Number of memory references committed +system.cpu3.commit.loads 6570460 # Number of loads committed +system.cpu3.commit.membars 179741 # Number of memory barriers committed +system.cpu3.commit.branches 6849330 # Number of branches committed +system.cpu3.commit.fp_insts 3728 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 31415410 # Number of committed integer instructions. +system.cpu3.commit.function_calls 1242435 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 23975618 66.65% 66.65% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 28907 0.08% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 2415 0.01% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 6567845 18.26% 84.99% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 5399344 15.01% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 23959277 66.63% 66.63% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 28780 0.08% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 2427 0.01% 66.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.72% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 6570460 18.27% 84.99% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 5397572 15.01% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 35974129 # Class of committed instruction -system.cpu3.commit.bw_lim_events 865160 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 90545687 # The number of ROB reads -system.cpu3.rob.rob_writes 85357421 # The number of ROB writes -system.cpu3.timesIdled 228818 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1930232 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 5160394940 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 29390613 # Number of Instructions Simulated -system.cpu3.committedOps 35948482 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.982118 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.982118 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.504511 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.504511 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 42625892 # number of integer regfile reads -system.cpu3.int_regfile_writes 24241203 # number of integer regfile writes -system.cpu3.fp_regfile_reads 14445 # number of floating regfile reads -system.cpu3.fp_regfile_writes 12329 # number of floating regfile writes -system.cpu3.cc_regfile_reads 138329125 # number of cc regfile reads -system.cpu3.cc_regfile_writes 14829178 # number of cc regfile writes -system.cpu3.misc_regfile_reads 76422783 # number of misc regfile reads -system.cpu3.misc_regfile_writes 345191 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 30181 # Transaction distribution -system.iobus.trans_dist::ReadResp 30181 # Transaction distribution +system.cpu3.commit.op_class_0::total 35958516 # Class of committed instruction +system.cpu3.commit.bw_lim_events 867862 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 90498066 # The number of ROB reads +system.cpu3.rob.rob_writes 85338530 # The number of ROB writes +system.cpu3.timesIdled 230176 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1934423 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 5160447116 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 29379012 # Number of Instructions Simulated +system.cpu3.committedOps 35932900 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.980941 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.980941 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.504811 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.504811 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 42612953 # number of integer regfile reads +system.cpu3.int_regfile_writes 24236017 # number of integer regfile writes +system.cpu3.fp_regfile_reads 14441 # number of floating regfile reads +system.cpu3.fp_regfile_writes 12266 # number of floating regfile writes +system.cpu3.cc_regfile_reads 138314528 # number of cc regfile reads +system.cpu3.cc_regfile_writes 14822107 # number of cc regfile writes +system.cpu3.misc_regfile_reads 76357386 # number of misc regfile reads +system.cpu3.misc_regfile_writes 345684 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 30184 # Transaction distribution +system.iobus.trans_dist::ReadResp 30184 # Transaction distribution system.iobus.trans_dist::WriteReq 59010 # Transaction distribution system.iobus.trans_dist::WriteResp 59010 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54148 # Packet count per connected master and slave (bytes) @@ -2073,9 +2066,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105436 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178388 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67865 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) @@ -2096,20 +2089,20 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159093 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480317 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 27670500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480341 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 27687500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 101500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 205000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 207000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 12500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 40500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) @@ -2117,482 +2110,480 @@ system.iobus.reqLayer19.occupancy 3000 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 3858000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 3849500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 22212000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 22107000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 78391042 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 78684521 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 48071000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 47950000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 15512000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 15518000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36409 # number of replacements -system.iocache.tags.tagsinuse 1.005312 # Cycle average of tags in use -system.iocache.tags.total_refs 30 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 249222416009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.005312 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062832 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062832 # Average percentage of cache occupancy +system.iocache.tags.replacements 36442 # number of replacements +system.iocache.tags.tagsinuse 1.005646 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 249220700509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.005646 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062853 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062853 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328227 # Number of tag accesses -system.iocache.tags.data_accesses 328227 # Number of data accesses -system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits -system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits -system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses -system.iocache.ReadReq_misses::total 249 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36195 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36195 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses -system.iocache.demand_misses::total 249 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 249 # number of overall misses -system.iocache.overall_misses::total 249 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 17512919 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 17512919 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 1978574123 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 1978574123 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 17512919 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 17512919 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 17512919 # number of overall miss cycles -system.iocache.overall_miss_latency::total 17512919 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) +system.iocache.tags.tag_accesses 328284 # Number of tag accesses +system.iocache.tags.data_accesses 328284 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses +system.iocache.ReadReq_misses::total 252 # number of ReadReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses +system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses +system.iocache.demand_misses::total 252 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 252 # number of overall misses +system.iocache.overall_misses::total 252 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 18163419 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 18163419 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 1911698102 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 1911698102 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 18163419 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 18163419 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 18163419 # number of overall miss cycles +system.iocache.overall_miss_latency::total 18163419 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 0.999199 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 0.999199 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 70333.008032 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 70333.008032 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 54664.294046 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 54664.294046 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 70333.008032 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 70333.008032 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 70333.008032 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 70333.008032 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 378 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 72077.059524 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 72077.059524 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 52774.351314 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 52774.351314 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 72077.059524 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 72077.059524 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 72077.059524 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 72077.059524 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 46 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.217391 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36160 # number of writebacks -system.iocache.writebacks::total 36160 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 148 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 148 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 15187 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 15187 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 148 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 148 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 10112919 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 10112919 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 1219224123 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1219224123 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 10112919 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10112919 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 10112919 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10112919 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.594378 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.419252 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.419252 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.594378 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.594378 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68330.533784 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68330.533784 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80280.774544 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80280.774544 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68330.533784 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68330.533784 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68330.533784 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68330.533784 # average overall mshr miss latency +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 151 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 15216 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 15216 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 151 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 151 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 151 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 151 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 10613419 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 10613419 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 1150219969 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1150219969 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 10613419 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10613419 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 10613419 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10613419 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.599206 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.599206 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.420053 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.420053 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.599206 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.599206 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.599206 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.599206 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70287.543046 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70287.543046 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75592.795018 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75592.795018 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70287.543046 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70287.543046 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70287.543046 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70287.543046 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104195 # number of replacements -system.l2c.tags.tagsinuse 65091.017513 # Cycle average of tags in use -system.l2c.tags.total_refs 5155167 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169447 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 30.423478 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 80140567000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48843.546061 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.971843 # Average occupied blocks per requestor +system.l2c.tags.replacements 104080 # number of replacements +system.l2c.tags.tagsinuse 65088.554606 # Cycle average of tags in use +system.l2c.tags.total_refs 5171027 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169261 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 30.550611 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 80144379500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 48906.749682 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.971842 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4254.039308 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2206.437116 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 715.458752 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 853.835982 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 22.288260 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2257.166509 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 817.070736 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 50.645979 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 3368.546938 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 1701.009935 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.745293 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4329.107732 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2210.968865 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 681.890061 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 812.278170 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 23.892428 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2284.499706 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 774.800315 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 49.745028 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 3338.045671 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 1675.605011 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.746258 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.064911 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.033668 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.010917 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000340 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034442 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.012468 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000773 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.051400 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.025955 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993210 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 64 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65188 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 64 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2135 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7652 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55293 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000977 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994690 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45555294 # Number of tag accesses -system.l2c.tags.data_accesses 45555294 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4129 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2050 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 1745 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 884 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 13470 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 1127 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 20610 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 4601 # number of ReadReq hits -system.l2c.ReadReq_hits::total 48616 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 692230 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 692230 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1942576 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1942576 # number of WritebackClean hits +system.l2c.tags.occ_percent::cpu0.inst 0.066057 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.033737 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.010405 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.012394 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000365 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.034859 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.011823 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000759 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.050935 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.025568 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993173 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 57 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65124 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 57 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2187 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7581 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55275 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000870 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.993713 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 45699914 # Number of tag accesses +system.l2c.tags.data_accesses 45699914 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4201 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 12425172006 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 562695000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1022622000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 1727239500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3312556500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 462306000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 787872000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data 1353651000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2603829000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1025001000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 1810494000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3.data 3080890500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5916385500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.002199 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003277 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.001980 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.997199 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.978003 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.945479 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.584162 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.379310 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.379310 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.404487 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.465969 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.493615 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.271232 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007683 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.010395 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.011721 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006704 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.033052 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.018935 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.029492 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.016267 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007683 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.139942 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002199 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010395 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.168932 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003277 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.011721 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.205063 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.035725 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007683 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.139942 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002199 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010395 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.168932 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003277 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.011721 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.205063 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.035725 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 123921.875000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 122919.117647 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 123240 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68022.471910 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68010.380623 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 68000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68008.510638 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 68545.454545 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68545.454545 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 118884.892961 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 117488.101512 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 122473.807083 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 120395.867514 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121451.735016 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 122360.696517 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 123289.647699 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122706.961443 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 120180.834002 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 123385.642317 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 127037.237002 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 124254.257858 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121451.735016 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 119102.893565 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 123921.875000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 122360.696517 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 117927.341288 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 122919.117647 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 123289.647699 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 122881.844896 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 121027.546228 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121451.735016 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 119102.893565 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 123921.875000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 122360.696517 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 117927.341288 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 122919.117647 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 123289.647699 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 122881.844896 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 121027.546228 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163716.904277 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 186066.593886 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 203635.875973 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 190212.833764 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165879.440258 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 185338.038109 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 201856.695497 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189452.051804 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 164685.250643 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 185748.845799 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 202850.309455 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 189877.258577 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40114 # Transaction distribution -system.membus.trans_dist::ReadResp 76341 # Transaction distribution +system.membus.trans_dist::ReadResp 76472 # Transaction distribution system.membus.trans_dist::WriteReq 27565 # Transaction distribution system.membus.trans_dist::WriteResp 27565 # Transaction distribution -system.membus.trans_dist::WritebackDirty 131541 # Transaction distribution -system.membus.trans_dist::CleanEvict 8827 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4550 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 10 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4560 # Transaction distribution -system.membus.trans_dist::ReadExReq 138388 # Transaction distribution -system.membus.trans_dist::ReadExResp 138388 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 36227 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36194 # Transaction distribution +system.membus.trans_dist::WritebackDirty 131266 # Transaction distribution +system.membus.trans_dist::CleanEvict 9256 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4564 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1783 # Transaction distribution +system.membus.trans_dist::ReadExReq 138006 # Transaction distribution +system.membus.trans_dist::ReadExResp 138006 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 36358 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 21008 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 489795 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 597247 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108913 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108913 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 706160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 486411 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 593863 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94027 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 94027 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 687890 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17309820 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17472945 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2320704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2320704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19793649 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 304 # Total snoops (count) -system.membus.snoop_fanout::samples 423653 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17273980 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17437105 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2322624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2322624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19759729 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 308 # Total snoops (count) +system.membus.snoop_fanout::samples 423370 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 423653 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 423370 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 423653 # Request fanout histogram -system.membus.reqLayer0.occupancy 54148500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 423370 # Request fanout histogram +system.membus.reqLayer0.occupancy 54054500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 680000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 683000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 485362066 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 487802765 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 587517958 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 583127250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 27144297 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 785081 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2905,60 +2896,60 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5660019 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2844678 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 45590 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 617 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 617 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5675245 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2851889 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 45299 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 358 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 358 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 111923 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2630935 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 112467 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2639200 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 761630 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1942576 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 139089 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2842 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 761596 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1988229 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 147548 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2816 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2870 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296497 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296497 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1981401 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 537613 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 15186 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5923303 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2617283 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26505 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 100543 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8667634 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 251163000 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97868601 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 43100 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 177856 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 349252557 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 193970 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4194071 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021768 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.145924 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 2845 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296735 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296735 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1988790 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 538004 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 15216 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5983726 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2626321 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26876 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 102356 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8739279 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 254557176 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97876281 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 44416 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 183100 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 352660973 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 192738 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4203717 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021388 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.144675 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4102776 97.82% 97.82% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 91295 2.18% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4113806 97.86% 97.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 89911 2.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4194071 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3475552499 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4203717 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3488536999 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 260919 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 176919 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1890152632 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1898856602 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 768668207 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 770188700 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11579475 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11632976 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 47680705 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 48177210 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed |