diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt | 3156 |
1 files changed, 1716 insertions, 1440 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 053f94faa..0523405d3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,153 +1,153 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.818075 # Number of seconds simulated -sim_ticks 2818074786500 # Number of ticks simulated -final_tick 2818074786500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.818071 # Number of seconds simulated +sim_ticks 2818071194500 # Number of ticks simulated +final_tick 2818071194500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 252135 # Simulator instruction rate (inst/s) -host_op_rate 306151 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5631568448 # Simulator tick rate (ticks/s) -host_mem_usage 564964 # Number of bytes of host memory used -host_seconds 500.41 # Real time elapsed on the host -sim_insts 126169808 # Number of instructions simulated -sim_ops 153199842 # Number of ops (including micro ops) simulated +host_inst_rate 294940 # Simulator instruction rate (inst/s) +host_op_rate 358127 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6587540433 # Simulator tick rate (ticks/s) +host_mem_usage 622484 # Number of bytes of host memory used +host_seconds 427.79 # Real time elapsed on the host +sim_insts 126171688 # Number of instructions simulated +sim_ops 153202470 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 666212 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4384416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 666276 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4385696 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 128384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1037892 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 127360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1038980 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.dtb.walker 6016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 504320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 4231744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 505600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 4227776 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10960328 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 666212 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 128384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 504320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1298916 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8261760 # Number of bytes written to this memory +system.physmem.bytes_read::total 10959048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 666276 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 127360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 505600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1299236 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8262336 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8279284 # Number of bytes written to this memory +system.physmem.bytes_written::total 8279860 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 18863 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 69025 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 18864 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 69045 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2006 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16218 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1990 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16235 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.dtb.walker 94 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 7880 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 66121 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 7900 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 66059 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180228 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 129090 # Number of write requests responded to by this memory +system.physmem.num_reads::total 180208 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 129099 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 133471 # Number of write requests responded to by this memory +system.physmem.num_writes::total 133480 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 236407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1555820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 236430 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1556276 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 45557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 368298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 45194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 368685 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.dtb.walker 2135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 178959 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1501644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 179413 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1500237 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3889296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 236407 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 45557 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 178959 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 460923 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2931704 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3888847 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 236430 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 45194 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 179413 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 461037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2931912 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2937922 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2931704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2938130 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2931912 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 236407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1562035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 236430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1562491 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 45557 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 368301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 45194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 368688 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.dtb.walker 2135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 178959 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1501644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 179413 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1500237 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6827218 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 92321 # Number of read requests accepted -system.physmem.writeReqs 90302 # Number of write requests accepted -system.physmem.readBursts 92321 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 90302 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5904000 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4544 # Total number of bytes read from write queue -system.physmem.bytesWritten 5704128 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5908484 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5779208 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 71 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1152 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2483 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6041 # Per bank write bursts -system.physmem.perBankRdBursts::1 5798 # Per bank write bursts -system.physmem.perBankRdBursts::2 5558 # Per bank write bursts -system.physmem.perBankRdBursts::3 6021 # Per bank write bursts -system.physmem.perBankRdBursts::4 5562 # Per bank write bursts -system.physmem.perBankRdBursts::5 5457 # Per bank write bursts -system.physmem.perBankRdBursts::6 6123 # Per bank write bursts -system.physmem.perBankRdBursts::7 6801 # Per bank write bursts -system.physmem.perBankRdBursts::8 6403 # Per bank write bursts -system.physmem.perBankRdBursts::9 6349 # Per bank write bursts -system.physmem.perBankRdBursts::10 5693 # Per bank write bursts -system.physmem.perBankRdBursts::11 5092 # Per bank write bursts -system.physmem.perBankRdBursts::12 5281 # Per bank write bursts -system.physmem.perBankRdBursts::13 5450 # Per bank write bursts -system.physmem.perBankRdBursts::14 5307 # Per bank write bursts -system.physmem.perBankRdBursts::15 5314 # Per bank write bursts -system.physmem.perBankWrBursts::0 5390 # Per bank write bursts -system.physmem.perBankWrBursts::1 4962 # Per bank write bursts -system.physmem.perBankWrBursts::2 5472 # Per bank write bursts -system.physmem.perBankWrBursts::3 5886 # Per bank write bursts -system.physmem.perBankWrBursts::4 5376 # Per bank write bursts -system.physmem.perBankWrBursts::5 5734 # Per bank write bursts -system.physmem.perBankWrBursts::6 5792 # Per bank write bursts -system.physmem.perBankWrBursts::7 6324 # Per bank write bursts -system.physmem.perBankWrBursts::8 6132 # Per bank write bursts -system.physmem.perBankWrBursts::9 6057 # Per bank write bursts -system.physmem.perBankWrBursts::10 5626 # Per bank write bursts -system.physmem.perBankWrBursts::11 4872 # Per bank write bursts -system.physmem.perBankWrBursts::12 5573 # Per bank write bursts -system.physmem.perBankWrBursts::13 5712 # Per bank write bursts -system.physmem.perBankWrBursts::14 5197 # Per bank write bursts -system.physmem.perBankWrBursts::15 5022 # Per bank write bursts +system.physmem.bw_total::total 6826977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 92280 # Number of read requests accepted +system.physmem.writeReqs 90311 # Number of write requests accepted +system.physmem.readBursts 92280 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 90311 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5901184 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4736 # Total number of bytes read from write queue +system.physmem.bytesWritten 5694528 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5905860 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5779784 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 74 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 1313 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2491 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6033 # Per bank write bursts +system.physmem.perBankRdBursts::1 5793 # Per bank write bursts +system.physmem.perBankRdBursts::2 5545 # Per bank write bursts +system.physmem.perBankRdBursts::3 6032 # Per bank write bursts +system.physmem.perBankRdBursts::4 5564 # Per bank write bursts +system.physmem.perBankRdBursts::5 5452 # Per bank write bursts +system.physmem.perBankRdBursts::6 6124 # Per bank write bursts +system.physmem.perBankRdBursts::7 6804 # Per bank write bursts +system.physmem.perBankRdBursts::8 6414 # Per bank write bursts +system.physmem.perBankRdBursts::9 6339 # Per bank write bursts +system.physmem.perBankRdBursts::10 5684 # Per bank write bursts +system.physmem.perBankRdBursts::11 5101 # Per bank write bursts +system.physmem.perBankRdBursts::12 5267 # Per bank write bursts +system.physmem.perBankRdBursts::13 5451 # Per bank write bursts +system.physmem.perBankRdBursts::14 5288 # Per bank write bursts +system.physmem.perBankRdBursts::15 5315 # Per bank write bursts +system.physmem.perBankWrBursts::0 5413 # Per bank write bursts +system.physmem.perBankWrBursts::1 4989 # Per bank write bursts +system.physmem.perBankWrBursts::2 5365 # Per bank write bursts +system.physmem.perBankWrBursts::3 5927 # Per bank write bursts +system.physmem.perBankWrBursts::4 5380 # Per bank write bursts +system.physmem.perBankWrBursts::5 5714 # Per bank write bursts +system.physmem.perBankWrBursts::6 5766 # Per bank write bursts +system.physmem.perBankWrBursts::7 6373 # Per bank write bursts +system.physmem.perBankWrBursts::8 6011 # Per bank write bursts +system.physmem.perBankWrBursts::9 5951 # Per bank write bursts +system.physmem.perBankWrBursts::10 5678 # Per bank write bursts +system.physmem.perBankWrBursts::11 4910 # Per bank write bursts +system.physmem.perBankWrBursts::12 5493 # Per bank write bursts +system.physmem.perBankWrBursts::13 5839 # Per bank write bursts +system.physmem.perBankWrBursts::14 5189 # Per bank write bursts +system.physmem.perBankWrBursts::15 4979 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2816508644000 # Total gap between requests +system.physmem.totGap 2816505052000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 1 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 92320 # Read request sizes (log2) +system.physmem.readPktSize::6 92279 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 90300 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 60706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 28069 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 90309 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 60465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 28317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2940 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 476 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -178,149 +178,149 @@ system.physmem.rdQLenPdf::31 0 # Wh system.physmem.wrQLenPdf::0 57 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 54 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 49 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 48 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 33954 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 341.872416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 193.139988 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 360.706061 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12607 37.13% 37.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7646 22.52% 59.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 2942 8.66% 68.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1742 5.13% 73.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1359 4.00% 77.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 780 2.30% 79.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 533 1.57% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 565 1.66% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5780 17.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 33954 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3432 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.875583 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 525.946384 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 3431 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 33947 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 341.579050 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 192.896082 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 361.051588 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12589 37.08% 37.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 7648 22.53% 59.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3047 8.98% 68.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1722 5.07% 73.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1227 3.61% 77.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 803 2.37% 79.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 549 1.62% 81.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 558 1.64% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5804 17.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 33947 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3440 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.800581 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 525.347088 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 3439 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3432 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3432 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.969406 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.900383 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 25.459060 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 4 0.12% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 2 0.06% 0.17% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 3440 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3440 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 25.865407 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.895854 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 25.306431 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 5 0.15% 0.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 1 0.03% 0.17% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::8-11 3 0.09% 0.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 2 0.06% 0.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 2696 78.55% 78.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 29 0.84% 79.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 30 0.87% 80.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 138 4.02% 84.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 83 2.42% 87.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 30 0.87% 87.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 20 0.58% 88.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 23 0.67% 89.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 73 2.13% 91.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.20% 91.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.15% 91.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.23% 91.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 20 0.58% 92.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 8 0.23% 92.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.23% 92.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 21 0.61% 93.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 41 1.19% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 8 0.23% 94.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.09% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 9 0.26% 95.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 65 1.89% 97.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.12% 97.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 7 0.20% 97.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 5 0.15% 97.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 7 0.20% 97.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.09% 97.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 8 0.23% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.09% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 4 0.12% 0.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 2693 78.28% 78.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 34 0.99% 79.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 21 0.61% 80.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 172 5.00% 85.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 62 1.80% 87.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 30 0.87% 87.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 17 0.49% 88.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 16 0.47% 88.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 84 2.44% 91.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 11 0.32% 91.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 14 0.41% 92.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 10 0.29% 92.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 20 0.58% 92.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.17% 93.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.17% 93.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 25 0.73% 94.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 46 1.34% 95.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.12% 95.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 4 0.12% 95.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 9 0.26% 95.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 47 1.37% 97.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.09% 97.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 6 0.17% 97.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.06% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 16 0.47% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.03% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 7 0.20% 98.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.06% 98.28% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 22 0.64% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 7 0.20% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.06% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.06% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.06% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.09% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.03% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.09% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 5 0.15% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.09% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.06% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 6 0.17% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 3 0.09% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.09% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.03% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.09% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.12% 99.65% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::168-171 1 0.03% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.09% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.06% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.03% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.03% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.06% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.03% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 3 0.09% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.03% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-227 1 0.03% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::228-231 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3432 # Writes before turning the bus around for reads -system.physmem.totQLat 1184332750 # Total ticks spent queuing -system.physmem.totMemAccLat 2914020250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 461250000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12838.30 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::248-251 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3440 # Writes before turning the bus around for reads +system.physmem.totQLat 1163516500 # Total ticks spent queuing +system.physmem.totMemAccLat 2892379000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 461030000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12618.66 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31588.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.10 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31368.66 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.09 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.02 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.10 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.05 # Average system write bandwidth in MiByte/s @@ -329,36 +329,41 @@ system.physmem.busUtil 0.03 # Da system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.03 # Average write queue length when enqueuing -system.physmem.readRowHits 76434 # Number of row buffer hits during reads -system.physmem.writeRowHits 70988 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.86 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.63 # Row buffer hit rate for writes -system.physmem.avgGap 15422529.71 # Average gap between requests -system.physmem.pageHitRate 81.27 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2704815148250 # Time in different power states -system.physmem.memoryStateTime::REF 94101540000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 19154581250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 134477280 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 122214960 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 73375500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 66684750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 369415800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 350110800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 291185280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 286357680 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 184062612240 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 184062612240 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 70840900170 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 70013903985 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1628700821250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1629426256500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1884472787520 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1884328140915 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.710440 # Core power per rank (mW) -system.physmem.averagePower::1 668.659112 # Core power per rank (mW) +system.physmem.avgWrQLen 6.25 # Average write queue length when enqueuing +system.physmem.readRowHits 76428 # Number of row buffer hits during reads +system.physmem.writeRowHits 70807 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.56 # Row buffer hit rate for writes +system.physmem.avgGap 15425212.92 # Average gap between requests +system.physmem.pageHitRate 81.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 134288280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 73012500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 369306600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 291126960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 178872248880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 68915344410 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1612195386000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1860850713630 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.510917 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2632883157750 # Time in different power states +system.physmem_0.memoryStateTime::REF 91447980000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14405588500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 122351040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 66577500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 349884600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 285444000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 178872248880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 68134185630 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1610493455250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1858324146900 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.557325 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2634053636000 # Time in different power states +system.physmem_1.memoryStateTime::REF 91447980000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 13230281250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -378,6 +383,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -399,27 +412,56 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 5757 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5757 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5757 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5757 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5757 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 166121609118 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.475514 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.499400 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 87128456868 52.45% 52.45% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 78993152250 47.55% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 166121609118 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3229 67.67% 67.67% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1543 32.33% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4772 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5757 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5757 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4772 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4772 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 10529 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 14476474 # DTB read hits -system.cpu0.dtb.read_misses 4869 # DTB read misses -system.cpu0.dtb.write_hits 11056177 # DTB write hits -system.cpu0.dtb.write_misses 893 # DTB write misses +system.cpu0.dtb.read_hits 14474153 # DTB read hits +system.cpu0.dtb.read_misses 4865 # DTB read misses +system.cpu0.dtb.write_hits 11054581 # DTB write hits +system.cpu0.dtb.write_misses 892 # DTB write misses system.cpu0.dtb.flush_tlb 188 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 401 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3212 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3207 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 944 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 943 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 196 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14481343 # DTB read accesses -system.cpu0.dtb.write_accesses 11057070 # DTB write accesses +system.cpu0.dtb.perms_faults 195 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14479018 # DTB read accesses +system.cpu0.dtb.write_accesses 11055473 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 25532651 # DTB hits -system.cpu0.dtb.misses 5762 # DTB misses -system.cpu0.dtb.accesses 25538413 # DTB accesses +system.cpu0.dtb.hits 25528734 # DTB hits +system.cpu0.dtb.misses 5757 # DTB misses +system.cpu0.dtb.accesses 25534491 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -441,8 +483,29 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 67995752 # ITB inst hits -system.cpu0.itb.inst_misses 2758 # ITB inst misses +system.cpu0.itb.walker.walks 2755 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2755 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2755 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2755 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2755 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 166121609118 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.475515 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.499400 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 87128348368 52.45% 52.45% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 78993260750 47.55% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 166121609118 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1528 75.53% 75.53% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 495 24.47% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2023 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2755 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2755 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2023 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2023 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4778 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 67991390 # ITB inst hits +system.cpu0.itb.inst_misses 2755 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -451,45 +514,45 @@ system.cpu0.itb.flush_tlb 188 # Nu system.cpu0.itb.flush_tlb_mva 401 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1969 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1966 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 67998510 # ITB inst accesses -system.cpu0.itb.hits 67995752 # DTB hits -system.cpu0.itb.misses 2758 # DTB misses -system.cpu0.itb.accesses 67998510 # DTB accesses -system.cpu0.numCycles 82558276 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 67994145 # ITB inst accesses +system.cpu0.itb.hits 67991390 # DTB hits +system.cpu0.itb.misses 2755 # DTB misses +system.cpu0.itb.accesses 67994145 # DTB accesses +system.cpu0.numCycles 82552372 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 66186941 # Number of instructions committed -system.cpu0.committedOps 80639436 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 70858992 # Number of integer alu accesses +system.cpu0.committedInsts 66182532 # Number of instructions committed +system.cpu0.committedOps 80633643 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 70853114 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5470 # Number of float alu accesses -system.cpu0.num_func_calls 7266542 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 8791397 # number of instructions that are conditional controls -system.cpu0.num_int_insts 70858992 # number of integer instructions +system.cpu0.num_func_calls 7266071 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 8791663 # number of instructions that are conditional controls +system.cpu0.num_int_insts 70853114 # number of integer instructions system.cpu0.num_fp_insts 5470 # number of float instructions -system.cpu0.num_int_register_reads 131380013 # number of times the integer registers were read -system.cpu0.num_int_register_writes 49295072 # number of times the integer registers were written +system.cpu0.num_int_register_reads 131368884 # number of times the integer registers were read +system.cpu0.num_int_register_writes 49289864 # number of times the integer registers were written system.cpu0.num_fp_register_reads 4246 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1228 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 245776790 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 29457750 # number of times the CC registers were written -system.cpu0.num_mem_refs 26204570 # number of memory refs -system.cpu0.num_load_insts 14653679 # Number of load instructions -system.cpu0.num_store_insts 11550891 # Number of store instructions -system.cpu0.num_idle_cycles 77949108.406676 # Number of idle cycles -system.cpu0.num_busy_cycles 4609167.593324 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055829 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944171 # Percentage of idle cycles -system.cpu0.Branches 16455876 # Number of branches fetched +system.cpu0.num_cc_register_reads 245759484 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 29458192 # number of times the CC registers were written +system.cpu0.num_mem_refs 26200850 # number of memory refs +system.cpu0.num_load_insts 14651277 # Number of load instructions +system.cpu0.num_store_insts 11549573 # Number of store instructions +system.cpu0.num_idle_cycles 77943726.541103 # Number of idle cycles +system.cpu0.num_busy_cycles 4608645.458897 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055827 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944173 # Percentage of idle cycles +system.cpu0.Branches 16455843 # Number of branches fetched system.cpu0.op_class::No_OpClass 2193 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 55779692 67.98% 67.99% # Class of executed instruction -system.cpu0.op_class::IntMult 58849 0.07% 68.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 55777669 67.99% 67.99% # Class of executed instruction +system.cpu0.op_class::IntMult 58831 0.07% 68.06% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.06% # Class of executed instruction @@ -513,294 +576,294 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.06% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4532 0.01% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4520 0.01% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::MemRead 14653679 17.86% 85.92% # Class of executed instruction -system.cpu0.op_class::MemWrite 11550891 14.08% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 14651277 17.86% 85.92% # Class of executed instruction +system.cpu0.op_class::MemWrite 11549573 14.08% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 82049836 # Class of executed instruction +system.cpu0.op_class::total 82044063 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3055 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 833965 # number of replacements +system.cpu0.dcache.tags.replacements 833838 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.996800 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 46972085 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 834477 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 56.289251 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 46974042 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 834350 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 56.300164 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.818118 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.670897 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.507786 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.948864 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032560 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018570 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.894462 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.632625 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.469713 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.949013 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032486 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018496 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 198452344 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 198452344 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 13787811 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 4397354 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 8501200 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 26686365 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10663716 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3166111 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 5160414 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18990241 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190628 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 60624 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 130481 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 381733 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235896 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 80331 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 134984 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 451211 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 237277 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 82832 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 139583 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459692 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 24451527 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 7563465 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 13661614 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 45676606 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 24642155 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 7624089 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 13792095 # number of overall hits -system.cpu0.dcache.overall_hits::total 46058339 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 191712 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 58922 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 315531 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 566165 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 143864 # 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number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 77996260209 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 2224535661 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 75771724548 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 77996260209 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 13977240 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 4455482 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 8821599 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 27254321 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 10806053 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 3200906 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 6694330 # 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number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 82830 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 139666 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 459709 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 24787103 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 7657781 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 15508786 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 47953670 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 25031731 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 7739619 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 15704754 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 48476104 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013714 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013222 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.035788 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.020775 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013311 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.011055 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.228875 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.082648 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.220743 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.259219 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.334172 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.269318 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018556 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.039413 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.066907 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.037203 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 24783293 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 7656388 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 15515929 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 47955610 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 25027959 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 7738138 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 15711943 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 48478040 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013701 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013233 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.035704 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.020746 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013315 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.011060 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.228876 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.082674 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.220758 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.259046 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.334425 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.269397 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018545 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.039461 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.067072 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.037258 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000107 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000037 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013538 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.012316 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.119105 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.047485 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.015563 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.014927 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.121789 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.049875 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15267.056448 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16821.983748 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10963.981973 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37534.226479 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46119.783369 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42064.106374 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14131.143811 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13679.124496 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10265.356811 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13800.066667 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12176.529412 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23623.265533 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41115.179568 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34331.428710 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19285.483528 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 39707.448360 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32333.523062 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 374153 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 25938 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 24753 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 535 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.115461 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 48.482243 # average number of cycles each access was blocked +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000115 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000039 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013533 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.012325 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.119048 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.047479 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.015558 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.014931 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.121735 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.049871 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.767550 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16642.926742 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10860.397820 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37446.527441 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46032.518019 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 41985.058666 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14080.606061 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13612.771261 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10226.470413 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16219 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14416.888889 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23574.486138 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41021.105356 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34255.702183 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19253.547815 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 39615.225320 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32261.521207 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 372760 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 22765 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 24978 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 525 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.923533 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 43.361905 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 692650 # number of writebacks -system.cpu0.dcache.writebacks::total 692650 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 119 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 155404 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 155523 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 1411618 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1411618 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1952 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 6678 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 8630 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 119 # 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number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 323871 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 438898 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 779470500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2130747955 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2910218455 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1251702570 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5436442471 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6688145041 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 266097500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 651596008 # 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number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8218786434 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10516057004 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1018847500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1696409500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2715257000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 779636500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1318509000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2098145500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1798484000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3014918500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4813402500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013196 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018162 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008033 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011055 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017935 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007508 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.254527 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.223103 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2292777571 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8203563695 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10496341266 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1019447000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1696986500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2716433500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 779587000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1319132500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2098719500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1799034000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3016119000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4815153000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013205 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018152 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008034 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011060 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017927 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007507 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.254373 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.224004 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.123850 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.016095 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019843 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.008998 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000115 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000035 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012309 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.018055 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.007807 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014866 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020624 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.009057 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13221.802978 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13267.774790 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13255.421973 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35276.913567 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45203.707464 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42942.374463 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12789.180091 # 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miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.017984 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012762 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011387 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.056695 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.017984 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012762 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011387 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.056695 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.017984 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13540.851445 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13712.999658 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 7250.593777 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13540.851445 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13712.999658 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 7250.593777 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13540.851445 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13712.999658 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 7250.593777 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6029 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 344 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 382 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.915698 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.782723 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 50040 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 50040 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 50040 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 50040 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 50040 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 50040 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 248802 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 681413 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 930215 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 248802 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 681413 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 930215 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 248802 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 681413 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 930215 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2869743000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8188546795 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11058289795 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2869743000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8188546795 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11058289795 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2869743000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8188546795 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11058289795 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011375 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.052851 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 50013 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 50013 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 50013 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 50013 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 50013 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 50013 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 249012 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 681189 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 930201 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 249012 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 681189 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 930201 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 249012 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 681189 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 930201 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2873083500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8182514470 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11055597970 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2873083500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8182514470 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11055597970 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2873083500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8182514470 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11055597970 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011387 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.052817 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009052 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011375 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.052851 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011387 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.052817 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.009052 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011375 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.052851 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011387 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.052817 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.009052 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11534.244098 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12017.009941 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11887.885913 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11534.244098 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12017.009941 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11887.885913 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11534.244098 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12017.009941 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11887.885913 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11537.931907 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12012.105994 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11885.171022 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11537.931907 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12012.105994 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11885.171022 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11537.931907 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12012.105994 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11885.171022 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -969,27 +1040,64 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 1854 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 1854 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 620 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1234 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 1854 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 1854 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 1854 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1496 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9777.746658 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 7722.280706 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6250.292235 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 511 34.16% 34.16% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 754 50.40% 84.56% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 230 15.37% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::73728-81919 1 0.07% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1496 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1000015000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000015000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1000015000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 885 59.16% 59.16% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 611 40.84% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1496 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1854 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1854 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1496 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1496 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3350 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4627532 # DTB read hits -system.cpu1.dtb.read_misses 1596 # DTB read misses -system.cpu1.dtb.write_hits 3288935 # DTB write hits -system.cpu1.dtb.write_misses 256 # DTB write misses +system.cpu1.dtb.read_hits 4626652 # DTB read hits +system.cpu1.dtb.read_misses 1593 # DTB read misses +system.cpu1.dtb.write_hits 3288334 # DTB write hits +system.cpu1.dtb.write_misses 261 # DTB write misses system.cpu1.dtb.flush_tlb 166 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 148 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 147 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1270 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1268 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 238 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 69 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4629128 # DTB read accesses -system.cpu1.dtb.write_accesses 3289191 # DTB write accesses +system.cpu1.dtb.read_accesses 4628245 # DTB read accesses +system.cpu1.dtb.write_accesses 3288595 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7916467 # DTB hits -system.cpu1.dtb.misses 1852 # DTB misses -system.cpu1.dtb.accesses 7918319 # DTB accesses +system.cpu1.dtb.hits 7914986 # DTB hits +system.cpu1.dtb.misses 1854 # DTB misses +system.cpu1.dtb.accesses 7916840 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1011,55 +1119,86 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 21872882 # ITB inst hits -system.cpu1.itb.inst_misses 825 # ITB inst misses +system.cpu1.itb.walker.walks 832 # Table walker walks requested +system.cpu1.itb.walker.walksShort 832 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 221 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 611 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 832 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 832 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 832 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 612 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 10456.699346 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8281.924765 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6395.528631 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::2048-4095 192 31.37% 31.37% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 1 0.16% 31.54% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 290 47.39% 78.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 12 1.96% 80.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-22527 105 17.16% 98.04% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 12 1.96% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 612 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 391 63.89% 63.89% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 221 36.11% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 612 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 832 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 832 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 612 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 612 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1444 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 21867839 # ITB inst hits +system.cpu1.itb.inst_misses 832 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 166 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 148 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 147 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 668 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 672 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 21873707 # ITB inst accesses -system.cpu1.itb.hits 21872882 # DTB hits -system.cpu1.itb.misses 825 # DTB misses -system.cpu1.itb.accesses 21873707 # DTB accesses -system.cpu1.numCycles 158012156 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 21868671 # ITB inst accesses +system.cpu1.itb.hits 21867839 # DTB hits +system.cpu1.itb.misses 832 # DTB misses +system.cpu1.itb.accesses 21868671 # DTB accesses +system.cpu1.numCycles 158011786 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 21172070 # Number of instructions committed -system.cpu1.committedOps 25390672 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22586857 # Number of integer alu accesses +system.cpu1.committedInsts 21167008 # Number of instructions committed +system.cpu1.committedOps 25384727 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22581810 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1738 # Number of float alu accesses -system.cpu1.num_func_calls 2402647 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2689176 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22586857 # number of integer instructions +system.cpu1.num_func_calls 2402385 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2688390 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22581810 # number of integer instructions system.cpu1.num_fp_insts 1738 # number of float instructions -system.cpu1.num_int_register_reads 41666783 # number of times the integer registers were read -system.cpu1.num_int_register_writes 15854927 # number of times the integer registers were written +system.cpu1.num_int_register_reads 41656503 # number of times the integer registers were read +system.cpu1.num_int_register_writes 15851657 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1290 # number of times the floating registers were read system.cpu1.num_fp_register_writes 448 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 92283936 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 9328431 # number of times the CC registers were written -system.cpu1.num_mem_refs 8130215 # number of memory refs -system.cpu1.num_load_insts 4674464 # Number of load instructions -system.cpu1.num_store_insts 3455751 # Number of store instructions -system.cpu1.num_idle_cycles 151523865.450182 # Number of idle cycles -system.cpu1.num_busy_cycles 6488290.549818 # Number of busy cycles -system.cpu1.not_idle_fraction 0.041062 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.958938 # Percentage of idle cycles -system.cpu1.Branches 5242761 # Number of branches fetched +system.cpu1.num_cc_register_reads 92262793 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 9324878 # number of times the CC registers were written +system.cpu1.num_mem_refs 8128633 # number of memory refs +system.cpu1.num_load_insts 4673659 # Number of load instructions +system.cpu1.num_store_insts 3454974 # Number of store instructions +system.cpu1.num_idle_cycles 151523982.353984 # Number of idle cycles +system.cpu1.num_busy_cycles 6487803.646016 # Number of busy cycles +system.cpu1.not_idle_fraction 0.041059 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.958941 # Percentage of idle cycles +system.cpu1.Branches 5241513 # Number of branches fetched system.cpu1.op_class::No_OpClass 34 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 17956106 68.78% 68.78% # Class of executed instruction -system.cpu1.op_class::IntMult 18827 0.07% 68.85% # Class of executed instruction +system.cpu1.op_class::IntAlu 17951469 68.78% 68.78% # Class of executed instruction +system.cpu1.op_class::IntMult 18860 0.07% 68.85% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 68.85% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 68.85% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 68.85% # Class of executed instruction @@ -1083,26 +1222,34 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.85% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.85% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.85% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1169 0.00% 68.86% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1172 0.00% 68.86% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 68.86% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.86% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.86% # Class of executed instruction -system.cpu1.op_class::MemRead 4674464 17.91% 86.76% # Class of executed instruction -system.cpu1.op_class::MemWrite 3455751 13.24% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 4673659 17.91% 86.76% # Class of executed instruction +system.cpu1.op_class::MemWrite 3454974 13.24% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 26106351 # Class of executed instruction +system.cpu1.op_class::total 26100168 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 17443399 # Number of BP lookups -system.cpu2.branchPred.condPredicted 9460519 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 398611 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 10920300 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 8161771 # Number of BTB hits +system.cpu2.branchPred.lookups 17449157 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9464735 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 398390 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 10718645 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 8165775 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 74.739439 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 4093630 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21092 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 76.182904 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4093661 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 20704 # Number of incorrect RAS predictions. +system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1124,27 +1271,100 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu2.dtb.walker.walks 43517 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 43517 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 13970 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 11118 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksSquashedBefore 18429 # Table walks squashed before starting +system.cpu2.dtb.walker.walkWaitTime::samples 25088 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::mean 493.961256 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::stdev 3141.545513 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0-8191 24512 97.70% 97.70% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::8192-16383 373 1.49% 99.19% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::16384-24575 135 0.54% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::24576-32767 33 0.13% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::32768-40959 15 0.06% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::40960-49151 7 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::49152-57343 6 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::57344-65535 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::65536-73727 1 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::122880-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 25088 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 9234 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 11931.507147 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 9422.312939 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 7440.393288 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-8191 2697 29.21% 29.21% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::8192-16383 4034 43.69% 72.89% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::16384-24575 2262 24.50% 97.39% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::24576-32767 120 1.30% 98.69% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::32768-40959 50 0.54% 99.23% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::40960-49151 64 0.69% 99.92% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::49152-57343 4 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::73728-81919 2 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 9234 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 52111304876 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::mean 0.433489 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::stdev 0.514696 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0-1 52056176876 99.89% 99.89% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::2-3 40469500 0.08% 99.97% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::4-5 8303000 0.02% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::6-7 2155500 0.00% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::8-9 1410500 0.00% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::10-11 753500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::12-13 454000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::14-15 1056000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::16-17 83500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::18-19 122000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::20-21 61500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::22-23 86000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::24-25 164500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::26-27 4000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::28-29 4500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 52111304876 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 2902 72.88% 72.88% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 1080 27.12% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 3982 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 43517 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 43517 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 3982 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 3982 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 47499 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 9671030 # DTB read hits -system.cpu2.dtb.read_misses 37752 # DTB read misses -system.cpu2.dtb.write_hits 7157940 # DTB write hits -system.cpu2.dtb.write_misses 5738 # DTB write misses +system.cpu2.dtb.read_hits 9677625 # DTB read hits +system.cpu2.dtb.read_misses 37716 # DTB read misses +system.cpu2.dtb.write_hits 7160348 # DTB write hits +system.cpu2.dtb.write_misses 5801 # DTB write misses system.cpu2.dtb.flush_tlb 182 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 368 # Number of times TLB was flushed by MVA +system.cpu2.dtb.flush_tlb_mva 369 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2464 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 439 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 949 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2469 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 429 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 945 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 419 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 9708782 # DTB read accesses -system.cpu2.dtb.write_accesses 7163678 # DTB write accesses +system.cpu2.dtb.perms_faults 418 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 9715341 # DTB read accesses +system.cpu2.dtb.write_accesses 7166149 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 16828970 # DTB hits -system.cpu2.dtb.misses 43490 # DTB misses -system.cpu2.dtb.accesses 16872460 # DTB accesses +system.cpu2.dtb.hits 16837973 # DTB hits +system.cpu2.dtb.misses 43517 # DTB misses +system.cpu2.dtb.accesses 16881490 # DTB accesses +system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1166,158 +1386,210 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 12894617 # ITB inst hits -system.cpu2.itb.inst_misses 6298 # ITB inst misses +system.cpu2.itb.walker.walks 6476 # Table walker walks requested +system.cpu2.itb.walker.walksShort 6476 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walksShortTerminationLevel::Level1 2218 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 4151 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksSquashedBefore 107 # Table walks squashed before starting +system.cpu2.itb.walker.walkWaitTime::samples 6369 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::mean 1246.035484 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::stdev 5374.992147 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0-8191 6033 94.72% 94.72% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::8192-16383 153 2.40% 97.13% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::16384-24575 113 1.77% 98.90% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::24576-32767 28 0.44% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::32768-40959 19 0.30% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::40960-49151 8 0.13% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::49152-57343 9 0.14% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::57344-65535 3 0.05% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::65536-73727 2 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::73728-81919 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 6369 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 1962 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 12125.644750 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 9197.080965 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 8421.034460 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-8191 606 30.89% 30.89% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::8192-16383 818 41.69% 72.58% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::16384-24575 463 23.60% 96.18% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::24576-32767 28 1.43% 97.60% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-40959 29 1.48% 99.08% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::40960-49151 11 0.56% 99.64% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::49152-57343 5 0.25% 99.90% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::57344-65535 1 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::73728-81919 1 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 1962 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 4866645120 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::mean 0.377306 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::stdev 0.486503 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 3033838520 62.34% 62.34% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::1 1830102100 37.61% 99.94% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::2 2122000 0.04% 99.99% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::3 461500 0.01% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::4 121000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 4866645120 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 1443 77.79% 77.79% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 412 22.21% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 1855 # Table walker page sizes translated +system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 6476 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 6476 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 1855 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 1855 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 8331 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 12898498 # ITB inst hits +system.cpu2.itb.inst_misses 6476 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 182 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 368 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb_mva 369 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1799 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1789 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1027 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1015 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 12900915 # ITB inst accesses -system.cpu2.itb.hits 12894617 # DTB hits -system.cpu2.itb.misses 6298 # DTB misses -system.cpu2.itb.accesses 12900915 # DTB accesses -system.cpu2.numCycles 69897742 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 12904974 # ITB inst accesses +system.cpu2.itb.hits 12898498 # DTB hits +system.cpu2.itb.misses 6476 # DTB misses +system.cpu2.itb.accesses 12904974 # DTB accesses +system.cpu2.numCycles 69896550 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 26768356 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 69154350 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 17443399 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 12255401 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 39728052 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2075674 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 91833 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 964 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 303 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 279943 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 102540 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 510 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 12893196 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 269600 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2749 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 68010313 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.222372 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.345734 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 26772867 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 69167442 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 17449157 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 12259436 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 39647350 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2075847 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 94572 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 925 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 261 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 361977 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 99094 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 575 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 12897087 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 269205 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2824 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 68015518 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.222532 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.345771 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 49396667 72.63% 72.63% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 2406815 3.54% 76.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 1558633 2.29% 78.46% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4908408 7.22% 85.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 1099721 1.62% 87.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 702073 1.03% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 3889062 5.72% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 750470 1.10% 95.15% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3298464 4.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 49396866 72.63% 72.63% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 2407853 3.54% 76.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 1558370 2.29% 78.46% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4909650 7.22% 85.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 1103212 1.62% 87.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 700919 1.03% 88.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 3889597 5.72% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 749830 1.10% 95.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3299221 4.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 68010313 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.249556 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.989365 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 18657683 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 36955851 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 10391299 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1075131 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 930120 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 1306172 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 109269 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 59268734 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 353681 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 930120 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 19279637 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4349454 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 27177493 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 10831041 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5442328 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 56795330 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2300 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 936981 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 152434 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 3851730 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 58689966 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 260889069 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 63678439 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 4318 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 48634410 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10055540 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 957404 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 893614 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 6253924 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 10259989 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 7928891 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 1377694 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 1916931 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 54575287 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 669934 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 51950842 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 68646 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7267604 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 18361034 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 68925 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 68010313 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.763867 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.465859 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 68015518 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.249643 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.989569 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 18660323 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 36954486 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 10395816 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1074729 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 929937 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 1306815 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 109505 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 59278443 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 354551 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 929937 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 19281301 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4387069 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 27167714 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 10836297 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5412952 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 56807794 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2395 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 934627 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 156415 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 3819110 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 58701003 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 260943920 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 63689416 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 4317 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 48649356 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10051631 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 957722 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 893887 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 6244990 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 10262812 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 7930622 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 1370921 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 1928187 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 54587761 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 670112 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 51973443 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 68390 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7260181 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 18315253 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 68730 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 68015518 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.764141 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.466174 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 47556715 69.93% 69.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6835010 10.05% 79.98% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 5099948 7.50% 87.47% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4195226 6.17% 93.64% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1610331 2.37% 96.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1069065 1.57% 97.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 1123688 1.65% 99.23% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 361159 0.53% 99.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 159171 0.23% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 47556774 69.92% 69.92% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6833375 10.05% 79.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 5102327 7.50% 87.47% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4195165 6.17% 93.64% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1616653 2.38% 96.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1064575 1.57% 97.58% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 1125788 1.66% 99.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 361184 0.53% 99.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 159677 0.23% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 68010313 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 68015518 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 78624 9.78% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 373360 46.42% 56.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 352326 43.80% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 78584 9.71% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 374915 46.33% 56.04% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 355764 43.96% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 110 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 34419657 66.25% 66.25% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 39271 0.08% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 34433275 66.25% 66.25% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 39265 0.08% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.33% # Type of FU issued @@ -1330,10 +1602,10 @@ system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.33% # Ty system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 2 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 3 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.33% # Type of FU issued @@ -1341,101 +1613,101 @@ system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.33% # Ty system.cpu2.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 2864 0.01% 66.34% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.34% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.34% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.34% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 9952470 19.16% 85.49% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 7536463 14.51% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 2873 0.01% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 9958899 19.16% 85.49% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 7539012 14.51% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 51950842 # Type of FU issued -system.cpu2.iq.rate 0.743241 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 804311 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.015482 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 172775366 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 62545429 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 50354259 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 9588 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 5092 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 4209 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 52749857 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 5186 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 265342 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 51973443 # Type of FU issued +system.cpu2.iq.rate 0.743577 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 809264 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.015571 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 172830468 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 62550700 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 50376095 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 9590 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 5049 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 4207 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 52777410 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 5187 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 265138 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1601303 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1888 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 38444 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 793651 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1600472 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1933 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 38461 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 793125 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 130825 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 118759 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 131320 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 120276 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 930120 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3238109 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 943841 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 55348166 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 92957 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 10259989 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 7928891 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 358502 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 33985 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 900757 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 38444 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 183146 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 162363 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 345509 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 51516440 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 9776464 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 391010 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 929937 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3246832 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 971285 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 55360766 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 91934 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 10262812 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 7930622 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 358706 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 34253 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 928134 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 38461 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 182765 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 162631 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 345396 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 51539725 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 9783295 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 390308 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 102945 # number of nop insts executed -system.cpu2.iew.exec_refs 17239257 # number of memory reference insts executed -system.cpu2.iew.exec_branches 9485344 # Number of branches executed -system.cpu2.iew.exec_stores 7462793 # Number of stores executed -system.cpu2.iew.exec_rate 0.737026 # Inst execution rate -system.cpu2.iew.wb_sent 51063802 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 50358468 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 26440569 # num instructions producing a value -system.cpu2.iew.wb_consumers 45930116 # num instructions consuming a value +system.cpu2.iew.exec_nop 102893 # number of nop insts executed +system.cpu2.iew.exec_refs 17248466 # number of memory reference insts executed +system.cpu2.iew.exec_branches 9490874 # Number of branches executed +system.cpu2.iew.exec_stores 7465171 # Number of stores executed +system.cpu2.iew.exec_rate 0.737372 # Inst execution rate +system.cpu2.iew.wb_sent 51085657 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 50380302 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 26454346 # num instructions producing a value +system.cpu2.iew.wb_consumers 45953910 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.720459 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.575670 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.720784 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.575671 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 8108589 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 601009 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 290869 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 66287251 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.712520 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.616760 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8107084 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 601382 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 290377 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 66292417 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.712682 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.616986 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 48204047 72.72% 72.72% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 8094433 12.21% 84.93% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 3998554 6.03% 90.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 1723968 2.60% 93.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 875669 1.32% 94.89% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 615346 0.93% 95.81% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 1257319 1.90% 97.71% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 299111 0.45% 98.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1218804 1.84% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 48208105 72.72% 72.72% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 8091600 12.21% 84.93% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 3999207 6.03% 90.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 1724132 2.60% 93.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 877027 1.32% 94.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 615427 0.93% 95.81% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 1259890 1.90% 97.71% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 297840 0.45% 98.16% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1219189 1.84% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 66287251 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 38872037 # Number of instructions committed -system.cpu2.commit.committedOps 47230974 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 66292417 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 38883433 # Number of instructions committed +system.cpu2.commit.committedOps 47245385 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 15793926 # Number of memory references committed -system.cpu2.commit.loads 8658686 # Number of loads committed -system.cpu2.commit.membars 225734 # Number of memory barriers committed -system.cpu2.commit.branches 8913791 # Number of branches committed +system.cpu2.commit.refs 15799837 # Number of memory references committed +system.cpu2.commit.loads 8662340 # Number of loads committed +system.cpu2.commit.membars 225899 # Number of memory barriers committed +system.cpu2.commit.branches 8915887 # Number of branches committed system.cpu2.commit.fp_insts 4128 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 41344274 # Number of committed integer instructions. -system.cpu2.commit.function_calls 1642310 # Number of function calls committed. +system.cpu2.commit.int_insts 41357490 # Number of committed integer instructions. +system.cpu2.commit.function_calls 1642928 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 31396236 66.47% 66.47% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 37948 0.08% 66.55% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 31404754 66.47% 66.47% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 37921 0.08% 66.55% # Class of committed instruction system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.55% # Class of committed instruction system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.55% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.55% # Class of committed instruction @@ -1459,36 +1731,36 @@ system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.55% # system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.55% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.55% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 2864 0.01% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 2873 0.01% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 8658686 18.33% 84.89% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 7135240 15.11% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 8662340 18.33% 84.89% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 7137497 15.11% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 47230974 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1218804 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 47245385 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1219189 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 112988408 # The number of ROB reads -system.cpu2.rob.rob_writes 112405622 # The number of ROB writes -system.cpu2.timesIdled 280375 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1887429 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 5250225403 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 38810797 # Number of Instructions Simulated -system.cpu2.committedOps 47169734 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.800987 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.800987 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.555251 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.555251 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 56393520 # number of integer regfile reads -system.cpu2.int_regfile_writes 31926452 # number of integer regfile writes -system.cpu2.fp_regfile_reads 15872 # number of floating regfile reads -system.cpu2.fp_regfile_writes 13692 # number of floating regfile writes -system.cpu2.cc_regfile_reads 182232541 # number of cc regfile reads -system.cpu2.cc_regfile_writes 19215539 # number of cc regfile writes -system.cpu2.misc_regfile_reads 124355307 # number of misc regfile reads -system.cpu2.misc_regfile_writes 481535 # number of misc regfile writes +system.cpu2.rob.rob_reads 113003070 # The number of ROB reads +system.cpu2.rob.rob_writes 112431430 # The number of ROB writes +system.cpu2.timesIdled 280451 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1881032 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 5250223632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 38822148 # Number of Instructions Simulated +system.cpu2.committedOps 47184100 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.800430 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.800430 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.555423 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.555423 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 56420474 # number of integer regfile reads +system.cpu2.int_regfile_writes 31939226 # number of integer regfile writes +system.cpu2.fp_regfile_reads 15888 # number of floating regfile reads +system.cpu2.fp_regfile_writes 13694 # number of floating regfile writes +system.cpu2.cc_regfile_reads 182315650 # number of cc regfile reads +system.cpu2.cc_regfile_writes 19227541 # number of cc regfile writes +system.cpu2.misc_regfile_reads 124375401 # number of misc regfile reads +system.cpu2.misc_regfile_writes 481787 # number of misc regfile writes system.iobus.trans_dist::ReadReq 30188 # Transaction distribution system.iobus.trans_dist::ReadResp 30188 # Transaction distribution system.iobus.trans_dist::WriteReq 59019 # Transaction distribution @@ -1544,7 +1816,7 @@ system.iobus.pkt_size_system.bridge.master::total 159119 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480367 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 18213000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 18225000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1570,25 +1842,25 @@ system.iobus.reqLayer23.occupancy 2807000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15730000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 15727000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 217719639 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 217868633 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 39873000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 39885000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 22974011 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 22990014 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 0.993341 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.993331 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 245004243009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.993341 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062084 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062084 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 245002453509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.993331 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062083 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062083 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1604,8 +1876,8 @@ system.iocache.overall_misses::realview.ide 252 # system.iocache.overall_misses::total 252 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 14419928 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 14419928 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6029712700 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6029712700 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6024842691 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6024842691 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ide 14419928 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 14419928 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 14419928 # number of overall miss cycles @@ -1628,17 +1900,17 @@ system.iocache.overall_miss_rate::realview.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 57221.936508 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 57221.936508 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 166456.291409 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 166456.291409 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 166321.849906 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 166321.849906 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 57221.936508 # average overall miss latency system.iocache.demand_avg_miss_latency::total 57221.936508 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 57221.936508 # average overall miss latency system.iocache.overall_avg_miss_latency::total 57221.936508 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34890 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 34568 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4513 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4486 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.730999 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.705751 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1646,323 +1918,327 @@ system.iocache.writebacks::writebacks 36190 # nu system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 127 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 127 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 22720 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 22720 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 22736 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 22736 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 127 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 127 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 127 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 127 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 7815928 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 7815928 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4848250722 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4848250722 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4842542719 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4842542719 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 7815928 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 7815928 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 7815928 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 7815928 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.503968 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.503968 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.627208 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.627208 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.627650 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.627650 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 0.503968 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 0.503968 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 0.503968 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.503968 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 61542.740157 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 61542.740157 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213391.316989 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213391.316989 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212990.091441 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212990.091441 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 61542.740157 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 61542.740157 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 61542.740157 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 61542.740157 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 100831 # number of replacements -system.l2c.tags.tagsinuse 65118.744874 # Cycle average of tags in use -system.l2c.tags.total_refs 2894730 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 166072 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 17.430572 # Average number of references to valid blocks. +system.l2c.tags.replacements 100812 # number of replacements +system.l2c.tags.tagsinuse 65118.584894 # Cycle average of tags in use +system.l2c.tags.total_refs 2893892 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 166052 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 17.427625 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 49795.493403 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939326 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 49801.969845 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939327 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5292.397633 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2853.974292 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969197 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1121.420686 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 949.232304 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 58.100226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 3505.367496 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1539.850216 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.759819 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5299.216432 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2852.911552 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969199 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1106.770268 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 948.162110 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 57.070020 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 3510.700878 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1538.875168 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.759918 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080756 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043548 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.080860 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043532 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.017112 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.014484 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000887 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.053488 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.023496 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993633 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 45 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65196 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 45 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.016888 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.014468 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000871 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.053569 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.023481 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993631 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 49 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65191 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 49 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3290 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7951 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53614 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000687 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994812 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27445059 # Number of tag accesses -system.l2c.tags.data_accesses 27445059 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5016 # 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Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7961 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53600 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000748 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994736 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 27438611 # Number of tag accesses +system.l2c.tags.data_accesses 27438611 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 5008 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2568 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 857894 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 243025 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 1381 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 686 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 247021 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 78422 # 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average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10002.886792 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.341382 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10003.356268 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.676727 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57766.563505 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62320.767201 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61486.916547 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57472.558521 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62169.148043 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61307.541942 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59455.882353 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58558.171601 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64755.319149 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 64427.787644 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62786.059428 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 62106.440817 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60462.060302 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58213.978994 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 71037.234043 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63863.659370 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62550.140576 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61856.475401 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59455.882353 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58558.171601 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64755.319149 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 64427.787644 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62786.059428 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 62106.440817 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60462.060302 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58213.978994 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 71037.234043 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63863.659370 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62550.140576 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61856.475401 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2117,55 +2393,55 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 74228 # Transaction distribution -system.membus.trans_dist::ReadResp 74227 # Transaction distribution +system.membus.trans_dist::ReadReq 74222 # Transaction distribution +system.membus.trans_dist::ReadResp 74221 # Transaction distribution system.membus.trans_dist::WriteReq 27571 # Transaction distribution system.membus.trans_dist::WriteResp 27571 # Transaction distribution -system.membus.trans_dist::Writeback 129090 # Transaction distribution +system.membus.trans_dist::Writeback 129099 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4545 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4548 # Transaction distribution -system.membus.trans_dist::ReadExReq 137060 # Transaction distribution -system.membus.trans_dist::ReadExResp 137060 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4550 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4556 # Transaction distribution +system.membus.trans_dist::ReadExReq 137047 # Transaction distribution +system.membus.trans_dist::ReadExResp 137047 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105462 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471586 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 579048 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 579034 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109015 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109015 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 688063 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 688049 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159119 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16930172 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17093291 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16929468 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17092587 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4642496 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4642496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21735787 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 288 # Total snoops (count) -system.membus.snoop_fanout::samples 341037 # Request fanout histogram +system.membus.pkt_size::total 21735083 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 289 # Total snoops (count) +system.membus.snoop_fanout::samples 341035 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 341037 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 341035 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 341037 # Request fanout histogram -system.membus.reqLayer0.occupancy 40803000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 341035 # Request fanout histogram +system.membus.reqLayer0.occupancy 40827000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 460500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 469500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 937458500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 937138500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 904148767 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 904275509 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 23873989 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 23892986 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2198,54 +2474,54 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2443122 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2443118 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2442249 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2442245 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27571 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27571 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 692650 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 22720 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2771 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2788 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296527 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296527 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3615529 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484690 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28930 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88144 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6217293 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115152760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97928947 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 48448 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 155392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 213285547 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 51952 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3431323 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.010630 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.102554 # Request fanout histogram +system.toL2Bus.trans_dist::Writeback 692729 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 22736 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2762 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2780 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296542 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296542 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3613854 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484499 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29280 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87986 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6215619 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115099320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97925875 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 49208 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 154964 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 213229367 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 51973 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3430536 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.010633 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.102566 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3394847 98.94% 98.94% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3394060 98.94% 98.94% # Request fanout histogram system.toL2Bus.snoop_fanout::6 36476 1.06% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3431323 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2376326693 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3430536 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2377189197 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 558000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4188826435 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4188720502 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2020844355 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2021336108 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11830425 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 12001413 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 39636892 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 39606873 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |