diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt | 2868 |
1 files changed, 1459 insertions, 1409 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 8e01cba8d..8f1b31c18 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,172 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403854 # Number of seconds simulated -sim_ticks 2403853586500 # Number of ticks simulated -final_tick 2403853586500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403852 # Number of seconds simulated +sim_ticks 2403852457500 # Number of ticks simulated +final_tick 2403852457500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171159 # Simulator instruction rate (inst/s) -host_op_rate 219830 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6819657603 # Simulator tick rate (ticks/s) -host_mem_usage 469520 # Number of bytes of host memory used -host_seconds 352.49 # Real time elapsed on the host -sim_insts 60331708 # Number of instructions simulated -sim_ops 77487722 # Number of ops (including micro ops) simulated +host_inst_rate 165592 # Simulator instruction rate (inst/s) +host_op_rate 212680 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6597855857 # Simulator tick rate (ticks/s) +host_mem_usage 469068 # Number of bytes of host memory used +host_seconds 364.34 # Real time elapsed on the host +sim_insts 60331653 # Number of instructions simulated +sim_ops 77487544 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 512776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7053720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 512456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7048216 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 63616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 681152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 186368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1342304 # Number of bytes read from this memory -system.physmem.bytes_read::total 124659968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 512776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 63616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 186368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 762760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3743360 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298364 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 159256 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558196 # Number of bytes written to this memory -system.physmem.bytes_written::total 6759176 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 63936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 680960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 186944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1348288 # Number of bytes read from this memory +system.physmem.bytes_read::total 124660704 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 512456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 63936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 186944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 763336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3743808 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298564 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 159248 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1558004 # Number of bytes written to this memory +system.physmem.bytes_written::total 6759624 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14224 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110250 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14219 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110164 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 994 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10643 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2912 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20981 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512403 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58490 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324591 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39814 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389549 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812444 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47764586 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 999 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10640 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2921 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 21067 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512407 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58497 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324641 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39812 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 389501 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812451 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47764609 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 213314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2934338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2932050 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 283358 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 77529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 558397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51858386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213314 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26464 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 77529 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317307 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557233 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540118 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 66250 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648208 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2811809 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557233 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47764586 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 283279 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 77769 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 560886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51858717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26597 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 77769 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317547 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557420 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540201 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 66247 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648128 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2811996 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47764609 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3474456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3472251 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 349609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 77529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1206604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54670195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13446822 # Number of read requests accepted -system.physmem.writeReqs 446449 # Number of write requests accepted -system.physmem.readBursts 13446822 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 446449 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 860596480 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue -system.physmem.bytesWritten 2823168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109564448 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2810956 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 402307 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2362 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 835680 # Per bank write bursts -system.physmem.perBankRdBursts::1 835344 # Per bank write bursts -system.physmem.perBankRdBursts::2 835508 # Per bank write bursts -system.physmem.perBankRdBursts::3 835965 # Per bank write bursts -system.physmem.perBankRdBursts::4 837088 # Per bank write bursts -system.physmem.perBankRdBursts::5 837779 # Per bank write bursts -system.physmem.perBankRdBursts::6 837907 # Per bank write bursts -system.physmem.perBankRdBursts::7 839147 # Per bank write bursts -system.physmem.perBankRdBursts::8 840641 # Per bank write bursts -system.physmem.perBankRdBursts::9 843268 # Per bank write bursts -system.physmem.perBankRdBursts::10 843373 # Per bank write bursts -system.physmem.perBankRdBursts::11 843869 # Per bank write bursts -system.physmem.perBankRdBursts::12 845852 # Per bank write bursts -system.physmem.perBankRdBursts::13 846016 # Per bank write bursts -system.physmem.perBankRdBursts::14 844806 # Per bank write bursts -system.physmem.perBankRdBursts::15 844577 # Per bank write bursts -system.physmem.perBankWrBursts::0 2668 # Per bank write bursts -system.physmem.perBankWrBursts::1 2526 # Per bank write bursts -system.physmem.perBankWrBursts::2 2530 # Per bank write bursts -system.physmem.perBankWrBursts::3 3005 # Per bank write bursts -system.physmem.perBankWrBursts::4 3419 # Per bank write bursts -system.physmem.perBankWrBursts::5 3167 # Per bank write bursts -system.physmem.perBankWrBursts::6 2515 # Per bank write bursts -system.physmem.perBankWrBursts::7 2303 # Per bank write bursts -system.physmem.perBankWrBursts::8 2186 # Per bank write bursts -system.physmem.perBankWrBursts::9 2396 # Per bank write bursts -system.physmem.perBankWrBursts::10 2346 # Per bank write bursts -system.physmem.perBankWrBursts::11 2792 # Per bank write bursts -system.physmem.perBankWrBursts::12 3710 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 26597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 349526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 77769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1209014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54670713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13446501 # Number of read requests accepted +system.physmem.writeReqs 446412 # Number of write requests accepted +system.physmem.readBursts 13446501 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 446412 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 860576000 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 64 # Total number of bytes read from write queue +system.physmem.bytesWritten 2816640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109567680 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2811588 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 402376 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2365 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 835689 # Per bank write bursts +system.physmem.perBankRdBursts::1 835334 # Per bank write bursts +system.physmem.perBankRdBursts::2 835514 # Per bank write bursts +system.physmem.perBankRdBursts::3 835992 # Per bank write bursts +system.physmem.perBankRdBursts::4 837083 # Per bank write bursts +system.physmem.perBankRdBursts::5 837766 # Per bank write bursts +system.physmem.perBankRdBursts::6 837910 # Per bank write bursts +system.physmem.perBankRdBursts::7 839140 # Per bank write bursts +system.physmem.perBankRdBursts::8 840643 # Per bank write bursts +system.physmem.perBankRdBursts::9 843328 # Per bank write bursts +system.physmem.perBankRdBursts::10 843395 # Per bank write bursts +system.physmem.perBankRdBursts::11 843892 # Per bank write bursts +system.physmem.perBankRdBursts::12 845429 # Per bank write bursts +system.physmem.perBankRdBursts::13 846004 # Per bank write bursts +system.physmem.perBankRdBursts::14 844795 # Per bank write bursts +system.physmem.perBankRdBursts::15 844586 # Per bank write bursts +system.physmem.perBankWrBursts::0 2674 # Per bank write bursts +system.physmem.perBankWrBursts::1 2534 # Per bank write bursts +system.physmem.perBankWrBursts::2 2538 # Per bank write bursts +system.physmem.perBankWrBursts::3 3024 # Per bank write bursts +system.physmem.perBankWrBursts::4 3410 # Per bank write bursts +system.physmem.perBankWrBursts::5 3131 # Per bank write bursts +system.physmem.perBankWrBursts::6 2493 # Per bank write bursts +system.physmem.perBankWrBursts::7 2267 # Per bank write bursts +system.physmem.perBankWrBursts::8 2164 # Per bank write bursts +system.physmem.perBankWrBursts::9 2378 # Per bank write bursts +system.physmem.perBankWrBursts::10 2328 # Per bank write bursts +system.physmem.perBankWrBursts::11 2803 # Per bank write bursts +system.physmem.perBankWrBursts::12 3718 # Per bank write bursts system.physmem.perBankWrBursts::13 3446 # Per bank write bursts -system.physmem.perBankWrBursts::14 2600 # Per bank write bursts -system.physmem.perBankWrBursts::15 2503 # Per bank write bursts +system.physmem.perBankWrBursts::14 2595 # Per bank write bursts +system.physmem.perBankWrBursts::15 2507 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2402817511500 # Total gap between requests +system.physmem.totGap 2402816386500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 8 # Read request sizes (log2) -system.physmem.readPktSize::3 13411280 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 13410864 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 35534 # Read request sizes (log2) +system.physmem.readPktSize::6 35637 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 429363 # Write request sizes (log2) +system.physmem.writePktSize::2 429313 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 17086 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 867414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 844196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 838512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 839224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 838671 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 838847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2475363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2475187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3292199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 19694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 19741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 19565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 19175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 19145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 22 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17099 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 877452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 853858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 853065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 937219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 861122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 912169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2402802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2330624 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3052022 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 86874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 80661 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 76244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 73288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 16291 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 16173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -184,8 +180,8 @@ system.physmem.rdQLenPdf::30 0 # Wh system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 99 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 96 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 96 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 95 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 95 # What write queue length does an incoming req see @@ -196,48 +192,48 @@ system.physmem.wrQLenPdf::10 93 # Wh system.physmem.wrQLenPdf::11 93 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 92 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 1586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -246,79 +242,63 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 844644 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1019.942660 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1014.395909 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 58.300980 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1516 0.18% 0.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 1237 0.15% 0.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 570 0.07% 0.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 375 0.04% 0.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 256 0.03% 0.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 198 0.02% 0.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 155 0.02% 0.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 158 0.02% 0.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 840179 99.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 844644 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 1621 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 8295.373226 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 315033.644502 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 1620 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.06% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 1621 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 1621 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.212832 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 24.563019 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.121341 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 1 0.06% 0.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 2 0.12% 0.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 1 0.06% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 1 0.06% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 1 0.06% 0.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 1 0.06% 0.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 1 0.06% 0.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 2 0.12% 0.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 6 0.37% 0.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 488 30.10% 31.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 27 1.67% 32.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 60 3.70% 36.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 333 20.54% 57.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 10 0.62% 57.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.19% 57.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.12% 57.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.19% 58.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 2 0.12% 58.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.19% 58.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.31% 58.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.25% 58.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 5 0.31% 59.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 7 0.43% 59.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.19% 59.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 2 0.12% 60.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 8 0.49% 60.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 2 0.12% 60.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.06% 60.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 50 3.08% 63.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 4 0.25% 64.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 167 10.30% 74.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 328 20.23% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 16 0.99% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 15 0.93% 96.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 23 1.42% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 17 1.05% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 13 0.80% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 2 0.12% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 2 0.12% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 1621 # Writes before turning the bus around for reads -system.physmem.totQLat 510864117000 # Total ticks spent queuing -system.physmem.totMemAccLat 601782495750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67234100000 # Total ticks spent in databus transfers -system.physmem.totBankLat 23684278750 # Total ticks spent accessing banks -system.physmem.avgQLat 37991.44 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1761.33 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 866032 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 996.952353 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 964.296727 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 145.584191 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8288 0.96% 0.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8846 1.02% 1.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6189 0.71% 2.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 800 0.09% 2.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 916 0.11% 2.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 687 0.08% 2.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7828 0.90% 3.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 243 0.03% 3.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 832235 96.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 866032 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2414 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 5570.207125 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 258157.496677 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 2413 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.04% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 2414 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2414 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.231152 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.108696 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.979905 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 1 0.04% 0.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 2 0.08% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 1 0.04% 0.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 1 0.04% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 2 0.08% 0.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 1 0.04% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12 1 0.04% 0.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 1 0.04% 0.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 7 0.29% 0.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 485 20.09% 20.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 15 0.62% 21.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 872 36.12% 57.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 845 35.00% 92.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 52 2.15% 94.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 24 0.99% 95.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 26 1.08% 96.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 34 1.41% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 13 0.54% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 5 0.21% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 6 0.25% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.04% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 6 0.25% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 7 0.29% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.08% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 4 0.17% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2414 # Writes before turning the bus around for reads +system.physmem.totQLat 345783645500 # Total ticks spent queuing +system.physmem.totMemAccLat 597905520500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67232500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25715.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44752.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 358.01 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44465.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 358.00 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 45.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s @@ -326,15 +306,19 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.81 # Data bus utilization in percentage system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 8.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 5.41 # Average write queue length when enqueuing -system.physmem.readRowHits 12595156 # Number of row buffer hits during reads -system.physmem.writeRowHits 38053 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.21 # Row buffer hit rate for writes -system.physmem.avgGap 172948.29 # Average gap between requests -system.physmem.pageHitRate 93.64 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.74 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.avgRdQLen 7.51 # Average read queue length when enqueuing +system.physmem.avgWrQLen 4.43 # Average write queue length when enqueuing +system.physmem.readRowHits 12586631 # Number of row buffer hits during reads +system.physmem.writeRowHits 37847 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.95 # Row buffer hit rate for writes +system.physmem.avgGap 172952.67 # Average gap between requests +system.physmem.pageHitRate 93.58 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2167477603250 # Time in different power states +system.physmem.memoryStateTime::REF 80269800000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 156101819250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -347,341 +331,322 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55667457 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13781916 # Transaction distribution -system.membus.trans_dist::ReadResp 13781916 # Transaction distribution -system.membus.trans_dist::WriteReq 432200 # Transaction distribution -system.membus.trans_dist::WriteResp 432200 # Transaction distribution -system.membus.trans_dist::Writeback 17086 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2361 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2362 # Transaction distribution -system.membus.trans_dist::ReadExReq 27973 # Transaction distribution -system.membus.trans_dist::ReadExResp 27973 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731598 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 210 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951620 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1683428 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26822560 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26822560 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28505988 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735468 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 420 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5085164 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5821052 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107290240 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107290240 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113111292 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133816415 # Total data (bytes) +system.membus.throughput 55667977 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13781620 # Transaction distribution +system.membus.trans_dist::ReadResp 13781620 # Transaction distribution +system.membus.trans_dist::WriteReq 432153 # Transaction distribution +system.membus.trans_dist::WriteResp 432153 # Transaction distribution +system.membus.trans_dist::Writeback 17099 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2365 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2365 # Transaction distribution +system.membus.trans_dist::ReadExReq 28041 # Transaction distribution +system.membus.trans_dist::ReadExResp 28041 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 214 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951729 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1683729 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26821728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26821728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28505457 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735662 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 428 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5092356 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5828446 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107286912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107286912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113115358 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133817603 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 416850000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 416874000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 198000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 199500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14576843000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14576510500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1595419615 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1596663785 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 33523642000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33229062000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 63235 # number of replacements -system.l2c.tags.tagsinuse 50381.174231 # Cycle average of tags in use -system.l2c.tags.total_refs 1749008 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128627 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.597518 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375559570500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36838.397677 # Average occupied blocks per requestor +system.l2c.tags.replacements 63248 # number of replacements +system.l2c.tags.tagsinuse 50398.234461 # Cycle average of tags in use +system.l2c.tags.total_refs 1749256 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128641 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.597966 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375562300000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36845.662788 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5238.516596 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3833.196793 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993316 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 493.229672 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 688.317801 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.879272 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.004789 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1684.639749 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1594.998425 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562109 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5231.089770 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3832.891832 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993317 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 496.025776 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 690.296020 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.797358 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1694.464698 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1598.012760 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562220 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079933 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058490 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079820 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058485 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007526 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010503 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000135 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025706 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024338 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768756 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65386 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.007569 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010533 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000134 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.025855 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.024384 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.769016 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65389 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6490 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55882 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997711 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17681539 # Number of tag accesses -system.l2c.tags.data_accesses 17681539 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8692 # number of ReadReq hits +system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2635 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6488 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55889 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997757 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17683113 # Number of tag accesses +system.l2c.tags.data_accesses 17683113 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 8690 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3137 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 468000 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 177035 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2622 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1183 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 129681 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 64527 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18896 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4217 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 281169 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 131701 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1290860 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597704 # number of Writeback hits -system.l2c.Writeback_hits::total 597704 # number of Writeback hits +system.l2c.ReadReq_hits::cpu0.inst 468117 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 177120 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2623 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1184 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 129717 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 64377 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18993 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4195 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 281260 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 131724 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1291137 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597632 # number of Writeback hits +system.l2c.Writeback_hits::total 597632 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 15 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 61997 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 18431 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33199 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113627 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8692 # number of demand (read+write) hits +system.l2c.UpgradeReq_hits::cpu2.data 12 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 4 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 62001 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 18409 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 33201 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113611 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8690 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 3137 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 468000 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 239032 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2622 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1183 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 129681 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 82958 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 18896 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 4217 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 281169 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 164900 # number of demand (read+write) hits -system.l2c.demand_hits::total 1404487 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8692 # number of overall hits +system.l2c.demand_hits::cpu0.inst 468117 # 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number of overall hits -system.l2c.overall_hits::cpu0.data 239032 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2622 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1183 # number of overall hits -system.l2c.overall_hits::cpu1.inst 129681 # number of overall hits -system.l2c.overall_hits::cpu1.data 82958 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 18896 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 4217 # number of overall hits -system.l2c.overall_hits::cpu2.inst 281169 # number of overall hits -system.l2c.overall_hits::cpu2.data 164900 # number of overall hits -system.l2c.overall_hits::total 1404487 # number of overall hits +system.l2c.overall_hits::cpu0.inst 468117 # number of overall hits +system.l2c.overall_hits::cpu0.data 239121 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 2623 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1184 # number of overall hits +system.l2c.overall_hits::cpu1.inst 129717 # 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number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34694058000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60700071100 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007607 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017001 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000529 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000237 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010251 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018825 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.005761 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991525 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.985507 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.506295 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.347113 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.364564 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.116780 # mshr miss rate for ReadExReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007643 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017085 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000474 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010279 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018967 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.005786 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991543 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.988361 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.507157 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.347268 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.365485 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.117086 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007607 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.116274 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000529 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000237 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010251 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.115688 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.023345 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007643 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.116469 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000474 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010279 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.116131 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.023410 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007607 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.116274 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000529 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000237 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010251 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.115688 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.023345 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007643 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.116469 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000474 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010279 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.116131 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.023410 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58128.521127 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65115.591398 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 66625 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 62767.771291 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64723.585279 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 63163.106732 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58264.514515 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64058.310992 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63034.748374 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64394.188850 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 63013.296340 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61297.583631 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61580.949808 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61484.690182 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59891.492036 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61174.798891 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60740.166229 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58128.521127 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61687.954375 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 66625 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 62767.771291 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61949.052146 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 61833.263466 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58264.514515 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60318.750389 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63034.748374 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61553.174888 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61213.045024 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58128.521127 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61687.954375 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 66625 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 62767.771291 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61949.052146 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 61833.263466 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58264.514515 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60318.750389 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63034.748374 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61553.174888 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61213.045024 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -854,52 +799,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58805312 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1019677 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1019676 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432200 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432200 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 265274 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1507 # Transaction distribution +system.toL2Bus.throughput 58808825 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1019736 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1019735 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432153 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432153 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 265208 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1504 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1511 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80476 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80476 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 830192 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2419562 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15560 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52654 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3317968 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26544384 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37373820 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21604 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 86116 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 64025924 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141258487 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 100872 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2176910263 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeResp 1508 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80528 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80528 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 830481 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2419466 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15414 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52803 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3318164 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26553408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37366366 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21516 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 86504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 64027794 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141267007 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 100732 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2176624753 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1870334166 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1870991697 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1845880168 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1845922726 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10179455 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10050964 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 31260469 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 31304739 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48758934 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13774305 # Transaction distribution -system.iobus.trans_dist::ReadResp 13774305 # Transaction distribution -system.iobus.trans_dist::WriteReq 2774 # Transaction distribution -system.iobus.trans_dist::WriteResp 2774 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11404 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3022 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48758959 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13773981 # Transaction distribution +system.iobus.trans_dist::ReadResp 13773981 # Transaction distribution +system.iobus.trans_dist::WriteReq 2776 # Transaction distribution +system.iobus.trans_dist::WriteResp 2776 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11410 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3028 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 252 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 254 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716614 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716788 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -915,18 +860,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 731598 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26822560 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26822560 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27554158 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6044 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 731786 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26821728 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26821728 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27553514 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15374 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6056 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 504 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 508 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 712940 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 713112 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -942,18 +887,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 735468 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107290240 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107290240 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108025708 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 117209339 # Total data (bytes) -system.iobus.reqLayer0.occupancy 7964000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 735662 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107286912 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107286912 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108022574 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 117209343 # Total data (bytes) +system.iobus.reqLayer0.occupancy 7968000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1511000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1514000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 126000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 127000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -961,7 +906,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 358810000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 358898000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -993,11 +938,11 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13411280000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13410864000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 728824000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 729010000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 33525822000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 33767373000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -1022,25 +967,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7997782 # DTB read hits -system.cpu0.dtb.read_misses 6203 # DTB read misses -system.cpu0.dtb.write_hits 6595987 # DTB write hits -system.cpu0.dtb.write_misses 1983 # DTB write misses +system.cpu0.dtb.read_hits 7995700 # DTB read hits +system.cpu0.dtb.read_misses 6195 # DTB read misses +system.cpu0.dtb.write_hits 6594454 # DTB write hits +system.cpu0.dtb.write_misses 1984 # DTB write misses system.cpu0.dtb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 675 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5673 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5669 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 123 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 121 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 209 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8003985 # DTB read accesses -system.cpu0.dtb.write_accesses 6597970 # DTB write accesses +system.cpu0.dtb.read_accesses 8001895 # DTB read accesses +system.cpu0.dtb.write_accesses 6596438 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14593769 # DTB hits -system.cpu0.dtb.misses 8186 # DTB misses -system.cpu0.dtb.accesses 14601955 # DTB accesses +system.cpu0.dtb.hits 14590154 # DTB hits +system.cpu0.dtb.misses 8179 # DTB misses +system.cpu0.dtb.accesses 14598333 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1062,433 +1007,468 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 32336935 # ITB inst hits -system.cpu0.itb.inst_misses 3451 # ITB inst misses +system.cpu0.itb.inst_hits 32327896 # ITB inst hits +system.cpu0.itb.inst_misses 3449 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 675 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2628 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2626 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32340386 # ITB inst accesses -system.cpu0.itb.hits 32336935 # DTB hits -system.cpu0.itb.misses 3451 # DTB misses -system.cpu0.itb.accesses 32340386 # DTB accesses -system.cpu0.numCycles 113724377 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32331345 # ITB inst accesses +system.cpu0.itb.hits 32327896 # DTB hits +system.cpu0.itb.misses 3449 # DTB misses +system.cpu0.itb.accesses 32331345 # DTB accesses +system.cpu0.numCycles 113683212 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31861763 # Number of instructions committed -system.cpu0.committedOps 42032224 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37415212 # Number of integer alu accesses +system.cpu0.committedInsts 31852389 # Number of instructions committed +system.cpu0.committedOps 42022034 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37405417 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4937 # Number of float alu accesses -system.cpu0.num_func_calls 1199152 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4246542 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37415212 # number of integer instructions +system.cpu0.num_func_calls 1199046 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4246321 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37405417 # number of integer instructions system.cpu0.num_fp_insts 4937 # number of float instructions -system.cpu0.num_int_register_reads 193939915 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39523913 # number of times the integer registers were written +system.cpu0.num_int_register_reads 193890675 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39514617 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3572 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1366 # number of times the floating registers were written -system.cpu0.num_mem_refs 15261638 # number of memory refs -system.cpu0.num_load_insts 8366552 # Number of load instructions -system.cpu0.num_store_insts 6895086 # Number of store instructions -system.cpu0.num_idle_cycles 110931893.434026 # Number of idle cycles -system.cpu0.num_busy_cycles 2792483.565974 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024555 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975445 # Percentage of idle cycles -system.cpu0.Branches 5615139 # Number of branches fetched +system.cpu0.num_mem_refs 15257672 # number of memory refs +system.cpu0.num_load_insts 8364380 # Number of load instructions +system.cpu0.num_store_insts 6893292 # Number of store instructions +system.cpu0.num_idle_cycles 110986808.765580 # Number of idle cycles +system.cpu0.num_busy_cycles 2696403.234420 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023719 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976281 # Percentage of idle cycles +system.cpu0.Branches 5614656 # Number of branches fetched +system.cpu0.op_class::No_OpClass 14792 0.04% 0.04% # Class of executed instruction +system.cpu0.op_class::IntAlu 26773719 63.60% 63.63% # Class of executed instruction +system.cpu0.op_class::IntMult 49650 0.12% 63.75% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 1431 0.00% 63.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 63.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.76% # Class of executed instruction +system.cpu0.op_class::MemRead 8364380 19.87% 83.63% # Class of executed instruction +system.cpu0.op_class::MemWrite 6893292 16.37% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 42097264 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 891249 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.602369 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43668526 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 891761 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 48.968867 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8187850250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 494.923201 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.626935 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 9.052233 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.966647 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014896 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.017680 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999223 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 891512 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.602542 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 43658005 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 892024 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 48.942635 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 8184230000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 494.829489 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.587272 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 9.185782 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.966464 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014819 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.017941 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999224 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 166 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 45475856 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 45475856 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 31863243 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8064619 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3740664 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43668526 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31863243 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8064619 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3740664 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43668526 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31863243 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8064619 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3740664 # number of overall hits -system.cpu0.icache.overall_hits::total 43668526 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 476340 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 130939 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 308276 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 915555 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 476340 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 130939 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 308276 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 915555 # 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Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970799 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015829 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013367 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.042290 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.061376 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.893452 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970786 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015745 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013464 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 98832175 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 98832175 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6866825 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1820637 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4638025 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13325487 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5964516 # 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number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 804849 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6465 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1759 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3713 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11937 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 98835293 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 98835293 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6864775 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1819119 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4641948 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13325842 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5963046 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1314313 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2132881 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9410240 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131790 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 33007 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73476 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 238273 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 138256 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34751 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74378 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247385 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12827821 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 3133432 # 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number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4908084 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13836467 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6132483 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1344252 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2739705 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216440 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138281 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34792 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77075 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250148 # 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average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 21882.044193 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20723.829629 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30600.203178 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21882.044193 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7912 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2132 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 872 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 43 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.073394 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 49.581395 # average number of cycles each access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026190 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028652 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.114974 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054776 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026190 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028652 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.114974 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054776 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14235.239679 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14413.316175 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9398.667588 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34670.987655 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37626.330752 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 29685.996789 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13127.723624 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13383.243432 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6098.345729 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20575.477583 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30492.657651 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 21812.458447 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20575.477583 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30492.657651 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 21812.458447 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8069 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3116 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 905 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 48 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.916022 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 64.916667 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597704 # number of writebacks -system.cpu0.dcache.writebacks::total 597704 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 139099 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 139099 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 554931 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 554931 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 402 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 402 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 694030 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 694030 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 694030 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 694030 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63884 # 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number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57672251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 56499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 56499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1730851510 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3543754841 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5274606351 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1730851510 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3543754841 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5274606351 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27378129500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28579482250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55957611750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1439295977 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13341687506 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14780983483 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28817425477 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41921169756 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70738595233 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033899 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026683 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014082 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 92428 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 184316 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 276744 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 92428 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 184316 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 276744 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 779830000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1694363864 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2474193864 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 934250758 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1848694495 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2782945253 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19406250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38393502 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57799752 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 44000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 44000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1714080758 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3543058359 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5257139117 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1714080758 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3543058359 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5257139117 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27392049000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28579464500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55971513500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1440396400 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13339396963 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14779793363 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28832445400 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41918861463 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70751306863 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033859 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026666 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014074 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021352 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019436 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008021 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050558 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.042958 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020268 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019443 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008026 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050186 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043054 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020255 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000016 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028675 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024087 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011508 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028675 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024087 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011508 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12244.912654 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12929.192868 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12704.836166 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33049.874922 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34752.722924 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34156.328208 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11146.105742 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11496.904561 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11375.197436 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18694.527358 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19237.685678 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19056.003002 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18694.527358 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19237.685678 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19056.003002 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028652 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024078 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011505 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028652 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024078 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011505 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12232.243694 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12934.667725 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12704.722377 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32579.535430 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34670.389239 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33939.184529 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11127.436927 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11550.391697 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11404.844515 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18545.037846 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19222.738986 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18996.397815 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18545.037846 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19222.738986 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18996.397815 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1522,25 +1502,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2097642 # DTB read hits +system.cpu1.dtb.read_hits 2096038 # DTB read hits system.cpu1.dtb.read_misses 2089 # DTB read misses -system.cpu1.dtb.write_hits 1419704 # DTB write hits -system.cpu1.dtb.write_misses 373 # DTB write misses +system.cpu1.dtb.write_hits 1418402 # DTB write hits +system.cpu1.dtb.write_misses 376 # DTB write misses system.cpu1.dtb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1767 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1770 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 37 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2099731 # DTB read accesses -system.cpu1.dtb.write_accesses 1420077 # DTB write accesses +system.cpu1.dtb.read_accesses 2098127 # DTB read accesses +system.cpu1.dtb.write_accesses 1418778 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3517346 # DTB hits -system.cpu1.dtb.misses 2462 # DTB misses -system.cpu1.dtb.accesses 3519808 # DTB accesses +system.cpu1.dtb.hits 3514440 # DTB hits +system.cpu1.dtb.misses 2465 # DTB misses +system.cpu1.dtb.accesses 3516905 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1562,8 +1542,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 8195558 # ITB inst hits -system.cpu1.itb.inst_misses 1195 # ITB inst misses +system.cpu1.itb.inst_hits 8190394 # ITB inst hits +system.cpu1.itb.inst_misses 1200 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1572,51 +1552,86 @@ system.cpu1.itb.flush_tlb 554 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 946 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 949 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8196753 # ITB inst accesses -system.cpu1.itb.hits 8195558 # DTB hits -system.cpu1.itb.misses 1195 # DTB misses -system.cpu1.itb.accesses 8196753 # DTB accesses -system.cpu1.numCycles 584703165 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8191594 # ITB inst accesses +system.cpu1.itb.hits 8190394 # DTB hits +system.cpu1.itb.misses 1200 # DTB misses +system.cpu1.itb.accesses 8191594 # DTB accesses +system.cpu1.numCycles 584767176 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7984738 # Number of instructions committed -system.cpu1.committedOps 10135701 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9107037 # Number of integer alu accesses +system.cpu1.committedInsts 7979697 # Number of instructions committed +system.cpu1.committedOps 10128513 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9101420 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 2019 # Number of float alu accesses -system.cpu1.num_func_calls 304651 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1115193 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9107037 # number of integer instructions +system.cpu1.num_func_calls 304592 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1114093 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9101420 # number of integer instructions system.cpu1.num_fp_insts 2019 # number of float instructions -system.cpu1.num_int_register_reads 53092313 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9899825 # number of times the integer registers were written +system.cpu1.num_int_register_reads 53054873 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9892627 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1441 # number of times the floating registers were read system.cpu1.num_fp_register_writes 580 # number of times the floating registers were written -system.cpu1.num_mem_refs 3684662 # number of memory refs -system.cpu1.num_load_insts 2190856 # Number of load instructions -system.cpu1.num_store_insts 1493806 # Number of store instructions -system.cpu1.num_idle_cycles 548865377.428164 # Number of idle cycles -system.cpu1.num_busy_cycles 35837787.571836 # Number of busy cycles -system.cpu1.not_idle_fraction 0.061292 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.938708 # Percentage of idle cycles -system.cpu1.Branches 1448177 # Number of branches fetched +system.cpu1.num_mem_refs 3681879 # number of memory refs +system.cpu1.num_load_insts 2189240 # Number of load instructions +system.cpu1.num_store_insts 1492639 # Number of store instructions +system.cpu1.num_idle_cycles 548440957.661697 # Number of idle cycles +system.cpu1.num_busy_cycles 36326218.338303 # Number of busy cycles +system.cpu1.not_idle_fraction 0.062121 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.937879 # Percentage of idle cycles +system.cpu1.Branches 1446987 # Number of branches fetched +system.cpu1.op_class::No_OpClass 5386 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 6616988 64.14% 64.19% # Class of executed instruction +system.cpu1.op_class::IntMult 11601 0.11% 64.31% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 298 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::MemRead 2189240 21.22% 85.53% # Class of executed instruction +system.cpu1.op_class::MemWrite 1492639 14.47% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 10316152 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4782343 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3901882 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 223184 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3184465 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2528356 # Number of BTB hits +system.cpu2.branchPred.lookups 4788852 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3906949 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 223643 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3181584 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2530711 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 79.396571 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 413120 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21664 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 79.542486 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 413887 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21714 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1640,25 +1655,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10925413 # DTB read hits -system.cpu2.dtb.read_misses 23157 # DTB read misses -system.cpu2.dtb.write_hits 3347832 # DTB write hits -system.cpu2.dtb.write_misses 6500 # DTB write misses +system.cpu2.dtb.read_hits 10930564 # DTB read hits +system.cpu2.dtb.read_misses 23215 # DTB read misses +system.cpu2.dtb.write_hits 3350483 # DTB write hits +system.cpu2.dtb.write_misses 6482 # DTB write misses system.cpu2.dtb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 542 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 543 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2330 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 739 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.flush_entries 2337 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 733 # Number of TLB faults due to alignment restrictions system.cpu2.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 476 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10948570 # DTB read accesses -system.cpu2.dtb.write_accesses 3354332 # DTB write accesses +system.cpu2.dtb.perms_faults 461 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10953779 # DTB read accesses +system.cpu2.dtb.write_accesses 3356965 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14273245 # DTB hits -system.cpu2.dtb.misses 29657 # DTB misses -system.cpu2.dtb.accesses 14302902 # DTB accesses +system.cpu2.dtb.hits 14281047 # DTB hits +system.cpu2.dtb.misses 29697 # DTB misses +system.cpu2.dtb.accesses 14310744 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1680,159 +1695,159 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 4050371 # ITB inst hits -system.cpu2.itb.inst_misses 4655 # ITB inst misses +system.cpu2.itb.inst_hits 4054306 # ITB inst hits +system.cpu2.itb.inst_misses 4589 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 542 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 543 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1717 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1707 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 991 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 958 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4055026 # ITB inst accesses -system.cpu2.itb.hits 4050371 # DTB hits -system.cpu2.itb.misses 4655 # DTB misses -system.cpu2.itb.accesses 4055026 # DTB accesses -system.cpu2.numCycles 88306923 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4058895 # ITB inst accesses +system.cpu2.itb.hits 4054306 # DTB hits +system.cpu2.itb.misses 4589 # DTB misses +system.cpu2.itb.accesses 4058895 # DTB accesses +system.cpu2.numCycles 88316329 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9346989 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32490356 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4782343 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2941476 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6854845 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1758076 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 51100 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19188137 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 264 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 924 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 33833 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 718254 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 435 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4048944 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 289644 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2020 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37402774 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.043825 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.431125 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9351504 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32524106 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4788852 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2944598 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6861719 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1761177 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 50498 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19190819 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 265 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 860 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 33145 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 719724 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 402 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4052907 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 289738 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2002 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37419321 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.044533 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.431855 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30553136 81.69% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 385541 1.03% 82.72% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 516309 1.38% 84.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 819811 2.19% 86.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 629209 1.68% 87.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 341976 0.91% 88.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1043472 2.79% 91.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 229749 0.61% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2883571 7.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30562706 81.68% 81.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 385991 1.03% 82.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 516133 1.38% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 820285 2.19% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 630351 1.68% 87.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 341631 0.91% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1045289 2.79% 91.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 230176 0.62% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2886759 7.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37402774 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.054156 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367925 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9974482 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19754417 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6192036 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 324676 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1156258 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 608942 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 52938 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36945008 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 178323 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1156258 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10522715 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6823267 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11427905 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5953488 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1518249 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34855169 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 324878 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 884563 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 125 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37394312 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 160859531 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 148302897 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3365 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26531284 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10863027 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 285247 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 261616 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3319534 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6621271 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3899723 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 529692 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 779693 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32174765 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 504636 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34747602 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 55361 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7180763 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19089893 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 148627 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37402774 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.929011 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.590003 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37419321 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.054224 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.368268 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9979534 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19757337 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6196813 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 326068 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1158658 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 609699 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 52950 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36983425 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 178083 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1158658 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10528432 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6814826 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11435729 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5959486 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1521262 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34891179 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 96 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 325442 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 887620 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 163 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37432161 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 161024301 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 148452649 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3370 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26548024 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10884136 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 285664 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 261962 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3325772 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6628163 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3904378 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 525369 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 781342 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32207136 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 505175 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34773283 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 55288 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7195240 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19128466 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 148705 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37419321 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.929287 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.589860 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24715445 66.08% 66.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3980638 10.64% 76.72% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2310084 6.18% 82.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1974798 5.28% 88.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2777209 7.43% 95.60% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 968528 2.59% 98.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 496348 1.33% 99.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 144954 0.39% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34770 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24716493 66.05% 66.05% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3990546 10.66% 76.72% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2313548 6.18% 82.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1974351 5.28% 88.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2779950 7.43% 95.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 967650 2.59% 98.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 497474 1.33% 99.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 144778 0.39% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34531 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37402774 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37419321 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19778 1.30% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1391818 91.56% 92.86% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 108581 7.14% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19609 1.29% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1392955 91.52% 92.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 109452 7.19% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 8338 0.02% 0.02% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19786480 56.94% 56.97% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 28071 0.08% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 8340 0.02% 0.02% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19803061 56.95% 56.97% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 28127 0.08% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.05% # Type of FU issued @@ -1845,129 +1860,164 @@ system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.05% # Ty system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 5 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 3 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 5 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 3 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 384 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11408808 32.83% 89.88% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3515506 10.12% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 386 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11414599 32.83% 89.88% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3518761 10.12% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34747602 # Type of FU issued -system.cpu2.iq.rate 0.393487 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1520177 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.043749 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108495492 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39865371 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28048299 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7541 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3951 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3361 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36255412 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 4029 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 205816 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34773283 # Type of FU issued +system.cpu2.iq.rate 0.393736 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1522017 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.043770 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108565265 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39912731 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28072202 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7477 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 4009 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3345 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36282976 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3984 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206198 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1533232 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1949 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9487 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 562230 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1536367 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2104 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9509 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 563915 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5287398 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 344554 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5287425 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 344896 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1156258 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5195373 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 88422 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32761739 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 61550 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6621271 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3899723 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 362828 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 29785 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2577 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9487 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 107399 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89296 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 196695 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33832847 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11137918 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 914755 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1158658 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5187034 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 87972 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32794480 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 61964 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6628163 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3904378 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 362952 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 29501 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2651 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9509 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 107755 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89629 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 197384 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33857007 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11143266 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 916276 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82338 # number of nop insts executed -system.cpu2.iew.exec_refs 14620271 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3761250 # Number of branches executed -system.cpu2.iew.exec_stores 3482353 # Number of stores executed -system.cpu2.iew.exec_rate 0.383128 # Inst execution rate -system.cpu2.iew.wb_sent 33431998 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28051660 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16098716 # num instructions producing a value -system.cpu2.iew.wb_consumers 29087027 # num instructions consuming a value +system.cpu2.iew.exec_nop 82169 # number of nop insts executed +system.cpu2.iew.exec_refs 14628489 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3765120 # Number of branches executed +system.cpu2.iew.exec_stores 3485223 # Number of stores executed +system.cpu2.iew.exec_rate 0.383361 # Inst execution rate +system.cpu2.iew.wb_sent 33455826 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28075547 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16112995 # num instructions producing a value +system.cpu2.iew.wb_consumers 29113416 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.317661 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.553467 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.317898 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.553456 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7131660 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356009 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 171002 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 36246314 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.700075 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.737192 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7147493 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356470 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 171471 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 36260461 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.700277 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.736744 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27334959 75.41% 75.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4433375 12.23% 87.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1255912 3.46% 91.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 639801 1.77% 92.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 511761 1.41% 94.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 317445 0.88% 95.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 418775 1.16% 96.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 310656 0.86% 97.18% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1023630 2.82% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27338017 75.39% 75.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4438533 12.24% 87.63% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1258858 3.47% 91.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 640995 1.77% 92.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 514559 1.42% 94.29% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 318215 0.88% 95.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 418287 1.15% 96.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 309870 0.85% 97.18% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1023127 2.82% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 36246314 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20540563 # Number of instructions committed -system.cpu2.commit.committedOps 25375153 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 36260461 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20554943 # Number of instructions committed +system.cpu2.commit.committedOps 25392373 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8425532 # Number of memory references committed -system.cpu2.commit.loads 5088039 # Number of loads committed -system.cpu2.commit.membars 94081 # Number of memory barriers committed -system.cpu2.commit.branches 3238597 # Number of branches committed +system.cpu2.commit.refs 8432259 # Number of memory references committed +system.cpu2.commit.loads 5091796 # Number of loads committed +system.cpu2.commit.membars 94283 # Number of memory barriers committed +system.cpu2.commit.branches 3240263 # Number of branches committed system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22633154 # Number of committed integer instructions. -system.cpu2.commit.function_calls 295425 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1023630 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 22648524 # Number of committed integer instructions. +system.cpu2.commit.function_calls 295510 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 16933133 66.69% 66.69% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 26595 0.10% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 386 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5091796 20.05% 86.84% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3340463 13.16% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::total 25392373 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1023127 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 67208837 # The number of ROB reads -system.cpu2.rob.rob_writes 66213984 # The number of ROB writes -system.cpu2.timesIdled 359252 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 50904149 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3546216081 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20485207 # Number of Instructions Simulated -system.cpu2.committedOps 25319797 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 20485207 # Number of Instructions Simulated -system.cpu2.cpi 4.310765 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.310765 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.231977 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.231977 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 156999830 # number of integer regfile reads -system.cpu2.int_regfile_writes 29869338 # number of integer regfile writes -system.cpu2.fp_regfile_reads 46882 # number of floating regfile reads -system.cpu2.fp_regfile_writes 45194 # number of floating regfile writes -system.cpu2.misc_regfile_reads 67020139 # number of misc regfile reads -system.cpu2.misc_regfile_writes 296788 # number of misc regfile writes +system.cpu2.rob.rob_reads 67255841 # The number of ROB reads +system.cpu2.rob.rob_writes 66282532 # The number of ROB writes +system.cpu2.timesIdled 358696 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 50897008 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3546076715 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20499567 # Number of Instructions Simulated +system.cpu2.committedOps 25336997 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20499567 # Number of Instructions Simulated +system.cpu2.cpi 4.308205 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.308205 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.232115 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.232115 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 157113831 # number of integer regfile reads +system.cpu2.int_regfile_writes 29893796 # number of integer regfile writes +system.cpu2.fp_regfile_reads 46822 # number of floating regfile reads +system.cpu2.fp_regfile_writes 45178 # number of floating regfile writes +system.cpu2.misc_regfile_reads 67223937 # number of misc regfile reads +system.cpu2.misc_regfile_writes 297064 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1984,10 +2034,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1539425711000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1539425711000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1539425711000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1539425711000 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1535534030000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1535534030000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1535534030000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1535534030000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |