diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt | 4500 |
1 files changed, 2463 insertions, 2037 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 22877557e..d3cb3428e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,154 +1,165 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.817750 # Number of seconds simulated -sim_ticks 2817750443000 # Number of ticks simulated -final_tick 2817750443000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.823452 # Number of seconds simulated +sim_ticks 2823451688000 # Number of ticks simulated +final_tick 2823451688000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 301376 # Simulator instruction rate (inst/s) -host_op_rate 365951 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6727532391 # Simulator tick rate (ticks/s) -host_mem_usage 628096 # Number of bytes of host memory used -host_seconds 418.84 # Real time elapsed on the host -sim_insts 126227981 # Number of instructions simulated -sim_ops 153274395 # Number of ops (including micro ops) simulated +host_inst_rate 255579 # Simulator instruction rate (inst/s) +host_op_rate 310019 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5872606908 # Simulator tick rate (ticks/s) +host_mem_usage 578280 # Number of bytes of host memory used +host_seconds 480.78 # Real time elapsed on the host +sim_insts 122878254 # Number of instructions simulated +sim_ops 149051775 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 653732 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4510496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 124544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1058884 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 5696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 520896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 4080320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 538148 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3049124 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 121344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 892800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 373376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2020416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 4416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 355840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 3621312 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10955912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 653732 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 124544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 520896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1299172 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8264128 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8281652 # Number of bytes written to this memory +system.physmem.bytes_read::total 10980232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 538148 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 121344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 373376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 355840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1388708 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8266880 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory +system.physmem.bytes_written::total 8284404 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 18668 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 70995 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1946 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16546 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 89 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 8139 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 63755 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 16862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 48162 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1896 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 13950 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 33 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5834 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 31569 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 69 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 5560 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 56583 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180159 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 129127 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 133508 # Number of write requests responded to by this memory +system.physmem.num_reads::total 180539 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 129170 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory +system.physmem.num_writes::total 133551 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 232005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1600744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 44200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 375791 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 2021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 184862 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1448077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3888177 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 232005 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 44200 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 184862 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 461067 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2932881 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2939101 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2932881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 190599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1079928 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 42977 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 316209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 132241 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 715584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1564 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 126030 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 1282583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3888939 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 190599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 42977 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 132241 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 126030 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 491848 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2927934 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6207 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2934141 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2927934 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 232005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1606960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 44200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 375793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 2021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 184862 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1448077 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6827277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 90477 # Number of read requests accepted -system.physmem.writeReqs 65811 # Number of write requests accepted -system.physmem.readBursts 90477 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 65811 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5784832 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5696 # Total number of bytes read from write queue -system.physmem.bytesWritten 4210432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5790468 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4211784 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 89 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 23137 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5834 # Per bank write bursts -system.physmem.perBankRdBursts::1 5704 # Per bank write bursts -system.physmem.perBankRdBursts::2 5463 # Per bank write bursts -system.physmem.perBankRdBursts::3 5405 # Per bank write bursts -system.physmem.perBankRdBursts::4 5372 # Per bank write bursts -system.physmem.perBankRdBursts::5 5837 # Per bank write bursts -system.physmem.perBankRdBursts::6 6284 # Per bank write bursts -system.physmem.perBankRdBursts::7 6486 # Per bank write bursts -system.physmem.perBankRdBursts::8 6223 # Per bank write bursts -system.physmem.perBankRdBursts::9 6339 # Per bank write bursts -system.physmem.perBankRdBursts::10 5440 # Per bank write bursts -system.physmem.perBankRdBursts::11 5142 # Per bank write bursts -system.physmem.perBankRdBursts::12 5381 # Per bank write bursts -system.physmem.perBankRdBursts::13 5279 # Per bank write bursts -system.physmem.perBankRdBursts::14 4952 # Per bank write bursts -system.physmem.perBankRdBursts::15 5247 # Per bank write bursts -system.physmem.perBankWrBursts::0 4133 # Per bank write bursts -system.physmem.perBankWrBursts::1 3840 # Per bank write bursts -system.physmem.perBankWrBursts::2 4117 # Per bank write bursts -system.physmem.perBankWrBursts::3 4118 # Per bank write bursts -system.physmem.perBankWrBursts::4 3952 # Per bank write bursts -system.physmem.perBankWrBursts::5 4415 # Per bank write bursts -system.physmem.perBankWrBursts::6 4512 # Per bank write bursts -system.physmem.perBankWrBursts::7 4650 # Per bank write bursts -system.physmem.perBankWrBursts::8 4383 # Per bank write bursts -system.physmem.perBankWrBursts::9 4609 # Per bank write bursts -system.physmem.perBankWrBursts::10 3956 # Per bank write bursts -system.physmem.perBankWrBursts::11 3578 # Per bank write bursts -system.physmem.perBankWrBursts::12 4192 # Per bank write bursts -system.physmem.perBankWrBursts::13 4199 # Per bank write bursts -system.physmem.perBankWrBursts::14 3505 # Per bank write bursts -system.physmem.perBankWrBursts::15 3629 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 190599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1086134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 42977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 316209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 132241 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 715584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1564 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 126030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 1282583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6823080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 115495 # Number of read requests accepted +system.physmem.writeReqs 70322 # Number of write requests accepted +system.physmem.readBursts 115495 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 70322 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 7384064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue +system.physmem.bytesWritten 4499904 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 7391680 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4500608 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 16728 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 7953 # Per bank write bursts +system.physmem.perBankRdBursts::1 7174 # Per bank write bursts +system.physmem.perBankRdBursts::2 7640 # Per bank write bursts +system.physmem.perBankRdBursts::3 7504 # Per bank write bursts +system.physmem.perBankRdBursts::4 7829 # Per bank write bursts +system.physmem.perBankRdBursts::5 7364 # Per bank write bursts +system.physmem.perBankRdBursts::6 7486 # Per bank write bursts +system.physmem.perBankRdBursts::7 7817 # Per bank write bursts +system.physmem.perBankRdBursts::8 7059 # Per bank write bursts +system.physmem.perBankRdBursts::9 7674 # Per bank write bursts +system.physmem.perBankRdBursts::10 7129 # Per bank write bursts +system.physmem.perBankRdBursts::11 6171 # Per bank write bursts +system.physmem.perBankRdBursts::12 6502 # Per bank write bursts +system.physmem.perBankRdBursts::13 7092 # Per bank write bursts +system.physmem.perBankRdBursts::14 6785 # Per bank write bursts +system.physmem.perBankRdBursts::15 6197 # Per bank write bursts +system.physmem.perBankWrBursts::0 4825 # Per bank write bursts +system.physmem.perBankWrBursts::1 4280 # Per bank write bursts +system.physmem.perBankWrBursts::2 4678 # Per bank write bursts +system.physmem.perBankWrBursts::3 4464 # Per bank write bursts +system.physmem.perBankWrBursts::4 4644 # Per bank write bursts +system.physmem.perBankWrBursts::5 4512 # Per bank write bursts +system.physmem.perBankWrBursts::6 4517 # Per bank write bursts +system.physmem.perBankWrBursts::7 4571 # Per bank write bursts +system.physmem.perBankWrBursts::8 4335 # Per bank write bursts +system.physmem.perBankWrBursts::9 5017 # Per bank write bursts +system.physmem.perBankWrBursts::10 4515 # Per bank write bursts +system.physmem.perBankWrBursts::11 3667 # Per bank write bursts +system.physmem.perBankWrBursts::12 3925 # Per bank write bursts +system.physmem.perBankWrBursts::13 4539 # Per bank write bursts +system.physmem.perBankWrBursts::14 4104 # Per bank write bursts +system.physmem.perBankWrBursts::15 3718 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 2816184296500 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2821880880500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 1 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 90476 # Read request sizes (log2) +system.physmem.readPktSize::6 115495 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 2 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 65809 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 59474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 27494 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 70322 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 87424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 24888 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2511 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -175,175 +186,169 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 42 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 32481 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 307.722545 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 177.643491 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.464678 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12661 38.98% 38.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7717 23.76% 62.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 2982 9.18% 71.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1687 5.19% 77.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1406 4.33% 81.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 745 2.29% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 513 1.58% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 495 1.52% 86.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4275 13.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 32481 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3213 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.128852 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 487.877717 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 3211 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::26624-27647 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3213 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3213 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.475568 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.644293 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.368139 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 6 0.19% 0.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 1 0.03% 0.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.03% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 2 0.06% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 2703 84.13% 84.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 65 2.02% 86.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 109 3.39% 89.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 35 1.09% 90.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 33 1.03% 91.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 100 3.11% 95.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 9 0.28% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.09% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 4 0.12% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.25% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.06% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.03% 95.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 103 3.21% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.06% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.09% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 4 0.12% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.03% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.06% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.03% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.03% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.22% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.06% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.06% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3213 # Writes before turning the bus around for reads -system.physmem.totQLat 1180806250 # Total ticks spent queuing -system.physmem.totMemAccLat 2875581250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 451940000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13063.75 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::59 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39789 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.674709 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.286017 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.421202 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15628 39.28% 39.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9455 23.76% 63.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3888 9.77% 72.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2213 5.56% 78.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1604 4.03% 82.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 939 2.36% 84.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 730 1.83% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 629 1.58% 88.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4703 11.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39789 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3745 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.804539 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 621.520984 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 3744 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::36864-38911 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3745 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3745 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.774633 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.746790 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 9.292289 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 6 0.16% 0.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 3 0.08% 0.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.03% 0.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 5 0.13% 0.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3351 89.48% 89.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 51 1.36% 91.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 76 2.03% 93.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 45 1.20% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 29 0.77% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 68 1.82% 97.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 12 0.32% 97.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.27% 97.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 5 0.13% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.11% 97.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.08% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.03% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 57 1.52% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.11% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.05% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 5 0.13% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 3 0.08% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3745 # Writes before turning the bus around for reads +system.physmem.totQLat 1373444750 # Total ticks spent queuing +system.physmem.totMemAccLat 3536744750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 576880000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11904.08 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31813.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.05 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.49 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.05 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.49 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30654.08 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.62 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.62 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 6.07 # Average write queue length when enqueuing -system.physmem.readRowHits 74627 # Number of row buffer hits during reads -system.physmem.writeRowHits 49067 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.56 # Row buffer hit rate for writes -system.physmem.avgGap 18019197.23 # Average gap between requests -system.physmem.pageHitRate 79.19 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 128285640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 69757875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 361803000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 218615760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 178850889360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 68913339435 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1610809853250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1859352544320 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.527151 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2632589257000 # Time in different power states -system.physmem_0.memoryStateTime::REF 91437060000 # Time in different power states +system.physmem.avgWrQLen 28.79 # Average write queue length when enqueuing +system.physmem.readRowHits 95547 # Number of row buffer hits during reads +system.physmem.writeRowHits 50351 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.60 # Row buffer hit rate for writes +system.physmem.avgGap 15186343.99 # Average gap between requests +system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 160211520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 87256125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 473982600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 236461680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 179691539040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 72230311935 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1621102009500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1873981772400 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.506366 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2640519481750 # Time in different power states +system.physmem_0.memoryStateTime::REF 91866840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14382937750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 18811132750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 117270720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 63772500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 343207800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 207690480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 178850889360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68192676180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1609047407250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1856822914290 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.575499 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2633644277500 # Time in different power states -system.physmem_1.memoryStateTime::REF 91437060000 # Time in different power states +system.physmem_1.actEnergy 140593320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76547625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 425950200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 219153600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 179691539040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 71075732760 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1618530580500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1870160097045 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.565551 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2642231800750 # Time in different power states +system.physmem_1.memoryStateTime::REF 91866840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 13328364750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17099623500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -393,48 +398,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 5725 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5725 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 5725 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5725 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5725 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 166068997868 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.475665 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.499407 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 87075845118 52.43% 52.43% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 78993152750 47.57% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 166068997868 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3165 67.41% 67.41% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1530 32.59% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4695 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5725 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 5044 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5044 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5044 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5044 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5044 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 56727881876 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.269097 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -15265283124 -26.91% -26.91% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 71993165000 126.91% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 56727881876 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 2868 68.19% 68.19% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1338 31.81% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4206 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5044 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5725 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4695 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5044 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4206 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4695 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 10420 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4206 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 9250 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 14454415 # DTB read hits -system.cpu0.dtb.read_misses 4808 # DTB read misses -system.cpu0.dtb.write_hits 11087884 # DTB write hits -system.cpu0.dtb.write_misses 917 # DTB write misses -system.cpu0.dtb.flush_tlb 190 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 12055693 # DTB read hits +system.cpu0.dtb.read_misses 4324 # DTB read misses +system.cpu0.dtb.write_hits 9053768 # DTB write hits +system.cpu0.dtb.write_misses 720 # DTB write misses +system.cpu0.dtb.flush_tlb 172 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 369 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3341 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2916 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 964 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 817 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 218 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14459223 # DTB read accesses -system.cpu0.dtb.write_accesses 11088801 # DTB write accesses +system.cpu0.dtb.perms_faults 183 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12060017 # DTB read accesses +system.cpu0.dtb.write_accesses 9054488 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 25542299 # DTB hits -system.cpu0.dtb.misses 5725 # DTB misses -system.cpu0.dtb.accesses 25548024 # DTB accesses +system.cpu0.dtb.hits 21109461 # DTB hits +system.cpu0.dtb.misses 5044 # DTB misses +system.cpu0.dtb.accesses 21114505 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -464,542 +468,650 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 2784 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2784 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2784 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2784 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2784 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 166068997868 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.475665 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.499407 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 87075735118 52.43% 52.43% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 78993262750 47.57% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 166068997868 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1521 75.19% 75.19% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 502 24.81% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2023 # Table walker page sizes translated +system.cpu0.itb.walker.walks 2455 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2455 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2455 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2455 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2455 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 56727881876 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.269099 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -15265389124 -26.91% -26.91% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 71993271000 126.91% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 56727881876 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1346 75.11% 75.11% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 446 24.89% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1792 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2784 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2784 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2455 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2455 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2023 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2023 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4807 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 67912569 # ITB inst hits -system.cpu0.itb.inst_misses 2784 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1792 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1792 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4247 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 56652194 # ITB inst hits +system.cpu0.itb.inst_misses 2455 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 190 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 172 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 369 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2012 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1791 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 67915353 # ITB inst accesses -system.cpu0.itb.hits 67912569 # DTB hits -system.cpu0.itb.misses 2784 # DTB misses -system.cpu0.itb.accesses 67915353 # DTB accesses -system.cpu0.numCycles 82537208 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 56654649 # ITB inst accesses +system.cpu0.itb.hits 56652194 # DTB hits +system.cpu0.itb.misses 2455 # DTB misses +system.cpu0.itb.accesses 56654649 # DTB accesses +system.cpu0.numCycles 68394939 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 66134007 # Number of instructions committed -system.cpu0.committedOps 80648826 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 70905199 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5550 # Number of float alu accesses -system.cpu0.num_func_calls 7283350 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 8754499 # number of instructions that are conditional controls -system.cpu0.num_int_insts 70905199 # number of integer instructions -system.cpu0.num_fp_insts 5550 # number of float instructions -system.cpu0.num_int_register_reads 131519590 # number of times the integer registers were read -system.cpu0.num_int_register_writes 49325288 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4326 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1228 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 245878640 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 29383702 # number of times the CC registers were written -system.cpu0.num_mem_refs 26210186 # number of memory refs -system.cpu0.num_load_insts 14630349 # Number of load instructions -system.cpu0.num_store_insts 11579837 # Number of store instructions -system.cpu0.num_idle_cycles 77938505.493998 # Number of idle cycles -system.cpu0.num_busy_cycles 4598702.506002 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055717 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944283 # Percentage of idle cycles -system.cpu0.Branches 16436363 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2195 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 55791644 67.98% 67.99% # Class of executed instruction -system.cpu0.op_class::IntMult 58049 0.07% 68.06% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4498 0.01% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::MemRead 14630349 17.83% 85.89% # Class of executed instruction -system.cpu0.op_class::MemWrite 11579837 14.11% 100.00% # Class of executed instruction +system.cpu0.committedInsts 55195414 # Number of instructions committed +system.cpu0.committedOps 66855615 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 58673965 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4653 # Number of float alu accesses +system.cpu0.num_func_calls 5764786 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7314754 # number of instructions that are conditional controls +system.cpu0.num_int_insts 58673965 # number of integer instructions +system.cpu0.num_fp_insts 4653 # number of float instructions +system.cpu0.num_int_register_reads 108155823 # number of times the integer registers were read +system.cpu0.num_int_register_writes 40952580 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3548 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1106 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 203459813 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 24562816 # number of times the CC registers were written +system.cpu0.num_mem_refs 21693456 # number of memory refs +system.cpu0.num_load_insts 12204686 # Number of load instructions +system.cpu0.num_store_insts 9488770 # Number of store instructions +system.cpu0.num_idle_cycles 64604124.391568 # Number of idle cycles +system.cpu0.num_busy_cycles 3790814.608432 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055425 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944575 # Percentage of idle cycles +system.cpu0.Branches 13394268 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2179 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 46192687 67.99% 67.99% # Class of executed instruction +system.cpu0.op_class::IntMult 50556 0.07% 68.07% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3909 0.01% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::MemRead 12204686 17.96% 86.03% # Class of executed instruction +system.cpu0.op_class::MemWrite 9488770 13.97% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 82066572 # Class of executed instruction +system.cpu0.op_class::total 67942787 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3052 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 831549 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997019 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 47051301 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 832061 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 56.547899 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 3087 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 832854 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.996678 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 45941048 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 833366 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.127097 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.952083 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.619501 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.425436 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.949125 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032460 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018409 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.291122 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.712491 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.320971 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 14.672094 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938069 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.022876 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010393 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.028656 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 198549695 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 198549695 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 13772496 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 4439535 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 8487535 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 26699566 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10693159 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3177520 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 5185286 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 19055965 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 188127 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 61521 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 132231 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 381879 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234713 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 80499 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 136030 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 451242 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236172 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 82928 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 140692 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459792 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 24465655 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 7617055 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 13672821 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 45755531 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 24653782 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 7678576 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 13805052 # number of overall hits -system.cpu0.dcache.overall_hits::total 46137410 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 187736 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 59438 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 321333 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 568507 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 147259 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 35061 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 1471187 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1653507 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54734 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 20499 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 66219 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 141452 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4535 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3220 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 9718 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 17473 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 16 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 334995 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 94499 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1792520 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2222014 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 389729 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 114998 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1858739 # number of overall misses -system.cpu0.dcache.overall_misses::total 2363466 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 910326500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4892855500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5803182000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1430484500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 70357084944 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 71787569444 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 43754500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 128953000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 172707500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 313500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 313500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 2340811000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 75249940444 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 77590751444 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 2340811000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 75249940444 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 77590751444 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 13960232 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 4498973 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 8808868 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 27268073 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 10840418 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 3212581 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 6656473 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 20709472 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 242861 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 82020 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 198450 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 523331 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239248 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 83719 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 145748 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 468715 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236175 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 82928 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 140708 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 459811 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 24800650 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 7711554 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 15465341 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 47977545 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 25043511 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 7793574 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 15663791 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 48500876 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013448 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013211 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.036478 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.020849 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013584 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.010914 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.221016 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.079843 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.225372 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.249927 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.333681 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.270292 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018955 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.038462 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.066677 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.037279 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000013 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000114 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000041 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013508 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.012254 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115906 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.046314 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.015562 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.014755 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.118665 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.048730 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15315.564117 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15226.744530 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10207.758216 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40799.877357 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 47823.346008 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43415.340512 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13588.354037 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13269.499897 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9884.249986 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 19593.750000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16500 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24770.748897 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41979.972577 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34919.110070 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20355.232265 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 40484.403913 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32829.222610 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 384529 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 27036 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 18388 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 711 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 20.911953 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 38.025316 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 193272549 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 193272549 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11424997 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 3591571 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4056566 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu3.data 6785067 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25858201 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 8716576 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 2652345 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 3172859 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu3.data 4239682 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18781462 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177203 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 53725 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 68062 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu3.data 87970 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 386960 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 215942 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 74003 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 70208 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 90799 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 450952 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 216982 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 75596 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 72811 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu3.data 95206 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 460595 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 20141573 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 6243916 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 7229425 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu3.data 11024749 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 44639663 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 20318776 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 6297641 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 7297487 # number of overall hits +system.cpu0.dcache.overall_hits::cpu3.data 11112719 # number of overall hits +system.cpu0.dcache.overall_hits::total 45026623 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 170763 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 51416 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 83405 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu3.data 222894 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 528478 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 111802 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 33494 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 105638 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu3.data 1237063 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1487997 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54554 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 16796 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 18757 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu3.data 47065 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 137172 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 3717 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2279 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3522 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 8436 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 17954 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu3.data 17 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 282565 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 84910 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 189043 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu3.data 1459957 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2016475 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 337119 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 101706 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 207800 # number of overall misses +system.cpu0.dcache.overall_misses::cpu3.data 1507022 # number of overall misses +system.cpu0.dcache.overall_misses::total 2153647 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 824607500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 1194074500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 3363398500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5382080500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1236116500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 5104811996 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 62105608982 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 68446537478 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 27718500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 44847000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 123322000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 195887500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 465000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 465000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 2060724000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 6298886496 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu3.data 65469007482 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 73828617978 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 2060724000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 6298886496 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu3.data 65469007482 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 73828617978 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 11595760 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 3642987 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4139971 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu3.data 7007961 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 26386679 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 8828378 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 2685839 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 3278497 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu3.data 5476745 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 20269459 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 231757 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 70521 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 86819 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 135035 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 524132 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 219659 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 76282 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 73730 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 99235 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 468906 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 216983 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 75596 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 72811 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 95223 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 460613 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 20424138 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 6328826 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7418468 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu3.data 12484706 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 46656138 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 20655895 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 6399347 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7505287 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu3.data 12619741 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 47180270 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.014726 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.014114 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.020146 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.031806 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.020028 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012664 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.012471 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.032221 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.225876 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.073411 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.235393 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.238170 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.216047 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.348539 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.261713 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016922 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.029876 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.047769 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.085010 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.038289 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000005 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000179 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000039 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013835 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013416 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.025483 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu3.data 0.116940 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.043220 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.016321 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015893 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.027687 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu3.data 0.119418 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.045647 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16037.955111 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14316.581740 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15089.677156 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10184.114571 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36905.609960 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48323.633503 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 50204.079325 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45999.109862 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12162.571303 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 12733.390119 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14618.539592 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10910.521332 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 27352.941176 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25833.333333 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24269.508892 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 33319.861069 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 44843.106668 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36612.711776 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20261.577488 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30312.254552 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 43442.635530 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34280.742377 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 334085 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 49646 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 14251 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 808 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.442916 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 61.443069 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 690633 # number of writebacks -system.cpu0.dcache.writebacks::total 690633 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 93 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 159890 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 159983 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 1354576 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1354576 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1940 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 6930 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 8870 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 93 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 1514466 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1514559 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 93 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 1514466 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1514559 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 59345 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 161443 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 220788 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 35061 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 116611 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 151672 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 20123 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 43935 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 64058 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1280 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 2788 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4068 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 16 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 94406 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 278054 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 372460 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 114529 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 321989 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 436518 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 5882 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 8601 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14483 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 4590 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 6802 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 11392 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 10472 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 15403 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 25875 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 849299000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2242226500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3091525500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1395423500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5679297435 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7074720935 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 276712000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 590115500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 866827500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 20457500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 37492500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57950000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 297500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 297500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2244722500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7921523935 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10166246435 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2521434500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8511639435 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11033073935 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1056963000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1715153500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2772116500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 811573000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1342286000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2153859000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1868536000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3057439500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4925975500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013191 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018327 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008097 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.010914 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017518 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007324 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.245343 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.221391 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.122404 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.015289 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019129 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.008679 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000114 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000035 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012242 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017979 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.007763 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014695 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020556 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.009000 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14311.214087 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13888.657297 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14002.235176 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39799.877357 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 48702.930555 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46644.871400 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13751.031158 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13431.557983 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13531.916388 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15982.421875 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13447.812052 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14245.329400 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 18593.750000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18593.750000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23777.328771 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 28489.156549 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27294.867731 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22015.685983 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26434.565886 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25275.186670 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179694.491670 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 199413.265899 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191404.853967 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176813.289760 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 197336.959718 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189067.679073 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 178431.627196 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 198496.364345 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190375.864734 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 691721 # number of writebacks +system.cpu0.dcache.writebacks::total 691721 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 98 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 8313 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 110368 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 118779 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 48697 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 1139929 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1188626 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1601 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 2421 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 5282 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 9304 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 98 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 57010 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu3.data 1250297 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1307405 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 98 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 57010 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu3.data 1250297 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1307405 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 51318 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 75092 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 112526 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 238936 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 33494 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 56941 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 97134 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 187569 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 16471 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 15216 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 32231 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 63918 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 678 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 1101 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 3154 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4933 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 17 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 84812 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 132033 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu3.data 209660 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 426505 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 101283 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 147249 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu3.data 241891 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 490423 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 4113 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 6742 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 7559 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18414 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3215 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 5150 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6001 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 14366 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 7328 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 11892 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 13560 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32780 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 771744500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1005172000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1614519000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3391435500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1202622500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2680384000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 4914737428 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8797743928 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 211413000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 208273000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 499697000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 919383000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8610500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 15891500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 52341000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76843000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 448000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 448000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1974367000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3685556000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 6529256428 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12189179428 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2185780000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3893829000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 7028953428 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13108562428 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 709683000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1313422000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1530005000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3553110000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 546320500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 978935500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1200341982 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2725597982 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1256003500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2292357500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2730346982 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6278707982 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014087 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018138 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016057 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009055 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012471 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017368 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017736 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009254 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.233562 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.175261 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.238686 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.121950 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.008888 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.014933 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.031783 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010520 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000179 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000037 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013401 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017798 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.016793 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.009141 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.015827 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019619 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019168 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.010395 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15038.475778 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13385.873329 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14347.964026 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14193.907574 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35905.609960 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 47073.005392 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50597.498590 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46904.040263 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12835.468399 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13687.762881 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15503.614533 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14383.788604 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12699.852507 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 14433.696639 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16595.117311 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15577.336307 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 26352.941176 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26352.941176 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23279.335471 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27913.900313 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 31142.117848 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28579.218129 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21580.916837 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26443.840026 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29058.350364 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26729.093921 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172546.316557 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 194811.925245 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202408.387353 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192956.989247 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169928.615863 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 190084.563107 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 200023.659723 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189725.600863 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171397.857533 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 192764.673730 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 201353.022271 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191540.817023 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1799604 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.542681 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 100855692 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1800115 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 56.027360 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10987259500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 478.414957 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 20.920922 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 12.206802 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.934404 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.040861 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.023841 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999107 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 157 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 104509492 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 104509492 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 67050712 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 21807219 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 11997761 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 100855692 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 67050712 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 21807219 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 11997761 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 100855692 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 67050712 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 21807219 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 11997761 # number of overall hits -system.cpu0.icache.overall_hits::total 100855692 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 863880 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 249894 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 739869 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1853643 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 863880 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 249894 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 739869 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1853643 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 863880 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 249894 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 739869 # number of overall misses -system.cpu0.icache.overall_misses::total 1853643 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 3388286000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 10019746984 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13408032984 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 3388286000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 10019746984 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13408032984 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 3388286000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 10019746984 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13408032984 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 67914592 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 22057113 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 12737630 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 102709335 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 67914592 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 22057113 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 12737630 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 102709335 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 67914592 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 22057113 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 12737630 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 102709335 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012720 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011329 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.058085 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.018047 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012720 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011329 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.058085 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.018047 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012720 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011329 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.058085 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.018047 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13558.892971 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13542.596033 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7233.341579 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13558.892971 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13542.596033 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7233.341579 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13558.892971 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13542.596033 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7233.341579 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 7691 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 1978248 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.476093 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 92919349 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1978760 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 46.958372 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 12310007500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 437.578218 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 12.969081 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 27.366613 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu3.inst 33.562181 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.854645 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.025330 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.053450 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu3.inst 0.065551 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998977 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 253 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 96919206 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 96919206 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 55909224 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 17523727 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 10076714 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu3.inst 9409684 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 92919349 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 55909224 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 17523727 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 10076714 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu3.inst 9409684 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 92919349 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 55909224 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 17523727 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 10076714 # number of overall hits +system.cpu0.icache.overall_hits::cpu3.inst 9409684 # number of overall hits +system.cpu0.icache.overall_hits::total 92919349 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 744762 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 210607 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 478701 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu3.inst 586999 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2021069 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 744762 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 210607 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 478701 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu3.inst 586999 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 2021069 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 744762 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 210607 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 478701 # number of overall misses +system.cpu0.icache.overall_misses::cpu3.inst 586999 # number of overall misses +system.cpu0.icache.overall_misses::total 2021069 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2873833000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6639070000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 7864379492 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 17377282492 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2873833000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 6639070000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu3.inst 7864379492 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 17377282492 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2873833000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 6639070000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu3.inst 7864379492 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 17377282492 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 56653986 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 17734334 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 10555415 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu3.inst 9996683 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 94940418 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 56653986 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 17734334 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 10555415 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu3.inst 9996683 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 94940418 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 56653986 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 17734334 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 10555415 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu3.inst 9996683 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 94940418 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013146 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011876 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.045351 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.058719 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.021288 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013146 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011876 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.045351 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu3.inst 0.058719 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.021288 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013146 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011876 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.045351 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu3.inst 0.058719 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.021288 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13645.477121 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13868.928621 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13397.602878 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8598.064931 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13645.477121 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13868.928621 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13397.602878 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8598.064931 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13645.477121 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13868.928621 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13397.602878 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8598.064931 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3152 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 418 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 204 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.399522 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.450980 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 53485 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 53485 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 53485 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 53485 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 53485 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 53485 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 249894 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 686384 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 936278 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 249894 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 686384 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 936278 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 249894 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 686384 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 936278 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 3138392000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8843257984 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11981649984 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 3138392000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8843257984 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11981649984 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 3138392000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8843257984 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11981649984 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011329 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.053886 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009116 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011329 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.053886 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009116 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011329 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.053886 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009116 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12558.892971 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12883.834681 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12797.107252 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12558.892971 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12883.834681 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12797.107252 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12558.892971 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12883.834681 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12797.107252 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 42281 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 42281 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu3.inst 42281 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 42281 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu3.inst 42281 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 42281 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 210607 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 478701 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 544718 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1234026 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 210607 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 478701 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu3.inst 544718 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1234026 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 210607 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 478701 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu3.inst 544718 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1234026 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2663226000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6160369000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 6946186993 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 15769781993 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2663226000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6160369000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 6946186993 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 15769781993 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2663226000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6160369000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 6946186993 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 15769781993 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045351 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.054490 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012998 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.045351 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.054490 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.012998 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045351 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.054490 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.012998 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12645.477121 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12868.928621 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12751.895463 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12779.132687 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12645.477121 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12868.928621 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12751.895463 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12779.132687 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12645.477121 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12868.928621 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12751.895463 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12779.132687 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1030,56 +1142,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 1911 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 1911 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 628 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1283 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 1911 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 1911 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 1911 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1624 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12817.118227 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11165.640992 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6539.405372 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 417 25.68% 25.68% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 849 52.28% 77.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 357 21.98% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1624 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1004 61.82% 61.82% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 620 38.18% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1624 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1911 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 1892 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 1892 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 543 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1348 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 1891 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 1891 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 1891 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1530 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11241.830065 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9576.039480 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6337.675963 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 0.98% 0.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-6143 582 38.04% 39.02% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::10240-12287 519 33.92% 72.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-14335 132 8.63% 81.57% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::14336-16383 18 1.18% 82.75% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::22528-24575 264 17.25% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1530 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1775778416 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.436843 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.495995 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000042500 56.32% 56.32% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 775735916 43.68% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1775778416 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 996 65.14% 65.14% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 533 34.86% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1529 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1892 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1911 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1624 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1892 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1529 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1624 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 3535 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1529 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3421 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4670594 # DTB read hits -system.cpu1.dtb.read_misses 1655 # DTB read misses -system.cpu1.dtb.write_hits 3300164 # DTB write hits -system.cpu1.dtb.write_misses 256 # DTB write misses -system.cpu1.dtb.flush_tlb 167 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 123 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 3793903 # DTB read hits +system.cpu1.dtb.read_misses 1653 # DTB read misses +system.cpu1.dtb.write_hits 2764720 # DTB write hits +system.cpu1.dtb.write_misses 239 # DTB write misses +system.cpu1.dtb.flush_tlb 152 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1332 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1225 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 239 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 65 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4672249 # DTB read accesses -system.cpu1.dtb.write_accesses 3300420 # DTB write accesses +system.cpu1.dtb.perms_faults 70 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3795556 # DTB read accesses +system.cpu1.dtb.write_accesses 2764959 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7970758 # DTB hits -system.cpu1.dtb.misses 1911 # DTB misses -system.cpu1.dtb.accesses 7972669 # DTB accesses +system.cpu1.dtb.hits 6558623 # DTB hits +system.cpu1.dtb.misses 1892 # DTB misses +system.cpu1.dtb.accesses 6560515 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1109,128 +1227,128 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 935 # Table walker walks requested -system.cpu1.itb.walker.walksShort 935 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 229 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 706 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 935 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 935 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 935 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 723 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 13501.383126 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11823.554991 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6487.735992 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 166 22.96% 22.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 228 31.54% 54.50% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 139 19.23% 73.72% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 7 0.97% 74.69% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 183 25.31% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 723 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 494 68.33% 68.33% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 229 31.67% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 723 # Table walker page sizes translated +system.cpu1.itb.walker.walks 978 # Table walker walks requested +system.cpu1.itb.walker.walksShort 978 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 197 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 781 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 978 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 978 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 978 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 708 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11807.909605 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9972.994087 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6711.668965 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 268 37.85% 37.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 195 27.54% 65.40% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 96 13.56% 78.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 3 0.42% 79.38% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 146 20.62% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 708 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1000001500 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000001500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000001500 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 511 72.18% 72.18% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 197 27.82% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 708 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 935 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 935 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 978 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 978 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 723 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 723 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 1658 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 22057113 # ITB inst hits -system.cpu1.itb.inst_misses 935 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 708 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 708 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1686 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 17734334 # ITB inst hits +system.cpu1.itb.inst_misses 978 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 167 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 123 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 152 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 783 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 735 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 22058048 # ITB inst accesses -system.cpu1.itb.hits 22057113 # DTB hits -system.cpu1.itb.misses 935 # DTB misses -system.cpu1.itb.accesses 22058048 # DTB accesses -system.cpu1.numCycles 158011873 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 17735312 # ITB inst accesses +system.cpu1.itb.hits 17734334 # DTB hits +system.cpu1.itb.misses 978 # DTB misses +system.cpu1.itb.accesses 17735312 # DTB accesses +system.cpu1.numCycles 143538852 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 21342205 # Number of instructions committed -system.cpu1.committedOps 25582989 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22730381 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1657 # Number of float alu accesses -system.cpu1.num_func_calls 2417962 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2740367 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22730381 # number of integer instructions -system.cpu1.num_fp_insts 1657 # number of float instructions -system.cpu1.num_int_register_reads 41903720 # number of times the integer registers were read -system.cpu1.num_int_register_writes 15946634 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1337 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 320 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 92962985 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 9452948 # number of times the CC registers were written -system.cpu1.num_mem_refs 8180627 # number of memory refs -system.cpu1.num_load_insts 4716601 # Number of load instructions -system.cpu1.num_store_insts 3464026 # Number of store instructions -system.cpu1.num_idle_cycles 151538894.643419 # Number of idle cycles -system.cpu1.num_busy_cycles 6472978.356581 # Number of busy cycles -system.cpu1.not_idle_fraction 0.040965 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.959035 # Percentage of idle cycles -system.cpu1.Branches 5307887 # Number of branches fetched -system.cpu1.op_class::No_OpClass 38 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 18096671 68.81% 68.81% # Class of executed instruction -system.cpu1.op_class::IntMult 19327 0.07% 68.89% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1187 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.89% # Class of executed instruction -system.cpu1.op_class::MemRead 4716601 17.94% 86.83% # Class of executed instruction -system.cpu1.op_class::MemWrite 3464026 13.17% 100.00% # Class of executed instruction +system.cpu1.committedInsts 17131755 # Number of instructions committed +system.cpu1.committedOps 20672467 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 18427801 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1229 # Number of float alu accesses +system.cpu1.num_func_calls 2005849 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2182476 # number of instructions that are conditional controls +system.cpu1.num_int_insts 18427801 # number of integer instructions +system.cpu1.num_fp_insts 1229 # number of float instructions +system.cpu1.num_int_register_reads 34218314 # number of times the integer registers were read +system.cpu1.num_int_register_writes 12924255 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 840 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 390 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 75293665 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 7369592 # number of times the CC registers were written +system.cpu1.num_mem_refs 6757135 # number of memory refs +system.cpu1.num_load_insts 3837451 # Number of load instructions +system.cpu1.num_store_insts 2919684 # Number of store instructions +system.cpu1.num_idle_cycles 136561451.428475 # Number of idle cycles +system.cpu1.num_busy_cycles 6977400.571525 # Number of busy cycles +system.cpu1.not_idle_fraction 0.048610 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.951390 # Percentage of idle cycles +system.cpu1.Branches 4295209 # Number of branches fetched +system.cpu1.op_class::No_OpClass 47 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 14510863 68.17% 68.17% # Class of executed instruction +system.cpu1.op_class::IntMult 16280 0.08% 68.25% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 958 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.25% # Class of executed instruction +system.cpu1.op_class::MemRead 3837451 18.03% 86.28% # Class of executed instruction +system.cpu1.op_class::MemWrite 2919684 13.72% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 26297850 # Class of executed instruction +system.cpu1.op_class::total 21285283 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 17205761 # Number of BP lookups -system.cpu2.branchPred.condPredicted 9385761 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 401350 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 10751395 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 8022189 # Number of BTB hits +system.cpu2.branchPred.lookups 5610171 # Number of BP lookups +system.cpu2.branchPred.condPredicted 2857915 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 501995 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3283896 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2333083 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 74.615331 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 4025562 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21207 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 71.046190 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 1583798 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 327364 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1260,89 +1378,56 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 43873 # Table walker walks requested -system.cpu2.dtb.walker.walksShort 43873 # Table walker walks initiated with short descriptors -system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 13923 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 10993 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksSquashedBefore 18957 # Table walks squashed before starting -system.cpu2.dtb.walker.walkWaitTime::samples 24916 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::mean 571.078825 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::stdev 3693.718026 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0-16383 24688 99.08% 99.08% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::16384-32767 176 0.71% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::32768-49151 30 0.12% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::49152-65535 9 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::65536-81919 9 0.04% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::98304-114687 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::114688-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::131072-147455 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 24916 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 9164 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 13158.828023 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 10878.635204 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 7680.126787 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-8191 2739 29.89% 29.89% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::8192-16383 3883 42.37% 72.26% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::16384-24575 2316 25.27% 97.53% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::24576-32767 72 0.79% 98.32% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::32768-40959 91 0.99% 99.31% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::40960-49151 60 0.65% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::81920-90111 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 9164 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 60380803468 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::mean 0.564289 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::stdev 0.516018 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0-1 60322207968 99.90% 99.90% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::2-3 41747500 0.07% 99.97% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::4-5 8670500 0.01% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::6-7 3297500 0.01% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::8-9 1514000 0.00% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::10-11 972000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::12-13 454500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::14-15 1161000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::16-17 173500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::18-19 164000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::20-21 123500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::22-23 89000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::24-25 134500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::26-27 15500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::28-29 5500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::30-31 73000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 60380803468 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 2766 73.10% 73.10% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::1M 1018 26.90% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 3784 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 43873 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walks 12445 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 12445 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7726 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4719 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 12445 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 12445 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 12445 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 2100 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 12636.428571 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 10856.238054 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 6881.912938 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-8191 609 29.00% 29.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1011 48.14% 77.14% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::16384-24575 478 22.76% 99.90% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::81920-90111 2 0.10% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 2100 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 2000071000 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0 2000071000 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 2000071000 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 1328 63.24% 63.24% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 772 36.76% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 2100 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12445 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 43873 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 3784 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12445 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2100 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 3784 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 47657 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2100 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 14545 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 9620013 # DTB read hits -system.cpu2.dtb.read_misses 37991 # DTB read misses -system.cpu2.dtb.write_hits 7129568 # DTB write hits -system.cpu2.dtb.write_misses 5882 # DTB write misses -system.cpu2.dtb.flush_tlb 179 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 348 # Number of times TLB was flushed by MVA +system.cpu2.dtb.read_hits 4343761 # DTB read hits +system.cpu2.dtb.read_misses 11112 # DTB read misses +system.cpu2.dtb.write_hits 3378115 # DTB write hits +system.cpu2.dtb.write_misses 1333 # DTB write misses +system.cpu2.dtb.flush_tlb 152 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 166 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2312 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 478 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 974 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 1535 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 222 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 301 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 415 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 9658004 # DTB read accesses -system.cpu2.dtb.write_accesses 7135450 # DTB write accesses +system.cpu2.dtb.perms_faults 123 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 4354873 # DTB read accesses +system.cpu2.dtb.write_accesses 3379448 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 16749581 # DTB hits -system.cpu2.dtb.misses 43873 # DTB misses -system.cpu2.dtb.accesses 16793454 # DTB accesses +system.cpu2.dtb.hits 7721876 # DTB hits +system.cpu2.dtb.misses 12445 # DTB misses +system.cpu2.dtb.accesses 7734321 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1372,392 +1457,601 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 5947 # Table walker walks requested -system.cpu2.itb.walker.walksShort 5947 # Table walker walks initiated with short descriptors -system.cpu2.itb.walker.walksShortTerminationLevel::Level1 1786 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksShortTerminationLevel::Level2 4054 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksSquashedBefore 107 # Table walks squashed before starting -system.cpu2.itb.walker.walkWaitTime::samples 5840 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::mean 1732.534247 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::stdev 7455.028366 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0-8191 5455 93.41% 93.41% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::8192-16383 164 2.81% 96.22% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::16384-24575 114 1.95% 98.17% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::24576-32767 45 0.77% 98.94% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::32768-40959 19 0.33% 99.26% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::40960-49151 8 0.14% 99.40% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::49152-57343 13 0.22% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::57344-65535 3 0.05% 99.67% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::65536-73727 6 0.10% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::73728-81919 3 0.05% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::81920-90111 5 0.09% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::90112-98303 1 0.02% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::98304-106495 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::106496-114687 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::122880-131071 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 5840 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 1844 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 13438.177874 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 11167.697103 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 8164.078124 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-8191 568 30.80% 30.80% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::8192-16383 796 43.17% 73.97% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::16384-24575 418 22.67% 96.64% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::24576-32767 27 1.46% 98.10% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-40959 12 0.65% 98.75% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::40960-49151 15 0.81% 99.57% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::49152-57343 4 0.22% 99.78% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::57344-65535 3 0.16% 99.95% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::65536-73727 1 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 1844 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 13135820712 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::mean 0.816052 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::stdev 0.388899 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 2421306500 18.43% 18.43% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::1 10711149212 81.54% 99.97% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::2 2311000 0.02% 99.99% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::3 636500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::4 285000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::5 97500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::6 35000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 13135820712 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 1342 77.26% 77.26% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::1M 395 22.74% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 1737 # Table walker page sizes translated +system.cpu2.itb.walker.walks 1343 # Table walker walks requested +system.cpu2.itb.walker.walksShort 1343 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walksShortTerminationLevel::Level1 245 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1098 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 1343 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 1343 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 1343 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 890 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 12592.696629 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 10799.035256 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 6603.898577 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::4096-6143 278 31.24% 31.24% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::10240-12287 236 26.52% 57.75% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::12288-14335 167 18.76% 76.52% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::14336-16383 5 0.56% 77.08% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::22528-24575 204 22.92% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 890 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 2000056500 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 2000056500 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 2000056500 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 648 72.81% 72.81% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 242 27.19% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 890 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 5947 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 5947 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1343 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1343 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 1737 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 1737 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 7684 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 12739134 # ITB inst hits -system.cpu2.itb.inst_misses 5947 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 890 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 890 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 2233 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 10557278 # ITB inst hits +system.cpu2.itb.inst_misses 1343 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 179 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 348 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb 152 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 166 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1664 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 930 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1123 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1750 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 12745081 # ITB inst accesses -system.cpu2.itb.hits 12739134 # DTB hits -system.cpu2.itb.misses 5947 # DTB misses -system.cpu2.itb.accesses 12745081 # DTB accesses -system.cpu2.numCycles 69598203 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 10558621 # ITB inst accesses +system.cpu2.itb.hits 10557278 # DTB hits +system.cpu2.itb.misses 1343 # DTB misses +system.cpu2.itb.accesses 10558621 # DTB accesses +system.cpu2.numCycles 1381989702 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 26515709 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 68908003 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 17205761 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 12047751 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 39848524 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2067901 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 93242 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 1673 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 258 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 197550 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 103741 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 733 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 12737635 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 269288 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2836 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 67795354 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.222311 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.353518 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 49366248 72.82% 72.82% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 2347568 3.46% 76.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 1568593 2.31% 78.59% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4737747 6.99% 85.58% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 1131198 1.67% 87.25% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 711180 1.05% 88.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 3791892 5.59% 93.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 790451 1.17% 95.06% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3350477 4.94% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 67795354 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.247216 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.990083 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 18554298 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 36869392 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 10385190 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1060917 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 925294 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 1315001 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 110273 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 59218991 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 355421 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 925294 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 19165450 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 3849841 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 27045066 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 10823220 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5986178 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 56757014 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 1753 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 886942 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 164990 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 4446768 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 58681863 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 260617277 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 63638433 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 4180 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 48518636 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10163211 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 951510 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 887874 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 5959133 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 10269621 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 7907555 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 1397245 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 1927093 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 54497262 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 673331 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 51805193 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 68913 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8128009 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 18480591 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 69367 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 67795354 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.764141 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.469300 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 47462334 70.01% 70.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6771907 9.99% 80.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 5071293 7.48% 87.48% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4140398 6.11% 93.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1621050 2.39% 95.98% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1073842 1.58% 97.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 1127363 1.66% 99.22% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 365418 0.54% 99.76% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 161749 0.24% 100.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 67795354 # Number of insts issued each cycle -system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 78874 9.93% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 365128 45.98% 55.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 350163 44.09% 100.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 104 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 34340504 66.29% 66.29% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 39551 0.08% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 1 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 1 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 2876 0.01% 66.37% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.37% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.37% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.37% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 9906412 19.12% 85.49% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 7515741 14.51% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 51805193 # Type of FU issued -system.cpu2.iq.rate 0.744347 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 794166 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.015330 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 172259378 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 63331070 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 50263649 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 9441 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 4992 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 4167 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 52594172 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 5083 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 269403 # Number of loads that had data forwarded from stores -system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1615728 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1799 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 38192 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 801002 # Number of stores squashed -system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 130832 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 65205 # Number of times an access to memory failed due to the cache being blocked -system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 925294 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3298023 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 403705 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 55280627 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 94381 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 10269621 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 7907555 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 360066 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 33263 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 361678 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 38192 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 184473 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 164818 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 349291 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 51367571 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 9727601 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 393852 # Number of squashed instructions skipped in execute -system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 110034 # number of nop insts executed -system.cpu2.iew.exec_refs 17167980 # number of memory reference insts executed -system.cpu2.iew.exec_branches 9465672 # Number of branches executed -system.cpu2.iew.exec_stores 7440379 # Number of stores executed -system.cpu2.iew.exec_rate 0.738059 # Inst execution rate -system.cpu2.iew.wb_sent 50970582 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 50267816 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 26418019 # num instructions producing a value -system.cpu2.iew.wb_consumers 45975704 # num instructions consuming a value -system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.722257 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.574608 # average fanout of values written-back -system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 8162826 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 603964 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 292667 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 66072678 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.712969 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.621762 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 48122515 72.83% 72.83% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 8016673 12.13% 84.97% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 3951454 5.98% 90.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 1700222 2.57% 93.52% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 874557 1.32% 94.84% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 615125 0.93% 95.77% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 1261958 1.91% 97.68% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 299480 0.45% 98.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1230694 1.86% 100.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 66072678 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 38816949 # Number of instructions committed -system.cpu2.commit.committedOps 47107760 # Number of ops (including micro ops) committed -system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 15760446 # Number of memory references committed -system.cpu2.commit.loads 8653893 # Number of loads committed -system.cpu2.commit.membars 226862 # Number of memory barriers committed -system.cpu2.commit.branches 8887739 # Number of branches committed -system.cpu2.commit.fp_insts 4128 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 41222164 # Number of committed integer instructions. -system.cpu2.commit.function_calls 1631970 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 31306209 66.46% 66.46% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 38229 0.08% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 2876 0.01% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.54% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 8653893 18.37% 84.91% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 7106553 15.09% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 47107760 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1230694 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 112781874 # The number of ROB reads -system.cpu2.rob.rob_writes 112267275 # The number of ROB writes -system.cpu2.timesIdled 279594 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1802849 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 5249879064 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 38751769 # Number of Instructions Simulated -system.cpu2.committedOps 47042580 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.796001 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.796001 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.556793 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.556793 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 56233169 # number of integer regfile reads -system.cpu2.int_regfile_writes 31866388 # number of integer regfile writes -system.cpu2.fp_regfile_reads 15654 # number of floating regfile reads -system.cpu2.fp_regfile_writes 13819 # number of floating regfile writes -system.cpu2.cc_regfile_reads 181781148 # number of cc regfile reads -system.cpu2.cc_regfile_writes 19208893 # number of cc regfile writes -system.cpu2.misc_regfile_reads 94223470 # number of misc regfile reads -system.cpu2.misc_regfile_writes 484431 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 30182 # Transaction distribution -system.iobus.trans_dist::ReadResp 30182 # Transaction distribution -system.iobus.trans_dist::WriteReq 59005 # Transaction distribution -system.iobus.trans_dist::WriteResp 59005 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54134 # Packet count per connected master and slave (bytes) +system.cpu2.committedInsts 19375420 # Number of instructions committed +system.cpu2.committedOps 23493929 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 1397443 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 550 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 4259392331 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 71.326955 # CPI: cycles per instruction +system.cpu2.ipc 0.014020 # IPC: instructions per cycle +system.cpu2.kern.inst.arm 0 # number of arm instructions executed +system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu2.tickCycles 41311098 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 1340678604 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 13646054 # Number of BP lookups +system.cpu3.branchPred.condPredicted 7543734 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 320434 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 8619119 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 6472050 # Number of BTB hits +system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu3.branchPred.BTBHitPct 75.089461 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 3094994 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 16257 # Number of incorrect RAS predictions. +system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu3.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu3.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu3.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu3.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu3.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu3.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu3.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu3.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu3.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu3.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu3.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu3.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu3.dtb.walker.walks 35143 # Table walker walks requested +system.cpu3.dtb.walker.walksShort 35143 # Table walker walks initiated with short descriptors +system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 12076 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7806 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 15261 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 19882 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 462.453476 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 3227.731349 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-16383 19738 99.28% 99.28% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::16384-32767 120 0.60% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::32768-49151 15 0.08% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::49152-65535 2 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-81919 3 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::81920-98303 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::98304-114687 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::114688-131071 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::131072-147455 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 19882 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 6311 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 11174.694977 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 9013.738443 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 7509.952707 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-16383 5234 82.93% 82.93% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::16384-32767 989 15.67% 98.61% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::32768-49151 83 1.32% 99.92% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::49152-65535 2 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 6311 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -8699062064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.943227 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-1 -8742325064 100.50% 100.50% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::2-3 30532500 -0.35% 100.15% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-5 6165000 -0.07% 100.08% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::6-7 1932500 -0.02% 100.05% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-9 1510500 -0.02% 100.04% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::10-11 932000 -0.01% 100.03% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-13 478000 -0.01% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::14-15 1202000 -0.01% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-17 269000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::18-19 118500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-21 46500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::22-23 12000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-25 31500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::26-27 8000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-29 6000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::30-31 19000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -8699062064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 1800 71.51% 71.51% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::1M 717 28.49% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 2517 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 35143 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 35143 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2517 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2517 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 37660 # Table walker requests started/completed, data/inst +system.cpu3.dtb.inst_hits 0 # ITB inst hits +system.cpu3.dtb.inst_misses 0 # ITB inst misses +system.cpu3.dtb.read_hits 7578904 # DTB read hits +system.cpu3.dtb.read_misses 29166 # DTB read misses +system.cpu3.dtb.write_hits 5839969 # DTB write hits +system.cpu3.dtb.write_misses 5977 # DTB write misses +system.cpu3.dtb.flush_tlb 158 # Number of times complete TLB was flushed +system.cpu3.dtb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA +system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu3.dtb.flush_entries 1718 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 425 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 723 # Number of TLB faults due to prefetch +system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu3.dtb.perms_faults 310 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 7608070 # DTB read accesses +system.cpu3.dtb.write_accesses 5845946 # DTB write accesses +system.cpu3.dtb.inst_accesses 0 # ITB inst accesses +system.cpu3.dtb.hits 13418873 # DTB hits +system.cpu3.dtb.misses 35143 # DTB misses +system.cpu3.dtb.accesses 13454016 # DTB accesses +system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu3.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu3.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu3.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu3.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu3.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu3.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu3.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu3.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu3.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu3.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu3.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu3.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu3.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu3.itb.walker.walks 4732 # Table walker walks requested +system.cpu3.itb.walker.walksShort 4732 # Table walker walks initiated with short descriptors +system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1951 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2718 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 63 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 4669 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1610.409081 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 7290.700462 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-16383 4501 96.40% 96.40% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::16384-32767 127 2.72% 99.12% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-49151 19 0.41% 99.53% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::49152-65535 9 0.19% 99.72% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-81919 6 0.13% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::81920-98303 3 0.06% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::98304-114687 2 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::114688-131071 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::147456-163839 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 4669 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 1251 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 12846.922462 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 10663.579337 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 7853.199891 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-4095 16 1.28% 1.28% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::4096-8191 403 32.21% 33.49% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::8192-12287 333 26.62% 60.11% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::12288-16383 200 15.99% 76.10% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::16384-20479 15 1.20% 77.30% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::20480-24575 250 19.98% 97.28% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::24576-28671 6 0.48% 97.76% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::28672-32767 4 0.32% 98.08% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-36863 2 0.16% 98.24% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::36864-40959 7 0.56% 98.80% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::40960-45055 12 0.96% 99.76% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::45056-49151 2 0.16% 99.92% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::57344-61439 1 0.08% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::total 1251 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -394920472 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean -1.156632 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -848106296 214.75% 214.75% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 450855824 -114.16% 100.59% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 1608500 -0.41% 100.18% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 392000 -0.10% 100.08% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 207000 -0.05% 100.03% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::5 65000 -0.02% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::6 26500 -0.01% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::7 31000 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -394920472 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 859 72.31% 72.31% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::1M 329 27.69% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 1188 # Table walker page sizes translated +system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4732 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4732 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1188 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1188 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 5920 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 9997642 # ITB inst hits +system.cpu3.itb.inst_misses 4732 # ITB inst misses +system.cpu3.itb.read_hits 0 # DTB read hits +system.cpu3.itb.read_misses 0 # DTB read misses +system.cpu3.itb.write_hits 0 # DTB write hits +system.cpu3.itb.write_misses 0 # DTB write misses +system.cpu3.itb.flush_tlb 158 # Number of times complete TLB was flushed +system.cpu3.itb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA +system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu3.itb.flush_entries 1217 # Number of entries that have been flushed from TLB +system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu3.itb.perms_faults 676 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.read_accesses 0 # DTB read accesses +system.cpu3.itb.write_accesses 0 # DTB write accesses +system.cpu3.itb.inst_accesses 10002374 # ITB inst accesses +system.cpu3.itb.hits 9997642 # DTB hits +system.cpu3.itb.misses 4732 # DTB misses +system.cpu3.itb.accesses 10002374 # DTB accesses +system.cpu3.numCycles 55587045 # number of cpu cycles simulated +system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu3.fetch.icacheStallCycles 20927206 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 54552679 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 13646054 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 9567044 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 32032256 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 1608040 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 79957 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 938 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 213 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 310222 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 78152 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 195 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 9996683 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 215580 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 2118 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 54233142 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.214742 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.347105 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 39601274 73.02% 73.02% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 1868483 3.45% 76.47% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 1208105 2.23% 78.69% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3698353 6.82% 85.51% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 956006 1.76% 87.28% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 647778 1.19% 88.47% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 2970918 5.48% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 646722 1.19% 95.14% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2635503 4.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::total 54233142 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.245490 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.981392 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 14598894 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 29797113 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 8084772 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 1033348 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 718831 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 1078244 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 86337 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 47705679 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 276961 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 718831 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 15136583 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 3024863 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 21172664 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 8572569 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 5607363 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 45758805 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 705 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 1147656 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 110939 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 3950348 # Number of times rename has blocked due to SQ full +system.cpu3.rename.RenamedOperands 47566105 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 210305694 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 51528880 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 3583 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 39455162 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 8110943 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 731184 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 676901 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 5765226 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 8100915 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 6455257 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 1173886 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 1646906 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 43984199 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 534989 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 41793570 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 55806 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 6489424 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 14897600 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 57980 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 54233142 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.770628 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.467625 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 37814670 69.73% 69.73% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 5400070 9.96% 79.68% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 4120767 7.60% 87.28% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 3382476 6.24% 93.52% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 1384183 2.55% 96.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 849283 1.57% 97.64% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 885452 1.63% 99.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 261249 0.48% 99.75% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 134992 0.25% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 54233142 # Number of insts issued each cycle +system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 63553 10.11% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 10.11% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 286976 45.65% 55.76% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 278158 44.24% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu3.iq.FU_type_0::No_OpClass 64 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 27814370 66.55% 66.55% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 30310 0.07% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 2311 0.01% 66.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 66.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.63% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 7807777 18.68% 85.31% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 6138736 14.69% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::total 41793570 # Type of FU issued +system.cpu3.iq.rate 0.751858 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 628687 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.015043 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 138497118 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 51032224 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 40586618 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 7657 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 4185 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 3350 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 42418091 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 4102 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 178986 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu3.iew.lsq.thread0.squashedLoads 1277727 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 1461 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 28401 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 648748 # Number of stores squashed +system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu3.iew.lsq.thread0.rescheduledLoads 106985 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 49122 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu3.iew.iewSquashCycles 718831 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 2574270 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 340639 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 44583748 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 79881 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 8100915 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 6455257 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 277620 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 23691 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 310856 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 28401 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 151779 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 129603 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 281382 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 41441394 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 7665414 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 317113 # Number of squashed instructions skipped in execute +system.cpu3.iew.exec_swp 0 # number of swp insts executed +system.cpu3.iew.exec_nop 64560 # number of nop insts executed +system.cpu3.iew.exec_refs 13741668 # number of memory reference insts executed +system.cpu3.iew.exec_branches 7578657 # Number of branches executed +system.cpu3.iew.exec_stores 6076254 # Number of stores executed +system.cpu3.iew.exec_rate 0.745523 # Inst execution rate +system.cpu3.iew.wb_sent 41128495 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 40589968 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 21345679 # num instructions producing a value +system.cpu3.iew.wb_consumers 37833149 # num instructions consuming a value +system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu3.iew.wb_rate 0.730206 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.564206 # average fanout of values written-back +system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu3.commit.commitSquashedInsts 6509597 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 477009 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 235228 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 52878842 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.719887 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.616953 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 38356720 72.54% 72.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 6383323 12.07% 84.61% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 3220180 6.09% 90.70% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 1427186 2.70% 93.40% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 783029 1.48% 94.88% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 553691 1.05% 95.93% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 963741 1.82% 97.75% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 249255 0.47% 98.22% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 941717 1.78% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::total 52878842 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 31212680 # Number of instructions committed +system.cpu3.commit.committedOps 38066779 # Number of ops (including micro ops) committed +system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu3.commit.refs 12629697 # Number of memory references committed +system.cpu3.commit.loads 6823188 # Number of loads committed +system.cpu3.commit.membars 185407 # Number of memory barriers committed +system.cpu3.commit.branches 7131780 # Number of branches committed +system.cpu3.commit.fp_insts 3315 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 33217803 # Number of committed integer instructions. +system.cpu3.commit.function_calls 1242593 # Number of function calls committed. +system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 25405548 66.74% 66.74% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 29226 0.08% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 2308 0.01% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.82% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 6823188 17.92% 84.75% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 5806509 15.25% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::total 38066779 # Class of committed instruction +system.cpu3.commit.bw_lim_events 941717 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 90938636 # The number of ROB reads +system.cpu3.rob.rob_writes 90509785 # The number of ROB writes +system.cpu3.timesIdled 219189 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1353903 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 5161759281 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 31175665 # Number of Instructions Simulated +system.cpu3.committedOps 38029764 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.783027 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.783027 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.560844 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.560844 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 45482682 # number of integer regfile reads +system.cpu3.int_regfile_writes 25425363 # number of integer regfile writes +system.cpu3.fp_regfile_reads 14224 # number of floating regfile reads +system.cpu3.fp_regfile_writes 12010 # number of floating regfile writes +system.cpu3.cc_regfile_reads 146149493 # number of cc regfile reads +system.cpu3.cc_regfile_writes 16057585 # number of cc regfile writes +system.cpu3.misc_regfile_reads 75089133 # number of misc regfile reads +system.cpu3.misc_regfile_writes 354942 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 30152 # Transaction distribution +system.iobus.trans_dist::ReadResp 30152 # Transaction distribution +system.iobus.trans_dist::WriteReq 59010 # Transaction distribution +system.iobus.trans_dist::WriteResp 59010 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1778,11 +2072,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105422 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67851 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105436 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178324 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67865 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1803,84 +2097,80 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159079 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480327 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 18337000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 159093 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480085 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 23980000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 32000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 2698000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 3354000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15728000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 18876000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 75000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 107120699 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 72450078 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 39854000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 50566000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 20948000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 14254000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 0.991924 # Cycle average of tags in use +system.iocache.tags.replacements 36410 # number of replacements +system.iocache.tags.tagsinuse 1.001831 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 244949964009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.991924 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.061995 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.061995 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 248566208509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.001831 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062614 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062614 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328284 # Number of tag accesses -system.iocache.tags.data_accesses 328284 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses -system.iocache.ReadReq_misses::total 252 # number of ReadReq misses +system.iocache.tags.tag_accesses 327996 # Number of tag accesses +system.iocache.tags.data_accesses 327996 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses +system.iocache.ReadReq_misses::total 220 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses -system.iocache.demand_misses::total 252 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 252 # number of overall misses -system.iocache.overall_misses::total 252 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 14446931 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 14446931 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 2442151768 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 2442151768 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 14446931 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14446931 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 14446931 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14446931 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses +system.iocache.demand_misses::total 220 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 220 # number of overall misses +system.iocache.overall_misses::total 220 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 16046914 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 16046914 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 1650207164 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 1650207164 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 16046914 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 16046914 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 16046914 # number of overall miss cycles +system.iocache.overall_miss_latency::total 16046914 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1889,14 +2179,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 57329.091270 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 57329.091270 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 67418.058966 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 67418.058966 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 57329.091270 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 57329.091270 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 57329.091270 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 57329.091270 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 72940.518182 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 72940.518182 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 45555.630632 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 45555.630632 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 72940.518182 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 72940.518182 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 72940.518182 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 72940.518182 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1907,341 +2197,418 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 122 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 122 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 20704 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 20704 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 122 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 122 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 122 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 122 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 8346931 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 8346931 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 1406951768 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1406951768 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8346931 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8346931 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8346931 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8346931 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.484127 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.484127 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.571555 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.571555 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.484127 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.484127 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.484127 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.484127 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68417.467213 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68417.467213 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67955.552937 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67955.552937 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68417.467213 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68417.467213 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68417.467213 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68417.467213 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::realview.ide 135 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 135 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 13984 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 13984 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 135 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 135 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 135 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 9296914 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 9296914 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 951007164 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 951007164 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9296914 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9296914 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9296914 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9296914 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.613636 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.613636 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.386042 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.386042 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.613636 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.613636 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.613636 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.613636 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68866.029630 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68866.029630 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68006.805206 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68006.805206 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68866.029630 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68866.029630 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68866.029630 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68866.029630 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 100800 # number of replacements -system.l2c.tags.tagsinuse 65125.449839 # Cycle average of tags in use -system.l2c.tags.total_refs 4808585 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 165996 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 28.968078 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 49726.772555 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939327 # Average occupied blocks per requestor +system.l2c.tags.replacements 101303 # number of replacements +system.l2c.tags.tagsinuse 65108.070418 # Cycle average of tags in use +system.l2c.tags.total_refs 5168936 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 166462 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 31.051748 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 79214811500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 48981.200793 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.935125 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5415.190350 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2959.237721 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969230 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1018.129085 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 815.178543 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 59.704078 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 3616.145822 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1512.183033 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.758770 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4737.303132 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1924.234554 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 793.012275 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 757.975635 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 22.711590 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.006773 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2669.581018 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 709.597353 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 49.846649 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2547.275002 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 1913.390425 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.747394 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.082629 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.045154 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.015535 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.012439 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000911 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.055178 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.023074 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993736 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 48 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65148 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 48 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2981 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8244 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53579 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994080 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 42763917 # Number of tag accesses -system.l2c.tags.data_accesses 42763917 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4590 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2386 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 1717 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 931 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 27091 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 5953 # number of ReadReq hits -system.l2c.ReadReq_hits::total 42668 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 690633 # number of Writeback hits -system.l2c.Writeback_hits::total 690633 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 10 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 34 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 48 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 11 # number of SCUpgradeReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.072286 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.029361 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.012100 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011566 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000347 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.040735 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.010828 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000761 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.038868 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.029196 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993470 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65109 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 50 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2282 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8086 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54700 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000763 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.993484 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 45646881 # Number of tag accesses +system.l2c.tags.data_accesses 45646881 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4200 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2163 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 1338 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 747 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 13212 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 1162 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.dtb.walker 20914 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.itb.walker 4752 # number of ReadReq hits +system.l2c.ReadReq_hits::total 48488 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 691721 # number of Writeback hits +system.l2c.Writeback_hits::total 691721 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 6 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 9 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3.data 21 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 47 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu3.data 10 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 81720 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 20255 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 55422 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 157397 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 854225 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 247947 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 678133 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1780305 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 239843 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 78268 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 203677 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 521788 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4590 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2386 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 854225 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 321563 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 1717 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 931 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 247947 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 98523 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 27091 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 5953 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 678133 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 259099 # number of demand (read+write) hits -system.l2c.demand_hits::total 2502158 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4590 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2386 # number of overall hits -system.l2c.overall_hits::cpu0.inst 854225 # number of overall hits -system.l2c.overall_hits::cpu0.data 321563 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 1717 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 931 # number of overall hits -system.l2c.overall_hits::cpu1.inst 247947 # number of overall hits -system.l2c.overall_hits::cpu1.data 98523 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 27091 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 5953 # number of overall hits -system.l2c.overall_hits::cpu2.inst 678133 # number of overall hits -system.l2c.overall_hits::cpu2.data 259099 # number of overall hits -system.l2c.overall_hits::total 2502158 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 67332 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 21178 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 26251 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3.data 44047 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 158808 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 736913 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 208708 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 472854 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 539069 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1957544 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 224011 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 66058 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 89648 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3.data 143036 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 522753 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4200 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2163 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 736913 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 291343 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 1338 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 747 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 208708 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 87236 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 13212 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 1162 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 472854 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 115899 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.dtb.walker 20914 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.itb.walker 4752 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 539069 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 187083 # number of demand (read+write) hits +system.l2c.demand_hits::total 2687593 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4200 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 2163 # number of overall hits +system.l2c.overall_hits::cpu0.inst 736913 # number of overall hits +system.l2c.overall_hits::cpu0.data 291343 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 1338 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 747 # number of overall hits +system.l2c.overall_hits::cpu1.inst 208708 # number of overall hits +system.l2c.overall_hits::cpu1.data 87236 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 13212 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 1162 # number of overall hits +system.l2c.overall_hits::cpu2.inst 472854 # number of overall hits +system.l2c.overall_hits::cpu2.data 115899 # number of overall hits +system.l2c.overall_hits::cpu3.dtb.walker 20914 # number of overall hits +system.l2c.overall_hits::cpu3.itb.walker 4752 # number of overall hits +system.l2c.overall_hits::cpu3.inst 539069 # number of overall hits +system.l2c.overall_hits::cpu3.data 187083 # number of overall hits +system.l2c.overall_hits::total 2687593 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 89 # number of ReadReq misses -system.l2c.ReadReq_misses::total 95 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1320 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 342 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 1053 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2715 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 3 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu2.data 5 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 8 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 64209 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 14460 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 60110 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 138779 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 9651 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1946 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 8147 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 19744 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 7162 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 2480 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 4481 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 14123 # number of ReadSharedReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 33 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.dtb.walker 69 # number of ReadReq misses +system.l2c.ReadReq_misses::total 108 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1068 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 470 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 477 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 737 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2752 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu3.data 7 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 7 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 43391 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 11840 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 30205 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 52337 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 137773 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 7845 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 1896 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 5840 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 5565 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 21146 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 5023 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 2409 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 1760 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3.data 4867 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 14059 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 9651 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 71371 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1946 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16940 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 89 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 8147 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 64591 # number of demand (read+write) misses -system.l2c.demand_misses::total 172741 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7845 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 48414 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1896 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 14249 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 33 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 5840 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 31965 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.dtb.walker 69 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 5565 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 57204 # number of demand (read+write) misses +system.l2c.demand_misses::total 173086 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 9651 # number of overall misses -system.l2c.overall_misses::cpu0.data 71371 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1946 # number of overall misses -system.l2c.overall_misses::cpu1.data 16940 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 89 # number of overall misses -system.l2c.overall_misses::cpu2.inst 8147 # number of overall misses -system.l2c.overall_misses::cpu2.data 64591 # number of overall misses -system.l2c.overall_misses::total 172741 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 82500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 7918000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 8000500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 92500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 339500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 432000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu2.data 127000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 127000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1119587000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 4880855000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6000442000 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 159178000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu2.inst 680250500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 839428500 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 203493500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2.data 391802000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 595295500 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 82500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 159178000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1323080500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 7918000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 680250500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 5272657000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 7443166500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 82500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 159178000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1323080500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 7918000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 680250500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 5272657000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 7443166500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4594 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2387 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 1718 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 931 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 27180 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 5953 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 42763 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 690633 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 690633 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1330 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 346 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 1087 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2763 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu2.data 16 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 145929 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 34715 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 115532 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296176 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 863876 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 249893 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu2.inst 686280 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1800049 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 247005 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 80748 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2.data 208158 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 535911 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4594 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2387 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 863876 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 392934 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 1718 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 931 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 249893 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 115463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 27180 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 5953 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 686280 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 323690 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2674899 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4594 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 2387 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 863876 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 392934 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 1718 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 931 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 249893 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 115463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 27180 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 5953 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 686280 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 323690 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2674899 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000871 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000419 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000582 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.003274 # miss rate for ReadReq accesses +system.l2c.overall_misses::cpu0.inst 7845 # number of overall misses +system.l2c.overall_misses::cpu0.data 48414 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1896 # number of overall misses +system.l2c.overall_misses::cpu1.data 14249 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 33 # number of overall misses +system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu2.inst 5840 # number of overall misses +system.l2c.overall_misses::cpu2.data 31965 # number of overall misses +system.l2c.overall_misses::cpu3.dtb.walker 69 # number of overall misses +system.l2c.overall_misses::cpu3.inst 5565 # number of overall misses +system.l2c.overall_misses::cpu3.data 57204 # number of overall misses +system.l2c.overall_misses::total 173086 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2811000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.itb.walker 82500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.dtb.walker 6272000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 9165500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 31000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 154500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3.data 184500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 370000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu3.data 194000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 194000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 915490000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 2302823000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 4277288000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7495601000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 155074500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 475343000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu3.inst 458780500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1089198000 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 195409500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 145904000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3.data 422430000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 763743500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 155074500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1110899500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 2811000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.itb.walker 82500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 475343000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 2448727000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.dtb.walker 6272000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 458780500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 4699718000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9357708000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 155074500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1110899500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 2811000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.itb.walker 82500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 475343000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 2448727000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.dtb.walker 6272000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 458780500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 4699718000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9357708000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4204 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2164 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 1338 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 747 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 13245 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 1163 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.dtb.walker 20983 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.itb.walker 4752 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 48596 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 691721 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 691721 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1079 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 476 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 486 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 758 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2799 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu3.data 17 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 18 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 110723 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 33018 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 56456 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 96384 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296581 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 744758 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 210604 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 478694 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu3.inst 544634 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1978690 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 229034 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 68467 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 91408 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3.data 147903 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 536812 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4204 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2164 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 744758 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 339757 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 1338 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 747 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 210604 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 101485 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 13245 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 1163 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 478694 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 147864 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.dtb.walker 20983 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.itb.walker 4752 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 544634 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 244287 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2860679 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4204 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2164 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 744758 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 339757 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 1338 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 747 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 210604 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 101485 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 13245 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 1163 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 478694 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 147864 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.dtb.walker 20983 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.itb.walker 4752 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 544634 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 244287 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2860679 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000951 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000462 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.002492 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000860 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.dtb.walker 0.003288 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.002222 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992481 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.988439 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.968721 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.982628 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.312500 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.421053 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.440002 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.416535 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.520289 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.468569 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.011172 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007787 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.011871 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.010969 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.028995 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.030713 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.021527 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.026353 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000871 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000419 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.011172 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.181636 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000582 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007787 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.146714 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.003274 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.011871 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.199546 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.064579 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000871 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000419 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.011172 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.181636 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000582 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007787 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.146714 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.003274 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.011871 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.199546 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.064579 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 88966.292135 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 84215.789474 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 270.467836 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 322.412156 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 159.116022 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 25400 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 15875 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77426.486860 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81198.719015 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 43237.391824 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81797.533402 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 83497.054130 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 42515.625000 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82053.830645 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 87436.286543 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 42150.782412 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 81797.533402 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 78103.925620 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 88966.292135 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 83497.054130 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 81631.450202 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 43088.592170 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 81797.533402 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 78103.925620 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 88966.292135 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 83497.054130 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 81631.450202 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 43088.592170 # average overall miss latency +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989805 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.987395 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.981481 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 0.972296 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.983208 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu3.data 0.411765 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.388889 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.391888 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.358592 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.535018 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 0.543005 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.464538 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.010534 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.009003 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.012200 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.010218 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.010687 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.021931 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.035185 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.019254 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.032907 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.026190 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000951 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000462 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.010534 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.142496 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009003 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.140405 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.002492 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.itb.walker 0.000860 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.012200 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.216178 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.dtb.walker 0.003288 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.010218 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.234167 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.060505 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000951 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000462 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.010534 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.142496 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009003 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.140405 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.002492 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.itb.walker 0.000860 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.012200 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.216178 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.dtb.walker 0.003288 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.010218 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.234167 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.060505 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 85181.818182 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 82500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 90898.550725 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 84865.740741 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 65.957447 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 323.899371 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 250.339213 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 134.447674 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data 27714.285714 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 27714.285714 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77321.790541 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 76239.794736 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 81725.891816 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 54405.442285 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81790.348101 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 81394.349315 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 82440.341420 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 51508.464958 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 81116.438356 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 82900 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 86794.740086 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 54324.169571 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 81790.348101 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 77963.330760 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 85181.818182 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.itb.walker 82500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 81394.349315 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 76606.507117 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 90898.550725 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 82440.341420 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 82157.156842 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 54063.921981 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 81790.348101 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 77963.330760 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 85181.818182 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.itb.walker 82500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 81394.349315 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 76606.507117 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 90898.550725 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 82440.341420 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 82157.156842 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 54063.921981 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2250,221 +2617,280 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 92937 # number of writebacks -system.l2c.writebacks::total 92937 # number of writebacks -system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 5 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2.data 44 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 44 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.data 44 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 49 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.data 44 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 49 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 89 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 342 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 1053 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1395 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 5 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 14460 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 60110 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 74570 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1946 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 8142 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 10088 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2480 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2.data 4437 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 6917 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1946 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 16940 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 89 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 8142 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 64547 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 91665 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1946 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 16940 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 89 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 8142 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 64547 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 91665 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5882 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2.data 8601 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 14483 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4590 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2.data 6802 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 11392 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10472 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2.data 15403 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 25875 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 72500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 7028000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 7100500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 7101000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 21856500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 28957500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 108000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 108000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 974987000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 4279755000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5254742000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 139718000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 598575000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 738293000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 178693500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 344725500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 523419000 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 72500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 139718000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1153680500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 7028000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 598575000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 4624480500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6523554500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 72500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 139718000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1153680500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 7028000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 598575000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 4624480500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6523554500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 983438000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1607640500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 2591078500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 758788000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1264062500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2022850500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1742226000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2871703000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4613929000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000582 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003274 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.988439 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.968721 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.504886 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.312500 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.263158 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.416535 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.520289 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.251776 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007787 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.011864 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005604 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.030713 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.021316 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.012907 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000582 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007787 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.146714 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003274 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011864 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.199410 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.034269 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000582 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007787 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.146714 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003274 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011864 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.199410 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.034269 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 78966.292135 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 78894.444444 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20763.157895 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20756.410256 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20758.064516 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 21600 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 21600 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67426.486860 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71198.719015 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 70467.238836 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71797.533402 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73516.949153 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73185.269627 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72053.830645 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 77693.373901 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75671.389331 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71797.533402 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68103.925620 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 78966.292135 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73516.949153 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71645.165538 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 71167.343043 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71797.533402 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68103.925620 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 78966.292135 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73516.949153 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71645.165538 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 71167.343043 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167194.491670 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 186913.207767 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 178904.819443 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165313.289760 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 185836.886210 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 177567.635183 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 166369.938885 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 186437.901707 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 178316.096618 # average overall mshr uncacheable latency +system.l2c.writebacks::writebacks 92980 # number of writebacks +system.l2c.writebacks::total 92980 # number of writebacks +system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 3 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 5 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2.data 23 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu3.data 42 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 65 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.data 23 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.data 42 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.data 23 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.data 42 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 73 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 33 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker 69 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 470 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 477 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 737 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1684 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu3.data 7 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 7 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 11840 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 30205 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3.data 52337 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 94382 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1896 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 5837 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 5560 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 13293 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2409 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 1737 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu3.data 4825 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 8971 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1896 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 14249 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 33 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 5837 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 31942 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.dtb.walker 69 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 5560 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.data 57162 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 116749 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1896 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 14249 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 33 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 5837 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 31942 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.dtb.walker 69 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 5560 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.data 57162 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 116749 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 4113 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2.data 6742 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu3.data 7559 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 18414 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3215 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2.data 5150 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu3.data 6001 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 14366 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 7328 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2.data 11892 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu3.data 13560 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 32780 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2481000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 72500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker 5582000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 8135500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 9755000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9901500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 15296000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 34952500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data 247500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 247500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 797090000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2000773000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 3753918000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 6551781000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 136114500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 416910500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 402899000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 955924000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 171319500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 126899000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 371197500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 669416000 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 136114500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 968409500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2481000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 72500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 416910500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2127672000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker 5582000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 402899000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 4125115500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 8185256500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 136114500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 968409500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2481000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 72500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 416910500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2127672000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 5582000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 402899000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 4125115500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 8185256500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 658270500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1229145000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 1435515500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3322931000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 509348000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 919708500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data 1131292500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2560349000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1167618500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2148853500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3.data 2566808000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5883280000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.002492 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000860 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003288 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.002120 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.987395 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.981481 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.972296 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.601643 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.411765 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.388889 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.358592 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.535018 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.543005 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.318233 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.009003 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.012194 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010209 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006718 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.035185 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.019003 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.032623 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.016712 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009003 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.140405 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002492 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000860 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012194 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.216023 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003288 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010209 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.233995 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.040812 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009003 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.140405 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002492 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000860 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012194 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.216023 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003288 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010209 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.233995 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.040812 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 75181.818182 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 72500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 80898.550725 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 78985.436893 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20755.319149 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20757.861635 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20754.409769 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20755.641330 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 35357.142857 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 35357.142857 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67321.790541 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 66239.794736 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 71725.891816 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 69417.696171 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71790.348101 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 71425.475415 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72463.848921 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71911.833296 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 71116.438356 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73056.419113 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 76932.124352 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74619.997771 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71790.348101 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67963.330760 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 75181.818182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 72500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 71425.475415 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66610.481498 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 80898.550725 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72463.848921 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 72165.345859 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 70109.863896 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71790.348101 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67963.330760 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75181.818182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 72500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 71425.475415 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66610.481498 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 80898.550725 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72463.848921 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 72165.345859 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 70109.863896 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 160046.316557 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 182311.628597 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 189908.122768 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 180456.772021 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 158428.615863 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 178584.174757 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 188517.330445 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 178222.817764 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 159336.585699 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 180697.401615 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 189292.625369 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 179477.730323 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 40110 # Transaction distribution -system.membus.trans_dist::ReadResp 74274 # Transaction distribution -system.membus.trans_dist::WriteReq 27559 # Transaction distribution -system.membus.trans_dist::WriteResp 27559 # Transaction distribution -system.membus.trans_dist::Writeback 129127 # Transaction distribution -system.membus.trans_dist::CleanEvict 7993 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4555 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4563 # Transaction distribution -system.membus.trans_dist::ReadExReq 136939 # Transaction distribution -system.membus.trans_dist::ReadExResp 136939 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34165 # Transaction distribution +system.membus.trans_dist::ReadReq 40114 # Transaction distribution +system.membus.trans_dist::ReadResp 75574 # Transaction distribution +system.membus.trans_dist::WriteReq 27565 # Transaction distribution +system.membus.trans_dist::WriteResp 27565 # Transaction distribution +system.membus.trans_dist::Writeback 129170 # Transaction distribution +system.membus.trans_dist::CleanEvict 8408 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4530 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4537 # Transaction distribution +system.membus.trans_dist::ReadExReq 135995 # Transaction distribution +system.membus.trans_dist::ReadExResp 135995 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 35460 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105422 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2000 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 479379 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 586811 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109150 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109150 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 695961 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159079 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 480552 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 588004 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109028 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109028 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 697032 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4000 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16928316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17091415 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2324480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2324480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19415895 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 278 # Total snoops (count) -system.membus.snoop_fanout::samples 416813 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16952892 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17116017 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2321600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2321600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19437617 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 336 # Total snoops (count) +system.membus.snoop_fanout::samples 417611 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 416813 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 417611 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 416813 # Request fanout histogram -system.membus.reqLayer0.occupancy 45715500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 417611 # Request fanout histogram +system.membus.reqLayer0.occupancy 56684000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 475000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 698000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 457691597 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 502688198 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 520011564 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 664974257 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 36772084 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 25114094 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2497,55 +2923,55 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 105713 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2441896 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27559 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27559 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 756453 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1923004 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2763 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 19 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2782 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296176 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296176 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1800158 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 536033 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 20704 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5399808 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2615033 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28551 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87799 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8131191 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115239416 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97644319 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 47800 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 155188 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 213086723 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 121684 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5505945 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.031256 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.174010 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 112988 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2628707 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 762046 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2097370 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2799 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2817 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296581 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296581 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1978788 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 536947 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 13984 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5930770 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2618508 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 27177 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 101121 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8677576 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 126672504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97797817 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 44504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 177192 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 224692017 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 129673 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5878617 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.031442 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.174509 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 5333849 96.87% 96.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 172096 3.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 5693781 96.86% 96.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 184836 3.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5505945 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1781656500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 5878617 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2191894997 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 172500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 178500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1404823682 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 679741283 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1851402273 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 767013811 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11544481 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11591991 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 39263676 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 48212755 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu2.kern.inst.arm 0 # number of arm instructions executed -system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu3.kern.inst.arm 0 # number of arm instructions executed +system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |