diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt | 3777 |
1 files changed, 1901 insertions, 1876 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 3492b3590..22877557e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,154 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.817778 # Number of seconds simulated -sim_ticks 2817777605000 # Number of ticks simulated -final_tick 2817777605000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.817750 # Number of seconds simulated +sim_ticks 2817750443000 # Number of ticks simulated +final_tick 2817750443000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 298084 # Simulator instruction rate (inst/s) -host_op_rate 361954 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6653597695 # Simulator tick rate (ticks/s) -host_mem_usage 624156 # Number of bytes of host memory used -host_seconds 423.50 # Real time elapsed on the host -sim_insts 126237777 # Number of instructions simulated -sim_ops 153286368 # Number of ops (including micro ops) simulated +host_inst_rate 301376 # Simulator instruction rate (inst/s) +host_op_rate 365951 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6727532391 # Simulator tick rate (ticks/s) +host_mem_usage 628096 # Number of bytes of host memory used +host_seconds 418.84 # Real time elapsed on the host +sim_insts 126227981 # Number of instructions simulated +sim_ops 153274395 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 655396 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4517280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 653732 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4510496 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 125824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1063044 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 5888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 519744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 4071296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 124544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1058884 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 5696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 520896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 4080320 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10959816 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 655396 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 125824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 519744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1300964 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8260864 # Number of bytes written to this memory +system.physmem.bytes_read::total 10955912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 653732 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 124544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 520896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1299172 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8264128 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8278388 # Number of bytes written to this memory +system.physmem.bytes_written::total 8281652 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 18694 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 71101 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 18668 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 70995 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1966 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16611 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 92 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 8121 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 63614 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1946 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16546 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 89 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 8139 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 63755 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180220 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 129076 # Number of write requests responded to by this memory +system.physmem.num_reads::total 180159 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 129127 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 133457 # Number of write requests responded to by this memory +system.physmem.num_writes::total 133508 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 232593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1603136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 232005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1600744 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 44654 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 377263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 2090 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 184452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1444861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 44200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 375791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 2021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 184862 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1448077 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3889525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 232593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 44654 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 184452 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 461699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2931695 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3888177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 232005 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 44200 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 184862 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 461067 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2932881 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2937914 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2931695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2939101 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2932881 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 232593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1609352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 232005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1606960 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 44654 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 377266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 2090 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 184452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1444861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 44200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 375793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 2021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 184862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1448077 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6827439 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 90406 # Number of read requests accepted -system.physmem.writeReqs 90720 # Number of write requests accepted -system.physmem.readBursts 90406 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 90720 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5783616 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2368 # Total number of bytes read from write queue -system.physmem.bytesWritten 4983552 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5785924 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5805960 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 37 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 12831 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2411 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5941 # Per bank write bursts -system.physmem.perBankRdBursts::1 5711 # Per bank write bursts -system.physmem.perBankRdBursts::2 5475 # Per bank write bursts -system.physmem.perBankRdBursts::3 5399 # Per bank write bursts -system.physmem.perBankRdBursts::4 5366 # Per bank write bursts -system.physmem.perBankRdBursts::5 5838 # Per bank write bursts -system.physmem.perBankRdBursts::6 6281 # Per bank write bursts -system.physmem.perBankRdBursts::7 6483 # Per bank write bursts -system.physmem.perBankRdBursts::8 6268 # Per bank write bursts -system.physmem.perBankRdBursts::9 6346 # Per bank write bursts -system.physmem.perBankRdBursts::10 5330 # Per bank write bursts -system.physmem.perBankRdBursts::11 5015 # Per bank write bursts -system.physmem.perBankRdBursts::12 5399 # Per bank write bursts -system.physmem.perBankRdBursts::13 5276 # Per bank write bursts -system.physmem.perBankRdBursts::14 4950 # Per bank write bursts -system.physmem.perBankRdBursts::15 5291 # Per bank write bursts -system.physmem.perBankWrBursts::0 4893 # Per bank write bursts -system.physmem.perBankWrBursts::1 4429 # Per bank write bursts -system.physmem.perBankWrBursts::2 4791 # Per bank write bursts -system.physmem.perBankWrBursts::3 4794 # Per bank write bursts -system.physmem.perBankWrBursts::4 4700 # Per bank write bursts -system.physmem.perBankWrBursts::5 5367 # Per bank write bursts -system.physmem.perBankWrBursts::6 5289 # Per bank write bursts -system.physmem.perBankWrBursts::7 5346 # Per bank write bursts -system.physmem.perBankWrBursts::8 5326 # Per bank write bursts -system.physmem.perBankWrBursts::9 5240 # Per bank write bursts -system.physmem.perBankWrBursts::10 4672 # Per bank write bursts -system.physmem.perBankWrBursts::11 4285 # Per bank write bursts -system.physmem.perBankWrBursts::12 5029 # Per bank write bursts -system.physmem.perBankWrBursts::13 5084 # Per bank write bursts -system.physmem.perBankWrBursts::14 4218 # Per bank write bursts -system.physmem.perBankWrBursts::15 4405 # Per bank write bursts +system.physmem.bw_total::total 6827277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 90477 # Number of read requests accepted +system.physmem.writeReqs 65811 # Number of write requests accepted +system.physmem.readBursts 90477 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 65811 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5784832 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5696 # Total number of bytes read from write queue +system.physmem.bytesWritten 4210432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5790468 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4211784 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 89 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 23137 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5834 # Per bank write bursts +system.physmem.perBankRdBursts::1 5704 # Per bank write bursts +system.physmem.perBankRdBursts::2 5463 # Per bank write bursts +system.physmem.perBankRdBursts::3 5405 # Per bank write bursts +system.physmem.perBankRdBursts::4 5372 # Per bank write bursts +system.physmem.perBankRdBursts::5 5837 # Per bank write bursts +system.physmem.perBankRdBursts::6 6284 # Per bank write bursts +system.physmem.perBankRdBursts::7 6486 # Per bank write bursts +system.physmem.perBankRdBursts::8 6223 # Per bank write bursts +system.physmem.perBankRdBursts::9 6339 # Per bank write bursts +system.physmem.perBankRdBursts::10 5440 # Per bank write bursts +system.physmem.perBankRdBursts::11 5142 # Per bank write bursts +system.physmem.perBankRdBursts::12 5381 # Per bank write bursts +system.physmem.perBankRdBursts::13 5279 # Per bank write bursts +system.physmem.perBankRdBursts::14 4952 # Per bank write bursts +system.physmem.perBankRdBursts::15 5247 # Per bank write bursts +system.physmem.perBankWrBursts::0 4133 # Per bank write bursts +system.physmem.perBankWrBursts::1 3840 # Per bank write bursts +system.physmem.perBankWrBursts::2 4117 # Per bank write bursts +system.physmem.perBankWrBursts::3 4118 # Per bank write bursts +system.physmem.perBankWrBursts::4 3952 # Per bank write bursts +system.physmem.perBankWrBursts::5 4415 # Per bank write bursts +system.physmem.perBankWrBursts::6 4512 # Per bank write bursts +system.physmem.perBankWrBursts::7 4650 # Per bank write bursts +system.physmem.perBankWrBursts::8 4383 # Per bank write bursts +system.physmem.perBankWrBursts::9 4609 # Per bank write bursts +system.physmem.perBankWrBursts::10 3956 # Per bank write bursts +system.physmem.perBankWrBursts::11 3578 # Per bank write bursts +system.physmem.perBankWrBursts::12 4192 # Per bank write bursts +system.physmem.perBankWrBursts::13 4199 # Per bank write bursts +system.physmem.perBankWrBursts::14 3505 # Per bank write bursts +system.physmem.perBankWrBursts::15 3629 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 38 # Number of times write queue was full causing retry -system.physmem.totGap 2816211460500 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 2816184296500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 1 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 90405 # Read request sizes (log2) +system.physmem.readPktSize::6 90476 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 90718 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 59525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 27440 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2853 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 545 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 65809 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 59474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 27494 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -175,7 +175,7 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 58 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 54 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 52 # What write queue length does an incoming req see @@ -185,164 +185,165 @@ system.physmem.wrQLenPdf::6 51 # Wh system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 51 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 3489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 105 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 33321 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 323.130758 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.789706 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 346.993140 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12624 37.89% 37.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7779 23.35% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3018 9.06% 70.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1714 5.14% 75.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1413 4.24% 79.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 752 2.26% 81.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 537 1.61% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 554 1.66% 85.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4930 14.80% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 33321 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2995 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.170618 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 514.809638 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 2993 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1098 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 42 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 32481 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 307.722545 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 177.643491 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.464678 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12661 38.98% 38.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 7717 23.76% 62.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2982 9.18% 71.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1687 5.19% 77.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1406 4.33% 81.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 745 2.29% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 513 1.58% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 495 1.52% 86.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4275 13.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 32481 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3213 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.128852 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 487.877717 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 3211 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2995 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2995 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.999332 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.796866 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 47.448084 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-15 17 0.57% 0.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 2784 92.95% 93.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 41 1.37% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 11 0.37% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 6 0.20% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 14 0.47% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 11 0.37% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 12 0.40% 96.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 7 0.23% 96.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 11 0.37% 97.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 7 0.23% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 15 0.50% 98.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 14 0.47% 98.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 4 0.13% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 1 0.03% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.07% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 4 0.13% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 3 0.10% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 3 0.10% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 6 0.20% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 1 0.03% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 6 0.20% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 5 0.17% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.03% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 2 0.07% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.07% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.10% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2995 # Writes before turning the bus around for reads -system.physmem.totQLat 1193098984 # Total ticks spent queuing -system.physmem.totMemAccLat 2887517734 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 451845000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13202.53 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::26624-27647 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3213 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3213 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.475568 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.644293 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.368139 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 6 0.19% 0.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 1 0.03% 0.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.03% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 2 0.06% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 2703 84.13% 84.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 65 2.02% 86.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 109 3.39% 89.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 35 1.09% 90.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 33 1.03% 91.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 100 3.11% 95.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 9 0.28% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.09% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 4 0.12% 95.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.25% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.06% 95.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.03% 95.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 103 3.21% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.06% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.09% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.12% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.03% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.06% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.03% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.03% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.22% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.06% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.06% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3213 # Writes before turning the bus around for reads +system.physmem.totQLat 1180806250 # Total ticks spent queuing +system.physmem.totMemAccLat 2875581250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 451940000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13063.75 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31952.53 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31813.75 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.05 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.77 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.49 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.05 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.06 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.49 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.64 # Average write queue length when enqueuing -system.physmem.readRowHits 74590 # Number of row buffer hits during reads -system.physmem.writeRowHits 60325 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.45 # Row buffer hit rate for writes -system.physmem.avgGap 15548355.62 # Average gap between requests -system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 130667040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 71094375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 362653200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 256666320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 178852415040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 68967490005 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1611945575250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1860586561230 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.497599 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2632498894488 # Time in different power states -system.physmem_0.memoryStateTime::REF 91437840000 # Time in different power states +system.physmem.avgWrQLen 6.07 # Average write queue length when enqueuing +system.physmem.readRowHits 74627 # Number of row buffer hits during reads +system.physmem.writeRowHits 49067 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.56 # Row buffer hit rate for writes +system.physmem.avgGap 18019197.23 # Average gap between requests +system.physmem.pageHitRate 79.19 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 128285640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 69757875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 361803000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 218615760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 178850889360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 68913339435 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1610809853250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1859352544320 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.527151 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2632589257000 # Time in different power states +system.physmem_0.memoryStateTime::REF 91437060000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14475823012 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14382937750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 121239720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 65934000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 342209400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 247918320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 178852415040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68215091715 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1611413256750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1859258064945 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.496864 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2633620948492 # Time in different power states -system.physmem_1.memoryStateTime::REF 91437840000 # Time in different power states +system.physmem_1.actEnergy 117270720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 63772500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 343207800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 207690480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 178850889360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 68192676180 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1609047407250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1856822914290 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.575499 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2633644277500 # Time in different power states +system.physmem_1.memoryStateTime::REF 91437060000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 13360607258 # Time in different power states +system.physmem_1.memoryStateTime::ACT 13328364750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -392,48 +393,48 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 5755 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5755 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 5755 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5755 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5755 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 166069431868 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.475663 # Table walker pending requests distribution +system.cpu0.dtb.walker.walks 5725 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5725 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5725 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5725 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5725 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 166068997868 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.475665 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::stdev 0.499407 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 87076283368 52.43% 52.43% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 78993148500 47.57% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 166069431868 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3189 67.65% 67.65% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1525 32.35% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4714 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5755 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walksPending::0 87075845118 52.43% 52.43% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 78993152750 47.57% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 166068997868 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3165 67.41% 67.41% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1530 32.59% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4695 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5725 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5755 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4714 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5725 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4695 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4714 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 10469 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4695 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 10420 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 14452204 # DTB read hits -system.cpu0.dtb.read_misses 4833 # DTB read misses -system.cpu0.dtb.write_hits 11089888 # DTB write hits -system.cpu0.dtb.write_misses 922 # DTB write misses -system.cpu0.dtb.flush_tlb 189 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 14454415 # DTB read hits +system.cpu0.dtb.read_misses 4808 # DTB read misses +system.cpu0.dtb.write_hits 11087884 # DTB write hits +system.cpu0.dtb.write_misses 917 # DTB write misses +system.cpu0.dtb.flush_tlb 190 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3319 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3341 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 937 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 964 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14457037 # DTB read accesses -system.cpu0.dtb.write_accesses 11090810 # DTB write accesses +system.cpu0.dtb.perms_faults 218 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14459223 # DTB read accesses +system.cpu0.dtb.write_accesses 11088801 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 25542092 # DTB hits -system.cpu0.dtb.misses 5755 # DTB misses -system.cpu0.dtb.accesses 25547847 # DTB accesses +system.cpu0.dtb.hits 25542299 # DTB hits +system.cpu0.dtb.misses 5725 # DTB misses +system.cpu0.dtb.accesses 25548024 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -463,35 +464,35 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 2817 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2817 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2817 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2817 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2817 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 166069431868 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.475664 # Table walker pending requests distribution +system.cpu0.itb.walker.walks 2784 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2784 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2784 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2784 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2784 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 166068997868 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.475665 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::stdev 0.499407 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 87076165368 52.43% 52.43% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 78993266500 47.57% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 166069431868 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1542 75.55% 75.55% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 499 24.45% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2041 # Table walker page sizes translated +system.cpu0.itb.walker.walksPending::0 87075735118 52.43% 52.43% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 78993262750 47.57% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 166068997868 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1521 75.19% 75.19% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 502 24.81% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2023 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2817 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2817 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2784 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2784 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2041 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2041 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4858 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 67891248 # ITB inst hits -system.cpu0.itb.inst_misses 2817 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2023 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2023 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4807 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 67912569 # ITB inst hits +system.cpu0.itb.inst_misses 2784 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 189 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 190 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 2012 # Number of entries that have been flushed from TLB @@ -501,504 +502,504 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 67894065 # ITB inst accesses -system.cpu0.itb.hits 67891248 # DTB hits -system.cpu0.itb.misses 2817 # DTB misses -system.cpu0.itb.accesses 67894065 # DTB accesses -system.cpu0.numCycles 82517225 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 67915353 # ITB inst accesses +system.cpu0.itb.hits 67912569 # DTB hits +system.cpu0.itb.misses 2784 # DTB misses +system.cpu0.itb.accesses 67915353 # DTB accesses +system.cpu0.numCycles 82537208 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 66111161 # Number of instructions committed -system.cpu0.committedOps 80627134 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 70885778 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5615 # Number of float alu accesses -system.cpu0.num_func_calls 7285085 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 8754092 # number of instructions that are conditional controls -system.cpu0.num_int_insts 70885778 # number of integer instructions -system.cpu0.num_fp_insts 5615 # number of float instructions -system.cpu0.num_int_register_reads 131498293 # number of times the integer registers were read -system.cpu0.num_int_register_writes 49310474 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4327 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1292 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 245812611 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 29370316 # number of times the CC registers were written -system.cpu0.num_mem_refs 26208491 # number of memory refs -system.cpu0.num_load_insts 14628012 # Number of load instructions -system.cpu0.num_store_insts 11580479 # Number of store instructions -system.cpu0.num_idle_cycles 77919171.769514 # Number of idle cycles -system.cpu0.num_busy_cycles 4598053.230486 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055722 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944278 # Percentage of idle cycles -system.cpu0.Branches 16437108 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2194 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 55772206 67.98% 67.98% # Class of executed instruction -system.cpu0.op_class::IntMult 58001 0.07% 68.05% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4497 0.01% 68.06% # Class of executed instruction +system.cpu0.committedInsts 66134007 # Number of instructions committed +system.cpu0.committedOps 80648826 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 70905199 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5550 # Number of float alu accesses +system.cpu0.num_func_calls 7283350 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 8754499 # number of instructions that are conditional controls +system.cpu0.num_int_insts 70905199 # number of integer instructions +system.cpu0.num_fp_insts 5550 # number of float instructions +system.cpu0.num_int_register_reads 131519590 # number of times the integer registers were read +system.cpu0.num_int_register_writes 49325288 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4326 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1228 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 245878640 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 29383702 # number of times the CC registers were written +system.cpu0.num_mem_refs 26210186 # number of memory refs +system.cpu0.num_load_insts 14630349 # Number of load instructions +system.cpu0.num_store_insts 11579837 # Number of store instructions +system.cpu0.num_idle_cycles 77938505.493998 # Number of idle cycles +system.cpu0.num_busy_cycles 4598702.506002 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055717 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944283 # Percentage of idle cycles +system.cpu0.Branches 16436363 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2195 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 55791644 67.98% 67.99% # Class of executed instruction +system.cpu0.op_class::IntMult 58049 0.07% 68.06% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4498 0.01% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::MemRead 14628012 17.83% 85.89% # Class of executed instruction -system.cpu0.op_class::MemWrite 11580479 14.11% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 14630349 17.83% 85.89% # Class of executed instruction +system.cpu0.op_class::MemWrite 11579837 14.11% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 82045389 # Class of executed instruction +system.cpu0.op_class::total 82066572 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3057 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 831864 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997018 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 47054976 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 832376 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 56.530914 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 3052 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 831549 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997019 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 47051301 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 832061 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 56.547899 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.861119 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.669659 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.466239 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.948947 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032558 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018489 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.952083 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.619501 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.425436 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.949125 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032460 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018409 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 198551178 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 198551178 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 13770345 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 4433242 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 8498402 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 26701989 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10695058 # 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miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.012272 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115604 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.046247 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.015568 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.014769 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.118368 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.048660 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15373.575448 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15303.005439 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10228.127886 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41417.356478 # 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average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20573.900322 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 40910.302594 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33161.333445 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 378962 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 29004 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 19067 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 710 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.875282 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 40.850704 # average number of cycles each access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013508 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.012254 # 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number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2242226500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3091525500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1395423500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5679297435 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7074720935 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 276712000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 590115500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 866827500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 20457500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 37492500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57950000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 297500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 297500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2244722500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7921523935 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10166246435 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2521434500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8511639435 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11033073935 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1056963000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1715153500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2772116500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 811573000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1342286000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2153859000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1868536000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3057439500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4925975500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013191 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018327 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008097 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.010914 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017518 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007324 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.245343 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.221391 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.122404 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.015289 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019129 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.008679 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000114 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000035 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012261 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017952 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.007759 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014711 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020546 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.009001 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13854.845904 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13367.668800 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13498.858280 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39739.698281 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 48377.991200 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46382.457285 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13152.662649 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13049.190384 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13081.502030 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15503.294574 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12812.307243 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13638.234832 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 19343.437500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19343.437500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23455.350361 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 28061.319979 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26892.807885 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21649.046667 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26000.062865 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24858.693436 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177408.078231 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 196862.425863 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188961.910353 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174550.967181 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 194575.011129 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186450.617284 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176153.849823 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 195857.412961 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 187858.921724 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012242 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017979 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.007763 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014695 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020556 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.009000 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14311.214087 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13888.657297 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14002.235176 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39799.877357 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 48702.930555 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46644.871400 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13751.031158 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13431.557983 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13531.916388 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15982.421875 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13447.812052 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14245.329400 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 18593.750000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18593.750000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23777.328771 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 28489.156549 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27294.867731 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22015.685983 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26434.565886 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25275.186670 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179694.491670 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 199413.265899 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191404.853967 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176813.289760 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 197336.959718 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189067.679073 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 178431.627196 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 198496.364345 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190375.864734 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1799096 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.534039 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 100909280 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1799607 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 56.072954 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10982089250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 477.173904 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 21.006307 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 13.353828 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.931980 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.041028 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.026082 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999090 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1799604 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.542681 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 100855692 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1800115 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 56.027360 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10987259500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 478.414957 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 20.920922 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 12.206802 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.934404 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.040861 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.023841 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999107 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 154 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 157 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 104560332 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 104560332 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 67029897 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 21781554 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 12097829 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 100909280 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 67029897 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 21781554 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 12097829 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 100909280 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 67029897 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 21781554 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 12097829 # number of overall hits -system.cpu0.icache.overall_hits::total 100909280 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 863392 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 250227 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 737787 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1851406 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 863392 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 250227 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 737787 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1851406 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 863392 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 250227 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 737787 # number of overall misses -system.cpu0.icache.overall_misses::total 1851406 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 3390224750 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 10026619709 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13416844459 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 3390224750 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 10026619709 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13416844459 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 3390224750 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 10026619709 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13416844459 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 67893289 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 22031781 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 12835616 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 102760686 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 67893289 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 22031781 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 12835616 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 102760686 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 67893289 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 22031781 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 12835616 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 102760686 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012717 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011358 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.057480 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.018017 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012717 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011358 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.057480 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.018017 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012717 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011358 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.057480 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.018017 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13548.596874 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13590.127922 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7246.840757 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13548.596874 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13590.127922 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7246.840757 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13548.596874 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13590.127922 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7246.840757 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 7212 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 104509492 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 104509492 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 67050712 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 21807219 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 11997761 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 100855692 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 67050712 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 21807219 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 11997761 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 100855692 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 67050712 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 21807219 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 11997761 # number of overall hits +system.cpu0.icache.overall_hits::total 100855692 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 863880 # 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number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11512746479 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 3014176750 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8498569729 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11512746479 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 3014176750 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8498569729 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11512746479 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011358 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.053447 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009111 # 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average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12388.079975 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12296.592786 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12045.769441 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12388.079975 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12296.592786 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 53485 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 53485 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 53485 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 53485 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 53485 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 53485 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 249894 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 686384 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 936278 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 249894 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 686384 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 936278 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 249894 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 686384 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 936278 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 3138392000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8843257984 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11981649984 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 3138392000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8843257984 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11981649984 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 3138392000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8843257984 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11981649984 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011329 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.053886 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009116 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011329 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.053886 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009116 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011329 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.053886 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009116 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12558.892971 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12883.834681 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12797.107252 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12558.892971 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12883.834681 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12797.107252 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12558.892971 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12883.834681 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12797.107252 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1029,56 +1030,56 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 1874 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 1874 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 637 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1237 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 1874 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 1874 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 1874 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1601 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12056.839475 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10248.777265 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6448.828751 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 390 24.36% 24.36% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 856 53.47% 77.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 354 22.11% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 1911 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 1911 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 628 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1283 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 1911 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 1911 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 1911 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1624 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12817.118227 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11165.640992 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6539.405372 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 417 25.68% 25.68% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 849 52.28% 77.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 357 21.98% 99.94% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1601 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1000015500 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1000015500 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1000015500 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 972 60.71% 60.71% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 629 39.29% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1601 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1874 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 1624 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1004 61.82% 61.82% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 620 38.18% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1624 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1911 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1874 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1601 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1911 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1624 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1601 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 3475 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1624 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3535 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4664064 # DTB read hits -system.cpu1.dtb.read_misses 1628 # DTB read misses -system.cpu1.dtb.write_hits 3297220 # DTB write hits -system.cpu1.dtb.write_misses 246 # DTB write misses -system.cpu1.dtb.flush_tlb 168 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 112 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 4670594 # DTB read hits +system.cpu1.dtb.read_misses 1655 # DTB read misses +system.cpu1.dtb.write_hits 3300164 # DTB write hits +system.cpu1.dtb.write_misses 256 # DTB write misses +system.cpu1.dtb.flush_tlb 167 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 123 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1307 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1332 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 257 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 60 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4665692 # DTB read accesses -system.cpu1.dtb.write_accesses 3297466 # DTB write accesses +system.cpu1.dtb.perms_faults 65 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 4672249 # DTB read accesses +system.cpu1.dtb.write_accesses 3300420 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7961284 # DTB hits -system.cpu1.dtb.misses 1874 # DTB misses -system.cpu1.dtb.accesses 7963158 # DTB accesses +system.cpu1.dtb.hits 7970758 # DTB hits +system.cpu1.dtb.misses 1911 # DTB misses +system.cpu1.dtb.accesses 7972669 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1108,128 +1109,128 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 876 # Table walker walks requested -system.cpu1.itb.walker.walksShort 876 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 230 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 646 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 876 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 876 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 876 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 692 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12877.167630 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11119.022104 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6272.001420 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::2048-4095 140 20.23% 20.23% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 230 33.24% 53.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 143 20.66% 74.13% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-22527 156 22.54% 96.68% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 23 3.32% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 692 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 935 # Table walker walks requested +system.cpu1.itb.walker.walksShort 935 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 229 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 706 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 935 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 935 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 935 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 723 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 13501.383126 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11823.554991 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6487.735992 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 166 22.96% 22.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 228 31.54% 54.50% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 139 19.23% 73.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 7 0.97% 74.69% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 183 25.31% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 723 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 462 66.76% 66.76% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 230 33.24% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 692 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 494 68.33% 68.33% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 229 31.67% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 723 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 876 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 876 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 935 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 935 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 692 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 692 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 1568 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 22031781 # ITB inst hits -system.cpu1.itb.inst_misses 876 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 723 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 723 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1658 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 22057113 # ITB inst hits +system.cpu1.itb.inst_misses 935 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 168 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 112 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 167 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 123 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 752 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 783 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 22032657 # ITB inst accesses -system.cpu1.itb.hits 22031781 # DTB hits -system.cpu1.itb.misses 876 # DTB misses -system.cpu1.itb.accesses 22032657 # DTB accesses -system.cpu1.numCycles 158012603 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 22058048 # ITB inst accesses +system.cpu1.itb.hits 22057113 # DTB hits +system.cpu1.itb.misses 935 # DTB misses +system.cpu1.itb.accesses 22058048 # DTB accesses +system.cpu1.numCycles 158011873 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 21317281 # Number of instructions committed -system.cpu1.committedOps 25549926 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22701009 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1608 # Number of float alu accesses -system.cpu1.num_func_calls 2410952 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2737582 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22701009 # number of integer instructions -system.cpu1.num_fp_insts 1608 # number of float instructions -system.cpu1.num_int_register_reads 41843043 # number of times the integer registers were read -system.cpu1.num_int_register_writes 15920660 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1288 # number of times the floating registers were read +system.cpu1.committedInsts 21342205 # Number of instructions committed +system.cpu1.committedOps 25582989 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22730381 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1657 # Number of float alu accesses +system.cpu1.num_func_calls 2417962 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2740367 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22730381 # number of integer instructions +system.cpu1.num_fp_insts 1657 # number of float instructions +system.cpu1.num_int_register_reads 41903720 # number of times the integer registers were read +system.cpu1.num_int_register_writes 15946634 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1337 # number of times the floating registers were read system.cpu1.num_fp_register_writes 320 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 92840963 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 9448697 # number of times the CC registers were written -system.cpu1.num_mem_refs 8172131 # number of memory refs -system.cpu1.num_load_insts 4710232 # Number of load instructions -system.cpu1.num_store_insts 3461899 # Number of store instructions -system.cpu1.num_idle_cycles 151539718.287508 # Number of idle cycles -system.cpu1.num_busy_cycles 6472884.712492 # Number of busy cycles -system.cpu1.not_idle_fraction 0.040964 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.959036 # Percentage of idle cycles -system.cpu1.Branches 5298424 # Number of branches fetched -system.cpu1.op_class::No_OpClass 41 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 18071289 68.81% 68.81% # Class of executed instruction -system.cpu1.op_class::IntMult 19339 0.07% 68.88% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1186 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu1.op_class::MemRead 4710232 17.93% 86.82% # Class of executed instruction -system.cpu1.op_class::MemWrite 3461899 13.18% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 92962985 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 9452948 # number of times the CC registers were written +system.cpu1.num_mem_refs 8180627 # number of memory refs +system.cpu1.num_load_insts 4716601 # Number of load instructions +system.cpu1.num_store_insts 3464026 # Number of store instructions +system.cpu1.num_idle_cycles 151538894.643419 # Number of idle cycles +system.cpu1.num_busy_cycles 6472978.356581 # Number of busy cycles +system.cpu1.not_idle_fraction 0.040965 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.959035 # Percentage of idle cycles +system.cpu1.Branches 5307887 # Number of branches fetched +system.cpu1.op_class::No_OpClass 38 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 18096671 68.81% 68.81% # Class of executed instruction +system.cpu1.op_class::IntMult 19327 0.07% 68.89% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1187 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.89% # Class of executed instruction +system.cpu1.op_class::MemRead 4716601 17.94% 86.83% # Class of executed instruction +system.cpu1.op_class::MemWrite 3464026 13.17% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 26263986 # Class of executed instruction +system.cpu1.op_class::total 26297850 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 17390044 # Number of BP lookups -system.cpu2.branchPred.condPredicted 9451928 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 400737 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 10830418 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 8125283 # Number of BTB hits +system.cpu2.branchPred.lookups 17205761 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9385761 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 401350 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 10751395 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 8022189 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 75.022802 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 4068079 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21097 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 74.615331 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4025562 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21207 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1259,88 +1260,89 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 43271 # Table walker walks requested -system.cpu2.dtb.walker.walksShort 43271 # Table walker walks initiated with short descriptors -system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 13795 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 11030 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksSquashedBefore 18446 # Table walks squashed before starting -system.cpu2.dtb.walker.walkWaitTime::samples 24825 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::mean 526.888218 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::stdev 3382.784717 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0-16383 24602 99.10% 99.10% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::16384-32767 180 0.73% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::32768-49151 23 0.09% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::49152-65535 14 0.06% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::65536-81919 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walks 43873 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 43873 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 13923 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 10993 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksSquashedBefore 18957 # Table walks squashed before starting +system.cpu2.dtb.walker.walkWaitTime::samples 24916 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::mean 571.078825 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::stdev 3693.718026 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0-16383 24688 99.08% 99.08% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::16384-32767 176 0.71% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::32768-49151 30 0.12% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::49152-65535 9 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::65536-81919 9 0.04% 99.98% # Table walker wait (enqueue to first request) latency system.cpu2.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::98304-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::98304-114687 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::114688-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu2.dtb.walker.walkWaitTime::131072-147455 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 24825 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 9018 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 12445.276336 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 10074.043051 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 7598.717395 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-8191 2712 30.07% 30.07% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::8192-16383 3866 42.87% 72.94% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::16384-24575 2205 24.45% 97.39% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::24576-32767 103 1.14% 98.54% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::32768-40959 58 0.64% 99.18% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::40960-49151 71 0.79% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkWaitTime::total 24916 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 9164 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 13158.828023 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 10878.635204 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 7680.126787 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-8191 2739 29.89% 29.89% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::8192-16383 3883 42.37% 72.26% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::16384-24575 2316 25.27% 97.53% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::24576-32767 72 0.79% 98.32% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::32768-40959 91 0.99% 99.31% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::40960-49151 60 0.65% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walkCompletionTime::81920-90111 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 9018 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 60407494468 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::mean 0.614556 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::stdev 0.505382 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0-1 60349981968 99.90% 99.90% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::2-3 42488500 0.07% 99.98% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::4-5 7802000 0.01% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::6-7 2924500 0.00% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::8-9 1368500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::10-11 844500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::12-13 331000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::14-15 1040000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::16-17 124500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::18-19 121000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::20-21 186000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::22-23 81500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::24-25 109000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::26-27 11000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walkCompletionTime::total 9164 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 60380803468 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::mean 0.564289 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::stdev 0.516018 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0-1 60322207968 99.90% 99.90% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::2-3 41747500 0.07% 99.97% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::4-5 8670500 0.01% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::6-7 3297500 0.01% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::8-9 1514000 0.00% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::10-11 972000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::12-13 454500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::14-15 1161000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::16-17 173500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::18-19 164000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::20-21 123500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::22-23 89000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::24-25 134500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::26-27 15500 0.00% 100.00% # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::28-29 5500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::30-31 75000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 60407494468 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 2796 73.35% 73.35% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::1M 1016 26.65% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 3812 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 43271 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walksPending::30-31 73000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 60380803468 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 2766 73.10% 73.10% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 1018 26.90% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 3784 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 43873 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 43271 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 3812 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 43873 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 3784 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 3812 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 47083 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 3784 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 47657 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 9630626 # DTB read hits -system.cpu2.dtb.read_misses 37535 # DTB read misses -system.cpu2.dtb.write_hits 7130235 # DTB write hits -system.cpu2.dtb.write_misses 5736 # DTB write misses +system.cpu2.dtb.read_hits 9620013 # DTB read hits +system.cpu2.dtb.read_misses 37991 # DTB read misses +system.cpu2.dtb.write_hits 7129568 # DTB write hits +system.cpu2.dtb.write_misses 5882 # DTB write misses system.cpu2.dtb.flush_tlb 179 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 360 # Number of times TLB was flushed by MVA +system.cpu2.dtb.flush_tlb_mva 348 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2330 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 520 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 952 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2312 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 478 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 974 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 414 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 9668161 # DTB read accesses -system.cpu2.dtb.write_accesses 7135971 # DTB write accesses +system.cpu2.dtb.perms_faults 415 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 9658004 # DTB read accesses +system.cpu2.dtb.write_accesses 7135450 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 16760861 # DTB hits -system.cpu2.dtb.misses 43271 # DTB misses -system.cpu2.dtb.accesses 16804132 # DTB accesses +system.cpu2.dtb.hits 16749581 # DTB hits +system.cpu2.dtb.misses 43873 # DTB misses +system.cpu2.dtb.accesses 16793454 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1370,395 +1372,392 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 6235 # Table walker walks requested -system.cpu2.itb.walker.walksShort 6235 # Table walker walks initiated with short descriptors -system.cpu2.itb.walker.walksShortTerminationLevel::Level1 2044 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksShortTerminationLevel::Level2 4088 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksSquashedBefore 103 # Table walks squashed before starting -system.cpu2.itb.walker.walkWaitTime::samples 6132 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::mean 1114.562948 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::stdev 4869.153513 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0-8191 5831 95.09% 95.09% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::8192-16383 152 2.48% 97.57% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::16384-24575 99 1.61% 99.18% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::24576-32767 29 0.47% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::32768-40959 9 0.15% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::40960-49151 4 0.07% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::49152-57343 3 0.05% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::57344-65535 1 0.02% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::65536-73727 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::90112-98303 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::106496-114687 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 6132 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 1857 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 12539.311255 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 10038.361952 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 8040.211817 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-4095 547 29.46% 29.46% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::4096-8191 43 2.32% 31.77% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::8192-12287 410 22.08% 53.85% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::12288-16383 373 20.09% 73.94% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::16384-20479 9 0.48% 74.42% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::20480-24575 413 22.24% 96.66% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::24576-28671 14 0.75% 97.42% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::28672-32767 13 0.70% 98.12% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-36863 11 0.59% 98.71% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::36864-40959 8 0.43% 99.14% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::40960-45055 10 0.54% 99.68% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::45056-49151 1 0.05% 99.73% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::49152-53247 1 0.05% 99.78% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::53248-57343 2 0.11% 99.89% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::57344-61439 1 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::61440-65535 1 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 1857 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 13162833212 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::mean 0.828087 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::stdev 0.377922 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 2265327000 17.21% 17.21% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::1 10895443212 82.77% 99.98% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::2 1802500 0.01% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::3 162000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::4 51500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::5 47000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 13162833212 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 1358 77.42% 77.42% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::1M 396 22.58% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 1754 # Table walker page sizes translated +system.cpu2.itb.walker.walks 5947 # Table walker walks requested +system.cpu2.itb.walker.walksShort 5947 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walksShortTerminationLevel::Level1 1786 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 4054 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksSquashedBefore 107 # Table walks squashed before starting +system.cpu2.itb.walker.walkWaitTime::samples 5840 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::mean 1732.534247 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::stdev 7455.028366 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0-8191 5455 93.41% 93.41% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::8192-16383 164 2.81% 96.22% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::16384-24575 114 1.95% 98.17% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::24576-32767 45 0.77% 98.94% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::32768-40959 19 0.33% 99.26% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::40960-49151 8 0.14% 99.40% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::49152-57343 13 0.22% 99.62% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::57344-65535 3 0.05% 99.67% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::65536-73727 6 0.10% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::73728-81919 3 0.05% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::81920-90111 5 0.09% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::90112-98303 1 0.02% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::98304-106495 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::106496-114687 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::122880-131071 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 5840 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 1844 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 13438.177874 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 11167.697103 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 8164.078124 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-8191 568 30.80% 30.80% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::8192-16383 796 43.17% 73.97% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::16384-24575 418 22.67% 96.64% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::24576-32767 27 1.46% 98.10% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-40959 12 0.65% 98.75% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::40960-49151 15 0.81% 99.57% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::49152-57343 4 0.22% 99.78% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::57344-65535 3 0.16% 99.95% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::65536-73727 1 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 1844 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 13135820712 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::mean 0.816052 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::stdev 0.388899 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 2421306500 18.43% 18.43% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::1 10711149212 81.54% 99.97% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::2 2311000 0.02% 99.99% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::3 636500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::4 285000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::5 97500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::6 35000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 13135820712 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 1342 77.26% 77.26% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 395 22.74% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 1737 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 6235 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 6235 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 5947 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 5947 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 1754 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 1754 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 7989 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 12837123 # ITB inst hits -system.cpu2.itb.inst_misses 6235 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 1737 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 1737 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 7684 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 12739134 # ITB inst hits +system.cpu2.itb.inst_misses 5947 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 179 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 360 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb_mva 348 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1683 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1664 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1125 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1123 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 12843358 # ITB inst accesses -system.cpu2.itb.hits 12837123 # DTB hits -system.cpu2.itb.misses 6235 # DTB misses -system.cpu2.itb.accesses 12843358 # DTB accesses -system.cpu2.numCycles 69616646 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 12745081 # ITB inst accesses +system.cpu2.itb.hits 12739134 # DTB hits +system.cpu2.itb.misses 5947 # DTB misses +system.cpu2.itb.accesses 12745081 # DTB accesses +system.cpu2.numCycles 69598203 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 26594039 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 69071466 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 17390044 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 12193362 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 39655163 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2070826 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 93322 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 918 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 302 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 323029 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 106475 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 727 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 12835626 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 269064 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2716 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 67809362 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.223662 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.348600 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 26515709 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 68908003 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 17205761 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 12047751 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 39848524 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2067901 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 93242 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 1673 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 258 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 197550 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 103741 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 733 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 12737635 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 269288 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2836 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 67795354 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.222311 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.353518 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 49260090 72.64% 72.64% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 2390617 3.53% 76.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 1561768 2.30% 78.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4865604 7.18% 85.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 1097205 1.62% 87.27% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 701816 1.03% 88.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 3870082 5.71% 94.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 751059 1.11% 95.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3311121 4.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 49366248 72.82% 72.82% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 2347568 3.46% 76.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 1568593 2.31% 78.59% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4737747 6.99% 85.58% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 1131198 1.67% 87.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 711180 1.05% 88.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 3791892 5.59% 93.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 790451 1.17% 95.06% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3350477 4.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 67809362 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.249797 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.992169 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 18546973 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 36871218 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 10413141 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1051163 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 926599 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 1313756 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 110434 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 59271705 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 356279 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 926599 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 19159512 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 3828211 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 27033628 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 10840093 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 6021054 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 56800254 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 1622 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 892733 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 160451 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 4475802 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 58727822 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 260839504 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 63695069 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 4195 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 48596346 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10131460 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 953771 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 889969 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 6004915 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 10275852 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 7909386 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 1396867 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 1932490 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 54546075 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 673336 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 51866821 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 68048 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8110099 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 18430167 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 68913 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 67809362 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.764892 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.469149 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 67795354 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.247216 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.990083 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 18554298 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 36869392 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 10385190 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1060917 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 925294 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 1315001 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 110273 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 59218991 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 355421 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 925294 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 19165450 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 3849841 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 27045066 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 10823220 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5986178 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 56757014 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 1753 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 886942 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 164990 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 4446768 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 58681863 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 260617277 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 63638433 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 4180 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 48518636 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10163211 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 951510 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 887874 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 5959133 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 10269621 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 7907555 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 1397245 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 1927093 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 54497262 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 673331 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 51805193 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 68913 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8128009 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 18480591 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 69367 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 67795354 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.764141 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.469300 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 47470041 70.01% 70.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6738750 9.94% 79.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 5086869 7.50% 87.44% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4143776 6.11% 93.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1653610 2.44% 95.99% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1071590 1.58% 97.57% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 1124885 1.66% 99.23% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 357423 0.53% 99.76% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 162418 0.24% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 47462334 70.01% 70.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6771907 9.99% 80.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 5071293 7.48% 87.48% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4140398 6.11% 93.58% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1621050 2.39% 95.98% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1073842 1.58% 97.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 1127363 1.66% 99.22% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 365418 0.54% 99.76% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 161749 0.24% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 67809362 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 67795354 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 76711 9.73% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 2 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 365050 46.29% 56.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 346827 43.98% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 78874 9.93% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 365128 45.98% 55.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 350163 44.09% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 102 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 34390478 66.31% 66.31% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 39542 0.08% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 1 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 1 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 2888 0.01% 66.39% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.39% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 66.39% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.39% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 9917724 19.12% 85.51% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 7516080 14.49% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 104 0.00% 0.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 34340504 66.29% 66.29% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 39551 0.08% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 1 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 1 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 2876 0.01% 66.37% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.37% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.37% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.37% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 9906412 19.12% 85.49% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 7515741 14.51% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 51866821 # Type of FU issued -system.cpu2.iq.rate 0.745035 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 788590 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.015204 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 172390251 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 63361989 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 50322136 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 9391 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 4966 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 4144 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 52650258 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 5051 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 268895 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 51805193 # Type of FU issued +system.cpu2.iq.rate 0.744347 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 794166 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.015330 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 172259378 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 63331070 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 50263649 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 9441 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 4992 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 4167 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 52594172 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 5083 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 269403 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1610409 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1859 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 38198 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 800698 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1615728 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1799 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 38192 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 801002 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 130635 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 68542 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 130832 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 65205 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 926599 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3277236 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 403345 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 55328961 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 92252 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 10275852 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 7909386 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 360332 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 33301 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 361214 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 38198 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 183568 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 164696 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 348264 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 51429187 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 9738477 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 394455 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 925294 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3298023 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 403705 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 55280627 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 94381 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 10269621 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 7907555 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 360066 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 33263 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 361678 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 38192 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 184473 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 164818 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 349291 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 51367571 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 9727601 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 393852 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 109550 # number of nop insts executed -system.cpu2.iew.exec_refs 17180160 # number of memory reference insts executed -system.cpu2.iew.exec_branches 9476518 # Number of branches executed -system.cpu2.iew.exec_stores 7441683 # Number of stores executed -system.cpu2.iew.exec_rate 0.738748 # Inst execution rate -system.cpu2.iew.wb_sent 51031347 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 50326280 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 26469079 # num instructions producing a value -system.cpu2.iew.wb_consumers 46041332 # num instructions consuming a value +system.cpu2.iew.exec_nop 110034 # number of nop insts executed +system.cpu2.iew.exec_refs 17167980 # number of memory reference insts executed +system.cpu2.iew.exec_branches 9465672 # Number of branches executed +system.cpu2.iew.exec_stores 7440379 # Number of stores executed +system.cpu2.iew.exec_rate 0.738059 # Inst execution rate +system.cpu2.iew.wb_sent 50970582 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 50267816 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 26418019 # num instructions producing a value +system.cpu2.iew.wb_consumers 45975704 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.722906 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.574898 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.722257 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.574608 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 8143906 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 604423 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 291897 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 66086949 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.713825 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.622364 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8162826 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 603964 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 292667 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 66072678 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.712969 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.621762 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 48131767 72.83% 72.83% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 7989880 12.09% 84.92% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 3968576 6.01% 90.93% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 1690353 2.56% 93.48% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 906489 1.37% 94.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 608385 0.92% 95.78% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 1262051 1.91% 97.69% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 299318 0.45% 98.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1230130 1.86% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 48122515 72.83% 72.83% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 8016673 12.13% 84.97% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 3951454 5.98% 90.95% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 1700222 2.57% 93.52% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 874557 1.32% 94.84% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 615125 0.93% 95.77% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 1261958 1.91% 97.68% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 299480 0.45% 98.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1230694 1.86% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 66086949 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 38874571 # Number of instructions committed -system.cpu2.commit.committedOps 47174544 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 66072678 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 38816949 # Number of instructions committed +system.cpu2.commit.committedOps 47107760 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 15774131 # Number of memory references committed -system.cpu2.commit.loads 8665443 # Number of loads committed -system.cpu2.commit.membars 227144 # Number of memory barriers committed -system.cpu2.commit.branches 8900555 # Number of branches committed -system.cpu2.commit.fp_insts 4112 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 41283041 # Number of committed integer instructions. -system.cpu2.commit.function_calls 1636102 # Number of function calls committed. +system.cpu2.commit.refs 15760446 # Number of memory references committed +system.cpu2.commit.loads 8653893 # Number of loads committed +system.cpu2.commit.membars 226862 # Number of memory barriers committed +system.cpu2.commit.branches 8887739 # Number of branches committed +system.cpu2.commit.fp_insts 4128 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 41222164 # Number of committed integer instructions. +system.cpu2.commit.function_calls 1631970 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 31359241 66.47% 66.47% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 38284 0.08% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 2888 0.01% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 8665443 18.37% 84.93% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 7108688 15.07% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 31306209 66.46% 66.46% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 38229 0.08% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 2876 0.01% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.54% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 8653893 18.37% 84.91% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 7106553 15.09% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 47174544 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1230130 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 112818862 # The number of ROB reads -system.cpu2.rob.rob_writes 112362949 # The number of ROB writes -system.cpu2.timesIdled 279332 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1807284 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 5249914577 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 38809335 # Number of Instructions Simulated -system.cpu2.committedOps 47109308 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.793812 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.793812 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.557472 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.557472 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 56301107 # number of integer regfile reads -system.cpu2.int_regfile_writes 31916155 # number of integer regfile writes -system.cpu2.fp_regfile_reads 15723 # number of floating regfile reads -system.cpu2.fp_regfile_writes 13758 # number of floating regfile writes -system.cpu2.cc_regfile_reads 181999487 # number of cc regfile reads -system.cpu2.cc_regfile_writes 19225356 # number of cc regfile writes -system.cpu2.misc_regfile_reads 94261250 # number of misc regfile reads -system.cpu2.misc_regfile_writes 485009 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 30180 # Transaction distribution -system.iobus.trans_dist::ReadResp 30180 # Transaction distribution -system.iobus.trans_dist::WriteReq 59003 # Transaction distribution -system.iobus.trans_dist::WriteResp 22779 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54126 # Packet count per connected master and slave (bytes) +system.cpu2.commit.op_class_0::total 47107760 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1230694 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 112781874 # The number of ROB reads +system.cpu2.rob.rob_writes 112267275 # The number of ROB writes +system.cpu2.timesIdled 279594 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1802849 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 5249879064 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 38751769 # Number of Instructions Simulated +system.cpu2.committedOps 47042580 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.796001 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.796001 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.556793 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.556793 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 56233169 # number of integer regfile reads +system.cpu2.int_regfile_writes 31866388 # number of integer regfile writes +system.cpu2.fp_regfile_reads 15654 # number of floating regfile reads +system.cpu2.fp_regfile_writes 13819 # number of floating regfile writes +system.cpu2.cc_regfile_reads 181781148 # number of cc regfile reads +system.cpu2.cc_regfile_writes 19208893 # number of cc regfile writes +system.cpu2.misc_regfile_reads 94223470 # number of misc regfile reads +system.cpu2.misc_regfile_writes 484431 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 30182 # Transaction distribution +system.iobus.trans_dist::ReadResp 30182 # Transaction distribution +system.iobus.trans_dist::WriteReq 59005 # Transaction distribution +system.iobus.trans_dist::WriteResp 59005 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54134 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1779,11 +1778,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105414 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105422 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178366 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67843 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67851 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1804,11 +1803,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159071 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159079 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480319 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 18225000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2480327 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 18337000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1830,29 +1829,29 @@ system.iobus.reqLayer19.occupancy 2000 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 2714000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 2698000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15729000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 15728000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 124959118 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 107120699 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 39808000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 39854000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 23061006 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 20948000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 0.992064 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.991924 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 244950709509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.992064 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062004 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062004 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 244949964009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.991924 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.061995 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.061995 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1860,377 +1859,389 @@ system.iocache.tags.tag_accesses 328284 # Nu system.iocache.tags.data_accesses 328284 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses system.iocache.demand_misses::total 252 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 252 # number of overall misses system.iocache.overall_misses::total 252 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 14858930 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 14858930 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 4185043182 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 4185043182 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 14858930 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14858930 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 14858930 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14858930 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 14446931 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 14446931 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 2442151768 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2442151768 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 14446931 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14446931 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 14446931 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14446931 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 58964.007937 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 58964.007937 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 115532.331659 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 115532.331659 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 58964.007937 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 58964.007937 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 58964.007937 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 58964.007937 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 14316 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 57329.091270 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 57329.091270 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 67418.058966 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 67418.058966 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 57329.091270 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 57329.091270 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 57329.091270 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 57329.091270 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2165 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.612471 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 125 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 125 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 22752 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 22752 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 125 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 125 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 125 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 125 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 8240930 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 8240930 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 3001927194 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 3001927194 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8240930 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8240930 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8240930 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8240930 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.496032 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.628092 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.628092 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.496032 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.496032 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 65927.440000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 65927.440000 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131941.244462 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131941.244462 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 65927.440000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 65927.440000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 65927.440000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 65927.440000 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::realview.ide 122 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 122 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 20704 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 20704 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 122 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 122 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 122 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 122 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 8346931 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 8346931 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 1406951768 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1406951768 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8346931 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8346931 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8346931 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8346931 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.484127 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.484127 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.571555 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.571555 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.484127 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.484127 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.484127 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.484127 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68417.467213 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68417.467213 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67955.552937 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67955.552937 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68417.467213 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68417.467213 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68417.467213 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68417.467213 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 100862 # number of replacements -system.l2c.tags.tagsinuse 65121.580421 # Cycle average of tags in use -system.l2c.tags.total_refs 2889469 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 166056 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 17.400570 # Average number of references to valid blocks. +system.l2c.tags.replacements 100800 # number of replacements +system.l2c.tags.tagsinuse 65125.449839 # Cycle average of tags in use +system.l2c.tags.total_refs 4808585 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 165996 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 28.968078 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 49829.873035 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939329 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 49726.772555 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939327 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5354.052994 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2949.398573 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5415.190350 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2959.237721 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969230 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1018.817810 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 810.859726 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 62.513746 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 3585.332677 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1507.823205 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.760344 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 1018.129085 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 815.178543 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 59.704078 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 3616.145822 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1512.183033 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.758770 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081696 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.045004 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.082629 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.045154 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.015546 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.012373 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000954 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.054708 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.023008 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993676 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65144 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 50 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.015535 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.012439 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000911 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.055178 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.023074 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993736 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 48 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65148 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 48 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2979 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8228 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53568 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000763 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994019 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27412273 # Number of tag accesses -system.l2c.tags.data_accesses 27412273 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4625 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2417 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 853709 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 239887 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 1714 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 910 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 248258 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 78311 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 26936 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 6133 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 677801 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 203846 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2344547 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 690587 # number of Writeback hits -system.l2c.Writeback_hits::total 690587 # number of Writeback hits +system.l2c.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2981 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8244 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53579 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994080 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 42763917 # Number of tag accesses +system.l2c.tags.data_accesses 42763917 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4590 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2386 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 1717 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 931 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 27091 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 5953 # number of ReadReq hits +system.l2c.ReadReq_hits::total 42668 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 690633 # number of Writeback hits +system.l2c.Writeback_hits::total 690633 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 10 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 33 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 47 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 10 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 81710 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 20207 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 55512 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 157429 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4625 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2417 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 853709 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 321597 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 1714 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 910 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 248258 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 98518 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 26936 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 6133 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 677801 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 259358 # number of demand (read+write) hits -system.l2c.demand_hits::total 2501976 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4625 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1742226000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2871703000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4613929000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000582 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003274 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.988439 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.968721 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.504886 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.312500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.263158 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.416535 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.520289 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.251776 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007787 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.011864 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005604 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.030713 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.021316 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.012907 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000582 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007787 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.146714 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003274 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011864 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.199410 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034269 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000582 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007787 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.146714 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003274 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011864 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.199410 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034269 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 78966.292135 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 78894.444444 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20763.157895 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20756.410256 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20758.064516 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 21600 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 21600 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67426.486860 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71198.719015 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70467.238836 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71797.533402 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73516.949153 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73185.269627 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72053.830645 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 77693.373901 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75671.389331 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71797.533402 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68103.925620 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 78966.292135 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73516.949153 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71645.165538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 71167.343043 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71797.533402 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68103.925620 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 78966.292135 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73516.949153 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71645.165538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 71167.343043 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167194.491670 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 186913.207767 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 178904.819443 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165313.289760 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 185836.886210 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 177567.635183 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 166369.938885 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 186437.901707 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 178316.096618 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 74250 # Transaction distribution -system.membus.trans_dist::ReadResp 74249 # Transaction distribution -system.membus.trans_dist::WriteReq 27555 # Transaction distribution -system.membus.trans_dist::WriteResp 27555 # Transaction distribution -system.membus.trans_dist::Writeback 129076 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4552 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 9 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4561 # Transaction distribution -system.membus.trans_dist::ReadExReq 137020 # Transaction distribution -system.membus.trans_dist::ReadExResp 137020 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105414 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 40110 # Transaction distribution +system.membus.trans_dist::ReadResp 74274 # Transaction distribution +system.membus.trans_dist::WriteReq 27559 # Transaction distribution +system.membus.trans_dist::WriteResp 27559 # Transaction distribution +system.membus.trans_dist::Writeback 129127 # Transaction distribution +system.membus.trans_dist::CleanEvict 7993 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4555 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4563 # Transaction distribution +system.membus.trans_dist::ReadExReq 136939 # Transaction distribution +system.membus.trans_dist::ReadExResp 136939 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34165 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105422 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471581 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 578995 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109017 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109017 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 688012 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159071 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2000 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 479379 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 586811 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109150 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109150 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 695961 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159079 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16928828 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17091899 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4642624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4642624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21734523 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 283 # Total snoops (count) -system.membus.snoop_fanout::samples 408724 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16928316 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17091415 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2324480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2324480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19415895 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 278 # Total snoops (count) +system.membus.snoop_fanout::samples 416813 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 408724 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 416813 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 408724 # Request fanout histogram -system.membus.reqLayer0.occupancy 45631500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 416813 # Request fanout histogram +system.membus.reqLayer0.occupancy 45715500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 463000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 475000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 565034415 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 457691597 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 525270598 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 520011564 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 23441994 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 36772084 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2475,50 +2497,53 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2441800 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2441792 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27555 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27555 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 690587 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 22777 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2762 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 105713 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2441896 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27559 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27559 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 756453 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1923004 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2763 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 19 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2781 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296286 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296286 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3617238 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2478347 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29055 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87637 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6212277 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115207096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97661699 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 48712 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 154828 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 213072335 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 51752 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3495385 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.029269 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.168561 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 2782 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296176 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296176 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1800158 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 536033 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 20704 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5399808 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2615033 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28551 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87799 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8131191 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115239416 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97644319 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 47800 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 155188 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 213086723 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 121684 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5505945 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.031256 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.174010 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3393077 97.07% 97.07% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 102308 2.93% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 5333849 96.87% 96.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 172096 3.13% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3495385 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1275217471 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 177000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 5505945 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1781656500 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 172500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1406471499 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1404823682 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 694961258 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 679741283 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11749485 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11544481 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 39124219 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 39263676 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |