diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt | 2808 |
1 files changed, 1574 insertions, 1234 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 7f7ee8a99..edfc62ccf 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,175 +1,163 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.401343 # Number of seconds simulated -sim_ticks 2401342505500 # Number of ticks simulated -final_tick 2401342505500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.401127 # Number of seconds simulated +sim_ticks 2401127269500 # Number of ticks simulated +final_tick 2401127269500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 199955 # Simulator instruction rate (inst/s) -host_op_rate 256803 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7959007704 # Simulator tick rate (ticks/s) -host_mem_usage 399904 # Number of bytes of host memory used -host_seconds 301.71 # Real time elapsed on the host -sim_insts 60329298 # Number of instructions simulated -sim_ops 77481139 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 142330 # Simulator instruction rate (inst/s) +host_op_rate 182788 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5664980832 # Simulator tick rate (ticks/s) +host_mem_usage 401540 # Number of bytes of host memory used +host_seconds 423.85 # Real time elapsed on the host +sim_insts 60327009 # Number of instructions simulated +sim_ops 77475387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 502112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7093136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 511520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7145552 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 84928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 676160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 78912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 687680 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.dtb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 175680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1309048 # Number of bytes read from this memory -system.physmem.bytes_read::total 124660776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 502112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 84928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 175680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 762720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3745536 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1490604 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1325756 # Number of bytes written to this memory -system.physmem.bytes_written::total 6761352 # Number of bytes written to this memory +system.physmem.bytes_read::cpu2.inst 173184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1243936 # Number of bytes read from this memory +system.physmem.bytes_read::total 124660496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 511520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 78912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 173184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 763616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3744064 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1523456 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 157860 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1334500 # Number of bytes written to this memory +system.physmem.bytes_written::total 6759880 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14048 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110864 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14195 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 111683 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1327 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10565 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1233 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10745 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.dtb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2745 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20467 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512410 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58524 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 372651 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 331439 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812478 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47814534 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu2.inst 2706 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 19444 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512400 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58501 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380864 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39465 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 333625 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812455 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47818820 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 209096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2953821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213033 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2975916 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 281576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 32865 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 286399 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 73159 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 545132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51912951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 209096 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35367 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 73159 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317622 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1559768 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 620738 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 83060 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 552090 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2815655 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1559768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47814534 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 72126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 518063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51917488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213033 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 32865 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 72126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318024 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1559294 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 634475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 65744 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 555781 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2815294 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1559294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47818820 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 209096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3574559 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3610391 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 364636 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 32865 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 352143 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 73159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1097221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54728606 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12618023 # Total number of read requests seen -system.physmem.writeReqs 398732 # Total number of write requests seen -system.physmem.cpureqs 54886 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 807553472 # Total number of bytes read from memory -system.physmem.bytesWritten 25518848 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 102909560 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2640668 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2360 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 789126 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 788779 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 788883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 789203 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 789028 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 788746 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 788896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 788935 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 788618 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 788026 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 788041 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 788281 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 788275 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 788125 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 788319 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 788742 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 24962 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 24831 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 24770 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 25056 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 24828 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 24649 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 24736 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 24783 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 25151 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 24834 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 24774 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 24883 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 25404 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 24880 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 24969 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 25222 # Track writes on a per bank basis +system.physmem.bw_total::cpu2.inst 72126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1073844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54732782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12420439 # Total number of read requests seen +system.physmem.writeReqs 390212 # Total number of write requests seen +system.physmem.cpureqs 53603 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 794908096 # Total number of bytes read from memory +system.physmem.bytesWritten 24973568 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 101274592 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2588168 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 2354 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 776339 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 775940 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 776092 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 776425 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 777292 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 776809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 775620 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 775424 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 775584 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 776041 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 775688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 776201 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 777483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 777433 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 776149 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 775918 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 25457 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 25320 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 25407 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 25903 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 26305 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 26088 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 25428 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 23374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 23183 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 23262 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 21306 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 21574 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 24629 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 24259 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 23496 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 25221 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 14347 # Number of times wr buffer was full causing retry -system.physmem.totGap 2400307282000 # Total gap between requests +system.physmem.numWrRetry 14413 # Number of times wr buffer was full causing retry +system.physmem.totGap 2400092064000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 14 # Categorize read packet sizes -system.physmem.readPktSize::3 12582912 # Categorize read packet sizes +system.physmem.readPktSize::2 8 # Categorize read packet sizes +system.physmem.readPktSize::3 12386304 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 35097 # Categorize read packet sizes +system.physmem.readPktSize::6 34127 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 381303 # Categorize write packet sizes +system.physmem.writePktSize::2 373090 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17429 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 815886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 792065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 797737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2998161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2260870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2261150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2249588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 49294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 49195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 91403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 133606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 91397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 6927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6910 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17122 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 803531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 778993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 809862 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3060255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2298083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2298065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2262695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 12148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 12111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 22591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 33065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 22584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -185,326 +173,482 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 17346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 17336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 17334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 17330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 17321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 17317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 17314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 14401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 14385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 14357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14349 # What write queue length does an incoming req see -system.physmem.totQLat 277119182500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 352940243750 # Sum of mem lat for all requests -system.physmem.totBusLat 63090115000 # Total cycles spent in databus access -system.physmem.totBankLat 12730946250 # Total cycles spent in bank access -system.physmem.avgQLat 21962.17 # Average queueing delay per request -system.physmem.avgBankLat 1008.95 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 16974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 16970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 16964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 16959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 16952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 16947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 16944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 16942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 16934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 16922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 16920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 14485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 14475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 14452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 14449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14427 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 20861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 39302.074493 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 6009.687839 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 33098.413312 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 3004 14.40% 14.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 1328 6.37% 20.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 811 3.89% 24.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 565 2.71% 27.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 381 1.83% 29.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 362 1.74% 30.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 265 1.27% 32.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 238 1.14% 33.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 172 0.82% 34.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 151 0.72% 34.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 130 0.62% 35.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 127 0.61% 36.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 66 0.32% 36.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 86 0.41% 36.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 45 0.22% 37.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 78 0.37% 37.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 36 0.17% 37.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 26 0.12% 37.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 22 0.11% 37.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 43 0.21% 38.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 28 0.13% 38.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 87 0.42% 38.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 101 0.48% 39.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 96 0.46% 39.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 23 0.11% 39.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 38 0.18% 39.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 20 0.10% 39.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 38 0.18% 40.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 12 0.06% 40.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 22 0.11% 40.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 8 0.04% 40.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 17 0.08% 40.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 10 0.05% 40.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 9 0.04% 40.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 4 0.02% 40.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 3 0.01% 40.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 5 0.02% 40.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 9 0.04% 40.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 4 0.02% 40.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 4 0.02% 40.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 2 0.01% 40.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 2 0.01% 40.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 6 0.03% 40.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 3 0.01% 40.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 7 0.03% 40.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 1 0.00% 40.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 2 0.01% 40.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 4 0.02% 40.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 1 0.00% 40.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 3 0.01% 40.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 3 0.01% 40.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 8 0.04% 40.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 2 0.01% 40.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 3 0.01% 40.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 1 0.00% 40.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 3 0.01% 40.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 2 0.01% 40.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 2 0.01% 40.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 2 0.01% 40.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 1 0.00% 40.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 1 0.00% 40.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 1 0.00% 40.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 6 0.03% 40.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 2 0.01% 40.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 3 0.01% 40.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4703 1 0.00% 40.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 2 0.01% 40.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4831 2 0.01% 40.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 1 0.00% 40.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 1 0.00% 41.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 1 0.00% 41.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 1 0.00% 41.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5535 1 0.00% 41.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 1 0.00% 41.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 4 0.02% 41.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6943 1 0.00% 41.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 2 0.01% 41.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7135 1 0.00% 41.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7391 2 0.01% 41.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 1 0.00% 41.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 2 0.01% 41.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 3 0.01% 41.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 1 0.00% 41.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 1 0.00% 41.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 2 0.01% 41.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11136-11167 1 0.00% 41.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11807 1 0.00% 41.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 1 0.00% 41.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15199 1 0.00% 41.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18463 1 0.00% 41.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19487 1 0.00% 41.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-31007 1 0.00% 41.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33567 2 0.01% 41.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 1 0.00% 41.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 12093 57.97% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::127424-127455 1 0.00% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 181 0.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 20861 # Bytes accessed per row activation +system.physmem.totQLat 241895050750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 315493767000 # Sum of mem lat for all requests +system.physmem.totBusLat 62102190000 # Total cycles spent in databus access +system.physmem.totBankLat 11496526250 # Total cycles spent in bank access +system.physmem.avgQLat 19475.57 # Average queueing delay per request +system.physmem.avgBankLat 925.61 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27971.12 # Average memory access latency -system.physmem.avgRdBW 336.29 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 10.63 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 42.86 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 25401.18 # Average memory access latency +system.physmem.avgRdBW 331.06 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 10.40 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 42.18 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.08 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.71 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 12563435 # Number of row buffer hits during reads -system.physmem.writeRowHits 392399 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.41 # Row buffer hit rate for writes -system.physmem.avgGap 184401.36 # Average gap between requests -system.l2c.replacements 63248 # number of replacements -system.l2c.tagsinuse 50357.471102 # Cycle average of tags in use -system.l2c.total_refs 1749120 # Total number of references to valid blocks. -system.l2c.sampled_refs 128641 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.596909 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2374433885500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36827.136068 # Average occupied blocks per requestor +system.physmem.busUtil 2.67 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.13 # Average read queue length over time +system.physmem.avgWrQLen 0.40 # Average write queue length over time +system.physmem.readRowHits 12404411 # Number of row buffer hits during reads +system.physmem.writeRowHits 385376 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.87 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.76 # Row buffer hit rate for writes +system.physmem.avgGap 187351.30 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 55731119 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 12759502 # Transaction distribution +system.membus.trans_dist::ReadResp 12759502 # Transaction distribution +system.membus.trans_dist::WriteReq 375940 # Transaction distribution +system.membus.trans_dist::WriteResp 375940 # Transaction distribution +system.membus.trans_dist::Writeback 17122 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2354 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2354 # Transaction distribution +system.membus.trans_dist::ReadExReq 26440 # Transaction distribution +system.membus.trans_dist::ReadExResp 26440 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 736482 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 836280 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 224 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1572986 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 24772608 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 24772608 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 736482 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 25608888 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 224 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 26345594 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 740439 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 4772328 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 448 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5513215 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 99090432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 99090432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 740439 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 103862760 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 448 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 104603647 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133817510 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 420513000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 13413227250 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.6 # Layer utilization (%) +system.membus.reqLayer3.occupancy 209500 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 1495675396 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 27962648500 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.2 # Layer utilization (%) +system.l2c.replacements 63244 # number of replacements +system.l2c.tagsinuse 50337.430960 # Cycle average of tags in use +system.l2c.total_refs 1749337 # Total number of references to valid blocks. +system.l2c.sampled_refs 128639 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.598808 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009032 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.114423 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000327 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009493 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.102934 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.022440 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60302.311436 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61622.920133 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 71666.666667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65644.401330 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 63731.587239 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 63532.977755 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10022.798658 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32483.490935 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40717.622247 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 37892.626884 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43207.669179 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33876.402251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 104667.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 51137.767577 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41759.345527 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40163.838908 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43207.669179 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33876.402251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 104667.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 51137.767577 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41759.345527 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40163.838908 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50485.006212 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 57409.873306 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 54920.116075 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60302.311436 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51699.757372 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 71666.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65644.401330 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 58211.212881 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 56811.908735 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60302.311436 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51699.757372 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 71666.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65644.401330 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 58211.212881 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 56811.908735 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -654,438 +801,631 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.toL2Bus.throughput 58868329 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1038711 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1038710 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 375940 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 375940 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 275281 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1501 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1503 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80190 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80190 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 843862 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2343005 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 15512 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 51160 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 3253539 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 26980864 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 38469375 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 21900 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 84004 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 65556143 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141250094 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 100256 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2175069728 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1900577406 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1863798035 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 10055959 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 30318675 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.throughput 48814240 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 12751762 # Transaction distribution +system.iobus.trans_dist::ReadResp 12751762 # Transaction distribution +system.iobus.trans_dist::WriteReq 2783 # Transaction distribution +system.iobus.trans_dist::WriteResp 2783 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11428 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 721384 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 736482 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 24772608 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 24772608 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 11428 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 3102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 721384 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sp810_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 24772608 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 25509090 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 717707 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 740439 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 99090432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 99090432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 15392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 6204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 717707 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 99090432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 99830871 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 117209202 # Total data (bytes) +system.iobus.reqLayer0.occupancy 7987000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 1551000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 131000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 361193000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 12386304000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) +system.iobus.respLayer0.occupancy 733699000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 24772608000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8064741 # DTB read hits -system.cpu0.dtb.read_misses 6215 # DTB read misses -system.cpu0.dtb.write_hits 6627061 # DTB write hits -system.cpu0.dtb.write_misses 2040 # DTB write misses +system.cpu0.dtb.read_hits 8064428 # DTB read hits +system.cpu0.dtb.read_misses 6238 # DTB read misses +system.cpu0.dtb.write_hits 6663212 # DTB write hits +system.cpu0.dtb.write_misses 2045 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 690 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 678 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5695 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5690 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 121 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 114 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8070956 # DTB read accesses -system.cpu0.dtb.write_accesses 6629101 # DTB write accesses +system.cpu0.dtb.read_accesses 8070666 # DTB read accesses +system.cpu0.dtb.write_accesses 6665257 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14691802 # DTB hits -system.cpu0.dtb.misses 8255 # DTB misses -system.cpu0.dtb.accesses 14700057 # DTB accesses -system.cpu0.itb.inst_hits 32689341 # ITB inst hits -system.cpu0.itb.inst_misses 3490 # ITB inst misses +system.cpu0.dtb.hits 14727640 # DTB hits +system.cpu0.dtb.misses 8283 # DTB misses +system.cpu0.dtb.accesses 14735923 # DTB accesses +system.cpu0.itb.inst_hits 32885888 # ITB inst hits +system.cpu0.itb.inst_misses 3493 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 690 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 678 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2596 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2597 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32692831 # ITB inst accesses -system.cpu0.itb.hits 32689341 # DTB hits -system.cpu0.itb.misses 3490 # DTB misses -system.cpu0.itb.accesses 32692831 # DTB accesses -system.cpu0.numCycles 114004049 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32889381 # ITB inst accesses +system.cpu0.itb.hits 32885888 # DTB hits +system.cpu0.itb.misses 3493 # DTB misses +system.cpu0.itb.accesses 32889381 # DTB accesses +system.cpu0.numCycles 114194187 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32197863 # Number of instructions committed -system.cpu0.committedOps 42390807 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37541776 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5152 # Number of float alu accesses -system.cpu0.num_func_calls 1189364 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4237827 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37541776 # number of integer instructions -system.cpu0.num_fp_insts 5152 # number of float instructions -system.cpu0.num_int_register_reads 191249726 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39627279 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3662 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu0.num_mem_refs 15356244 # number of memory refs -system.cpu0.num_load_insts 8432602 # Number of load instructions -system.cpu0.num_store_insts 6923642 # Number of store instructions -system.cpu0.num_idle_cycles 13418877123.276752 # Number of idle cycles -system.cpu0.num_busy_cycles -13304873074.276752 # Number of busy cycles -system.cpu0.not_idle_fraction -116.705268 # Percentage of non-idle cycles -system.cpu0.idle_fraction 117.705268 # Percentage of idle cycles +system.cpu0.committedInsts 32400694 # Number of instructions committed +system.cpu0.committedOps 42604041 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37748945 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5021 # Number of float alu accesses +system.cpu0.num_func_calls 1185552 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4241024 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37748945 # number of integer instructions +system.cpu0.num_fp_insts 5021 # number of float instructions +system.cpu0.num_int_register_reads 192241357 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39867524 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3591 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1432 # number of times the floating registers were written +system.cpu0.num_mem_refs 15390684 # number of memory refs +system.cpu0.num_load_insts 8430090 # Number of load instructions +system.cpu0.num_store_insts 6960594 # Number of store instructions +system.cpu0.num_idle_cycles 13437222906.022394 # Number of idle cycles +system.cpu0.num_busy_cycles -13323028719.022394 # Number of busy cycles +system.cpu0.not_idle_fraction -116.669938 # Percentage of non-idle cycles +system.cpu0.idle_fraction 117.669938 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 82893 # number of quiesce instructions executed -system.cpu0.icache.replacements 891776 # number of replacements -system.cpu0.icache.tagsinuse 511.602850 # Cycle average of tags in use -system.cpu0.icache.total_refs 44220417 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 892288 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 49.558458 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 8123363500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 478.597837 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 17.659572 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 15.345442 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.934761 # 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Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.942472 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.043019 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.013732 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.999224 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 32220796 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8246178 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3753443 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 44220417 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32220796 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8246178 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3753443 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 44220417 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32220796 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8246178 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3753443 # number of overall hits -system.cpu0.icache.overall_hits::total 44220417 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 471225 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 133904 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 311110 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916239 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 471225 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 133904 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 311110 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 916239 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 471225 # 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number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 4064553 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 45136656 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014414 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015979 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076542 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.020299 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014414 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015979 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076542 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.020299 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014414 # 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number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3229425493 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 4672112493 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27590939000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28973644000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56564583000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1276412500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14137928134 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15414340634 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28867351500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43111572134 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71978923634 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033321 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028970 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014672 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021547 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019429 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008082 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048269 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044950 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020668 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000016 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028455 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025495 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011872 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028455 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025495 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011872 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11938.226767 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13012.144312 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12668.859595 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22637.159303 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27034.857496 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25461.720983 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11091.014493 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11689.459930 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11489.746566 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597640 # number of writebacks +system.cpu0.dcache.writebacks::total 597640 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 147191 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 147191 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 530305 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 530305 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 415 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 415 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 677496 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 677496 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 677496 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 677496 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65203 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 140329 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 205532 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29806 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 51832 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 81638 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1787 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3452 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5239 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 95009 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 192161 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 287170 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 95009 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 192161 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 287170 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 798657500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1814845381 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2613502881 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 853492500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1663883074 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2517375574 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19875000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 39692503 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59567503 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1652150000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3478728455 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5130878455 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1652150000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3478728455 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5130878455 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27438525500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28895903000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56334428500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1439019500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13930302419 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15369321919 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28877545000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42826205419 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71703750419 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033512 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029420 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014862 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021489 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019306 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007991 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049609 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044631 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020906 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028508 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025777 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011943 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028508 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025777 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011943 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12248.784565 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12932.789238 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12715.795501 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28634.922499 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32101.463845 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30835.831035 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11121.992166 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11498.407590 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11370.013934 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15286.425718 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16904.712140 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16369.598173 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15286.425718 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16904.712140 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16369.598173 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17389.405214 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18103.197085 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17867.042013 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17389.405214 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18103.197085 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17867.042013 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1098,219 +1438,219 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2161402 # DTB read hits -system.cpu1.dtb.read_misses 2114 # DTB read misses -system.cpu1.dtb.write_hits 1457218 # DTB write hits -system.cpu1.dtb.write_misses 386 # DTB write misses +system.cpu1.dtb.read_hits 2160353 # DTB read hits +system.cpu1.dtb.read_misses 2072 # DTB read misses +system.cpu1.dtb.write_hits 1463428 # DTB write hits +system.cpu1.dtb.write_misses 375 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 237 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1741 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 41 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2163516 # DTB read accesses -system.cpu1.dtb.write_accesses 1457604 # DTB write accesses +system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 2162425 # DTB read accesses +system.cpu1.dtb.write_accesses 1463803 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3618620 # DTB hits -system.cpu1.dtb.misses 2500 # DTB misses -system.cpu1.dtb.accesses 3621120 # DTB accesses -system.cpu1.itb.inst_hits 8380082 # ITB inst hits -system.cpu1.itb.inst_misses 1132 # ITB inst misses +system.cpu1.dtb.hits 3623781 # DTB hits +system.cpu1.dtb.misses 2447 # DTB misses +system.cpu1.dtb.accesses 3626228 # DTB accesses +system.cpu1.itb.inst_hits 8343384 # ITB inst hits +system.cpu1.itb.inst_misses 1170 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 237 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 830 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 867 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8381214 # ITB inst accesses -system.cpu1.itb.hits 8380082 # DTB hits -system.cpu1.itb.misses 1132 # DTB misses -system.cpu1.itb.accesses 8381214 # DTB accesses -system.cpu1.numCycles 574618954 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8344554 # ITB inst accesses +system.cpu1.itb.hits 8343384 # DTB hits +system.cpu1.itb.misses 1170 # DTB misses +system.cpu1.itb.accesses 8344554 # DTB accesses +system.cpu1.numCycles 576594127 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8175033 # Number of instructions committed -system.cpu1.committedOps 10410069 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9322021 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1998 # Number of float alu accesses -system.cpu1.num_func_calls 315375 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1140852 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9322021 # number of integer instructions -system.cpu1.num_fp_insts 1998 # number of float instructions -system.cpu1.num_int_register_reads 53738545 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10097471 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1549 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written -system.cpu1.num_mem_refs 3791152 # number of memory refs -system.cpu1.num_load_insts 2256757 # Number of load instructions -system.cpu1.num_store_insts 1534395 # Number of store instructions -system.cpu1.num_idle_cycles 532868716.793879 # Number of idle cycles -system.cpu1.num_busy_cycles 41750237.206121 # Number of busy cycles -system.cpu1.not_idle_fraction 0.072657 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.927343 # Percentage of idle cycles +system.cpu1.committedInsts 8139213 # Number of instructions committed +system.cpu1.committedOps 10387341 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9296011 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2143 # Number of float alu accesses +system.cpu1.num_func_calls 319457 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1149983 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9296011 # number of integer instructions +system.cpu1.num_fp_insts 2143 # number of float instructions +system.cpu1.num_int_register_reads 53626328 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10059981 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1630 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written +system.cpu1.num_mem_refs 3800206 # number of memory refs +system.cpu1.num_load_insts 2257531 # Number of load instructions +system.cpu1.num_store_insts 1542675 # Number of store instructions +system.cpu1.num_idle_cycles 550949024.070645 # Number of idle cycles +system.cpu1.num_busy_cycles 25645102.929355 # Number of busy cycles +system.cpu1.not_idle_fraction 0.044477 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.955523 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4722397 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3838487 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 221435 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 2952816 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2527233 # Number of BTB hits +system.cpu2.branchPred.lookups 4706679 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3828645 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 220746 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3114772 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2519361 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 85.587216 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 411089 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21408 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.884283 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 411150 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21524 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10881575 # DTB read hits -system.cpu2.dtb.read_misses 22640 # DTB read misses -system.cpu2.dtb.write_hits 3277177 # DTB write hits -system.cpu2.dtb.write_misses 5849 # DTB write misses +system.cpu2.dtb.read_hits 10881090 # DTB read hits +system.cpu2.dtb.read_misses 22334 # DTB read misses +system.cpu2.dtb.write_hits 3233578 # DTB write hits +system.cpu2.dtb.write_misses 5962 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 512 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2319 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 814 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 160 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2292 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 695 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 165 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 478 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10904215 # DTB read accesses -system.cpu2.dtb.write_accesses 3283026 # DTB write accesses +system.cpu2.dtb.perms_faults 471 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10903424 # DTB read accesses +system.cpu2.dtb.write_accesses 3239540 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14158752 # DTB hits -system.cpu2.dtb.misses 28489 # DTB misses -system.cpu2.dtb.accesses 14187241 # DTB accesses -system.cpu2.itb.inst_hits 4065885 # ITB inst hits -system.cpu2.itb.inst_misses 4502 # ITB inst misses +system.cpu2.dtb.hits 14114668 # DTB hits +system.cpu2.dtb.misses 28296 # DTB misses +system.cpu2.dtb.accesses 14142964 # DTB accesses +system.cpu2.itb.inst_hits 3988029 # ITB inst hits +system.cpu2.itb.inst_misses 4597 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 512 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1576 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1713 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1005 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 994 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4070387 # ITB inst accesses -system.cpu2.itb.hits 4065885 # DTB hits -system.cpu2.itb.misses 4502 # DTB misses -system.cpu2.itb.accesses 4070387 # DTB accesses -system.cpu2.numCycles 88259873 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 3992626 # ITB inst accesses +system.cpu2.itb.hits 3988029 # DTB hits +system.cpu2.itb.misses 4597 # DTB misses +system.cpu2.itb.accesses 3992626 # DTB accesses +system.cpu2.numCycles 88357796 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9453176 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32426467 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4722397 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2938322 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6835194 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1814499 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 51467 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 18689225 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 953 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 32914 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 708494 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 306 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4064555 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 309850 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1926 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37018169 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.050897 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.436881 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9310481 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32575007 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4706679 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2930511 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6844695 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1834626 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 50535 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 18792292 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 211 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 834 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 32689 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 721380 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3986556 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 271694 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2030 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37012176 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.054575 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.442886 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30188064 81.55% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 383346 1.04% 82.58% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 510640 1.38% 83.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 813031 2.20% 86.16% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 657801 1.78% 87.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 343878 0.93% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1012409 2.73% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 238466 0.64% 92.25% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2870534 7.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30172484 81.52% 81.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 383589 1.04% 82.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 509700 1.38% 83.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 816595 2.21% 86.14% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 649845 1.76% 87.90% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 340688 0.92% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1002283 2.71% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 233105 0.63% 92.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2903887 7.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37018169 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053506 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367398 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10067654 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19275483 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6184949 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 295259 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1193811 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 613325 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53657 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36756215 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 182103 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1193811 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10642239 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6572797 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11156885 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5885889 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1565553 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34514239 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2456 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 419835 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 882809 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 92 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37003284 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 157776579 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 157748805 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 27774 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 25809996 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11193287 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 230807 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 207161 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3357083 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6535673 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3850744 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 536963 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 792176 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 31747463 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 511528 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34289699 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 55083 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7395646 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19879544 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 155324 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37018169 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.926294 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.580927 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37012176 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053268 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.368672 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9923582 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19398911 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6192413 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 289708 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1206624 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 608704 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53227 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36668894 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 179672 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1206624 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10457732 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6796532 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11090349 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5929465 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1530564 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34717207 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2441 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 375073 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 892617 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 118 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37295857 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 158754403 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 158727276 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 27127 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 25598469 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11697387 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 231672 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 208131 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3300393 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6518889 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3789656 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 530954 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 691805 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 31588093 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 511099 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34136489 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 54725 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7434189 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19599124 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 154239 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37012176 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.922304 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.578312 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24442328 66.03% 66.03% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3909913 10.56% 76.59% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2354045 6.36% 82.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1974122 5.33% 88.28% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2799200 7.56% 95.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 884316 2.39% 98.23% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 484064 1.31% 99.54% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 134882 0.36% 99.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 35299 0.10% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24481195 66.14% 66.14% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3912173 10.57% 76.71% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2318887 6.27% 82.98% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2014061 5.44% 88.42% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2743513 7.41% 95.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 884212 2.39% 98.22% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 492586 1.33% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 130661 0.35% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34888 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37018169 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37012176 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 18550 1.21% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 18493 1.21% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.21% # attempts to use FU when none available @@ -1338,148 +1678,148 @@ system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.21% # at system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1408407 91.61% 92.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 110486 7.19% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1405660 91.60% 92.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 110389 7.19% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61448 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19376629 56.51% 56.69% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 26012 0.08% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 8 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 381 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11380471 33.19% 89.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3444734 10.05% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61311 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19306288 56.56% 56.74% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 26277 0.08% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 7 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 369 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11344167 33.23% 90.05% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3398057 9.95% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34289699 # Type of FU issued -system.cpu2.iq.rate 0.388508 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1537443 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044837 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 107211457 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39659859 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27420215 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 6989 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3825 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3150 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 35761973 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3721 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 208327 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34136489 # Type of FU issued +system.cpu2.iq.rate 0.386344 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1534543 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044953 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 106895526 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39538518 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27366143 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7075 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3717 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3145 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 35605938 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3783 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206498 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1579914 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1893 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9373 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 582518 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1561517 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1841 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9166 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 566678 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5363105 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 352533 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5349938 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 380447 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1193811 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4877812 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 91796 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32340028 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 60265 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6535673 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3850744 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 369403 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 31610 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2472 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9373 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 105135 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 88586 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 193721 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33297921 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11093060 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 991778 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1206624 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5097630 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 92333 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32182024 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 61203 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6518889 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3789656 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 368677 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 31621 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2335 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9166 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 105355 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 88176 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 193531 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33238932 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11092763 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 897557 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 81037 # number of nop insts executed -system.cpu2.iew.exec_refs 14504508 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3695173 # Number of branches executed -system.cpu2.iew.exec_stores 3411448 # Number of stores executed -system.cpu2.iew.exec_rate 0.377271 # Inst execution rate -system.cpu2.iew.wb_sent 32878469 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27423365 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15687848 # num instructions producing a value -system.cpu2.iew.wb_consumers 28539684 # num instructions consuming a value +system.cpu2.iew.exec_nop 82832 # number of nop insts executed +system.cpu2.iew.exec_refs 14457569 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3671446 # Number of branches executed +system.cpu2.iew.exec_stores 3364806 # Number of stores executed +system.cpu2.iew.exec_rate 0.376186 # Inst execution rate +system.cpu2.iew.wb_sent 32811396 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27369288 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15602510 # num instructions producing a value +system.cpu2.iew.wb_consumers 28268763 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.310712 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.549685 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.309755 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.551935 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7335381 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356204 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 168508 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35824220 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.690433 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.719118 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7374898 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356860 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 168297 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35805367 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.685358 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.714033 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27176930 75.86% 75.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4185525 11.68% 87.55% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1261410 3.52% 91.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 649563 1.81% 92.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 571804 1.60% 94.48% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 316250 0.88% 95.36% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 400543 1.12% 96.48% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 292091 0.82% 97.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 970104 2.71% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27231349 76.05% 76.05% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4142496 11.57% 87.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1257531 3.51% 91.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 645964 1.80% 92.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 562986 1.57% 94.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 317406 0.89% 95.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 386660 1.08% 96.48% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 302677 0.85% 97.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 958298 2.68% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35824220 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20010366 # Number of instructions committed -system.cpu2.commit.committedOps 24734227 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35805367 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 19842604 # Number of instructions committed +system.cpu2.commit.committedOps 24539507 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8223985 # Number of memory references committed -system.cpu2.commit.loads 4955759 # Number of loads committed -system.cpu2.commit.membars 94186 # Number of memory barriers committed -system.cpu2.commit.branches 3169280 # Number of branches committed -system.cpu2.commit.fp_insts 3103 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 21954082 # Number of committed integer instructions. -system.cpu2.commit.function_calls 294910 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 970104 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8180350 # Number of memory references committed +system.cpu2.commit.loads 4957372 # Number of loads committed +system.cpu2.commit.membars 94561 # Number of memory barriers committed +system.cpu2.commit.branches 3152552 # Number of branches committed +system.cpu2.commit.fp_insts 3091 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 21772655 # Number of committed integer instructions. +system.cpu2.commit.function_calls 294654 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 958298 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66398809 # The number of ROB reads -system.cpu2.rob.rob_writes 65374131 # The number of ROB writes -system.cpu2.timesIdled 360148 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51241704 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3567295976 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 19956402 # Number of Instructions Simulated -system.cpu2.committedOps 24680263 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 19956402 # Number of Instructions Simulated -system.cpu2.cpi 4.422635 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.422635 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.226110 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.226110 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 153855471 # number of integer regfile reads -system.cpu2.int_regfile_writes 29258344 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22383 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20838 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9035132 # number of misc regfile reads -system.cpu2.misc_regfile_writes 240694 # number of misc regfile writes +system.cpu2.rob.rob_reads 66237138 # The number of ROB reads +system.cpu2.rob.rob_writes 65080734 # The number of ROB writes +system.cpu2.timesIdled 362582 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51345620 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3559271384 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 19787102 # Number of Instructions Simulated +system.cpu2.committedOps 24484005 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 19787102 # Number of Instructions Simulated +system.cpu2.cpi 4.465424 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.465424 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.223943 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.223943 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 153570043 # number of integer regfile reads +system.cpu2.int_regfile_writes 29228694 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22407 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20832 # number of floating regfile writes +system.cpu2.misc_regfile_reads 8993137 # number of misc regfile reads +system.cpu2.misc_regfile_writes 241651 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1494,10 +1834,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981038235668 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 981038235668 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981038235668 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 981038235668 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1181598504500 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1181598504500 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1181598504500 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1181598504500 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |